Generating a non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction

A non-reversible state is generated in the bit cell with the first magnetic tunnel junction and the second magnetic tunnel junction

The present invention generally relates to a one-time programmable bit cell based on a magnetic tunnel junction.

Advances in technology have produced smaller and more powerful computing devices. These portable computing devices may include a security architecture based on one-time programmable components, such as non-volatile memory devices with one-time programmable (OTP) memory cells. Once the OTP memory cell is programmed, the cell remains in a permanent state. For example, polysilicon fuses have been used as OTP devices. A polysilicon memory cell can be programmed by applying a voltage to the cell so that the cell is "blown" during programming. For example, one-shot programming is usually performed by fusing silicon with a high current (e.g., about a few milliamps) in a relatively long time (e.g., a few microseconds). One of the disadvantages of polysilicon fuses is that it is difficult to test the integrity of the fuse before the fuse is blown. Another disadvantage of the polysilicon fuse is that the fusing state is visibly detected, which may compromise safety.

Describe a single programmable device based on magnetic tunnel junction (MTJ) technology. The one-time programmable element is configured as a one-bit cell with a first resistive memory element and a second resistive memory element. The first resistive memory element and the second resistive memory element may each be an MTJ. The MTJ's natural unfused state has a higher resistance and the MTJ's fused state has a lower resistance. A program signal can be applied to one of the first MTJ and the second MTJ without applying the program signal to the other of the first MTJ and the second MTJ to generate an irreversible state at the bit cell. For example, the irreversible state can be generated by breaking down the tunneling oxide of one of the MTJs. When the tunneling oxide is broken down, a permanent low resistance state is created.

In a specific embodiment, a method for generating an irreversible state at a bit cell having a first magnetic tunnel junction (MTJ) and a second MTJ includes: applying a program voltage to the bit cell The first MTJ of the cell does not apply the program voltage to the second MTJ of the bit cell.

In another specific embodiment, a memory device includes a magnetic tunnel junction (MTJ) bit cell. The MTJ bit cell includes a first MTJ, a second MTJ, and a programming circuit configured to apply a programming signal to the first MTJ and the second MTJ of the bit cell One of the selected ones produces an irreversible state at the bit cell.

A particular advantage provided by at least one of the disclosed embodiments is that it can be obtained by programming an irreversible state to a one-bit cell having a first magnetic tunnel junction (MTJ) and a second MTJ Achieve high-speed programming.

Another particular advantage provided by at least one of the disclosed embodiments is that the operation of the bit cell can be tested before programming.

Another particular advantage provided by at least one of the disclosed embodiments is enhanced security because the visual detection of the programmed state of the bit cell is more difficult than in the case of polysilicon fuses.

Other aspects, advantages and features of the present invention will become apparent after reviewing the complete application. The complete application includes the following parts: [Schematic Description], [Implementation Mode] and [Applicable Patent Scope].

1, a specific illustrative embodiment of a memory device is depicted and generally designated as 100. The memory device includes an irreversible state programming circuit and a memory unit that stores data in a dual-element unit as an irreversible state. . The memory device 100 includes a representative memory cell 102 and an irreversible state programming circuit 104. The memory unit 102 includes a first resistive memory element 106 and a second resistive memory element 108. In a specific embodiment, the first resistive memory element 106 is a first magnetic tunnel junction (MTJ) element and the second resistive memory element 108 is a second MTJ element. The irreversible state programming circuit 104 is configured to apply a programming signal to one of the first resistive memory element 106 and the second resistive memory element 108 of the memory unit 102 to program an irreversible state to The memory unit 102.

In a specific embodiment, one-time programmability is achieved by irreversibly programming one of the two resistive memory elements 106, 108 in the memory cell 102. For example, the program voltage can be applied to the first resistive memory element 106 of the memory cell 102 through the irreversible state programming circuit 104 without applying the program voltage to the second resistive memory element 108 of the memory cell 102 to An irreversible state is generated at the memory cell 102. Alternatively, the program voltage can be applied to the second resistive memory element 108 of the memory cell 102 through the irreversible state programming circuit 104 without applying the program voltage to the first resistive memory element 106 of the memory cell 102, so that the memory An irreversible state is generated at the body unit 102. To illustrate, when the first resistive memory element 106 is an MTJ, the programming voltage can cause the tunneling oxide of the first resistive memory element 106 to break down, thereby generating a permanent low resistance of the first resistive memory element 106 state. Similarly, when the second resistive memory element 108 is MTJ, the programming voltage can cause the tunneling oxide of the second resistive memory element 108 to break down, resulting in a permanent low resistance of the second resistive memory element 108 state. In a specific embodiment, the tunneling oxide can be a magnesium oxide barrier layer in the MTJ and the programming voltage can be greater than about 1.3 volts.

When the tunnel oxide of one of the resistive memory elements is broken down, a permanent low resistance state is produced. For example, once blown (for example, once the tunnel oxide is blown), the resistance of the blown resistive memory element can be about 250 ohms. The natural unfused state of the resistive memory device can be a relatively high resistance, such as 2500 ohms. For example, as described in Table 110, if the first resistive memory element 106 is blown and the second resistive memory element 108 is not blown, the data stored at the memory cell 102 may represent a logic "1" state. Alternatively, if the first resistive memory element 106 is not blown and the second resistive memory element 108 is blown, the data stored in the memory cell 102 may indicate a logic "0" state.

In a specific embodiment, before programming an irreversible state to the memory cell 102, a write voltage (instead of a programming voltage) can be applied to the first resistive memory element 106 or the second resistive memory element. 108 stores a reversible value in the memory unit 102 and uses the memory unit 102 as a multi-time programmable (MTP) unit. An example of an MTP unit is further described with respect to FIG. 4. Using the memory cell 102 as a one-time programmable (OTP) cell or an MTP cell enables the reading of the first resistive memory element 106 or the second resistive memory element 108 after applying a write voltage to the first resistive memory element 106 or the second resistive memory element 108 Each of the resistive memory element 106 and the second resistive memory element 108 is used to test the operation of the memory cell 102.

In a specific embodiment, when the memory cell 102 is configured as an OTP memory cell, the value read at the first resistive memory element 106 can be compared with the value read at the second resistive memory element 108 It can sense the irreversible state without the need of a separate reference unit. For example, in order to sense the reversible write state of the MTJ, a reference voltage can be applied. When the memory cell 102 is configured as an OTP memory cell, the sensing is self-referenced sensing, because the complementary cell value is maintained at the first resistive memory element 106 and the second resistive memory element 108. This makes it possible to sense the irreversible state by comparing the value read at the first resistive memory element 106 with the value read at the second resistive memory element 108.

Because the memory unit 102 can be configured as an OTP memory unit or an MTP memory unit, the security architecture of the electronic device incorporating the memory unit can be enhanced. For example, after using a single final test for programmability, the hardware features of the mobile electronic device, such as the Joint Test Action Group (JTAG), can be disabled. In addition, the original equipment manufacturer's hardware key can be used with one-time programmability to provide user information, digital copyright management, and so on. In addition, compared with polysilicon-based fuse systems, electronic devices incorporating the memory unit 102 may be less susceptible to tampering (due to anti-processing) and less susceptible to data manipulation.

Referring to FIG. 2, a specific illustrative embodiment of a memory device is depicted and generally designated as 200. The memory device includes an irreversible state programming circuit and a single-time programming based on a magnetic tunnel junction (MTJ) A memory array of memory cells. The memory device 200 includes an irreversible programming circuit 202, a test circuit 204, and a memory array 206 having an OTP unit. The memory array 206 may include other memory cells that are non-OTP memory cells, such as other MTJ memory cells. The same technology can be used to manufacture OTP memory cells and other MTJ memory cells. The memory array 206 includes a representative first single-time programmable unit 208 and a representative second single-time programmable unit 210. In a specific embodiment, the first single-shot programmable unit 208 includes a first dual magnetic tunnel junction (MTJ) bit cell and the second single-shot programmable unit 210 includes a second dual MTJ bit unit cell. The first single-time programmable unit 208 includes a first resistive memory element 212, a first access transistor 213, a second resistive memory element 214, and a second access transistor 215. The second single-time programmable unit 210 includes a third resistive memory element 216, a third access transistor 217, a fourth resistive memory element 218, and a fourth access transistor 219. In a particular embodiment, each of the resistive memory elements 212 to 218 includes a magnetic tunnel junction element. The word line 220 is coupled to the first access transistor 213, to the second access transistor 215, to the third access transistor 217, and to the fourth access transistor 219.

The irreversible programming circuit 202 is coupled to the first single-shot programmable unit 208 via the bit line 230 and the bit line 232, and is coupled to the second single-shot programmable unit via the bit line 240 and the bit line 242 210. The irreversible programming circuit 202 is configured to apply the programming voltage to the first resistive memory element 212 of the first single-shot programmable unit 208 via the bit line 230 without applying the programming voltage to the first single-shot programmable The second resistive memory element 214 of the cell 208 generates a first irreversible state (for example, logic "0") at the first single-shot programmable cell 208. Alternatively, the irreversible programming circuit 202 can apply the programming voltage to the second resistive memory element 214 of the first single-shot programmable unit 208 via the bit line 232 without applying the programming voltage to the first single-shot programmable unit 208 The first resistive memory element 212 of 208 generates a second irreversible state (for example, logic "1") at the first single-shot programmable unit 208.

Similarly, the irreversible programming circuit 202 is configured to apply the programming voltage to the third resistive memory element 216 of the second single-shot programmable unit 210 via the bit line 240 without applying the programming voltage to the second single-shot The fourth resistive memory element 218 of the programmable unit 210 generates the first irreversible state at the second single-shot programmable unit 210. Alternatively, the irreversible programming circuit 202 can apply the programming voltage to the fourth resistive memory element 218 of the second single-shot programmable unit 210 via the bit line 242 without applying the programming voltage to the second single-shot programmable unit 210 The third resistive memory element 216 of 210 generates a second irreversible state at the second single-shot programmable unit 210.

In a specific embodiment, the value read at the first resistive memory element 212 can be compared with the value read at the second resistive memory element 214 in the first single-shot programmable unit 208 The irreversible state is sensed everywhere. In a specific embodiment, the irreversible state of the first single-shot programmable unit can be sensed without requiring a separate reference unit.

For example, the sensing of the first single-shot programmable cell 208 is self-referenced sensing, because the complementary cell value (for example, , The tunnel oxide of one of the resistive memory elements 212, 214 is fused while the tunnel oxide of the other of the resistive memory elements 212, 214 is not fused). This can be done by comparing the value read at the first resistive memory element 212 with the value read at the second resistive memory element 214 (for example, by comparing the signal at the bit line 230 with the bit line 232) and sense the irreversible state. There is no need for a separate reference voltage to sense the reversible state of the resistive memory elements 212 and 214.

The test circuit 204 can be configured to test one or more cells of the memory array 206 before programming. For example, before applying the programming voltage to the first resistive memory element 212 of the first single-shot programmable unit 208, a write voltage may be applied to the first resistive memory element 212 to store the reversible value to the first resistive memory element 212 A single programmable unit 208. After applying the write voltage to the first resistive memory element 212, the first resistive memory element 212 can be read to test the operation of the first single-shot programmable unit 208. Alternatively, before applying the programming voltage to the second resistive memory element 214 of the first single-shot programmable cell 208, a write voltage can be applied to the second resistive memory element 214 to store the reversible value in the first single Sub-programmable unit 208. After the write voltage is applied to the second resistive memory element 214, the second resistive memory element 214 can be read to test the operation of the first single-shot programmable unit 208.

In a specific embodiment, the third resistive memory element 216 and the fourth resistive memory element 218 may be substantially similar to the first resistive memory element 212 and the second resistive memory element 214. In a specific embodiment, the resistive memory elements 216 and 218 can be used as multiple programmable memory elements by providing a write voltage, where the write voltage is lower than the program voltage (for example, with low At the magnitude of the program voltage), the write voltage causes the resistive memory element 216 or 218 to enter a reversible state.

The single-shot programmability obtained by using MTJ elements in the bit cell of the memory array can be attributed to the smaller current and shorter time required for the programmed MTJ element (compared to the programmed polysilicon fuse element) The higher current required and the longer time are compared) to achieve high-speed programming.

3, a specific illustrative embodiment of the system 300 includes a one-bit cell 302 with a first resistive memory element 310 and a second resistive memory element 314 and also includes a one-bit cell 302 configured to provide programming The voltage to the irreversible state programming circuit 304 of the bit cell 302.

The programming circuit 304 includes a read row selection circuit 320, a sense amplifier circuit 322, a word line generation circuit 324, a write data path circuit 326, a write data circuit 328, a write row selection circuit 330, and a pair of bit lines 332 . The read row selection circuit 320 is configured to receive address data 340 and read data 342, and is configured to provide input to the sense amplifier circuit 322. The sense amplifier circuit 322 is configured to amplify the differential signal at the pair of bit lines 332 and generate a data output signal (Do). The write data circuit 328 is configured to latch the received data input (Di) 362 and write signal 360. The write row selection circuit 330 is configured to latch the received address data 340. The write data path circuit 326 responds to the write data circuit 328 and the write row selection circuit 330 to apply a signal to the pair of bit lines 332. The word line generating circuit 324 is configured to selectively bias the word line 334 in response to the address data 340, the read signal 350, and the write signal 360.

The bit cell 302 includes a first resistive memory element 310 and a second resistive memory element 314. In a specific embodiment, the first resistive memory element 310 includes a first magnetic tunnel junction (MTJ), and the second resistive memory element includes a second MTJ. The bit cell 302 includes a first access transistor 312 coupled to the first MTJ 310 and a second access transistor 316 coupled to the second MTJ 314. In a particular embodiment, the first access transistor 312 may have a tunnel oxide having an oxide thickness T1 311, and the second access transistor 316 may have a tunnel oxide having an oxide thickness T2 315 Things. The oxide thickness T1 311 may be substantially similar to the oxide thickness T2 315. The first access transistor 312 and the second access transistor 316 respond to the word line 334.

During operation, the irreversible state programming circuit 304 can apply a programming voltage to the first MTJ 310 of the bit cell 302 without applying a programming voltage to the second MTJ 314 of the bit cell 302, so as to be at the bit cell 302 Produce an irreversible state. Alternatively, the irreversible state programming circuit 304 may apply a program voltage to the second MTJ 314 of the bit cell 302 without applying a program voltage to the first MTJ 310 of the bit cell 302, so as to generate an irreversibility at the bit cell 302 state.

For example, in a specific embodiment, the program voltage can cause the tunneling oxide of the first MTJ 310 to break down, thereby generating the permanent low resistance state of the first MTJ 310. In a specific embodiment, the tunneling oxide may be a magnesium oxide barrier layer and the programming voltage may be greater than about 1.3 volts. After the tunneling oxide of the first MTJ 310 is broken down, the permanent short or low resistance state of the first MTJ 310 is generated. For example, once it is blown, the resistance of the blown first MTJ 310 can be about 250 ohms. The natural unfused state of the second MTJ 314 may be a relatively high resistance, such as 2500 ohms. In a particular embodiment, the state of the first MTJ 310 (for example, blown) can be maintained to be complementary to the state of the second MTJ 314 (for example, not blown). The sensing of the bit cell 302 is self-referenced sensing, because it can compare the value read at the first MTJ 310 with the value read at the second MTJ 314 without a separate reference voltage. Value (for example, by comparing the signal at the pair of bit lines 332) to sense the irreversible state.

Referring to FIG. 4, a specific illustrative embodiment of the shape of a single programmable magnetic tunnel junction (MTJ) bit cell is depicted and designated generally as 400. The first MTJ has a generally elliptical shape 402, the second MTJ has a generally circular shape 404, and the third MTJ has a generally circular shape 406 smaller than the second MTJ. The arrows illustrate examples of the magnetic moment of the free layer of each of MTJs 402 to 406 as an illustrative non-limiting example.

When the MTJ 402 is not fused, the MTJ 402 with an oval shape has a bistable state. When in a bistable state, the MTJ 402 may have a low resistance R Low (for example, about 2500 ohms) or a high resistance R High (for example, greater than 3000 ohms). In the blown state, the MTJ 402 may have a resistance at the blown resistance R Blown (for example, about 250 ohms). In a specific embodiment, the ellipse MTJ 402 has a first axis length 403 greater than the second axis length 405 so that the magnetic moments in the MTJ 402 can be aligned in the parallel and anti-parallel states. The parallel and anti-parallel states correspond to A first reversible multiple programmable (MTP) state and a second reversible MTP state.

In a specific embodiment, when the second MTJ 404 is not fused, the second MTJ 404 having a circular shape is in a monostable state. For example, in the unfused state, the second MTJ 404 may have a high resistance R High (for example, greater than 3000 ohms) of the second MTJ 404 and a low resistance R Low (for example, 2500 ohms) of the second MTJ 404. Between half of the resistance. In the blown state, the second MTJ 404 may have a resistance at the blown resistance R Blown (for example, about 250 ohms).

In a specific embodiment, the third MTJ 406 having a circular shape has a diameter smaller than the diameter of the circular MTJ 404, so that when the third MTJ 406 is not fused, the third MTJ 406 is in a metastable state. For example, in the unfused state, the third MTJ 406 may have a high resistance R High (for example, greater than 3000 ohms) of the third MTJ 406 and a low resistance R Low (for example, 2500 ohms) of the third MTJ 406. The resistance at a certain point in between. In the blown state, the third MTJ 406 may have a resistance at the blown resistance R Blown (for example, about 250 ohms).

Referring to FIG. 5, a flowchart of an illustrative embodiment of a method for programming an irreversible state to a one-bit unit cell having a first magnetic tunnel junction (MTJ) and a second MTJ is depicted and generally specified Is 500. As an illustrative example, the method 500 may be performed by the memory device of FIG. 1, the memory device of FIG. 2, the system of FIG. 3, or any combination thereof.

At 502, before applying the program voltage to the bit cell, a write voltage may be applied to the first MTJ to store the reversible value to the bit cell, and at 504, after the write voltage is applied to the first MTJ , The first MTJ can be read to test the operation of the bit cell. In a specific embodiment, the bit cell may be the memory cell 102 of FIG. 1, the first single programmable cell 208 of FIG. 2, or the bit cell 302 of FIG. In a specific embodiment, the first MTJ may be the first resistive memory element 106 of FIG. 1, the first resistive memory element 212 of FIG. 2, or the first resistive memory element 310 of FIG. The two MTJs can be the second resistive memory element 108 in FIG. 1, the second resistive memory element 214 in FIG. 2, or the second resistive memory element 314 in FIG. 3.

For example, the test circuit 204 may be configured to test one or more cells of the memory array 206 before programming any of the cells of the memory array 206. For example, before applying the program voltage, a write voltage may be applied to the first resistive memory element 212 to store the reversible value in the first single-shot programmable unit 208. After the write voltage is applied to the first resistive memory element 212, the first resistive memory element 212 can be read to test the operation of the first single-shot programmable unit 208. Alternatively, a write voltage can be applied to the second resistive memory element 214 to store the reversible value in the first single-shot programmable unit 208. After applying the write voltage to the second resistive memory element 214, the second resistive memory element 214 can be read to test the operation of the first single-shot programmable unit 208.

At 506, an irreversible state can be generated at the bit cell by applying the program voltage to the first MTJ of the bit cell without applying the program voltage to the second MTJ of the bit cell. In a specific embodiment, the program voltage can be generated by the irreversible state programming circuit 104 of FIG. 1, the irreversible state programming circuit 202 of FIG. 2, or the irreversible state programming circuit 304 of FIG.

At 508, the first MTJ and the second MTJ can be maintained as complementary cell values. For example, in a specific embodiment, the program voltage can cause the tunneling oxide (such as the tunneling oxide having a thickness of T1 311 of the first MTJ 310) to break down, thereby generating the permanent low resistance state of the first MTJ 310 . After the tunneling oxide of the first MTJ 310 is broken down, the permanent short or low resistance state of the first MTJ 310 is generated. For example, once it is blown, the resistance of the blown first MTJ 310 can be about 250 ohms. The natural unfused state of the second MTJ 314 may be a relatively high resistance, such as 2500 ohms. Therefore, the cell value (for example, blown) of the first MTJ 310 can be maintained to be complementary to the cell value (for example, not blown) of the second MTJ 314.

At 510, the irreversible state can be sensed by comparing the value read at the first MTJ with the value read at the second MTJ of the bit cell. For example, the sense amplifier circuit 322 may be configured to generate the output Do in response to comparing the signal (eg, current or voltage) read at the first MTJ 310 with the signal read at the second MTJ 314.

6 is a block diagram of an embodiment of a wireless communication device 600, the wireless communication device 600 has an irreversible state programming circuit and includes a first tunnel junction (MTJ) and a second MTJ one-bit unit cell 664 . The wireless communication device 600 may be implemented as a portable electronic device that includes a processor 610 (such as a digital signal processor (DSP)) coupled to a memory 632.

The irreversible state programming circuit and the bit cell 664 including the first MTJ and the second MTJ may include one or more of the components, memories, or circuits of FIGS. 1 to 4, or any combination thereof, operating according to FIG. 5 . The irreversible state programming circuit and the bit cell 664 including the first MTJ and the second MTJ may be in the memory 632 or may be separate devices. Although the irreversible state programming circuit and the bit cell 664 including the first MTJ and the second MTJ are described as being integrated with the memory 632, in other embodiments, the irreversible state programming circuit and including the first MTJ and the second MTJ The bit cell 664 of the MTJ may be external to the memory 632, such as embedded in the processor 610.

In a specific embodiment, the display controller 626 is coupled to the processor 610 and the display device 628. An encoder/decoder (CODEC) 634 may also be coupled to the processor 610. The speaker 636 and the microphone can be coupled to the CODEC 634. The wireless controller 640 can be coupled to the processor 610 and the wireless antenna 642.

The memory 632 may include a computer-readable medium that stores instructions (eg, software 635) that can be executed by a processor such as the processor 610. For example, the software 635 may include instructions that can be executed by a computer to perform the following operations: apply a program voltage to the first MTJ (e.g., the first resistor of FIG. 1) of the bit cell (e.g., the memory cell 102 of FIG. 1) The memory element 106) does not apply a program voltage to the second MTJ of the bit cell (for example, the second resistive memory element 108 of FIG. 1) to generate an irreversible state at the bit cell.

In a specific embodiment, the signal processor 610, the display controller 626, the memory 632, the CODEC 634, and the wireless controller 640 are included in a system-in-package or a system-on-chip device 622. In a specific embodiment, the input device 630 and the power supply 644 are coupled to the on-chip system device 622. In addition, in a specific embodiment, as illustrated in FIG. 6, the display device 628, the input device 630, the speaker 636, the microphone 638, the wireless antenna 642, and the power supply 644 are external to the on-chip system device 622. However, each of the display device 628, the input device 630, the speaker 636, the microphone 638, the wireless antenna 642, and the power supply 644 may be coupled to a component of the on-chip system device 622 (such as an interface or a controller).

The devices and functions disclosed above can be designed and configured into computer files (for example, RTL, GDSII, GERBER, etc.) stored on a computer-readable medium. Some or all of these files can be provided to the manufacturing handler who manufactures devices based on these files. The resulting products include semiconductor wafers, which are then cut into semiconductor dies and packaged in semiconductor wafers. These wafers are then used in the devices described above.

FIG. 7 depicts a specific illustrative embodiment of an electronic device manufacturing process 700. The physical device information 702 is received at the manufacturing process 700 (such as at the research computer 706). The physical device information 702 may include design information representing at least one physical property of a semiconductor device (such as the memory device 100 of FIG. 1, the memory device 200 of FIG. 2, the system 300 of FIG. 3, or any combination thereof). For example, the physical device information 702 may include physical parameters, material properties, and structural information entered through the user interface 704 coupled to the research computer 706. The research computer 706 includes a processor 708 (such as one or more processor cores) coupled to a computer-readable medium (such as a memory 710). The memory 710 can store computer-readable instructions, which are executable to enable the processor 708 to convert the physical device information 702 to conform to the file cell format and generate a library file 712.

In a specific embodiment, the library file 712 includes at least one data file, and the at least one data file includes the converted design information. For example, the library file 712 may include a library of semiconductor devices. The semiconductor device includes: a device including the memory device 100 of FIG. 1; a device including the memory device 200 of FIG. 2; and includes the system 300 of FIG. 3 Or any combination thereof, the library is provided for use with the electronic design automation (EDA) tool 720.

The library file 712 can be used in combination with the EDA tool 720 at the design computer 714. The design computer 714 includes a processor 716 (such as one or more processing cores) coupled to the memory 718. The EDA tool 720 can be stored in the memory 718 as a processor executable instruction, so that the user of the design computer 714 can design a circuit, the circuit includes a device of the library file 712, and the device includes the memory of FIG. 1 A device of the bulk device 100; a device including the memory device 200 of FIG. 2; a device including the system 300 of FIG. 3; or any combination thereof. For example, the user of the design computer 714 can enter the circuit design information 722 through the user interface 724 coupled to the design computer 714. The circuit design information 722 may include a semiconductor device (such as a device including the memory device 100 of FIG. 1, a device including the memory device 200 of FIG. 2, a device including the system 300 of FIG. 3, or any combination thereof ) At least one physical design information. To illustrate, the nature of the circuit design may include: identification of a specific circuit and its relationship with other components in the circuit design, positioning information, feature size information, interconnection information, or other information indicating the physical nature of the semiconductor device.

The design computer 714 can be configured to convert design information (including circuit design information 722) to comply with the file cell format. For illustration, the file format may include a database binary file cell format (such as a graphics data system (GDSII) file cell format) that expresses planar geometric shapes, text labels, and other information about circuit layout in a hierarchical cell format. . The design computer 714 can be configured to generate data files that include converted design information, such as information that includes describing the memory device 100 of FIG. 1, the memory device 200 of FIG. 2, the system 300 of FIG. 3, or any combination thereof, and others GDSII file 726 of circuits or information. To illustrate, the data file may include information corresponding to an on-chip system (SOC). The SOC includes the memory device 100 of FIG. 1 and also includes additional electronic circuits and components in the SOC.

The GDSII file 726 can be received at the manufacturing process 728 to manufacture the memory device 100 of FIG. 1, the memory device 200 of FIG. 2, the system 300 of FIG. 3, or any combination thereof based on the converted information in the GDSII file 726 . For example, the device manufacturing process may include providing the GDSII file 726 to the mask manufacturer 730 to generate one or more masks (such as masks for photolithography processing), the one or more masks being illustrated as Representative mask 732. The mask 732 may be used during the manufacturing process to produce one or more wafers 734, which may be tested and divided into dies, such as representative dies 736. The die 736 includes a circuit including: a device including the memory device 100 of FIG. 1; a device including the memory device 200 of FIG. 2; a device including the system 300 of FIG. 3; or any combination thereof .

The die 736 may be provided to the packaging process 738 in which the die 736 is incorporated in the representative package 740. For example, the package 740 may include a single die 736 or multiple dies, such as a system in package (SiP) configuration. The package 740 may be configured to comply with one or more standards or specifications, such as the Joint Electron Device Engineering Council (JEDEC) standard.

Information about the package 740 (such as via a component library stored at the computer 746) can be distributed to various product designers. The computer 746 may include a processor 748 (such as one or more processing cores) coupled to the memory 750. A printed circuit board (PCB) tool can be stored in the memory 750 as processor executable instructions to process the PCB design information 742 received from the user of the computer 746 via the user interface 744. The PCB design information 742 may include the physical positioning information of the packaged semiconductor device on the circuit board. The packaged semiconductor device corresponds to the memory device 100 in FIG. 1, the memory device 200 in FIG. 2, the system 300 in FIG. Any combination of packages 740.

The computer 746 can be configured to convert the PCB design information 742 to generate a data file, such as a GERBER file 752, which has physical positioning information including the packaged semiconductor devices on the circuit board and electrical connections (such as traces and vias) For the layout information, the packaged semiconductor device corresponds to a package 740 including the memory device 100 of FIG. 1, the memory device 200 of FIG. 2, the system 300 of FIG. 3, or any combination thereof. In other embodiments, the data file generated by the converted PCB design information may have a cell type different from the GERBER cell type.

The GERBER file 752 can be received at the board assembly process 754 and used to generate a PCB manufactured based on the design information stored in the GERBER file 752, such as a representative PCB 756. For example, the GERBER file 752 can be uploaded to one or more machines to execute each step of the PCB production process. The PCB 756 may be filled with electronic components including the package 740 to form a representative printed circuit assembly (PCA) 758.

The PCA 758 may be received at the product manufacturing process 760 and integrated into one or more electronic devices (such as the first representative electronic device 762 and the second representative electronic device 764). As an illustrative non-limiting example, the first representative electronic device 762, the second representative electronic device 764, or both may be selected from a set-top box, a music player, a video player, an entertainment unit, a navigation device, a communication device , Personal Digital Assistant (PDA), fixed position data unit and computer group, the irreversible state programming circuit of Fig. 6 and the bit cell 664 including the first MTJ and the second MTJ are integrated into the device. As another illustrative non-limiting example, one or more of the electronic devices 762 and 764 may be remote units, such as mobile phones, palm-sized personal communication system (PCS) units, portable data units (such as personal Data assistant), GPS-enabled devices, navigation devices, fixed location data units (such as meter reading devices), or any other device that stores or retrieves data or computer commands, or any combination thereof. Although FIG. 7 illustrates a remote unit according to the teachings of the present invention, the present invention is not limited to these illustrative illustrative units. The embodiments of the present invention can be suitably used in any device including active integrated circuits (including memory and on-chip circuits).

As described in the illustrative procedure 700, the device including the memory device 100 of FIG. 1, the device including the memory device 200 of FIG. 2, the device including the system 300 of FIG. 3, or any combination thereof may be manufactured, processed, and Incorporated into electronic devices. One or more aspects of the embodiments disclosed in FIGS. 1 to 4 can be included in each processing stage (such as included in the library file 712, GDSII file 726, and GERBER file 752), and stored in the research computer The memory 710 of 706, the memory 718 of the design computer 714, the memory 750 of the computer 746, one or more other computers or processors (not shown) used in each stage (such as in the board assembly process 754) (Shown), and also incorporated into one or more other physical embodiments (such as mask 732, die 736, package 740, PCA 758, other products such as prototype circuits or devices (not shown) , Or any combination thereof). Although various representative production stages are depicted from the physical device design to the final product, in other embodiments, fewer stages may be used or additional stages may be included. Similarly, the process 700 can be executed by a single entity or by one or more entities that execute each stage of the process 700.

Those familiar with this technology should further understand that the various illustrative logic blocks, configurations, modules, circuits, and algorithm steps described in the embodiments disclosed herein can be implemented as electronic hardware and executed by a processor. Computer software, or a combination of the two. Various illustrative components, blocks, configurations, modules, circuits, and steps have generally been described above in terms of functionality. The implementation of this functionality as hardware or processor-executable instructions depends on the specific application and design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in varying ways for each specific application, but these implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The steps of the method or algorithm described in conjunction with the embodiments disclosed herein can be directly embodied in hardware, in a software module executed by a processor, or a combination of the two. The software module can reside in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory ( EPROM), electrically erasable programmable read-only memory (EEPROM), scratchpad, hard disk, removable disk, compact disc read-only memory (CD-ROM), or any known in this technology Other forms of non-temporary storage media. The exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. In the alternative, the storage medium may be integrated into the processor. The processor and storage medium can reside in an application-specific integrated circuit (ASIC). The ASIC can reside in a computing device or a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a computing device or a user terminal.

The foregoing description of the disclosed embodiments is provided to enable those familiar with the art to make or use the disclosed embodiments. Without departing from the scope of the present invention, various modifications to these embodiments will be readily apparent to those skilled in the art, and the principles defined herein can be applied to other embodiments. Therefore, the present invention is not intended to be limited to the embodiments shown in this text, but should conform to the widest scope that may be consistent with the principles and novel features defined in the scope of the following patent applications.

<p>100. . . Memory device</p><p>102. . . Representative memory unit</p><p>104. . . Irreversible programming circuit</p><p>106. . . First resistive memory element</p><p>108. . . Second resistive memory element</p><p>110. . . surface</p><p>200. . . Memory device</p><p>202. . . Irreversible programming circuit</p><p>204. . . Test circuit</p><p>206. . . Memory array</p><p>208. . . Representative first single programmable unit</p><p>210. . . Representative second single programmable unit</p><p>212. . . First resistive memory element</p><p>213. . . First access transistor</p><p>214. . . Second resistive memory element</p><p>215. . . Second access transistor</p><p>216. . . Third resistive memory element</p><p>217. . . Third access transistor</p><p>218. . . Fourth resistive memory element</p><p>219. . . Fourth access transistor</p><p>220. . . Word line</p><p>230. . . Bit line</p><p>232. . . Bit line</p><p>240. . . Bit line</p><p>242. . . Bit line</p><p>300. . . system</p><p>302. . . Bit cell</p><p>304. . . Irreversible programming circuit</p><p>310. . . The first resistive memory element/the first MTJ</p><p>311. . . Oxide thickness T1</p><p>312. . . First access transistor</p><p>314. . . Second resistive memory element/Second MTJ</p><p>315. . . Oxide thickness T2</p><p>316. . . Second access transistor</p><p>320. . . Read line selection circuit</p><p>322. . . Sense amplifier circuit</p><p>324. . . Word line generation circuit</p><p>326. . . Write data path circuit</p><p>328. . . Write data circuit</p><p>330. . . Write row selection circuit</p><p>332. . . Bit line</p><p>334. . . Word line</p><p>340. . . Address data</p><p>342. . . Read data</p><p>350. . . Read signal</p><p>352. . . Write signal</p><p>360. . . Write signal</p><p>362. . . Data input received (Di)</p><p>400. . . Single programmable magnetic tunnel junction (MTJ) bit cell shape</p><p>402. . . Oval shape/MTJ</p><p>403. . . Length of first axis</p><p>404. . . Round shape/MTJ</p><p>405. . . Second axis length</p><p>406. . . Round shape/MTJ</p><p>600. . . Wireless communication device</p><p>610. . . Processor/Digital Signal Processor (DSP)</p><p>622. . . On-chip system devices</p><p>626. . . Display controller</p><p>628. . . Display device</p><p>630. . . Input device</p><p>632. . . Memory</p><p>634. . . Encoder/decoder (CODEC)</p><p>635. . . software</p><p>636. . . speaker</p><p>638. . . microphone</p><p>640. . . Wireless Controller</p><p>642. . . Wireless antenna</p><p>644. . . Power Supplier</p><p>664. . . Irreversible state programming circuit and bit cell including first MTJ and second MTJ</p><p>700. . . Electronic device manufacturing process</p><p>702. . . Physical device information</p><p>704. . . user interface</p><p>706. . . Research computer</p><p>708. . . processor</p><p>710. . . Memory</p><p>712. . . Library file</p><p>714. . . Design computer</p><p>716. . . processor</p><p>718. . . Memory</p><p>720. . . Electronic Design Automation (EDA) Tool</p><p>722. . . Circuit Design Information</p><p>724. . . user interface</p><p>726. . . GDSII file</p><p>728. . . Manufacturing process</p><p>730. . . Mask maker</p><p>732. . . Mask</p><p>734. . . Wafer</p><p>736. . . Grain</p><p>738. . . Wrapper</p><p>740. . . Encapsulation</p><p>742. . . PCB design information</p><p>744. . . user interface</p><p>746. . . computer</p><p>748. . . processor</p><p>750. . . Memory</p><p>752. . . GERBER file</p><p>754. . . Board assembly procedure</p><p>756. . . Representative printed circuit board (PCB)</p><p>758. . . Representative printed circuit assembly (PCA)</p><p>760. . . Product manufacturing process</p><p>762. . . The first representative electronic device</p><p>764. . . Second representative electronic device</p>

1 is a block diagram of a specific illustrative embodiment of a memory device including an irreversible state programming circuit and a memory including a first resistive memory element and a second resistive memory element unit;

2 is a diagram of a specific illustrative embodiment of a memory device including an irreversible state programming circuit and a memory with a single-time programmable memory cell based on a magnetic tunnel junction (MTJ) Array

3 is a diagram of a specific illustrative embodiment of a system including a bit cell having a first MTJ and a second MTJ and configured to provide a programmed voltage to the bit cell Irreversible programming circuit;

Figure 4 is a diagrammatic representation of a specific illustrative embodiment of MTJ shapes and the attributes of each MTJ shape;

5 is a flowchart of a specific illustrative embodiment of a method of programming an irreversible state to a one-bit unit cell having a first MTJ and a second MTJ;

6 is a block diagram of a specific illustrative embodiment of a device including an irreversible state programming circuit configured to provide a programming voltage to one of the first MTJ and the second MTJ of the bit cell ;and

FIG. 7 is a diagram of a specific illustrative embodiment of a manufacturing process that can be used to produce a wireless device that includes a one-bit crystal configured to program an irreversible state for a first MTJ and a second MTJ Cells irreversible state programming circuit.