Cross-point memory utilizing Ru/Si diode

Cross-point memory using ruthenium/silicon diode

The present invention relates generally to semiconductor memory, and in particular, in one or more embodiments, the present invention relates to a cross-point memory using a diode containing ruthenium and silicon.

Generally, memory devices are provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including (for example) random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory ( SDRAM) and flash memory.

Generally speaking, the cross-point memory system appears at one of the intersections of two conductive lines (for example, an access line (usually called a word line) and a data line (usually called a bit line)). A resistance element is defined. FIG. 1 is a schematic diagram of a part of a basic cross-point memory array 100 having a memory cell 102 appearing at the intersection of an access line 138 (for example, a word line) and a data line 126 (for example, a bit line) .

Each memory cell 102 in the array 100 includes a resistive element 104 coupled between an access line 138 and a data line 126. Generally speaking, the difference in the resistivity of the resistance element 104 defines the data value of each memory cell 102. For example, a memory cell 102 with a resistive element 104 with a relatively high resistivity can define a data value such as a logic 0, and a memory cell 102 with a resistive element 104 with a relatively low resistivity can define a data value A different data value such as a logic 1 can be defined. By applying a potential difference across a specific group of an access line 138 and a data line 126, a resultant current between the two lines can be sensed to determine whether the memory cell 102 appearing at the intersection has a relatively high value. High or relatively low resistance. Several different resistivity values can be used to define more than two data states.

Cross-point memory is usually very space efficient, providing high memory density. However, in larger arrays, leakage through unselected or partially selected memory cells can become a problem. Due to the above-mentioned reasons, and due to the following other reasons that will become apparent to those skilled in the art after reading and understanding this specification, an alternative cross-point memory array architecture is required in this technology.

Various embodiments include a memory cell having a resistive element coupled in series with a diode between two conductors (eg, an access line and a data line). These diodes contain ruthenium and silicon.

In the following detailed description, reference is made to the drawings that form a part of this description, and specific embodiments are shown diagrammatically in these drawings. In the drawings, substantially similar components are described with the same numbers throughout the several views. Other embodiments can be used, and structural, logical, and electrical changes can be made without departing from the scope of the present invention. For example, the term semiconductor can refer to a material layer, a wafer or a substrate and includes any base semiconductor structure. "Semiconductor" should be understood to include silicon on sapphire (SOS) technology, silicon on insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, and silicon supported by a base semiconductor structure. The epitaxial layer, and other semiconductor structures known to those familiar with the technology. In addition, when referring to one of the semiconductors in the following description, the previous processing steps can be used to form regions/junctions in the base semiconductor structure. Therefore, the following detailed description should not be regarded as limiting.

FIG. 2 is a top view of a portion of a memory array 200 according to an embodiment, so as to provide a frame of reference for the discussion of FIGS. 3A to 9B. The memory array 200 includes memory cells 202 formed at intersections of a plurality of first conductors (for example, data lines) 226 and a plurality of second conductors (for example, access lines) 238. Generally speaking, the access lines 238 and the data lines 226 are formed in a cross pattern, but do not need to be formed orthogonal as shown in FIG. 2. Generally speaking, whether a conductor of the memory array 200 is an access line 238 or a data line 226 depends on whether the conductor is used to select (e.g., activate) a memory cell 202 or to sense (e.g., read) ) Select a data value of the memory cell 202.

3A to 3H show cross-sectional views of a portion of the memory array 200 taken along the line of sight AAof FIG. 2 during various manufacturing stages according to an embodiment. 4A to 4H show cross-sectional views of a portion of the memory array 200 taken along the line of sight BBof FIG. 2 during various manufacturing stages according to an embodiment. The cross-sectional views of FIGS. 3A to 3H correspond to the cross-sectional views of FIGS. 4A to 4H so that FIGS. 3A and 4A are taken at the same manufacturing stage, and FIGS. 3B and 4B are taken at the same manufacturing stage, and so on.

3A and 4A show a portion of a memory array after several processing steps may have taken place. Generally speaking, FIGS. 3A and 4A can show that a support 220 of the memory array 200 will be formed thereon. As an example, the support 220 may be a dielectric material. Exemplary dielectric materials include silicon oxide (SiO/SiO₂), silicon nitride (SiN/Si₂N/Si₃N₄) Or silicon oxynitride (SiOxNy) materials. Further exemplary dielectric materials include doped silicon oxide materials, such as a borophosphosilicate glass (BPSG), that is, a silicon dioxide material doped with boron and phosphorus. Other dielectric materials are known and used in the technology of semiconductor manufacturing. Generally speaking, the support 220 should be selected to generally suppress the current between future data lines formed thereon, and this can also be accomplished by forming an isolation area in the support 220 between adjacent data lines.

3A and 4A further illustrate a patterned dielectric 222a. The patterned dielectric 222a is generally a dielectric material. Although the patterned dielectric 222a can be the same dielectric material as the support 220, choosing a different dielectric material allows selective removal. For example, the patterned dielectric 222a can be formed by forming a dielectric material on the support 220, and then by patterning the dielectric material to form a trench 224 for the formation of future access lines. As shown in FIGS. 3A and 4A, the trench 224 may be formed to expose part of the support 220, or the trench 224 may be terminated before the part of the support 220 is exposed. By choosing different dielectric materials for the support 220 and the patterned dielectric 222a, the support 220 can serve as a stop layer by using a removal process that is selective to the patterned dielectric 222a. For example, in order to form the trench 224 that terminates before exposing the portion of the support 220, a timed removal process can be used.

In FIGS. 3B and 4B, the first conductor 226 is formed. Generally speaking, the first conductor 226 is formed to contain one or more conductive materials, such as metals, metal alloys, conductive metal nitrides, other conductive materials, or some combination thereof. For example, forming the first conductor 226 may include forming a barrier (not shown in FIG. 3B or 4B) on the bottom and sidewalls of the trench 224, and then filling the trench 224 with a metal. For one embodiment, the barrier may include forming a first metal or metal nitride to cover the bottom and sidewalls of a trench 224, and then forming a second metal to fill the trench 224 (for example, see the formation of FIGS. 9A and 9B The barrier 225 of the first conductor 226 and the conductive material 227). In particular, for certain embodiments, the barrier may include tungsten, titanium nitride, or tantalum (but only as a few examples). Generally speaking, the barrier will depend on the conductive material filling the trench 224, that is, what type of impurities or other diffused components the barrier will be intended to reduce. Examples of conductive materials may include copper, aluminum, tungsten, gold, and/or alloys thereof. In some embodiments, a seed layer (not shown) may be used to facilitate the process of filling the trench 224. Suitable techniques for forming the first conductor 226 may include, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and electroless plating. For some embodiments, the trench 224 is filled beyond an upper surface of the patterned dielectric 222a, such as a blanket deposition process that forms a conductive material over all exposed surfaces. In this case, a chemical-mechanical planarization (CMP) process may be performed to remove the portion of the conductive material extending on the upper surface of the patterned dielectric 222a.

In FIGS. 3C and 4C, a part of the first conductor 226 is removed. For example, an upper surface of the first conductor is recessed below an upper surface of the patterned dielectric 222a. An isotropic or anisotropic removal process can be used for a specific time desired to recess the first conductor 226 by a specific amount. For example, a wet etching process can be used with an etchant that is selective to the material of the first conductor 226 over the patterned dielectric 222a. For one embodiment, the first conductor 226 is recessed to approximately 1/2 of its original height. As an alternative, the patterned dielectric 222a can be formed to the desired height of the first conductor 226, the trench 224 can be filled and any excess can be removed (such as by CMP).

In FIGS. 3D and 4D, a ruthenium material 228 is formed on the first conductor 226. For example, a material containing ruthenium (Ru) can be used to fill the portion of the trench 224 that is reopened when the portion of the first conductor 226 is removed. Suitable techniques for forming the ruthenium material 228 may include, for example, CVD, PVD, ALD, and electroless plating. For some embodiments, by using ruthenium or ruthenium silicide (Ru₂Si₃) The target is sputtered to form the ruthenium material 228.

For various embodiments, the ruthenium material 228 contains ruthenium at a level sufficient to make ruthenium one of the largest metal components of the ruthenium material 228. For certain embodiments, the ruthenium material 228 consists essentially of elemental ruthenium. For additional embodiments, the ruthenium material 228 consists essentially of ruthenium silicide. As described with respect to the first conductor 226, filling the trench 224 with the ruthenium material 228 can extend over an upper surface of the patterned dielectric 222a, and the excess material can be removed (such as by CMP) to planarize the surface.

In FIGS. 3E and 4E, a part of the ruthenium material 228 is removed. For example, an upper surface of the ruthenium material 228 is recessed below an upper surface of the patterned dielectric 222a. An isotropic or anisotropic removal process can be used for a specific time expected to sink the ruthenium material 228 by a specific amount. For example, exposure to O can be used₃Or O₂/Cl₂To selectively remove the material of the ruthenium material 228 above the patterned dielectric 222a. For one embodiment, the ruthenium material 228 is recessed to approximately 1/2 of its original height.

In FIGS. 3F and 4F, a silicon material 230 is formed on the ruthenium material 228. For example, a material containing silicon (Si) can be used to fill the part of the trench 224 that is reopened when the part of the ruthenium material 228 is removed. Suitable techniques for forming the silicon material 230 may include, for example, CVD, PVD, and ALD. For various embodiments, the silicon material 230 contains silicon at a level sufficient to make silicon one of the largest components of the silicon material 230. For some embodiments, the silicon material 230 is basically composed of monocrystalline silicon, polycrystalline silicon (ie, polycrystalline silicon), or amorphous silicon. For additional embodiments, the silicon material 230 is conductively doped. For further embodiments, the silicon material 230 has an n-type conductivity. Providing an n-type conductivity may include doping with n-type impurities such as arsenic (Ar) or phosphorus (P). This doping can occur during or after the formation of the silicon material 230. As described with respect to the first conductor 226, filling the trench 224 with the silicon material 230 can extend over an upper surface of the patterned dielectric 222a, and the excess material can be removed (such as by CMP) to planarize the surface.

In FIGS. 3G and 4G, a part of the silicon material 230 is removed. For example, an upper surface of the silicon material 230 is recessed below an upper surface of the patterned dielectric 222a. An isotropic or anisotropic removal process can be used for a specific time that is expected to dent the silicon material 230 by a specific amount. For example, a wet etching process can be used with an etchant that is selective to the material of the silicon material 230 over the patterned dielectric 222a. For one embodiment, the silicon material 230 is recessed to approximately 1/2 of its original height. The silicon material 230 and the ruthenium material 228 together with an optional ruthenium silicide interface (not shown in FIGS. 3G and 4G) formed between the ruthenium material 228 and the silicon material 230 together form a diode of a memory cell. For example, where the ruthenium material 228 is ruthenium and the silicon material 230 is polysilicon, for embodiments in which the ruthenium silicide interface is not formed after the silicon material 230 is formed, the diode may have one interface of ruthenium on the polysilicon, or two The polar body may have an interface of ruthenium silicide formed from the reaction of ruthenium and one of the polysilicon on the polysilicon. A discussion of forming an optional ruthenium silicide interface on the silicon material 230 will follow with reference to FIG. 3I.

In FIGS. 3H and 4H, the first electrode 232 may be formed on the silicon material 230. Generally speaking, the first electrode 232 is formed to contain one or more conductive materials, such as metals, metal alloys, conductive metal nitrides, other conductive materials, or some combination thereof. For example, the part of the trench 224 that is reopened when the part of the silicon material 230 is removed can be filled with one or more conductive materials of the first electrode 232. Suitable techniques for forming the ruthenium material 228 may include, for example, CVD, PVD, ALD, and electroless plating. As described with respect to the first conductor 226, filling the trench 224 with the conductive material of the first electrode 232 can extend above one of the upper surface of the patterned dielectric 222a, and this excess material can be removed (such as by CMP) to flattenChemicalThe surface.

After the first electrode 232 is formed, a material 234 having a variable resistivity is formed on the first electrode 232. The variable resistivity material 234 may include chalcogenides or other phase change materials, ferroelectric materials, magnetoresistive materials, or other materials that can change the resistivity by applying a suitable potential difference across the material. Some specific examples include NiO, Nb₂O₅, TiO₂, HfO₂, Al₂O₃, MgOx, ZrOx, CrO₂, VO, BN and AlN. Generally speaking, the aforementioned materials are regarded as materials capable of reversibly changing their resistivity. The material 234 with variable resistivity may further include a fusible material so that the resistivity can be changed from an initial value to a different value but not easily restored to its initial value. For example, the material 234 can be an anti-fuse so that it exhibits dielectric or semi-conductive properties until the application of a sufficient potential difference across the anti-fuse allows the conductive material on opposite sides of the anti-fuse to be shorted together . For embodiments such as those shown in FIGS. 3H and 4H, the variable resistivity material 234 can be formed as a continuous layer and can span one length of the first electrode 232 in one direction and across the first electrode 232 in the other direction. One length of the two electrodes 236.

After the formation of the material 234 with variable resistivity, the second electrode 236 may be formed on the material 234 with variable resistivity. The first electrode 232, the material 234 with variable resistivity, and the second electrode 236 together form the resistance elements of the memory cells. Generally speaking, the second conductor 236 is formed to contain one or more conductive materials, such as metals, metal alloys, conductive metal nitrides, other conductive materials, or some combination thereof. For example, forming the second electrode 236 may include forming a patterned dielectric 222b, filling the trench with one or more conductive materials, and recessing as explained with reference to the first conductor 226. As further described with respect to the first conductor 226, filling the trench with the conductive material of the second electrode 236 can extend over an upper surface of the patterned dielectric 222b and can remove (such as by CMP) this excess material for planarization The surface. The material selection of the patterned dielectric 222b can follow the same guidelines as those presented with respect to the patterned dielectric 222a, but the dielectric 222b and the dielectric 222a need not be the same dielectric material.

After the second electrode 236 is formed, a second conductor 238 may be formed on the second electrode 236. Generally speaking, the second conductor 238 is formed to contain one or more conductive materials, such as metals, metal alloys, conductive metal nitrides, other conductive materials, or some combination thereof. The second conductor 238 may have the same structure as the first conductor 226. For example, forming the second conductor 238 may include filling the trenches of the patterned dielectric 222 b with one or more conductive materials and removing excess material, such as described with reference to the first conductor 232.

As an alternative to the processes described with reference to FIGS. 3A to 3H and 4A to 4H, processes other than those described herein can be used to form the first conductor 226, the ruthenium material 228, the silicon material 230, The structure of the second electrode 236 and the second conductor 238. Using the first conductor 226 as an example, the depression can be avoided by the following steps: forming the patterned dielectric 222a to the desired height of the first conductor 226, filling the trench 224 with one or more conductive materials, and removing (such as by CMP) any excess material, or by forming one or more conductive materials to the desired height, patterning to define the first conductor 226, and filling the space between the first conductors 226 with a dielectric material. Other methods of forming the structure described in this article will be obvious to those familiar with semiconductor manufacturing technology.

Figure 3I shows ruthenium silicide (Ru₂Si₃) A cross-sectional view of a diode of the interface 229. The ruthenium silicide interface 229 is formed on the silicon material 230 between the silicon material 230 and the ruthenium material 228. For various embodiments, the ruthenium silicide interface 229 is a polycrystalline ruthenium silicide. The ruthenium silicide interface 229 can be formed by annealing the ruthenium material 228 and the silicon material 230 (for example, a rapid thermal annealing), thereby promoting the reaction between the ruthenium of the ruthenium material 228 and the silicon of the silicon material 230. For example, the structures of FIGS. 3G and 4G can withstand a time and temperature sufficient to form a polycrystalline ruthenium silicide interface 229, for example, a temperature between 500°C and 800°C in a nitrogen (N₂) 5 to 30 minutes in the environment.

Additional embodiments will now be explained with reference to FIGS. 5A to 5B, FIGS. 6A to 6B, FIGS. 7A to 7B, FIGS. 8A to 8B, and FIGS. 9A to 9B. In these drawings, the various manufacturing stages are omitted. However, the structure described therein can be manufactured using the processes described with reference to FIGS. 3A to 3H, 3I, and 4A to 4H. Unless otherwise specified, the guidance provided with respect to various elements in conjunction with FIGS. 3A to 3H, 3I, and 4A to 4H can be applied to each of the illustrated embodiments.

5A and 5B are cross-sectional views of a part of a memory array taken along the line of sight AAand B-Bof FIG. 2, respectively, according to an embodiment. For the embodiment shown in FIGS. 3A to 3H and FIGS. 4A to 4H, the two-pole system is in contact with the adjacent memory cell along the direction of the first conductor 226, but with the adjacent memory cell along the direction of the second conductor 238 Somatic isolation. For the embodiment shown in FIGS. 5A and 5B, the two-pole system is isolated from adjacent memory cells along the direction of the first conductor 226 and along the direction of the second conductor 238. This structure can be formed by using an additional patterned dielectric such as one of the patterned dielectrics 222b in FIGS. 5A and 5B. For example, a patterned dielectric 222a can be formed to a desired height of the first conductor 226, and the first conductor 226 can be formed. Then a patterned dielectric 222b can be formed to a desired height of the stack of the ruthenium material 228, the silicon material 230, and the first electrode 232, defining a through hole for the subsequent formation of the diode and the first electrode 232. The material 234 with variable resistivity can be formed as described with reference to FIGS. 3H and 4H, and the second electrode 236 and the second conductor 238 can be formed as described with reference to FIGS. 3H and 4H. The patterned dielectric 222c corresponds to the patterned dielectric 222b of FIG. 4H. Although not identified in FIGS. 5A and 5B, as described with reference to FIG. 3I, a ruthenium silicide interface can be formed between the ruthenium material 228 and the silicon material 230.

6A and 6B are cross-sectional views of a part of a memory array taken along the line of sight AAand B-Bof FIG. 2, respectively, according to an embodiment. For the embodiment shown in FIGS. 5A and 5B, the material 234 with variable resistivity is in contact with adjacent memory cells along the direction of the first conductor 226 and along the direction of the second conductor 238. For the embodiment shown in FIGS. 6A and 6B, the material 234 with variable resistivity is isolated from adjacent memory cells in the direction of the first conductor 226 and the direction of the second conductor 238. The processing can be similar to the processing described with reference to FIGS. 5A and 5B, but the patterned dielectric 222b can be formed to one of the stacks of the ruthenium material 228, the silicon material 230, the first electrode 232, and the material 234 with variable resistivity. high. Although not identified in FIGS. 6A and 6B, as described with reference to FIG. 3I, a ruthenium silicide interface can be formed between the ruthenium material 228 and the silicon material 230.

7A and 7B are cross-sectional views of a part of a memory array taken along the line of sight AAand B-Bof FIG. 2, respectively, according to an embodiment. For the embodiments shown in FIGS. 3A to 3H and FIGS. 4A and 4H, the two-pole system is between the resistance element of a memory cell and the first conductor 226. For the embodiment shown in FIGS. 7A and 7B, the two-pole system is between the resistance element of a memory cell and the second conductor 238. In addition, although the embodiment shown in FIGS. 3A to 3H and FIGS. 4A to 4H has the diode of a memory cell in contact with the adjacent memory cell along the direction of the first conductor 226, it is shown in FIG. The embodiments of 7A to 7B have diodes isolated from adjacent memory cells in the direction of both the first conductor 226 and the second conductor 238. From the foregoing discussion, the manufacture of this structure will be obvious. Although not identified in FIGS. 7A and 7B, as described with reference to FIG. 3I, a ruthenium silicide interface can be formed between the ruthenium material 228 and the silicon material 230.

8A and 8B show cross-sectional views of a part of a memory array taken along the line of sight AAand B-Bof FIG. 2, respectively, according to an embodiment. For the embodiment shown in FIGS. 7A and 7B, the material 234 with variable resistivity is in contact with adjacent memory cells along the direction of both the first conductor 226 and the second conductor 238. For the embodiment shown in FIGS. 8A and 8B, the variable resistivity material 234 is isolated from adjacent memory cells along the direction of both the first conductor 226 and the second conductor 238. From the foregoing discussion, the manufacture of this structure will be obvious. Although not identified in FIGS. 8A and 8B, as described with reference to FIG. 3I, a ruthenium silicide interface can be formed between the ruthenium material 228 and the silicon material 230.

9A and 9B are cross-sectional views of a part of a memory array taken along the line of sight AAand B-Bof FIG. 2, respectively, according to an embodiment. The embodiment shown in FIGS. 9A and 9B shows an example of the first conductor 226 formed with a barrier 225 and a conductive material 227 within the barrier. The embodiment shown in Figs. 9A and 9B is similar to the embodiment shown in Figs. 3A to 3H and Figs. 4A and 4H, but these two-pole systems are formed in a memory cell's resistance element and Between a second conductor 238, and the two-pole systems are in contact with adjacent memory cells along the direction of the second conductor 238 and isolated from adjacent memory cells along the direction of the first conductor 226. Although not identified in FIGS. 9A and 9B, as described with reference to FIG. 3I, a ruthenium silicide interface can be formed between the ruthenium material 228 and the silicon material 230.

It should be noted that additional layers may be used in the structure described with reference to FIGS. 3A to 9B, such as a barrier layer that inhibits diffusion between opposing layers or an adhesion layer that promotes adhesion between opposing layers.

in conclusion

The use of a memory device including a resistor element and a memory cell of a diode coupled in series between two conductors has been described. The diodes include ruthenium materials and silicon materials. The diodes further include an interface on a silicon material composed of ruthenium or ruthenium silicide. The ruthenium silicide interface can be a polycrystalline ruthenium silicide.

Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that any arrangement calculated to achieve the same purpose can be substituted for the specific embodiments shown. Those familiar with the technology will understand many modifications of the embodiments. Therefore, this application is intended to cover any modifications or variations of these embodiments.

<p>100. . . Basic Crosspoint Memory Array</p><p>102. . . Memory cell</p><p>104. . . Resistance element</p><p>126. . . Data line</p><p>138. . . Access line</p><p>200. . . Memory array</p><p>202. . . Memory cell</p><p>220. . . Support</p><p>222a. . . Patterned dielectric</p><p>222b. . . Patterned dielectric</p><p>222c. . . Patterned dielectric</p><p>224. . . ditch</p><p>225. . . Barrier</p><p>226. . . Data line/first conductor</p><p>227. . . Conductive material</p><p>228. . . Ruthenium material</p><p>229. . . Ruthenium Silicide Interface</p><p>230. . . Silicon material</p><p>232. . . First electrode</p><p>234. . . Materials with variable resistivity</p><p>236. . . Second electrode</p><p>238. . . Access line/second conductor</p>

Figure 1 is a schematic diagram of a part of a basic cross-point memory array.

2 is a top view of a portion of a memory array that provides a frame of reference for the discussion of FIGS. 3A to 9B according to an embodiment.

3A to 3H show cross-sectional views of a portion of a memory array taken along the line of sight AAof FIG. 2 during various manufacturing stages according to an embodiment.

FIG. 3I shows a cross-sectional view of a diode showing a ruthenium silicide interface on a silicon material according to some embodiments.

4A to 4H show cross-sectional views of a portion of a memory array taken along the line of sight BBof FIG. 2 during various manufacturing stages according to an embodiment.

5A and 5B are cross-sectional views of a part of a memory array taken along the line of sight AAand B-Bof FIG. 2, respectively, according to an embodiment.

6A and 6B are cross-sectional views of a portion of a memory array taken along the line of sight AAand B-Bof FIG. 2, respectively, according to an embodiment.

7A and 7B are cross-sectional views of a part of a memory array taken along the line of sight AAand B-Bof FIG. 2, respectively, according to an embodiment.

8A and 8B show cross-sectional views of a part of a memory array taken along the line of sight AAand B-Bof FIG. 2, respectively, according to an embodiment.

9A and 9B are cross-sectional views of a part of a memory array taken along the line of sight AAand B-Bof FIG. 2, respectively, according to an embodiment.