Variable-resistance memory device

Variable resistance memory device

The present invention relates to a variable resistance memory device using memory cells. Each of the memory cells includes a storage element and an access transistor connected in series with the storage element. The storage element is The resistance of the component's voltage change. The invention also relates to a method for driving a variable resistance memory device.

Such as K. Aratani, K. Ohba, T. Mizuguchi, S. Yasuda, T. Shiimoto, T. Tsushima, T. Sone, K. Endo, A. Kouchiyama, S. Sasaki, A. Maesaka, N. Yamada and As described in H. Narisawas "A Novel Resistance Memory with High Scalability and Nanosecond Switching", Technical Digest IEDM 2007, pages 783 to 786, it is known to use memories each including a storage element The variable resistance memory device of the cell. In each of the memory cells, by injecting conductive ions into or extracting conductive ions from the insulating film of the storage element, the resistance of the storage element can be changed.

The storage element has a structure produced by laminating a conductive ion supply layer on an insulating layer between two electrodes, and the conductive ion supply layer serves as a layer for supplying conductive ions. Each of the memory cells is configured to have the storage element and an access transistor connected to the storage element in series between the first common line and the second common line. The first common line and the second common line can be Driven by the active matrix method.

Since this memory cell therefore has a transistor T and a variable resistor R of the storage element, the variable resistance memory device is one of the 1T1R type current-driven memory. This variable resistance memory device is called ReRAM.

In ReRAM, the magnitude of the resistance of the storage element indicates whether data has been written to or deleted from the storage element. Pulses with a short duration on the order of nanoseconds can be used to perform operations for writing data into or erasing data from the storage device. Therefore, ReRAM, which is similar to RAM (Random Access Memory) and can operate at high speed as NVM (Non Volatile Memory), has attracted a lot of attention.

In a read or read verification operation performed on the ReRAM, a voltage is applied between the two electrodes of the storage element and the current flowing through the storage element as a result of the applied voltage is read. In the following description, the read verification operation is also simply referred to as a verification operation. The verification operation may be a verification operation performed after the erase operation or a verification operation performed after the write operation. However, the post-erase verify operation is basically the same as the post-write verify operation, although the polarity of the applied voltage in the former verify operation is different from the polarity of the applied voltage in the latter verify operation. That is, the direction of the flowing current in the verify operation after erasing is different from the direction of the flowing current in the verify operation after writing.

In addition, regardless of the type of verification operation, it is necessary to limit the voltage applied during the verification operation to a relatively low read voltage VR in order to prevent interference from occurring unintentionally. This is because the excessive voltage applied during the verification operation can cause such interference that data is unintentionally erased from the storage device or unintentionally written into the storage device.

As a method for controlling the voltage applied to the bit line during the verification operation, there are Japanese Patent Laid-Open No. 2006-127672 (Patent Document 1) and Japanese Patent Laid-Open No. 2005-310196 ( The known method disclosed in Patent Document 2).

According to the method disclosed in Patent Document 1, an NMOS transistor with a gate voltage set to VBIAS is provided on the read current path. The source electrode of the NMOS transistor is connected to the bit line in order to control the BL potential appearing on the bit line. At this time, the NMOS transistor operates as a source follower that controls the BL voltage to (VBIAS-Vgs), where the symbol Vgs represents the voltage appearing between the source electrode and the gate electrode of the NMOS transistor.

According to the method disclosed in Patent Document 2, on the other hand, the read voltage VR is generated as a part of the voltage obtained by charging a predetermined node. This part is determined by a capacitance ratio. Then, in the state of dynamically maintaining the read voltage VR, a negative feedback operational amplifier is used to clamp the BL voltage to the read voltage VR. That is, the negative feedback operational amplifier operates as an amplifier for controlling the BL voltage to the read voltage VR. Therefore, according to the method disclosed in Patent Document 2, the magnitude of the cell current flowing through the memory cell is detected as a value determined by the following relationship: cell current=read voltage VR/storage element resistance.

Under the condition of the method disclosed in Patent Document 1, a VBIAS generating circuit is required and the VBIAS generating circuit must be a high-precision analog circuit. Therefore, even in the standby state, DC current still flows, thereby serving as one of the reasons that hinder efforts to reduce power consumption.

Under the conditions of the method disclosed in Patent Document 2, on the other hand, an analog circuit for generating a low read voltage VR as only a part of the determination by the capacitance ratio is required. In this situation, power consumption can be reduced.

However, since the DC current is generated by an operational amplifier acting as a feedback element, the standby current does not completely become equal to zero. Therefore, there are also obstacles to efforts to further reduce power consumption.

Therefore, the object of the present invention is to implement a variable resistance memory device that does not require an analog circuit for reducing power consumption.

The variable resistance memory device according to the present invention uses: a memory cell array including a plurality of memory cells, each of the plurality of memory cells includes a storage element and is between a bit line and a source line An access transistor connected in series to the storage element, the storage element having a resistance that varies according to the direction of a voltage applied to the storage element; and a voltage supply circuit for setting a read voltage The read voltage is used to read the read voltage on the selected location line connected to the memory cell serving as a read object in an operation of supplying the read voltage to a selected location cell line by the following steps The resistance of the storage element: the charge is precharged to each of the bit lines mentioned above as a common one for these bit lines and/or any arbitrary number of bit lines mentioned above Any arbitrary number of common lines of the line, and discharge the precharged charge to any arbitrary number of other aforementioned bit lines including the selected location line to share the charge in a charge sharing process.

In the configuration described above, the read voltage is determined by the ratio of the capacitance of the line capacitor used to store the charge before and after the discharge of the charge from the common line and the bit line and other bit lines. Therefore, by performing control for selecting a pre-charged object and a discharging object to set the ratio to an appropriate value, the magnitude of the read voltage can be set arbitrarily.

According to the present invention, it is possible to implement a variable resistance memory device that does not require an analog circuit and can therefore reduce power consumption.

The embodiments of the present invention are explained by referring to the figures in the chapters arranged as follows:

1: The first embodiment

2: The second embodiment

3: The third embodiment

4: Fourth embodiment

5: The fifth embodiment

6: Modify

1: The first embodiment

Memory cell configuration

FIG. 1A and FIG. 1B are each a diagram showing an equivalent circuit of a memory cell common to the embodiments. It should be noted that FIG. 1A shows an equivalent circuit with a write current and FIG. 1B shows an equivalent circuit with an erase current. However, the memory cell configurations shown in these figures are the same as each other.

The memory cell MC shown in FIG. 1A and FIG. 1B uses a variable resistance storage resistor Re and an access transistor AT serving as storage elements. In the following description, the variable resistance storage resistor Re is also referred to as the variable resistance storage element Re.

One of the two ends of the variable resistance storage element Re is connected to the source line SL, and the other end is connected to the source electrode of the access transistor AT. The drain electrode of the access transistor AT is connected to the bit line BL, and the gate electrode of the access transistor AT is connected to the word line WL.

In the configuration shown in FIGS. 1A and 1B, the bit line BL and the source line SL are parallel to each other. However, it should be noted that the bit line BL and the source line SL do not have to be parallel to each other.

In the first embodiment, in the 3-wire configuration given as a premise, as described above, the memory cell MC is connected to three lines, namely, the bit line BL, the source line SL, and the control access Transistor AT ZigZag WL.

2 is a cross-sectional view showing the structure of two adjacent memory cells MC of a variable resistance memory device. Figure 2 is a cross-sectional view of the model showing the part without hatching. The blank part of Fig. 2 is the part filled with insulating film or other configuration part, even if the figure does not indicate so.

In the memory cell MC shown in FIG. 2, an access transistor AT of the memory cell MC is generated on the substrate 100.

In detail, two impurity regions serving as the source electrode S of the access transistor AT (which is AT1 or AT2) and the drain electrode D of the access transistor AT are respectively generated on the substrate 100, and the source electrode S and the drain electrode S The polysilicon or the like on the gate substrate area between the electrodes D produces the gate electrode G. The gate electrode G is separated from the gate region on the substrate 100 by the gate insulating film. The gate electrode G is formed to stretch the zigzag line WL in the column direction (that is, the horizontal direction in FIG. 2). The impurity region used as the drain electrode D is placed on the front side of the word line WL, and the impurity region used as the source electrode S is placed on the back side of the word line WL. The front side of the word line WL is the front side in the direction perpendicular to the surface of the page showing the figure, and the back side of the word line WL is the back side in the direction perpendicular to the surface of the page showing the figure. In FIG. 2, the positions of the impurity region used as the drain electrode D and the impurity region used as the source electrode S are shifted from each other in the horizontal direction so that the drain electrode D and the source electrode S can be easily identified. However, the positions of the impurity region used as the drain electrode D and the impurity region used as the source electrode S may also overlap each other in the direction perpendicular to the surface of the page showing the figure.

The drain electrode D is connected to the bit line BL generated by the first wire layer (1M) through the bit line contact BLC.

On the source electrode S, the source line contact SLC is generated by repeatedly stacking the plug 104 and the positioning pad 105. The positioning pads 105 are each produced by a wire layer. On the source line contact SLC, a variable resistance storage element Re is generated.

It is possible to arbitrarily select a layer from the multilayer wire structure to serve as the layer on which the variable resistance storage element Re is to be produced. However, in this situation, the fourth layer or the fifth layer is selected as the layer on which the variable resistance storage element Re is to be generated.

The variable resistance storage element Re forms a thin film configuration (or laminate) between the bottom electrode 101 and the top electrode serving as the source line SL. The film configuration includes an insulator film 102 and a conductor film 103.

Typical examples of materials used to make the insulator film 102 usually include SiN, SiO₂And Gd₂O₃。

Typical examples of the material used to manufacture the conductive film 103 generally include metal films, alloy films, and metal compound films. The metal thin film includes one or more elements selected from Cu, Ag, Zr, and Al. A typical example of alloy film is CuTe alloy film. It should be noted that the elements used for manufacturing the metal thin film can also be selected from elements other than Cu, Ag, Zr, and Al, provided that these elements have the property of being easily ionized. In addition, one or more elements S, Se, and Te need to be used as elements to be combined with one or more of the aforementioned elements Cu, Ag, Zr, and Al. The conductive film 103 is produced as a conductive ion supply layer.

FIG. 2 shows two variable resistance elements Re connected to different source lines SL. Insulator films 102 each serving as one of the storage layers of adjacent memory cells MC separated from each other in the same direction as the bit line BL are generated on the same layer. For the same reason, the conductive films 103 each serving as one of the conductive ion supply layers of these memory cells MC are also produced on the same layer. In the same way, the source lines SL of these memory cells MC are also generated on the same layer. In addition, as another configuration, the source line SL is shared by the memory cells MC separated from each other in the same direction as the bit line BL, and the storage layer and the conductive ion supply layer are related to each memory cell. MC is generated independently.

It should be noted that in the first embodiment, the source line SL is generated by the conductive layer above the bit line BL. The bit line BL is generated by the first wire layer (1M), and the source line SL is generated by the fourth wire layer or the fifth wire layer. However, the source line SL can be generated by the first wire layer (1M), and the bit line BL can be generated by the fourth wire layer or the fifth wire layer. In addition, the wire layer used to generate the source line SL and the bit line BL can be arbitrarily selected.

3A and 3B are model diagrams each showing the direction of current flowing through the variable resistance storage element Re used in the variable resistance memory device and the typical magnitude of the voltage applied to the variable resistance storage element .

As an example, FIGS. 3A and 3B show that the insulator film 102 is made of SiO₂A configuration in which the conductor thin film 103 is produced from a Cu-Te-based alloy compound material is produced. The insulator film 102 has an area in contact with the lower electrode 101. The contact area is defined by the pores on the nitride film (or SiN film) 104.

More specifically, FIG. 3A shows that a voltage is applied between the lower electrode 101 and the top electrode serving as the source line SL in the direction in which the insulator film 102 is placed on the negative electrode side and the conductor film 103 is placed on the positive electrode side. The situation between. For example, using this voltage, the bit line BL is connected to the ground having a potential of 0 V, and the source line SL is set to a typical potential of +3 V.

This state causes a property showing a phenomenon that Cu, Ag, Zr, or Al included in the conductor thin film 103 is ionized and the resulting ions are attracted to the negative electrode side. These metal conductive ions are implanted into the insulator film 102. Therefore, the insulating ability of the insulator film 102 is reduced, and as a result, the insulator film 102 exhibits conductive characteristics. As a result, the write current Iw having the direction shown in FIG. 3A flows. This operation is called a write operation or a set operation.

Contrary to the above description, FIG. 3B shows that a voltage is applied to the top of the lower electrode 101 and serving as the source line SL in the direction in which the conductor film 103 is placed on the negative electrode side and the insulator film 102 is placed on the positive electrode side. The condition between the electrodes. For example, using this voltage, the source line SL is connected to the ground having a potential of 0 V, and the bit line BL is set to a typical potential of +1.7 V.

This state causes the conductive ions injected into the insulator film 102 to return to the conductor film 103, thereby restoring the resistance to a high pre-written value. This operation is called an erase operation or a reset operation. In the erase operation or reset operation, the erase current Ie having the direction shown in FIG. 3B flows.

It should be noted that in the following description, the setting operation is defined as an operation for implanting sufficient conductive ions into the insulator film, and the reset operation is defined as an operation for extracting sufficient conductive ions from the insulator film.

On the other hand, the setting operation can be arbitrarily regarded as a data writing operation, and the reset operation can be arbitrarily regarded as a data erasing operation or vice versa.

In the following description, the setting operation is regarded as a data writing operation, and the reset operation is regarded as a data erasing operation. That is, the data writing operation or setting operation is defined as an operation to reduce the insulating property of the insulator film 102 so as to reduce the resistance of the entire variable resistance storage element Re to a sufficiently low level, thereby erasing data The operation or reset operation is defined as an operation for restoring the insulating properties of the insulator film 102 to the original initial state so as to increase the resistance of the entire variable resistance storage element Re to a sufficiently high level.

The direction of current indicated by the arrows shown in FIGS. 1A and 3A is the direction of the write current Iw flowing through the variable resistive storage element Re in the setting operation, and the direction of current indicated by the arrows shown in FIGS. 1B and 3B It is the direction of the erasing current Ie flowing through the variable resistance storage element Re during the reset operation.

Therefore, it is possible to implement a binary memory, on which the setting operation and reset operation described above are repeatedly performed to change the resistance of the variable resistance storage element Re from a larger value to a smaller value in a reversible manner Value and vice versa. In addition, since even if the voltage applied to the variable resistance storage element Re is removed, the variable resistance storage element Re still maintains its resistance and the data stored in it, so the binary memory acts as a non-volatile Memory.

However, in addition to binary memories, the present invention can also be applied to multi-value memories, such as memories capable of storing three or more values.

It should be noted that in the setting operation, the resistance of the variable resistance storage element Re actually changes according to the number of metal ions injected into the insulator film 102. Therefore, the insulator film 102 can be regarded as a storage layer for storing and retaining data.

It is possible to configure the memory cell array of the variable resistance memory device to include many memory cells MC each using a variable resistance storage element Re. The variable resistance memory device itself is configured to include a memory cell array and a driving circuit also called a peripheral circuit.

Configuration of IC chip

4 is a block diagram showing the configuration of a variable resistance memory device usually implemented as an IC chip.

The variable resistance memory device shown in FIG. 4 uses a memory cell array 1 and its peripheral circuits integrated in the same semiconductor chip. The memory cell array 1 is constructed by arranging the memory cells MC shown in FIGS. 1A to 3B to form a matrix composed of N columns and M rows, each of the N columns includes M memories arranged in the column direction The somatic cells MC and the M rows each include N memory cells MC arranged in the row direction. In this situation, the symbols M and N are each relatively large integers that can be arbitrarily set to a specific value.

It should be noted that FIG. 4 shows a typical configuration of a part of the memory cell array 1. This part includes memory cells MC configured to form N columns and four rows. In this typical configuration, a sense amplifier reads out the data of four memory cells MC arranged on each of the rows in the row direction.

Since there are N columns as part of the memory cell array 1 in the part shown in FIG. 4, N word lines WL<0> to WL<N-1> are respectively used for the N columns. The N word lines WL<0> to WL<N-1> are laid out at predetermined intervals in the row direction. In FIG. 4, N word lines WL<0> to WL<N-1> are represented by reference symbols WL<N:0>. The gate electrodes of the access transistors AT in the four memory cells MC arranged on each of the N rows in the column direction are connected to each other by the word line WL<N:0>.

In addition, the drain electrodes or the source electrodes of the access transistor AT in the N memory cells MC arranged in the row direction are connected to each other by the bit line BL. Since there are M rows in the memory cell array 1, M bit lines BL<0> to BL<M-1> are used. The M bit lines BL<0> to BL<M-1> are laid out at predetermined intervals in the column direction.

In the same way, specific ends of the variable resistance elements Re in the N memory cells MC arranged in the row direction are connected to each other by the source line SL. Since there are M rows in the memory cell array 1, M source lines SL<0> to SL<M-1> not shown in FIG. 4 are used. The M source lines SL<0> to SL<M-1> are laid out at predetermined intervals in the column direction. The specific end of the variable resistance storage element Re used in each memory cell MC is the end on the side opposite to the access transistor AT used in the same memory cell MC.

Generally, the four source lines included in the M source lines SL<0> to SL<M-1>, which are the four source lines respectively provided for four adjacent rows, are connected to each other. The four source lines can be connected to lines for supplying reference voltages such as GND (ground) voltage. The bit lines BL and the source lines SL are alternately arranged in the column direction.

The peripheral circuit has a write/erase driver 10 and a sense amplifier (SA) 7. Each write/erase driver 10 drives the bit line BL and the source line SL. SA (Sense Amplifier) 7 reads the data from the bit line BL.

The write/erase driver 10 and SA (Sense Amplifier) 7 form a row drive circuit. The row driving circuit corresponds to the main section of the driving circuit according to the present invention. It should be noted that the driving circuit according to the embodiment of the present invention includes the write/erase driver 10, but does not necessarily include the SA (Sense Amplifier) 7.

In the configuration shown in FIG. 4, each source line SL is connected to ground. However, the connection of each source line SL to the ground only shows a model of the voltage application state in the read state. In fact, each source line SL is connected to an erase driver 10 by a selection switch assigned to the source line SL individually. However, the selector switch itself is not shown in FIG. 4.

In addition, the peripheral circuit also has a predecoder 3, a column driving circuit 4, and a row switching circuit 6.

The predecoder 3 is a circuit for splitting the input address signal into the column address of the X system and the row address of the Y system.

The column driving circuit 4 has an X-address main decoder, a Y-address main decoder, a row switch control circuit, and a WL (word line) driver.

The row switch circuit 6 is a circuit for controlling the following operations: connecting a predetermined plurality of bit lines BL to a common bit line CBL or a line for supplying a reference voltage such as GND (ground) voltage, and making the bit lines BL is disconnected from the common bit line CBL or the line for supplying the reference voltage. In the case of the configuration shown in FIG. 4, the predetermined plural number is usually 4. That is, the bit lines BL are the bit lines BL<0> and BL<3>.

In addition, the peripheral circuit also has an I/O (input/output) buffer 9, a control circuit 11, and a logic block 16.

The logic block 16 is a logic circuit section for controlling the operation for inputting and outputting data, the operation for storing data, and the control system of a buffer operation. When necessary, the logic block 16 can also be configured to perform control of the write inhibit state of each row of the memory cell array 1.

It should be noted that FIG. 4 does not show other circuits, such as a circuit for generating various voltages from the voltage of a power supply and a circuit for controlling the generation of a clock signal.

Next, the configuration of the row switch circuit 6 shown in FIGS. 4 and 5 is explained as follows. FIG. 5 is a diagram showing the connection between the memory cell array 1, SA (Sense Amplifier) 7 shown in FIG. 4 and each other section.

As shown in FIGS. 4 and 5, the row switch circuit 6 has a common line isolation switch section 6B and a discharge switch section 6C.

The common line isolation switch section 6B is used to connect the four bit lines BL<3:0> to the common bit line CBL and to make the four bit lines BL<3:0> from the common bit line respectively. A collection of four NMOS switches that are turned off by CBL. The four bit lines BL<3:0> are bit lines BL<0> to BL<3>. Among the four bit lines BL<3:0>, the bit line BL<0> is the bit line with the smallest bit line number, and the bit line BL<3> is the bit line with the largest bit line number Yuan line. In the following description, the four NMOS switches are referred to as isolation switches 61<3:0>.

The isolation switch 61<0> is connected between the bit line BL<0> and the common bit line CBL and is controlled by the row selection signal YSW<0> supplied to the gate electrode of the isolation switch 61<0>. For the same reason, the isolation switch 61<1> is connected between the bit line BL<1> and the common bit line CBL and is controlled by the row selection signal YSW<1> supplied to the gate electrode of the isolation switch 61<1> . In the same way, the isolation switch 61<2> is connected between the bit line BL<2> and the common bit line CBL and is controlled by the row selection signal YSW<2> supplied to the gate electrode of the isolation switch 61<2> . Similarly, the isolation switch 61<3> is connected between the bit line BL<3> and the common bit line CBL and is controlled by the row selection signal YSW<3> supplied to the gate electrode of the isolation switch 61<3>.

On the other hand, the discharge switch section 6C is a set of four NMOS switches for respectively discharging the charges from the four bit lines BL<3:0>. In the following description, the four NMOS switches are referred to as discharge switches 62<3:0>.

According to the control based on the inverted row selection signal /YSW<3:0> respectively supplied to the discharging switch 62<3:0>, the discharging switch 62<3:0> executes and uses the discharging switch 62<3 :0>The associated isolation switch 61<3:0> performs the opposite operation of the operation.

The discharge switch 62<0> is connected between the bit line BL<0> and the ground and is controlled by the inverted row selection signal /YSW<0> supplied to the gate electrode of the discharge switch 62<0>. For the same reason, the discharge switch 62<1> is connected between the bit line BL<1> and the ground by the inverted row selection signal /YSW<1> supplied to the gate electrode of the discharge switch 62<1> control. In the same way, the discharge switch 62<2> is connected between the bit line BL<2> and the ground and is supplied by the inverted row selection signal /YSW<2> to the gate electrode of the discharge switch 62<2> control. Similarly, the discharge switch 62<3> is connected between the bit line BL<3> and ground and is controlled by the inverted row selection signal /YSW<3> supplied to the gate electrode of the discharge switch 62<3> .

It should be noted that the parts of the fifth bit line BL to the (M-1)th bit line BL that are not shown in FIGS. 4 and 5 have the same array configuration as the configuration shown in these figures.

The common bit line CBL is connected to a precharge transistor 71 which is a PMOS transistor. The precharge transistor 71 is usually connected between the line for supplying the power supply voltage Vdd or another voltage set to a high level and the common bit line CBL used as a typical common line. The precharge transistor 71 is controlled by the inverted BL precharge signal /BLPRE supplied to the gate electrode of the precharge transistor 71.

Each of the bit lines BL<3:0> has a wire capacitor connected to the bit line BL as a wire capacitor of a load capacitor. In FIGS. 4 and 5, the load capacitor connected to the bit line BL is represented by the reference symbol Cb1 which is also used to indicate the wire capacitance of the bit line BL.

In addition, the common bit line CBL also has a wire capacitance and a capacitance with the contact of the isolation switch 61<3:0>. The wire capacitance and the capacitance of the contact are the capacitance of the wire/contact capacitor connected to the common bit line CBL as a load capacitor. In FIGS. 4 and 5, the load capacitor connected to the common bit line CBL is represented by the reference symbol Ccb1, which is also used to indicate the wire and contact capacitance of the common bit line CBL.

As described above, the row switch circuit 6 implements the connection between the bit line BL<3:0> and the common bit line CBL or the ground line. Therefore, the voltage VR to be read can be set without using an analog circuit as a voltage generating circuit. As will be described in detail later, the read voltage VR can be set by using the precharge transistor 71 to recharge the charge on the common bit line CBL and any arbitrary number of bit lines BL. Spread to any arbitrary number of other bit lines BL.

The column driving circuit 4 has the function of a main decoder. The column driving circuit 4 is configured to include an X selector 20 and a Y selector 30 in order to perform this function.

The column driving circuit 4 also has the function of the control circuit of the CSW (row switch) circuit 6. The column driving circuit 4 is configured to include a plurality of CSW driver units 6A in order to perform this function.

In addition, the column driving circuit 4 also has the function of a WL driver. The column driving circuit 4 is configured to include as many WL driver units 4A as the word lines WL to perform this function. As previously described, the number of word lines is N.

Typical specific circuits of the X selector 20, Y selector 30, CSW driver unit 6A, and WL driver unit 4A will be described later.

As explained above, the predecoder 3 is a circuit for splitting the input address signal into X address signals (X0, X1, etc.) and Y address signals (Y0, Y1, etc.).

The X address signals (X0, X1, etc.) are supplied to the X selector 20 used in the column driving circuit 4. The X selector 20 decodes the X address signal. As a decoding result, the X selector 20 generates X selection signals X_SEL<0> to <N-1> for selecting the WL driver unit 4A. That is, the X selection signals X_SEL<0> to <N-1> are respectively supplied to the N WL driver units 4A.

On the other hand, Y address signals (Y0, Y1, etc.) are supplied to the Y selector 30 used in the column driving circuit 4. The Y selector 30 decodes the Y address signal. As a decoding result, the Y selector 30 generates a Y selection signal Y_SEL for selecting the CSW driver unit 6A. The number of Y selection signals Y_SEL varies according to the configuration of the row switch circuit 6 used in the variable resistance memory device shown in FIG. 4. Therefore, the number of CSW driver units 6A used to drive the row switch circuit 6 based on the Y selection signal Y_SEL also changes according to the configuration of the row switch circuit 6.

When a WL driver unit 4A is selected by an X selection signal X_SEL, the WL driver unit 4A applies a predetermined voltage to the word line WL connected to the output terminal of the WL driver unit 4A. The details of the WL driver unit 4A will be described later.

The erase driver 10 is a circuit for outputting voltage to the common bit line CBL and the common source line not shown in any figures. The direction of the voltage output in the write operation or the setting operation under the condition of this embodiment is opposite to the direction of the voltage output in the erase operation or the reset operation under the condition of this embodiment.

In the control of writing and erasing operations, in detail, the common line isolation switch section 6B used in the row switch circuit 6 works, making it possible to arbitrarily select the memory that each serves as the object of the writing or erasing operation Cell line.

It should be noted that in order to control the connection between the common source line and the row of the memory cell MC, which is not shown in any figure, the same circuit as the common line isolation switch section 6B can be provided between the common source line and the source Between polar lines SL. Among the four memory cells MC provided on each matrix row of the memory cell array shown in FIGS. 4 and 5, a write operation is performed for each memory cell MC. However, the erase operation can be performed for each matrix row or for all memory cells MC together. If the erase operation is performed for each matrix row or for all memory cells MC that are together, the same circuit as the common line isolation switch section 6B is not absolutely necessary on the source line side.

The control circuit 11 receives a write signal WRT, an erase signal ERS, and a data read signal RD, and based on the write signal WRT, the erase signal ERS, and the data read signal RD, the control circuit 11 generates various signals and Various voltages. The control circuit 11 has the following five functions.

(1) At the read time, the control circuit 11 generates an SA enable signal SAEN or an SA disable signal /SAEN, a bit line isolation signal BLI, and a reference potential VREF, so as to stop the SA enable signal SAEN or the SA The signal /SAEN, the bit line isolation signal BLI, and the reference potential VREF are output to SA (Sense Amplifier) 7. It should be noted that instead of the control circuit 11, a voltage generating circuit not shown in any figure can supply the reference potential VREF to the SA (Sense Amplifier) 7.

(2) During the reading time, the control circuit 11 outputs the inverted BL precharge signal /BLPRE to the precharge transistor 71 and the SA (sense amplifier) 7.

(3) During the writing or erasing time, the control circuit 11 controls the writing/erasing driver 10.

(4) During the writing or erasing time and the reading time, the control circuit 11 performs overall control of the column drive circuit 4 and the row switch circuit 6. It should be noted that the control performed at the read time will be specifically described later.

(5) When necessary, the control circuit 11 controls the logic block 16 to control data input/output operations and data buffering.

The I/O buffer 9 is connected to the SA (Sense Amplifier) 7 and the write/erase driver 10.

The logic block 16 performs control in order to input data from an external source, and buffer the data in the I/O buffer 9 when necessary. The buffered data is later supplied to the write/erase driver 10 at a predetermined timing to be used to control the write or erase operation.

In addition, the logic block 16 performs control to output the data read by the SA (sense amplifier) 7 via the write/erase driver 10 to the external data receiving terminal via the I/O buffer 9.

Control system circuit

Next, the following description explains typical circuits of the X selector 20, Y selector 30, WL driver unit 4A, and CSW driver unit 6A. FIG. 6 is a diagram showing a typical logic circuit of the X selector 20. As shown in FIG. 6, the X selector 20 uses four inverters INV0 to INV3 provided in the previous stage, four NAND circuits NAND0 to NAND3 provided in the intermediate stage, and four other inverters INV4 provided in the subsequent stage. To INV7. The X selector 20 receives the X address signal bits X0 and X1, thereby decoding the X address signal bits X0 and X1. As a result of the decoding, the X selector 20 activates one of the four X selection signals X_SEL0 to X_SEL3 by usually raising one of the four X selection signals X_SEL0 to X_SEL3 to a high level. Figure 6 shows the configuration of a typical 2-bit decoder. However, according to the number of X address signal bits, the configuration shown in FIG. 6 can be extended to a multi-bit configuration, thereby allowing more bits of the X address signal to be supplied to the decoder. That is, it is possible to adopt a configuration for decoding two or more X address signal bits. FIG. 7 is a diagram showing a typical logic circuit of the Y selector 30.

As shown in Fig. 7, the Y selector 30 uses four inverters INV8 to INV11 provided in the previous stage, four NAND circuits NAND4 to NAND7 provided in the middle stage, and four other inverters INV12 provided in the latter stage. To INV15.

The Y selector 30 receives the Y address signal bits Y0 and Y1, thereby decoding the Y address signal bits Y0 and Y1. As a result of the decoding, the Y selector 30 activates one of the four Y selection signals Y_SEL0 to Y_SEL3 by usually raising one of the four Y selection signals Y_SEL0 to Y_SEL3 to a high level. Figure 7 shows the configuration of a typical 2-bit decoder. However, according to the number of Y address signal bits, the configuration shown in FIG. 7 can be extended to a multi-bit configuration, thereby allowing more bits of the Y address signal to be supplied to the decoder. That is, it is possible to adopt a configuration for decoding two or more Y address signal bits. FIG. 8 is a diagram showing a typical logic circuit of two adjacent WL driver units 4A.

The column driving circuit 4 actually includes (N-1) WL driver units 4A, two of which are shown in the figure. The number (N-1) is the number of memory cells laid out in the row direction on each row. One of (N-1) WL driver units 4A is selected to operate according to the X selection signal X_SEL0 or X_SEL1 activated by the X selector 20 shown in FIG. 6. Then, the selected WL driver unit 4A activates the word line WL<0> or the word line WL<1> corresponding to the X selection signal X_SEL0 or the X selection signal X_SEL1, respectively.

As shown in FIG. 8, each WL driver unit 4A uses a NAND circuit (e.g., NAND8) and an inverter (e.g., INV16). One of the two input terminals of the NAND circuit NAND8 receives the WL selection enable signal WLEN, and the other input terminal receives the X selection signal X_SEL0 or X_SEL1 activated by the X selector 20 shown in FIG. 6. The output terminal of the NAND circuit NAND8 is connected to the input terminal of the inverter INV16. Therefore, the word line WL<0> or WL<1> connected to the output terminal of the inverter INV16 is activated or deactivated. FIG. 9 is a diagram showing a typical logic circuit of two adjacent CSW driver units 6A.

As shown in FIG. 9, each CSW driver unit 6A uses a NAND circuit (e.g., NAND12) and an inverter (e.g., INV21). One of the two input terminals of the NAND circuit NAND12 receives the Y switch enable signal YSWEN, and the other input terminal receives the Y selection signal Y_SEL0 or Y_SEL1 activated by the Y selector 30 shown in FIG. 7. When the Y selection signal Y_SEL0 or Y_SEL1 and the Y switch enable signal YSWEN are both set to the high level of the activated state, the signal output by the NAND circuit NAND12 drops to the low level. Therefore, the row selection signal YSW<0> or YSW<1> output by the inverter INV21 connected to the output terminal of the NAND circuit NAND12 changes to the activated level, and the activated level is in the state of the first embodiment The lower is the high level. Sense Amplifier FIG. 10 is a diagram showing a typical configuration of SA (sense amplifier) 7 shown in FIGS. 4 and 5.

The SA (Sense Amplifier) 7 shown in FIG. 10 is a single-ended sense amplifier. The basic configuration of SA (Sense Amplifier) 7 includes a latch circuit 72 for sensing the potential appearing on the sensing bit line SABL as a voltage and taking the sensing position as a reference The potential of the meta reference line/SABL is used to amplify the sensed voltage. The latch circuit 72 according to this embodiment uses two inverters that are cross-connected to each other. In detail, the output terminal of a specific one of the inverters is connected to the input terminal of the other inverter, and the output terminal of the other inverter is connected to the input terminal of the specific inverter. Each of the inverters has a PMOS transistor 21 and an NMOS transistor 22. The PMOS transistor 23 is connected between the common source electrode shared by the two PMOS transistors 21 and the line for supplying the power supply voltage Vdd. The PMOS transistor 23 is controlled by the inverted SA enable signal /SAEN supplied to the gate electrode of the PMOS transistor 23. The inverted SA enable signal /SAEN is an active low signal. On the other hand, the NMOS transistor 24 is connected between the common source electrode shared by the two NMOS transistors 22 and the line for supplying the GND (ground) voltage. The NMOS transistor 24 is controlled by the SA enable signal SAEN supplied to the gate electrode of the NMOS transistor 24. The SA enable signal SAEN is an active high signal obtained by inverting the inverted SA enable signal /SAEN. The control circuit 11 used in the variable resistance memory device shown in FIG. 4 receives the SA enable signal SAEN and the inverted SA enable signal /SAEN.

It should be noted that the inverted SA enable signal /SAEN can also be generated internally in SA (sense amplifier) 7 by using an inverter to invert the SA enable signal SAEN.

In addition, an NMOS transistor 51 serving as a bit line isolation switch is connected between the sensing bit line SABL and the common bit line CBL. In addition, the NMOS transistor 52 for controlling the application of the reference potential VREF proposed above to the latch circuit 72 is connected between the sensing bit reference line /SABL and the line for supplying the reference potential VREF. The NMOS transistor 52 is controlled by the inverted BL precharge signal /BLPRE/ supplied to the gate electrode of the NMOS transistor 52. The control circuit 11 used in the variable resistance memory device shown in FIG. 4 receives the inverted BL precharge signal /BLPRE.

Using the above configuration given as a premise, two typical operations are explained as follows by using the waveforms shown in FIGS. 11A and 12F and by appropriately referring to FIGS. 5 and 10. It should be noted that, as a premise, after a write or erase operation, the read verification operation is performed under the conditions of this embodiment and all the typical operations described below. However, the scope of the present invention is by no means limited to this scheme. That is, the present invention can also be applied to a normal read operation. In addition, in all typical operations described below, the precharge voltage is set to the power supply voltage Vdd, and the discharge voltage is set to the reference voltage Vss, which is usually the GND (ground) voltage. However, the present invention is by no means limited to this voltage setting. That is, each of the pre-charge voltage and the post-discharge voltage can be set to any level as long as the pre-charge voltage is higher than the post-discharge voltage.

The first typical operation

In the first typical operation represented by the waveforms shown in FIGS. 11A to 11E, the charge is precharged to the bit line BL<0> selected by the row selection signal YSW<0> and toward the power supply voltage Vdd, And later, the charge is discharged to the other bit lines BL<1> to BL<3> to share the charge between the bit lines BL<0> to BL<3> in the charge sharing operation. First, as is obvious from the waveform shown in FIG. 11B, the row selection signal YSW<0> is activated by raising the row selection signal YSW<0> to the H level, and as is obvious from the waveform shown in FIG. 11C , By lowering the other row selection signals YSW<1> to YSW<3> to the L level to deactivate the other row selection signals YSW<1> to YSW<3>. As shown in FIG. 11C, the other row selection signals YSW<1> to YSW<3> are represented by reference symbols YSW<3:1>. In this state, during the period before time T1 on the waveform shown in FIG. 11A, the gate electrode of the precharge transistor 71 used in the memory cell array 1 shown in FIG. 5 will be supplied to the reversed The BL precharge signal /BLPRE is set to L level.

Therefore, the pre-charge transistor 71 is placed in an on state, thereby pre-charging the common bit line CBL to the power supply voltage Vdd. At this time, the bit line BL<0> which is also selected by the activated row selection signal YSW<0> and connected to the common bit line CBL by the activated row selection signal YSW<0> is precharged to the power supply Supply voltage Vdd. During this precharge period, only the inverted row selection signal 1YSW<0> is set to the L level. Therefore, the discharge switch 62<0> used in the memory cell array 1 shown in FIG. 5 is placed in the off state, and the other discharge switches 62<1> to 62<3> are each placed in the on state. state. Therefore, the potential appearing on each of the other bit lines BL<1> to BL<3> is set to the level of the reference voltage Vss which is usually the GND (ground) voltage. The discharge state of each of the other bit lines BL<1> to BL<3> is referred to as the BL reset state.

Next, at time T1 on the waveform shown in FIG. 11A, the precharge transistor 71 is turned off to terminate the precharge operation. Therefore, the potentials appearing on the common bit line CBL and the bit line BL<0> are placed in a floating state. As a result, it starts to dynamically maintain the state of the power supply voltage Vdd. Next, at time T2 on the waveform shown in FIG. 11C, the state where the bit lines BL<1> to BL<3> of the memory cell array 1 shown in FIG. 5 are connected to the reference voltage Vss is terminated, and all The other row selection signal YSW<3:1> is selected, and thus is set to the H level indicating the effective state. Therefore, all other discharge switches 62<3:0> of the memory cell array 1 shown in FIG. 5 are placed in the off state, and all other isolation switches 61<3 of the memory cell array 1 shown in FIG. 5 :0> is placed in the connected state.

In this state, the charges precharged on the common bit line CBL and the bit line BL<0> are discharged to the bit lines BL<1> to BL<3>, so that the charge on the bit line can be The charge is shared between BL<0> to BL<3>. The voltage appearing on the bit line BL<0> after the charge sharing operation has been completed is about 114 of the voltage appearing on the bit line BL<0> at the precharge time. That is, after the charge sharing operation has been completed, the voltage appearing on the bit line BL<0> decays to Vdd/4. In this way, the read voltage VR of Vdd/4 is uniformly set on the four bit lines BL<0> to BL<3>. The read voltage VR obtained after the voltage attenuation is expressed by the equation (1) given below: VR=Vdd×(Cbl×Nsel)/(Ccbl+Cbl×(Nsel+Nvss)) (1) is given above In the equation (1), the reference symbol Ccbl represents the capacitance of the common bit line CBL, and the reference symbol Cbl represents the capacitance of each bit line BL. The reference symbol Nsel represents the number of specific bit lines BL sharing the charge to be discharged to other bit lines BL after precharging the charge to the specific bit line BL toward the power supply voltage Vdd. The reference symbol Nvss represents the number of the aforementioned other bit lines BL each serving as a charge sharing object after the charge of each of these other bit lines BL has been reset to the reference voltage Vss in the discharge process.

As is obvious from the waveform shown in Figure 11E, due to the discharge process, the potential appearing on the bit line BL<0> decreases, and due to the charging process, it appears in the reference symbol BL<3:1>. The potentials on the other bit lines BL<1> to BL<3> increase. It is also obvious that the potential appearing on the bit line BL<0> and the potentials appearing on the other bit lines BL<1> to BL<3> converge to the read voltage VR. Later, at time T3 on the waveform shown in FIG. 11C, the potential appearing on the row selection signal YSW<3:1> decreases, and the potential appearing on the word line WL<0> increases.

As a result, the charge of the bit line BL<0> charged to the read voltage VR is discharged to the source line SL<0> through the memory cell MC. In the waveform shown in FIG. 11E, the reference symbol LRS represents the low resistance state of the variable resistance storage element Re, and the reference symbol HRS represents the high resistance state of the variable resistance storage element Re. In the HRS, the magnitude of the current flowing through the variable resistance storage element Re used in the memory cell MC is not so large. On the other hand, in the LRS, a relatively large current flows through the variable resistance storage element Re used in the memory cell MC. Therefore, under this condition, during the discharge process, the potential appearing on the bit line BL decreases by a potential difference.

Using the timing sequence that causes a sufficient potential difference, the SA (Sense Amplifier) 7 shown in FIG. 10 performs a voltage sensing operation.

Specifically, during the read period after the time T1 on the waveform shown in FIG. 11A, the NMOS transistor 52 used in the SA (sense amplifier) 7 shown in FIG. The potential VREF has been set on the reference node of the latch circuit 72. The SA enable signal SAEN or the inverted SA enable signal /SAEN is placed in an active state to activate SA (sense amplifier) 7. In this state, if the bit line isolation signal BL1 not shown in FIGS. 11A to 11E is set to a high level, the decrease in the voltage appearing on the bit line BL<0> will propagate to SA (sense amplifier ) 7 sensor nodes. This timing is the timing when the reduced voltage in the LRS becomes sufficiently lower than the reference potential VREF for a maintained margin. The reference potential VREF is set to an intermediate potential between the final level to which the voltage is reduced in LRS and the final level to which the voltage is reduced in HRS, or is set to be higher than the intermediate potential in consideration of the shortening of the sensing period The level of the difference that is considered necessary under the circumstances. In the first typical operation described above, in the charge sharing operation, the charge is precharged to the bit line BL<0>, and the precharged charge is discharged to the three other bit lines BL<3:1>. Instead of the bit line BL<0>, the charge can also be precharged to any one of the bit lines BL<0>, BL<1>, BL<2>, and BL<3>, and the precharged charge is then Discharge to the three remaining bit lines BL. In addition, the charge can also be precharged to any two of the bit lines BL<0>, BL<1>, BL<2> and BL<3>, and the precharged charge is then discharged to the two remaining bits Element line BL.

In addition, the charge can also be precharged to any three of the bit lines BL<0>, BL<1>, BL<2> and BL<3>, and the precharged charge is then discharged to the remaining bits Element line BL.

In the second typical operation, under the conditions of the first typical operation, the potential appearing on any bit line BL except the precharged bit line BL can be used as a read object.

Under the second typical operation condition described below, on the other hand, the bit line BL<0> is precharged, and the potential appearing on the bit line BL<1> is read out. In FIGS. 12A to 12F, the waveform shown in FIG. 11C for the row selection signal YSW<3:1> is split into two waveforms, that is, shown as shown in FIG. 12C for the row selection signal YSW< The waveform of 1> and the waveform of another waveform for the row selection signal YSW<3:2> shown in FIG. 12D. Therefore, the second typical operation is different from the first typical operation. In addition, the timing of the falling edge of the waveform for the row select signal YSW<0> shown in FIG. 12B is changed from the timing of FIG. 11B.

Specifically, the potential of the row selection signal YSW<0> shown in FIG. 12B is lowered at time T3 so as to establish a deselected state thereafter. In the deselected state, the bit line BL<0> is from the common bit The line CBL is detached. In fact, since the potential appearing on the bit line BL<1> is taken as the read object as described above, it appears on the row selection signal YSW<1> shown in FIG. 12C during the period after the time T3 The potential is maintained at the H level of the activated state. As is obvious from the waveform shown in FIG. 12C, the potential appearing on the row selection signal YSW<1> shown in FIG. 12C has risen to the H level at time T2. In this way, the potential appearing on the bit line BL<1> can be used as the read object.

At time T3, the bit lines BL<2> and BL<3> are separated from the common bit line CBL in the same manner as the first typical operation. For clarity in this situation, the reader is asked to compare the waveform shown in Figure 11C with the waveform shown in Figure 12D.

In addition, the control and sensing operations of other signals are basically the same as the first typical operation.

The third typical operation

13A to 13G are timing diagrams showing waveforms for the third typical operation, which is performed to precharge the charge to the bit lines BL<0>, BL<1>, BL<2> and BL Any two of <3> and then discharge the precharged charge to the two remaining bit lines BL.

The difference between FIGS. 13A to 13G and FIGS. 11A to 11E is that under the conditions of FIGS. 13A to 13G, at time T1 that coincides with the start of the precharge operation, except for the row selection signal YSW<0> , The row selection signal YSW<1> has also been preset to the H level in order to precharge the charge to the two bit lines BL (that is, in addition to the bit line BL<0>, there is also a bit line BL <1>) To the power supply voltage Vdd.

Then, at time T2, the pre-charged charge is shared with two other bit lines BL<2> and BL<3> to set the read voltage VR to about 1/2 of the power supply voltage Vdd.

Later, at time T3, in order to remove the bit line BL<1> from the group of read objects, the potential appearing on the row selection signal YSW<1> is lowered. At the same time, the potential appearing on the word line WL<0> is raised to discharge the cell current flowing at the read time.

The control and sensing operations of other signals are basically the same as the first typical operation.

Fourth typical operation

In the first to third typical operations described so far, the number of bit lines BL sharing charges is four, but the number of bit lines BL sharing charges can be reduced to two or three.

As an example, FIGS. 14A to 14G show waveforms for operations used to share the charge precharged to one bit line BL by two bit lines BL.

The difference between FIGS. 14A to 14G and FIGS. 11A to 11E is that under the conditions of FIGS. 14A to 14G, the row selection signals YSW<0> and YSW<3> are neither precharged objects nor read objects. Therefore, during the read operation, as is apparent from the waveforms shown in FIGS. 14C and 14D, the row select signals YSW<0> and YSW<3> are maintained at the L level.

Therefore, the charge precharged to the bit line BL<0> at time T1 is shared by the bit line BL<2> at time T2, and at time T3, the bit line BL<2> is deselected for reading A change in the potential appearing on the bit line BL<0>.

The typical operations described above are only a part of the typical operations performed according to the first embodiment.

Even in operations other than the first to fourth typical operations described above, if two bit lines BL or three bit lines BL have been precharged, it is easy to freely use the bit lines BL to pass through The operation of switching the selected state to the deselected state and the bit line BL from the deselected state to the selected state is inferred to switch the bit line BL between the precharged bit lines BL Operation or operation for changing the bit line BL serving as the read object to the bit line BL that is not pre-charged but will share the pre-charged charge.

In addition, the number of bit lines BL sharing the precharged charge is not limited to two of the conditions shown in FIGS. 13A to 13G. For example, the number of bit lines BL sharing the precharged charge can also be three.

Based on the magnitude of the voltage to which the read voltage VR is to be set, the number of bit lines BL to be precharged and the number of bit lines BL sharing the precharged charge are determined.

The feature of the operation according to this embodiment is that the process of generating the read voltage VR is performed by dividing the wire capacitance. Therefore, in the process of generating the read voltage VR, there is no need for an analog voltage at all.

That is, in the process of generating the read voltage VR, there is no circuit that requires a DC standby current. Therefore, the absence of this circuit allows reading operations to be performed with less power consumption.

The waveform diagrams of FIGS. 11A to 14G do not show the waveform of the signal used to control the SA (sense amplifier) 7.

15A to 15E are diagrams showing waveforms for the read verification operation for the condition that the variable resistance storage element Re is in the LRS, and FIGS. 16A to 16E are diagrams showing the waveforms used for the variable resistance storage element Re in the LRS A diagram of the waveform of the read verification operation of the HRS status. The SA (Sense Amplifier) 7 used to perform the read verification operation has a configuration that has been explained with reference to FIG. 10.

When the potential appearing on the word line WL connected to the memory cell MC serving as the read object rises at time T3, the potential of the bit line BL is discharged by flowing the cell current through the memory cell MC The program begins.

Under the conditions of the LRS shown in FIGS. 15A to 15E, the speed of the discharge process is higher. In the period beginning at time T34, the potential appearing on the sensing bit line (or the common bit line CBL) becomes a level not higher than the reference potential VREF. Time T4 is the time after a time margin has elapsed since time T34. At time T4, the bit line isolation signal BLI is turned off and the SA enable signal SAEN is set to the H level in order to activate the SA (sense amplifier) 7 shown in FIG. 10.

The potential appearing on the sensing node is supplied to an external bus as output data through the I/O buffer 9 used in the variable resistance memory device shown in FIG. 4.

In the case of the HRS shown in FIGS. 16A to 16E, even at time T4, the sensing node on the CBL side maintains a state higher than the original reference potential VREF. Therefore, the logic of the output data supplied to the external bus is the inverse logic of the logic for the LRS condition.

The SA (Sense Amplifier) 7 shown in FIG. 10 is a cross latch type single-ended sense amplifier. The SA (sense amplifier) 7 is activated only during the period in which the SA (sense amplifier) 7 needs to be activated.

Sense amplifiers using components such as operational amplifiers need to be placed in an activated state all the time. However, unlike sense amplifiers that use components such as operational amplifiers, the configuration of SA (Sense Amplifier) 7 and the system adopted thereby are designed so that the sense amplifier operation itself requires almost no DC current.

According to the first embodiment described above, in the operation for generating the read voltage VR, there is no need for an analog circuit that consumes a large amount of power. The process of precharging the bit line BL can be completed by only changing the state of the switch to allow the read voltage VR to be set on the desired bit line BL. Therefore, power consumption can be reduced.

In addition, the wire capacitance ratio for determining the read voltage VR is determined by the properties of wires produced as a batch in the semiconductor manufacturing process. In this case, these attributes include thickness, depth, and material. Therefore, the wire capacitance ratio can be specified with relatively high accuracy. In addition, even if there is a change in the voltage indicating the amount of charge precharged to one or more bit lines BL, the charge is still shared with other bit lines BL later. Therefore, when the read voltage VR is generated, the error component of the voltage representing the amount of charge precharged to one or more bit lines BL attenuates to a fraction. As a result, the read voltage VR can be set with relatively high accuracy.

It should be noted that in the configuration of SA (Sense Amplifier) 7 shown in FIG. 10, during the process of amplifying or sensing the voltage appearing on the bit line BL, in order to avoid the The interference caused by the amplitude of the voltage uses the voltage control of the bit line isolation signal BLI to isolate the common bit line CBL and the load on the bit line side from the sensing node of the SA (sense amplifier) 7 during the amplification operation. It is therefore possible to avoid this interference and thus perform the sensing operation at a high speed.

2: The second embodiment

FIG. 17 is an enlarged view showing the configuration of the memory cell array according to the second embodiment and the connection between the memory blocks 1_0 and 1_1 of the memory cell array and SA (sense amplifier) 7.

The configuration of the memory cell array according to the second embodiment is divided into two memory blocks 1_0 and 1_1, each of the two memory blocks 1_0 and 1_1 has a corresponding memory cell array 1 shown in FIG. 5 The storage capacity of the storage capacity. The two memory blocks 1_0 and 1_1 are connected to an SA (sense amplifier) 7.

Each of the memory blocks 1_0 and 1_1 uses a memory cell MC configured to form a matrix consisting of N columns and four rows. The storage capacity of each of the memory blocks 1_0 and 1_1 is the same as the storage capacity of the memory cell array 1 shown in FIG. 5.

However, each of the memory blocks 1_0 and 1_1 is different from the memory cell array 1 shown in FIG. 5 in that: each of the memory blocks 1_0 and 1_1 includes Refer to at least one row of the reference section 1R of the memory cell MCr.

In the memory cell array shown in FIG. 17, each of the memory blocks 1_0 and 1_1 has a common line isolation switch section 6B and a discharge switch 6C each having the configuration explained previously . In the memory block 1_0, the SA (sense amplifier) 7 is connected to the memory cell MC or the reference memory cell MCr via the common line isolation switch section 6B and the common bit line CBL0. For the same reason, in the memory block 1_1, the SA (sense amplifier) 7 is connected to the memory cell MC or the reference memory cell MCr via the common line isolation switch section 6B and the common bit line CBL1.

It should be noted that in the connection shown in FIG. 17, the connection between SA (sense amplifier) 7 and common bit line CBL0 and the connection between SA (sense amplifier) 7 and common bit line CBL1 are not related to SA (Sense amplifier) 7 is symmetrical. Therefore, under some conditions, the wire capacitance Ccbl of the common bit line CBL0 may be different from the wire capacitance Ccbl of the common bit line CBL1. In order to make the wire capacitance Ccbl of the common bit line CBL0 the same as the wire capacitance Ccbl of the common bit line CBL1, it is necessary to make the memory block 1_0 and the memory block 1_1 symmetrical about the SA (sense amplifier) 7. That is, if SA (Sense Amplifier) 7 is used as a mirror, it is necessary to layout memory block 1_0 and memory block 1_1 so that memory block 1_0 becomes an object and memory block 1_1 becomes memory block 1_0 The mirror image, or the memory block 1_1 becomes an object and the memory block 1_0 becomes the mirror image of the memory block 1_1.

In FIG. 17, in order to distinguish the row selection signal YSW in the memory block 1_0 and the memory block 1_1 from each other, the suffix number 0 is added to the reference symbol YSW to indicate that the row selection signal YSW in the memory block 1_0 The row selection signal under the condition is to form the reference symbol YSW0 representing the row selection signal in the memory block 1_0. On the other hand, in the case of the memory block 1_1, the suffix number 1 is appended to the reference symbol YSW forms a reference symbol YSW1 representing the row selection signal in the memory block 1_1.

For the same reason, in order to distinguish the word lines WL in the memory block 1_0 and the memory block 1_1 from each other, the suffix number 0 is added to the reference symbol WL to indicate the condition of the memory block 1_0 The word line in the memory block 1_0 forms the reference symbol WL0 representing the word line in the memory block 1_0. On the other hand, in the case of the memory block 1_1, the suffix number 1 is appended to the reference symbol WL to form a representation The reference symbol WL1 of the word line in the memory block 1_1.

It should be noted that the reference symbol Ref.WL represents the word line used to control the reference memory cell MCr. In the same way as the row selection signal YSW and the word line WL, in order to distinguish the word lines WL used to control the reference memory cell MCr in the memory block 1_0 and the memory block 1_1, in the memory block 1_0 Under the situation, the suffix number 0 is appended to the reference symbol Ref.WL to form the reference symbol Ref.WL0, and in the memory block 1_1 situation, the suffix number 1 is appended to the reference symbol Ref. WL to form the reference symbol Ref.WL1.

The latch circuit 72 controlled by the inverted BL precharge signal/BLPRE is connected to both the common bit lines CBL0 and CBL1.

FIG. 18 is a diagram of a circuit of a complementary signal differential sense amplifier 7 ideally suitable for the configuration shown in FIG. 17.

The difference between the SA (Sense Amplifier) 7 shown in FIG. 18 and the SA (Sense Amplifier) 7 shown in FIG. 10 is that in the condition of the SA (Sense Amplifier) 7 shown in FIG. 18, the The NMOS transistor 52 used in the SA (Sense Amplifier) 7 shown in FIG. 10, and the NMOS transistor 51 is additionally connected between the sensing bit reference line /SABL and the common bit line CBL1.

The bit line isolation signal BLI is used to simultaneously control the NMOS transistor 51 connected between the sensing bit reference line /SABL and the common bit line CBL1 and between the sensing bit line SABL and the common bit line CBL0.ofNMOS transistor 51.

Other configurations of the latch circuit 72 used in the SA (sense amplifier) 7 shown in FIG. 18 and their configuration of the latch circuit 72 used in the SA (sense amplifier) 7 shown in FIG. 10 same.

In the configuration shown in FIG. 18 as described above, when the storage state of the memory cell MC is read from the memory block 1_0 or the memory block 1_1, another common bit line is connected to the reference memory Perform a sensing operation in the state of the somatic MCr. At this time, the read operation is also performed on the reference memory cell MCr. Therefore, the reference potential changes dynamically. That is, the reference potential becomes lower. The storage state of the memory cell implies HRS or LRS.

The resistance of the variable resistance storage element Re used in the reference memory cell MCr is preset to a value between the resistance of the MC in the HRS and the resistance of the MC in the LRS. Ideally, the value between the resistance of the MC in the HRS and the resistance of the MC in the LRS is about the middle value between the resistance of the MC in the HRS and the resistance of the MC in the LRS.

This sensing method has the advantage that even if the sense amplifier 7 operates at a high speed, there is never a malfunction. Generally speaking, to a certain extent, there are changes in the characteristics of the memory cell MC and changes in the bias voltage used to generate the reference voltage, such as the power supply voltage Vdd. However, according to this sensing method, the reference potential is dynamically changed to follow the bit line potentials affected by the changes. Therefore, SA (Sense Amplifier) 7 hardly performs failures caused by such changes, so that it does not take time to confirm logic. Therefore, this operation can be performed at a high speed.

It should be noted that the determination of which of the memory blocks 1_0 and 1_1 is selected as the read object and which of the memory blocks 1_0 and 1_1 is selected as the reference, for example, the variable shown in FIG. 4 The predecoder 3 used in the resistive memory device recognizes the predetermined bit of the input address as the block selection address. In the column driving circuit 4, a WL driver unit 4A and a CSW driver unit 6A are provided for each memory block. In addition, in the column driving circuit 4, a block selector having the same configuration as that of the X selector 20 is provided.

The block selector decodes the block selection address received from the predecoder 3, thereby driving the two WL driver units 4A provided for each block to select the memory cell MC and driving the other WL driver unit 4A to select Refer to the memory cell MCr. In addition, the block selector controls the two CSW driver units 6A provided for each block, so that the block including the memory cell MC serving as the read object and the block that does not include the memory cell MC serving as the read object The block performs different row selection operations.

It should be noted that the details of the block selector will be explained later in the description of another embodiment.

19A to 19E are timing diagrams showing the waveforms of the operation for the following conditions: the memory block is in a manner similar to the first typical operation performed by the first embodiment as explained above with reference to FIGS. 11A to 11E Subject to the setting of the read voltage VR. 20A to 20D are timing diagrams showing waveforms used for the sensing operation in LRS. 21A to 21D are timing diagrams showing waveforms used for the sensing operation in HRS.

At time T1 shown in FIGS. 19A to 19E, a precharge operation is started. At time T1, row selection signals YSW0<0> and YSW1<0> have been preset to H level, so that in both memory blocks 1_0 and 1_1, bit line BL<0> is precharged to power supply The voltage of the device is Vdd.

Select a total of six other bit lines BL0<3:1> and BL1<3:1> of memory blocks 1_0 and 1_1 respectively, and set the six other bit lines BL0<3:1> and BL1<3: 1>Connect to its common bit line in order to perform the pre-charge procedure. It should be noted that the number of bit lines to be selected can be arbitrarily determined. That is, the number of bit lines to be selected is any number within the range between the minimum value of 0 and the maximum value of 6.

In the period between time T2 and T3, the read voltage VR is generated. The magnitude of the read voltage VR is almost determined by the ratio of the precharge bit line count and the charge shared bit line count. In this situation, the precharge bit line count is the number of bit lines undergoing the precharge process, and the charge sharing bit line count is the number of bit lines sharing the charge accumulated in the precharge process.

At time T3, the potentials on the read object bit line BL0<0> and the reference word line Ref.WL appearing in the memory block 1_0 simultaneously rise to a high level. Therefore, the cell current of the read time flows to the memory cell MC, and the reference current flows to the reference memory cell MCr.

The resistance of the reference resistor Re of the reference memory cell MCr has been set to a value between the resistance of the variable resistance storage element Re in the HRS and the resistance of the variable resistance storage element Re in the LRS. Therefore, as is obvious from the waveform shown in FIG. 19E, the potentials appearing on the bit line and the reference bit line change.

Figure 20D shows the discharge curve for LRS, and Figure 21D shows the discharge curve for HRS.

At time T4, the potential of the bit line isolation signal BLI decreases, and the potential of the SA enable signal SAEN increases, so that the sensing operation of the SA (sense amplifier) 7 starts.

In the case of LRS, the potential appearing on the common bit line CBL0 connected to the memory cell MC undergoes a transition on the low side. Therefore, after the sensing operation has been completed, the potential appearing on the common bit line CBL0 connected to the memory cell MC is pulled down to the reference voltage Vss. On the other hand, in the case of HRS, the potential appearing on the common bit line CBL0 connected to the memory cell MC undergoes a transition on the high side. Therefore, after the sensing operation has been completed, the potential appearing on the common bit line CBL0 connected to the memory cell MC is pulled up to the power supply voltage Vdd.

It should be noted that, contrary to the operation described above, if the memory cell MC in the memory block 1_1 is selected, the reference resistor Rer in the memory block 1_0 is selected.

The basic operation is the same as the operation described above.

Under the condition of the first embodiment, SA (Sense Amplifier) 7 has a configuration similar to that shown in FIG. 10. However, the read voltage VR must be supplied, so that it cannot be said that the analog voltage is completely unnecessary.

Under the condition of the second embodiment, on the other hand, due to the discharge process of the reference memory cell, the analog reference voltage is automatically generated, making it possible to perform a differential read operation using the dynamically changed reference voltage. Therefore, it is not necessary to supply the read voltage VR from a source outside the SA (Sense Amplifier) 7, and therefore it is not necessary to supply the analog voltage at all. As a result, it is possible to perform a read verification operation that consumes less power.

3: The third embodiment

In the case of the first embodiment, one memory block is connected to one SA (Sense Amplifier) 7. However, it is also possible to provide many memory blocks in advance and the configuration of one of the memory blocks to be connected to the sense amplifier 7 can be arbitrarily selected from the many memory blocks provided in advance. This configuration provides more generality and allows fine control of the read voltage VR.

The third embodiment provides a memory cell array with a structure that provides better generality and finer setting of the read voltage VR.

FIG. 22 is a diagram showing the configuration of the memory cell array and the connection between the sense amplifier 7 and the memory block according to the third embodiment.

This embodiment has a configuration in which a plurality of memory blocks are connected in parallel to a common bit line. In the following description, the common bit line to which a plurality of memory blocks are connected in parallel is called a global bit line GBL, and the bit line BL in each of the memory blocks is called Local bit line LBL.

The third embodiment is configured so that, in each memory block with N columns and four rows, the whole area can be made by using the isolating switch 61<3:0> of the common line isolating switch section 6B. The bit line GBL and the local bit line LBL<3:0> are selectively connected to each other. By using the discharge switch 62<3:0> of the discharge switch 6C, the local bit line LBL<3:0> can be selected as the discharge object.

In this embodiment, as shown in FIG. 22, (K-1) memory blocks each having this configuration are connected in parallel to the same global bit line GBL common to the memory blocks. (K-1) memory blocks are represented by reference numbers 1_0, 1_1,..., 1_(K-1), and 1_K, respectively.

In the design of this hierarchical structure of the bit line BL, for all memory blocks, the memory cell row count N and the memory cell row count M can each be set to any arbitrary number. In addition, the memory block count K can also be set to any arbitrary number.

Very similar to the SA (Sense Amplifier) 7 used in the memory cell array 1 shown in Figure 5, the SA (Sense Amplifier) 7 connected to the global bit line GBL is also a single-ended sense amplifier. And therefore, it is necessary to provide the reference potential VREF from an external source to the sensing node of SA (Sense Amplifier) 7.

Very similar to the common bit line CBL0 used in the memory cell array 1 shown in FIG. 5, the global bit line GBL is connected to the precharge transistor 71, which is supplied to the precharge transistor 71 The inverted BL precharge signal/BLPRE control of the gate electrode.

Figures 23A to 23H are timing diagrams showing the waveforms used for the operation of the following conditions: the setting of the read voltage VR is executed on any local bit line of all memory blocks and the word line of memory block 1_0 is adopted WL_0<0> is used as the word line WL of the read object.

At time T1 on the waveform shown in FIG. 23A, the global bit line GBL is precharged to the power supply voltage Vdd. At this time, all the local bit lines LBL of all memory blocks are in a state of being disconnected from the global bit line GBL. Therefore, the power supply voltage Vdd is only precharged to the global bit line GBL. The local bit line LBL has been discharged and is preset as the reference voltage Vss.

At time T2 on the waveform shown in FIG. 23B, any local bit line LBL including the local bit line LBL_0<0> of the memory block 1_0 is selected. In detail, the selected local bit line LBL includes the local bit line LBL_0<0> that serves as a read object controlled by the row selection line YSW_0<0>, and the local bit line LBL_0<0> controlled by the row selection line YSW_0<0 >The row selection line YSW_0<3:1> of the same memory block 1_0 and other local bit lines LBL controlled by the row selection lines YSW_i<3:0> of other memory blocks, where i is between 1 and An integer within the range of M. These local bit lines LBL are selected by activating their respective row selection lines YSW.

By selecting these local bit lines LBL, the precharged charge is discharged to the selected local bit line LBL so as to share the charge with the selected local bit line LBL. Therefore, a read voltage VR having a predetermined magnitude is set on each of the selected local bit lines LBL.

After the process of sharing the charge has been performed, the voltage appearing on the local bit line LBL decays from the voltage appearing during the precharge to the read voltage VR having a magnitude predetermined by the wire capacitance ratio.

The read voltage VR obtained due to attenuation is expressed by the equation (2) given below:

VR=Vdd×Cgbl/(Cgbl+Clbl×Nvss) (2)

In equation (2), the symbol Cgbl represents the capacitance of the global bit line GBL, and the symbol Clbl represents the capacitance of each local bit line LBL. In addition, the symbol Nvss represents the number of bit lines BL sharing charges after resetting to the reference voltage Vss in a discharge process.

Then, the resistance of the variable resistance storage element Re is read from the memory cell MC connected to the local bit line LBL_0<0> selected by the row selection line YSW_0<0>.

Specifically, at the time T3 shown in FIGS. 23A to 23H, all the row selection lines except for the row selection line YSW_0<0> are set to the L level indicating the deactivated state. Therefore, all the row selection lines except the local bit line LBL_0<0> are disconnected from the global bit line GBL.

At time t3, only the word line WL_0<0> in the memory block 1_0 rises to the H level. Therefore, the discharge process that allows the cell current to flow is performed at a speed that depends on whether the variable resistance storage element Re of the memory cell MC connected to the word line WL_0<0> is in the LRS or the HRS.

In the same manner as in the first embodiment, a single-ended SA (sense amplifier) 7 is activated to sense the potential of the voltage appearing on the local bit line LBL undergoing the discharge process through the global bit line GBL.

In this embodiment, the capacitance of the global bit line GBL is much larger than the capacitance of the local bit line LBL, so that the pre-charging process is only executed on the global bit line GBL. However, if it is desired to further increase the amount of precharged charge, any arbitrary number of local bit lines LBL can be used as an additional precharge object.

In this embodiment, as is apparent from FIG. 22, the number of local bit lines LBL that can withstand charge sharing is extremely large. Therefore, it is possible to set any arbitrary reference potential VREF in fine steps according to the equation (2) given above.

4: Fourth embodiment

According to the fourth embodiment, a configuration capable of performing a differential read operation within the hierarchical structure implemented as the structure of the bit line BL by the third embodiment is proposed.

FIG. 24 is a block diagram showing the configuration of a variable resistance memory device usually implemented as an IC chip.

As in the case of the third embodiment shown in FIG. 22, there are K memory blocks. As in the same situation as in the third embodiment shown in FIG. 17, each of the memory blocks includes a memory cell row with a reference memory cell MCr. The reference sign 1R in FIG. 24 represents a reference segment of the memory cell row with the reference memory cell MCr.

The structure of the memory cell array used in the variable resistance memory device shown in FIG. 24 is different from those shown in FIG. 22 and FIG. 17 in that: under the condition of the structure shown in FIG. 24 , K memory blocks have two global bit lines, that is, the global bit line GBL0 connected to odd-numbered memory blocks and the global bit line GBL1 connected to even-numbered memory blocks.

The global bit lines GLB0 and GLB1 correspond to the common bit lines CBL0 and CBL1 used in the variable resistance memory device shown in FIG. 17, respectively. When one of the global bit lines GLB0 and GLB1 is connected to the memory cell MC on the read side, the other global bit line is controlled to connect with the reference memory cell MCr. That is, under the condition of the fourth embodiment, the common bit lines CBL0 and CBL1 used in the variable resistance memory device shown in FIG. 17 are placed in a hierarchical structure, and the common bit line CBL0 Each of CBL1 and CBL1 is assigned to (K/2) memory blocks connected in parallel to the common bit line.

The variable resistance memory device shown in FIG. 24 newly includes an extra block decoder 40 in the column driving circuit 4 to serve as a decoder for selecting memory blocks.

The block decoder 40 usually receives the address bits X2 and X3 to be decoded (instead of the address bits X0 and X1 of the configuration shown in FIG. 6) in order to select a memory block. The block decoder 40 then outputs the memory block selection signals from the output terminals of the inverters INV4 to INV7. The memory block selection signal is supplied to the WL driver unit 4A and the CSW driver unit 6A associated with one of the memory blocks.

25A to 25K are timing diagrams showing waveforms for typical operations performed in the fourth embodiment.

In these typical operations, at time T1, the global bit lines GBL0 and GBL1 are precharged to the power supply voltage Vdd.

Then, discharge the charges precharged to the global bit lines GBL0 and GBL1 to any arbitrary number of local bit lines LBL so as to share the charge with the local bit lines LBL, and any number of local bit lines LBL Including the local bit line LBL<0> of the memory block 1_0 which is the first of the odd-numbered memory blocks. In the waveform shown in FIG. 25C, the local bit line LBL<0> of memory block 1_1 and the local bit of memory block 1_0 are taken as the first of the even-numbered memory blocks The line LBL<0> serves as a line for sharing charges. However, any other arbitrary local bit line LBL can also be adopted as the line for sharing charges.

The local bit line LBL taken as a line for sharing charges can be arbitrarily selected from any memory block. In addition, the number of local bit lines LBL to be used as lines for sharing charges, which are arbitrarily selected from any memory block, is also arbitrary.

The read voltage VR is represented by equation (2). As shown by this equation, the magnitude of the read voltage VR is determined by the wire capacitance according to the number of local bit lines LBL to be used as lines for sharing charges, which are arbitrarily selected from any memory block.

In this situation, the local bit line LBL<0> of the memory block 1_0 is used as the object from which data is read, and the reference memory cell MCr in the memory block 1_1 is used as the reference potential for reading from it. object. Therefore, as is apparent from the waveforms shown in FIGS. 25G and 25H, the potentials appearing on the two word lines WL are activated.

Therefore, the dynamically decreasing potential of the global bit line GBL1 connected to the reference memory cell MCr is taken as a reference, and in the memory cell MC that reads data from the global bit line GBL0 in the HRS or LRS, in In the differential sensing operation, the voltage level that occurs during the discharging operation is sensed.

The method for selecting a reference memory cell MCr, the location of the local bit lines LBL for sharing charges, and the number of these local bit lines LBL can be arbitrarily determined. In addition, any arbitrary number of local bit lines LBL can be added as precharge objects.

According to the fourth embodiment, a stable operation based on differential sensing can be performed with fine setting of the read voltage VR with a wide adjustment range. Therefore, even if the resistance of the variable resistance storage element Re changes with the passage of time, when the read voltage VR is finely adjusted for the change in resistance to an appropriate read voltage VR, the read operation can still be performed at a high speed and with a high degree of reliability.

5: The fifth embodiment

FIG. 26 is a block diagram showing the configuration of the memory cell array according to the fifth embodiment. The difference between the memory cell array according to the fifth embodiment shown in FIG. 26 and the memory cell array according to the fourth embodiment shown in FIG. 24 is that under the condition of the fifth embodiment, each memory cell The block does not include the reference zone 1R.

Under the condition of the fifth embodiment, the reference potential cannot be dynamically changed by using the reference memory cell MCr to follow the potential generated by the memory cell MC.

In the case of the fifth embodiment, in order to control the reference potential to a level between the level of HRS and the level of LRS, a reference voltage generated due to charge sharing is used instead of an analog voltage generated by an external source .

27A to 27H are timing diagrams showing waveforms for typical operations performed according to the fifth embodiment.

In the case of the fifth embodiment, due to the necessity of setting the read voltage VR, the local bit line LBL<0> associated with the row selection signal YSW_0<0> shown in FIG. 27B is used as the read object. As the object of the charge sharing program. However, local bit lines other than the local bit line LBL<0> can also be arbitrarily selected to serve as the object of the charge sharing program.

In this situation, the potential of the read voltage VR is determined by the number of local bit lines connected to the global bit line GBL0, and the number of local bit lines LBL connected to the global bit line GBL1 is determined The potential of the reference potential VREF.

As shown by the waveform of FIG. 27H, when the reference potential VREF is set to an appropriate level lower than the read voltage VR, the single-ended SA (sense amplifier) 7 performs a voltage sensing operation.

In the system according to the fifth embodiment, compared with the method using the reference memory cell MCr, the change has a greater effect on the characteristics of the memory cell MC. However, it is not necessary to provide the reference memory cell MCr in each memory block. Therefore, the bit cost can be reduced corresponding to the difference in the number of eliminated reference memory cells MCr. In addition, there is no need for an analog voltage generated by a generator outside the memory cell array. Therefore, the power consumption can also be reduced corresponding to the difference in the external generator used to generate the analog voltage.

6: Modify

In the first to fifth embodiments described so far, the timing of the start of the discharge process is determined by the trigger for activating the word line WL.

However, the timing of the start of the discharge process does not need to be determined by the trigger for activating the word line WL. For example, the timing of the start of the discharge process can also be determined by the trigger for activating the row selection signal YSW.

28A to 28H are timing diagrams of waveforms for operations performed by the modified version of the third embodiment shown in FIGS. 23A to 23H.

At time T1 in the operation represented by the waveforms shown in FIGS. 28A to 28H, the potential appearing on the word line WL_0<0> connected to the memory cell MC serving as the read object is usually equal to the precharge global bit The timing of the same timing of the element line GBL is raised in advance. At this stage, there is no potential difference between the local bit line LBL and the source line SL. Therefore, the read time discharge process of the memory cell MC does not start.

Later, at time T2, the first charge sharing procedure is performed on the local bit line LBL except for the local bit line LBL serving as the read object. At this stage, the final potential of the read voltage VR is not confirmed.

Then, at time T3, the charge after the first charge sharing process is shared with the bit line BL serving as the read object. As a result, the discharge process for one local bit line LBL further reduces the read voltage VR, and the read time cell current flows to the memory cell MC.

The final magnitude of the read voltage VR is lower than the potential determined by the first charge sharing procedure by a downward difference. However, since the magnitude of the downward difference has been estimated, the number of local bit lines LBL subjected to the first charge sharing process can be determined by predicting the downward difference.

In the case of the verification operation initiated by the word line flip-flop, due to the high layout density of the word line WL normally defined by the lower layer such as a polysilicon layer, the time constant of the word line change is relatively large. Therefore, under some conditions, the delay of the discharge verification operation and the dependence on the address of the discharge verification operation may occur. The dependence on the address of the discharge verification operation is the following phenomenon: depending on the position of the memory cell array, the change of the potential appearing on the word line WL has a greater effect on the delay of the discharge verification operation, causing the speed of the discharge process to change .

Under the conditions of these embodiments, the timing of the flip-flop generated by the row select signal YSW can be changed to change the timing of the start of the discharge process, so that compared with the state of the verification operation initiated by the word line flip-flop, it can be faster The method executes a uniform verification discharge process in the memory cell array.

The present invention contains an invention subject related to the subject of the invention disclosed in the Japanese priority patent application JP 2010-170934 filed at the Japan Patent Office on July 29, 2010. The entire content of the case is hereby incorporated by reference. In this article.

Those familiar with this technology should understand that depending on design requirements and other factors, various modifications, combinations, sub-combinations and changes can occur, as long as these various modifications, combinations, sub-combinations and changes are within the scope of the attached patent application or their equivalent Within the scope of things.

<p>1. . . Memory cell array</p><p>1M. . . First wire layer</p><p>1R. . . Reference section</p><p>1_0. . . Memory block</p><p>1_1. . . Memory block</p><p>1_(K-1). . . Memory block</p><p>1_K. . . Memory block</p><p>3. . . Predecoder</p><p>4. . . Column drive circuit</p><p>4A. . . WL drive unit</p><p>6. . . Row switch circuit/CSW (row switch) circuit</p><p>6A. . . CSW drive unit</p><p>6B. . . Common line isolation switch section</p><p>6C. . . Discharge switch section</p><p>7. . . SA (Sense Amplifier)</p><p>9. . . I/O (input/output) buffer</p><p>10. . . Write/erase drive</p><p>11. . . Control circuit</p><p>16. . . Logical block</p><p>20. . . X selector</p><p>twenty one. . . PMOS transistor</p><p>twenty two. . . NMOS transistor</p><p>twenty three. . . PMOS transistor</p><p>twenty four. . . NMOS transistor</p><p>30. . . Y selector</p><p>40. . . Block decoder</p><p>51. . . NMOS transistor</p><p>52. . . NMOS transistor</p><p>61&lt;0&gt;. . . Isolating switch</p><p>61&lt;1&gt;. . . Isolating switch</p><p>61&lt;2&gt;. . . Isolating switch</p><p>61&lt;3&gt;. . . Isolating switch</p><p>62&lt;0&gt;. . . Discharge switch</p><p>62&lt;1&gt;. . . Discharge switch</p><p>62&lt;2&gt;. . . Discharge switch</p><p>62&lt;3&gt;. . . Discharge switch</p><p>71. . . Pre-charged transistor</p><p>72. . . Latch circuit</p><p>100. . . Substrate</p><p>101. . . Lower electrode</p><p>102. . . Insulator film</p><p>103. . . Conductor film</p><p>104. . . Plug/nitride film</p><p>105. . . Positioning pad</p><p>AT. . . Access transistor</p><p>AT1. . . Access transistor</p><p>AT2. . . Access transistor</p><p>BL. . . Bit line</p><p>BLI. . . Bit line isolation signal</p><p>BL&lt;0&gt;. . . Bit line</p><p>BL&lt;1&gt;. . . Bit line</p><p>BL&lt;2&gt;. . . Bit line</p><p>BL&lt;3&gt;. . . Bit line</p><p>BL&lt;3:1&gt;. . . Bit line</p><p>BL&lt;0&gt; to BL&lt;M-1&gt;. . . Bit line</p><p>BL0&lt;0&gt;. . . Read object bit line</p><p>BL0&lt;3:1&gt;. . . Bit line</p><p>BL1&lt;3:1&gt;. . . Bit line</p><p>BLC. . . Bit line contacts</p><p>/BLPRE. . . Inverted BL precharge signal</p><p>CBL. . . Common bit line</p><p>CBL0. . . Common bit line</p><p>CBL1. . . Common bit line</p><p>Cbl. . . Wire capacitance of bit line</p><p>Ccbl. . . Common bit line wire and contact capacitance/common bit line wire capacitance</p><p>Cgbl. . . Capacitance of global bit line</p><p>Clbl. . . Capacitance of local bit line</p><p>D. . . Drain electrode of access transistor</p><p>ERS. . . Erase signal</p><p>GBL. . . Global bitline</p><p>GBL0. . . Global bitline</p><p>GBL1. . . Global bitline</p><p>GND. . . Grounded</p><p>HRS. . . The high resistance state of the variable resistance storage element Re</p><p>Ie. . . Erase current</p><p>INV0 to INV3. . . inverter</p><p>INV4 to INV7. . . inverter</p><p>INV8 to INV11. . . inverter</p><p>INV12 to INV15. . . inverter</p><p>INV16. . . inverter</p><p>INV21. . . inverter</p><p>Iw. . . Write current</p><p>LBL&lt;0&gt;. . . Local bit line</p><p>LBL&lt;3:0&gt;. . . Local bit line</p><p>LRS. . . Low resistance state of variable resistance storage element Re</p><p>MC. . . Memory cell</p><p>MCr. . . Reference memory cell</p><p>NAND0 to NAND3. . . NAND circuit</p><p>NAND4 to NAND7. . . NAND circuit</p><p>NAND8. . . NAND circuit</p><p>NAND12. . . NAND circuit</p><p>RD. . . Data reading signal</p><p>Re. . . Variable resistance storage resistor/variable resistance storage element</p><p>Ref.WL0. . . Used to control the ZigZag of the reference memory cell</p><p>Ref.WL1. . . Used to control the word line of the reference memory cell</p><p>Rer. . . Reference resistor</p><p>S. . . Source electrode of access transistor</p><p>SABL. . . Sensing bit line</p><p>/SABL. . . Sensing bit reference line</p><p>SAEN. . . SA enable signal</p><p>/SAEN. . . SA disable signal/inverted SA enable signal</p><p>SL. . . Source line</p><p>SL&lt;0&gt; to SL&lt;M-1&gt;. . . Source line</p><p>SLC. . . Source line contact</p><p>T1. . . time</p><p>T2. . . time</p><p>T3. . . time</p><p>T34. . . time</p><p>T4. . . time</p><p>Vdd. . . Power supply voltage</p><p>VR. . . Read voltage</p><p>VREF. . . Reference potential</p><p>Vss. . . Reference voltage</p><p>WL. . . Word line</p><p>WL0. . . Word line</p><p>WL1. . . Word line</p><p>WL&lt;0&gt;. . . Word line</p><p>WL&lt;1&gt;. . . Word line</p><p>WL&lt;N:0&gt;. . . Word line</p><p>WL_0&lt;0&gt;. . . Word line</p><p>WLEN. . . WL select enable signal</p><p>WRT. . . Write signal</p><p>X0. . . X address signal bit/address bit</p><p>X0, X1. . . X address signal</p><p>X1. . . X address signal bit/address bit</p><p>X2. . . Address bit</p><p>X3. . . Address bit</p><p>X_SEL0 to X_SEL3. . . X selection signal</p><p>X_SEL&lt;0&gt; to &lt;N-1&gt;. . . X selection signal</p><p>Y0. . . Y address signal bit</p><p>Y0, Y1. . . Y address signal</p><p>Y1. . . Y address signal bit</p><p>YSW0. . . Line selection signal</p><p>YSW0&lt;0&gt;. . . Line selection signal</p><p>YSW1. . . Line selection signal</p><p>YSW1&lt;0&gt;. . . Line selection signal</p><p>YSW&lt;0&gt;. . . Line selection signal</p><p>YSW&lt;1&gt;. . . Line selection signal</p><p>YSW&lt;2&gt;. . . Line selection signal</p><p>YSW&lt;3&gt;. . . Line selection signal</p><p>YSW&lt;3:0&gt;. . . Line selection signal</p><p>YSW&lt;3:1&gt;. . . Line selection signal</p><p>YSW&lt;3:2&gt;. . . Line selection signal</p><p>YSW_0&lt;0&gt;. . . Row selection line</p><p>YSW_0&lt;3:1&gt;. . . Row selection line</p><p>YSWEN. . . Y switch enable signal</p><p>/YSW&lt;3:0&gt;. . . Inverted line selection signal</p><p>Y_SEL. . . Y select signal</p><p>Y_SEL0 to Y_SEL3. . . Y select signal</p>

1A and 1B are diagrams each showing an equivalent circuit of a memory cell common to the embodiments;

2 is a cross-sectional view showing the structure of two adjacent memory cells of a variable resistance memory device;

3A and 3B are model diagrams each showing the direction of current flowing through the variable resistance storage element used in the memory cell and the typical magnitude of the voltage applied to the variable resistance storage element;

4 is a block diagram showing the variable resistance memory device according to the first embodiment;

FIG. 5 is an enlarged view showing the memory cell array used in the variable resistance memory device shown in FIG. 4;

Figure 6 is a diagram showing the logic circuit of the X selector;

Figure 7 is a diagram showing the logic circuit of the Y selector;

Figure 8 is a diagram showing the logic circuit of the WL driver unit;

Figure 9 is a diagram showing the logic circuit of the CSW driver unit;

Figure 10 is a circuit diagram showing a single-ended sense amplifier;

11A to 11E are timing diagrams showing waveforms used in the first typical operation;

12A to 12F are timing diagrams showing waveforms used in the second typical operation;

13A to 13G are timing diagrams showing waveforms used in the third typical operation;

14A to 14G are timing diagrams showing waveforms used in the fourth typical operation;

15A to 15E are timing diagrams showing the waveforms of the operation of the sense amplifier in the fourth typical operation;

16A to 16E are timing diagrams showing the waveforms of the operation of the sense amplifier in the fourth typical operation;

FIG. 17 is an enlarged view showing the memory cell array according to the second embodiment;

Figure 18 is a circuit diagram showing the sense amplifier;

FIGS. 19A to 19E are timing diagrams showing waveforms of operations that are similar to the first typical operation performed by the first embodiment as explained by referring to FIGS. 11A to 11E for the memory block. Understand the condition of reading the voltage setting;

20A to 20D are timing diagrams showing waveforms used in the sensing operation in LRS;

21A to 21D are timing diagrams showing waveforms used in the sensing operation in HRS;

22 is a diagram showing the configuration of the memory cell array and the connection between the sense amplifier and the memory block according to the third embodiment;

Figures 23A to 23H are timing diagrams showing waveforms for operations. These operations are performed on any local bit line of all memory blocks for setting the read voltage and take the word line WL_0 of memory block 1_0. &lt;0&gt; as the status of the word line WL of the read object;

24 is a block diagram of the configuration of a variable resistance memory device usually implemented as an IC chip;

25A to 25K are timing diagrams showing waveforms for typical operations performed in the fourth embodiment;

26 is a block diagram showing the configuration of the memory cell array according to the fifth embodiment;

27A to 27H are timing diagrams showing waveforms for typical operations performed according to the fifth embodiment; and

28A-28H are timing diagrams showing waveforms for operations performed by the modified version.