Magnetic memory, electronic system, memory and method for the same

Magnetic memory, electronic system, memory and method thereof

The present invention relates to a programmable memory device, such as a programmable resistance device used in a memory array.

Programmable resistance element usually means that the resistance state of the element can be changed after programming. The resistance state can be determined by the resistance value. For example, the resistive element can be a one-time programmable OTP (One-Time Programmable) element (such as an electrical fuse), and the programming method can apply a high voltage to generate a high current through the OTP element. When this large current flows through the OTP element through the open programming selector, the OTP element will be burned to a high or low resistance state (depending on whether it is a fuse or an anti-fuse) for programming.

Electrical fuse is a common OTP, and this kind of programmable resistance element can be polysilicon, silicide polysilicon, silicide, thermally isolated active area, metal, metal alloy or a combination thereof. The metal can be aluminum, copper or other transition metals. The most commonly used electrical fuse is siliconized polysilicon, which is made of complementary metal oxide semiconductor transistor (CMOS) gate and used as an interconnect. The electrical fuse can also be one or more contacts or vias, rather than internal connections of small segments. High current can burn contacts or interlayer points into a high resistance state. The electrical fuse can be an anti-fuse, where high voltage reduces the resistance instead of increasing the resistance. The anti-fuse can be composed of one or more contacts or interlayer points, and contains an insulator in between. The anti-fuse can also be coupled to the CMOS body by a CMOS gate, which contains a gate oxide layer as an insulator.

A traditional programmable resistive memory memory cell is shown in the first figure. The memory cell 10 includes a resistance element 11 and an N-type metal oxide semiconductor transistor (NMOS) programming selector 12. One end of the resistance element 11 is coupled to the drain of the NMOS 12, and the other end is coupled to the positive voltage V+. The gate of the NMOS12 is coupled to the select signal (SEL), and the source is coupled to the negative voltage V-. When a high voltage is applied to V+ and a low voltage is applied to V-, the resistive element 10 can be programmed, and the NMOS 12 can be turned on by increasing the programming select signal (SEL). One of the most common resistor elements is silicided polysilicon, which is the same material used when making MOS gates at the same time. The area of the NMOS programming selector 12 needs to be large enough to provide the required programming current for several microseconds. The programming current of silicide polysilicon is usually from a few milliamperes (for a fuse with a width of about 40 nanometers) to 20 mA (for a fuse with a width of about 0.6 micron). Therefore, the area of the electrical fuse memory cell using silicided polysilicon is often very large.

The programmable resistance element can be a reversible resistance element, which can be repeatedly programmed and reversibly programmed into a digital logic value "0" or "1". Programmable resistance elements can be manufactured from phase change materials, such as germanium (Ge), antimony (Sb), tellurium (Te) consisting of Ge2Sb2Te5 (GST-225) or including the composition of indium (In), tin (Sn) or selenium ( Se) GeSbTe materials. Through high-voltage short pulses or low-voltage long pulses, the phase change material can be programmed into an amorphous high-resistance state or a crystalline low-resistance state. The reversible resistance element can be a resistive random access memory (resistive memory RRAM), and the memory cell is composed of metal oxides between metal or metal alloy electrodes, such as platinum/nickel oxide/platinum (Pt/NiO/Pt) , Made of titanium nitride/zinc oxide/hafnium oxide/titanium nitride (TiN/TiOx/HfO2/TiN). The reversibility of the resistance state is changed through the polarity, intensity, and duration of the voltage or current pulse to produce or destroy the conductive filament. Another type of programmable resistive element similar to resistive random access memory (RRAM) is conductive bridge random access memory (CBRAM). This memory is based on electrochemical deposition and removal of metal ions in a solid electrolyte film between metal or metal alloy electrodes. The electrode can be an oxidizable anode and an inert cathode, and the electrolyte can be silver or copper doped chalcogenide glass such as germanium selenide (GeSe) Or sulfur selenide (GeS) and so on. The reversibility of the resistance state is changed through the polarity, intensity, and duration of the voltage or current pulse to create or destroy the conductive bridge.

As shown in the second figure a, a phase change memory (PCM) is another conventional programmable resistance element 20. The PCM memory cell includes a phase change material (Phase Change Material) film 21 and a bipolar transistor 22 as a programming selector, which has a P+ emitter 23, an N-type base 27 and a collector 25 (which is a P-type base) . One end of the phase change film 21 is coupled to the emitter 23 of the bipolar transistor 22, and the other end is coupled to the positive voltage V+. The N-type base 27 of the bipolar transistor 22 is coupled to the negative voltage V-, and the collector 25 is coupled to ground. Applying a proper voltage between V+ and-for a proper time, the phase change film 21 can be programmed to a high or low resistance state, depending on the voltage and duration. By convention, programming a phase change memory into a high-resistance state (or reset state) requires a voltage of 3V that lasts about 50ns and consumes about 300uA of current. Programming the phase change memory into a low resistance state (or setting state) requires a 2V voltage lasting about 300ns and consumes about 100uA current. This kind of memory cell requires a special process to properly isolate each memory cell, and therefore requires 3-4 more photomasks than the standard CMOS logic process, which makes it more expensive to manufacture.

Another programmable resistance element of phase change memory (PCM) is shown in Figure 2b. The phase change memory material includes a phase change film 21' and a diode 22'. The phase change film 21' is coupled between the diode anode 22' and the positive voltage V+. The cathode 22' of the diode is coupled to a negative voltage V-. Applying an appropriate voltage between V+ and V- for an appropriate period of time, the phase change film 21' can be programmed to a high or low resistance state, depending on the voltage and duration. Please see "Kwang-Jin Lee et al.,"A90nm1.8V512Mb Diode-Switch PRAM with 266MB/s Read Throughput,"International Solid-State Circuit Conference,2007,pp.472-273", the second figure c shows An example of using a diode as a programming selector for each phase change memory (PCM) memory cell. Although this technology can reduce the size of the PCM memory cell to only 6.8F2 (F stands for feature size), the diode requires a very complicated manufacturing process, such as selective epitaxial growth (SEG). As a result, the application of embedded PCM will become very expensive.

The third diagram a and the third diagram b show schematic diagrams of programming a magnetic memory (MRAM) memory cell 210 to be magnetically parallel (or state 0) and magnetically anti-parallel (or state 1) via the direction of current. The MRAM memory cell 210 is composed of a magnetic tunnel junction (MTJ) 211 and an NMOS programming selector 218. The magnetic tunnel junction 211 has multiple layers of ferromagnetic or antiferromagnetic stacks and metal oxides such as Al2O3 and MgO, which act as an insulator between the multiple layers. The magnetic tunnel junction 211 includes a free stacked layer 212 and a fixed stacked layer 213. Turn on the programming selector CMOS218, apply appropriate current to the magnetic tunnel junction (MTJ) 211, and the free layer stack 212 can be arranged magnetically parallel or antiparallel to the fixed layer stack 213. This depends on the current flowing out or flowing into the fixed layer stack. 213 depends. Therefore, the magnetic state can be programmed, and the state result can be determined by the resistance value, that is, the low resistance in the magnetic parallel state or the high resistance in the magnetic antiparallel state. State 0 or 1 resistance value is about 5kΩ or 10KΩ respectively, and the programming current is about +/-100-200μA. An example of programming MRAM memory cells is described in "2Mb Spin-Transfer Torque RAM with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read, "International Solid-State Circuit Conference, 2007, pp.480-481".

Diodes can also be made from polysilicon. The fourth figure a shows a cross section of a polysilicon diode. To form a polysilicon diode, polysilicon is implanted with N+ at one end and P+ at the other end. The distance Lc between the two ends contains an intrinsic dopant. Inherent dopants are slight N-type or P-type dopants caused by external diffusion or contamination, rather than deliberate doping. The silicide barrier layer is applied on the polysilicon to prevent the formation of silicide on the surface of the polysilicon, thereby preventing short circuits. The P+ and N+ ends of the polysilicon are brought out by the contacts to form the PN ends of the diode. As an example, for polysilicon diodes, see Ming-Dou Ker et al., "Ultra High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes with Polysilicon Diodes," IEEE Transaction of Circuit and System-II, Vol.54, No. 1, January 2007, pp. 47-51.

The fourth graph b shows the current-voltage characteristics of the polysilicon diode in the fourth graph a. Current current-voltage curves show useful diode behavior, for example, the threshold voltage of the diode is about 0.6V and the leakage current is less than 1nA. By changing the distance Lc, the breakdown voltage and leakage current of the polysilicon diode can be adjusted accordingly.

This patent is about an embodiment of a programmable resistance element memory cell using a diode as a programming selector. Programmable resistance elements can use standard complementary metal oxide semiconductor (CMOS) logic processes to reduce the size and cost of memory cells.

Therefore, the present invention provides a memory including: a plurality of memory storage units, at least one memory storage unit includes: a memory element having a first end and a second end, the first end is coupled to a first power supply voltage line; and a The first diode includes at least a first end and a second end, wherein the first end has a first type doping, the second end has a second type doping, and the second end of the first diode One end is coupled to the second end of the memory element, a second diode includes at least a first end and a second end, wherein the first end has a first type of doping, and the second end has a In the second type of doping, the second end of the second diode is coupled to the second end of the memory element, and the second end of the first diode is coupled to a second power supply voltage line , Wherein the first end of the second diode is coupled to the second or third power supply voltage line.

The doping of the first end or the second end of the first or second diode is manufactured by doping implantation of the source or drain of a complementary metal oxide semiconductor (CMOS) device, wherein at least A diode is constructed on a polysilicon substrate, wherein, by applying a voltage to the first, second and/or third power supply voltage lines, the first diode is turned on and the second diode is cut off Body to a logic state, or turning on the second diode to cut off the first diode to another logic state, the memory element is configured to be programmable to a different logic state.

Therefore, the present invention provides a memory including: a plurality of memory storage units, at least one memory storage unit includes: a memory element having a first end and a second end, the first end is coupled to a first power supply voltage line; and a The first diode includes at least a first end and a second end, wherein the first end has a first type doping, the second end has a second type doping, and the first diode has a The first end is coupled to the second end of the memory element, a second diode includes at least a first end and a second end, wherein the first end has a first type of doping, and the second end With a second type of doping, the second end of the second diode is coupled to the second end of the memory element, wherein the second end of the first diode and the second diode The first end of the body is coupled to a second power supply voltage line, wherein the doping of the first or second diode is implanted from the source or drain of a complementary metal oxide semiconductor (CMOS) device. Into manufacturing, where at least one diode is constructed on the polysilicon substrate, wherein, by applying a voltage to the first and second power supply voltage lines, the first diode is turned on and the second diode is cut off. The pole body enters a logic state, or turns on the second diode body to cut off the first diode body to another logic state, and the memory element is configured to be programmable to a different logic state.

Therefore, the present invention provides an electronic system, including: a processor; and a memory operably connected to the processor, the memory includes at least a plurality of memory storage units to provide data storage, each memory storage unit includes: a The memory element has a first end and a second end, the first end is coupled to a first power supply voltage line; and a first diode includes at least a first end and a second end, wherein the first end has A first type doping, the second end has a second type doping, the first end of the first diode is coupled to the second end of the memory element, and the The second terminal is coupled to the second power supply voltage line; a second pole body includes at least a first terminal and a second terminal, wherein the first terminal has a first type doping, and the second terminal has a The second type of doping, the second end of the second diode is coupled to the second end of the memory element, and the first end of the second diode is coupled to the second or third power source Voltage line; wherein the dopant of the first or second diode is implanted from the source or drain of a complementary metal oxide semiconductor (CMOS) device, wherein at least one diode It is built on a polysilicon substrate, wherein, by applying a voltage to the first, second and/or third power supply voltage lines, the first diode is turned on and the second diode is cut off to a logic state , Or turn on the second diode to cut off the first diode to another logic state, and the memory element is configured to be programmable to a different logic state.

Therefore, the present invention provides a method to provide a memory, including: providing a plurality of memory storage units, at least one memory storage unit includes at least (i) a memory element having a first end and a second end, the first end is coupled to A first power supply voltage line; and (ii) a first diode includes at least a first end and a second end, the first end has a first type of doping, and the second end has a second type of doping , The first and second dopants are manufactured by doping implantation of the source or drain of a complementary metal oxide semiconductor (CMOS) device, and the first end of the first diode is coupled to the The second end of the memory element and the second end of the first diode are coupled to a second power supply voltage line; (iii) a second diode includes at least a first end and a second end, the The first end has a first type of doping, and the second end has a second type of doping. The first and second doping are implanted from the source or drain of the CMOS device. The second The second end of the diode is coupled to the second end of the memory element and the first end of the second diode is coupled to the second or third power supply voltage line (iv) at least one and two poles The body is constructed on a polysilicon substrate, and the first, second and/or third power supply voltage lines are applied to the first, second and/or third power supply voltage lines in it, thereby turning on the first diode and cutting off the second diode to a logic State, or turning on the second diode to cut off the first diode to another logic state, the memory element is configured to be programmable to a different logic state.

Therefore, the present invention provides a magnetic memory including: a plurality of magnetic memory storage units, at least one magnetic memory storage unit includes: a magnetic memory element has a first end and a second end, and the first end is coupled to a first power supply voltage Line; and a first diode includes at least a first end and a second end, wherein the first end has a first type of doping, the second end has a second type of doping, the first two The first end of the pole body is coupled to the second end of the memory element, a second diode includes at least a first end and a second end, wherein the first end has a first type doping, The second end has a second type doping, the second end of the second diode is coupled to the second end of the memory element, wherein the second end of the first diode and the second end The first end of the diode is coupled to the second power supply voltage line, wherein the doping of the first or second diode is derived from the source or drain of a complementary metal oxide semiconductor (CMOS) device Doping implant manufacturing, wherein at least one diode is constructed on the polysilicon substrate, wherein the first and second power supply voltage lines are applied with voltage to turn on the first diode and cut off the The second diode goes to a logic state, or turns on the second diode to cut off the first diode to another logic state, and the magnetic memory element is configured to be programmable to a different logic state.

The embodiment disclosed herein uses at least one polysilicon diode as the programmable resistive element of the programming selector. The diode may include P+ and N+ implanted layers in a polysilicon substrate. Since both the P+ and N+ implant layers are made with standard CMOS logic processes, these components can be made in an efficient and cost-effective way. There are no additional photomasks or process steps to save costs. The programmable resistive element can be included in an electronic system.

FIG. 5 shows a block diagram of an embodiment of a memory cell 30 using at least one polysilicon diode. In particular, the memory cell 30 includes a resistance element 31 and diodes 32a and 32b. The resistance element 31 may be coupled between the anode of the polysilicon diode 32a and the voltage V. The cathode of the polysilicon diode 32a may be coupled to a negative voltage V-. The resistance element 31 may be coupled between the cathode of the polysilicon diode 32b and the voltage V. The anode of the polysilicon diode 32b may be coupled to a positive voltage V+. In one embodiment, the memory storage unit 30 may be a magnetic memory (MRAM) storage unit, which includes a magnetic tunnel junction (MTJ) 31. At least one polysilicon diode 32a or 32b can be used as a programming selector. The resistance element 31 and the diodes 32a, 32b are interchangeable between the power supply voltages V+ and V-. By applying an appropriate voltage between V, V+ and V- for an appropriate time, the resistive element 31 can be programmed to a high or low resistance state according to turning on one diode and blocking the other diode. Therefore, programming The memory storage unit 30 can store data values (for example, bits of data). The P+ and N+ implant layers of the polysilicon diode can be isolated using a silicide barrier layer (SBL).

The sixth figure a shows a top view of a programmable resistive element 30 using polysilicon diodes as the programming selector. The programmable resistive unit 30 includes a programmable resistive element 31, such as a magnetic tunnel junction (MTJ), coupled to a first power supply voltage V+ and a diode 32. The diode 32 serves as a programming selector of the programmable resistive unit 30. The diode 32 is built on a polysilicon 34, that is, a polysilicon substrate. The P+ and N+ implant layers 33 and 37 are used to construct the source or drain of the PMOS or NMOS device, thereby forming the P and N ends of the polysilicon diode 32 on the polysilicon 34. The silicide barrier layer 36 prevents silicide from being formed on the surface of the polysilicon to prevent the P and N terminals of the polysilicon diode 32 from being short-circuited. The distance d between the P+ implant layer 33 and the N+ implant layer 37 can be used to adjust the breakdown voltage and leakage current. An option layer 39 can introduce N-type shallow source-drain (NLDD), P-type shallow source-drain (PLDD) implantation layers, NMOS and PMOS threshold voltage doping implantation technology in the N+ implantation layer 37 and P+ implantation Between the layers 33 to further control the on-resistance of the diode. The implanted area of the option layer 39 can produce various types of implanted layers on the standard CMOS without additional cost.

The sixth figure b shows an embodiment of an MRAM memory cell 310, which uses diodes 317 and 318 as programming selectors. According to this embodiment, the MRAM storage unit 310 is a three-terminal MRAM storage unit in the sixth figure b. The MRAM memory cell 310 has an MTJ311 (including a free stacked layer 312, a fixed stacked layer 313, and a dielectric film in between), and two diodes 317 and 318. The free stacked layer 312 is coupled to the power supply voltage V and is coupled to the fixed stacked layer 313 via a dielectric thin film such as metal oxide aluminum oxide (Al 2 O 3) or magnesium oxide (MgO). The diode 317 has an N terminal coupled to the fixed stacked layer 313, and a P terminal coupled to V+ to program 1. The diode 318 has a P terminal coupled to the fixed stacked layer 313, and an N terminal coupled to V- to program 0. If the V+ voltage is higher than V, current flows from V+ to V to program MTJ311 to state 1. Similarly, if V- voltage is lower than V, current flows from V to V- to program MTJ311 into state 0. During the programming process, the other diode should be in the cut-off area. For reading, both V+ and V- can be set to 0V and the resistance between nodes V and V+/V- can be induced to determine whether the magnetic tunnel junction 311 is in state 0 or 1.

The seventh figure a shows a top view of an MRAM cell 80 according to an embodiment, which has a magnetic tunnel junction (MTJ) 89 as a resistance element and polysilicon diodes 86 and 88 as a programming selector. MTJ89 is an oblique ellipse, with free layer stacks and fixed layer stacks, and the dielectric forms a magnetic tunnel junction in the middle. The magnetic tunnel junction is coupled to a metal 3 (metal3) bit line extending vertically thereon. Programming 1 and programming 0 diodes 86, 88 are polysilicon diodes built on two segments (such as rectangular) polysilicon 81, placed side by side and connected at one end, that is, the N terminal of the diode 86 is connected to the diode P end of body 88. The P+ implant layer 83 and the N+ implant layer 87 define the P and N ends of the diodes 86 and 88. The silicide barrier layer (SBL) is used to isolate the P and N terminals to prevent short circuits. The P terminal of the programming 1 diode 86 is coupled to the power supply voltage V+ and the N terminal is coupled to the fixed stacked layer of MTJ89. The N terminal of the programming 0 diode 88 is coupled to the power supply voltage V-, and the P terminal is coupled to the fixed stacked layer of the MTJ89. The V+ and V- voltages of each MRAM cell 80 are respectively connected to the word lines WLP and WLN of metal 2 in the horizontal direction.

The seventh figure b shows a top view of an MRAM cell 80' of another embodiment, which has a magnetic tunnel junction MTJ89 as a resistive element and polysilicon diodes 86 and 88 as a programming selector. MTJ89 is an oblique ellipse, with free layer stacks and fixed layer stacks, and the dielectric forms a magnetic tunnel junction in the middle. The magnetic tunnel junction 89 is coupled to a metal 3 (metal3) bit line extending vertically thereon. The program 1 and program 0 diodes 86 and 88 are polysilicon diodes and are integrally connected to the polysilicon 81 (eg, rectangular), that is, the N terminal of the diode 86 is connected to the P terminal of the diode 88. The P+ implant layer 83 and the N+ implant layer 87 define the P and N ends of the diodes 86 and 88. The silicide barrier layer (SBL) is used to isolate the P terminal and the N terminal to prevent short circuits. The P terminal of the programming 1 diode 86 is coupled to the power supply voltage V+ and the N terminal is coupled to the fixed stacked layer of MTJ89. The N terminal of the programming 0 diode 88 is coupled to the power supply voltage V-, and the P terminal is coupled to the fixed stacked layer of the MTJ89. The V+ and V- power supply voltages of each MRAM cell 80' are respectively connected to metal 2 (metal2) word lines WLP and WLN in the horizontal direction. The seventh diagram a and seventh diagram b are shown for illustrative purposes. Those skilled in the art will know that there are many ways of doing things about polysilicon diodes, magnetic tunnel junctions, and metals.

The seventh figure c shows a top view of another embodiment of the MRAM cell 80", with the magnetic tunnel junction 89 as the resistance element, and the polysilicon diode 88 and the junction diode 86' as the programming selector. P+ implantation The layer 83' and the N+ implant layer 87 define the P and N ends of the diodes 88 and 86' on the polysilicon 91 and the active region 92. The junction diode 86' is in a CMOS N well, and its P end Coupled to the power supply voltage V+, and the N terminal is coupled to the P terminal of the polysilicon diode 88, and is coupled to another power supply voltage V via MTJ89 and metal 193. Dummy MOS gate 85 isolation diode 86' Similarly, the N terminal of the polysilicon diode 88 is coupled to the power supply voltage V-, and the P terminal is coupled to the N terminal of the junction diode 86', and through MTJ89 and metal 1 (metal1) 93 is coupled to another power supply voltage V. A silicide barrier layer (SBL) is used to isolate the P and N terminals of the diode 88 to prevent short circuits. The power supply voltage V is coupled to the metal 3 bit line in the vertical direction , And the power supply voltages V+ and V- are respectively coupled to the word lines WLP and WLN of metal 2 in the horizontal direction.

The seventh figure d shows a top view of an MRAM cell 80"' of another embodiment, with a magnetic tunnel junction 89 as a resistance element, a polysilicon diode 88 and a junction diode 86' as a programming selector, and adjacent Abut contact 84. The P+ implant layer 83' and the N+ implant layer 87 define the P and N ends of the diodes 88 and 86' on the polysilicon 91 and the active region 92. The junction diode 86' is In a CMOS N-well, its P terminal is coupled to the power supply voltage V+, and the N terminal is coupled to the P terminal of the polysilicon diode 88, and is coupled to another power supply voltage V via MTJ89 and metal 1 (metal1) 93. The Dummy MOS gate 85 isolates the P and N terminals of the diode 86'. Similarly, the N terminal of the polysilicon diode 88 is coupled to the power supply voltage V-, and the P terminal is coupled to the junction diode The N terminal of 86' is coupled to another power supply voltage V via MTJ98 and metal 1 (metal1) 93. A silicide barrier layer (SBL) is used to isolate the P and N terminals of the diode 88 to prevent short circuits. Power The voltage V is coupled to the metal 3 (metal3) bit line in the vertical direction, and the power supply voltages V+ and V- are respectively coupled to the metal 2 (metal2) word lines WLP and WLN in the horizontal direction. One contact is coupled to junction two The N-terminal of the polar body 86' and the P-terminal of the polysilicon diode 88 are connected via an adjacent contact (abut contact)84. The polysilicon 91 overlaps the active region 92 and connects the polysilicon and the active region at a single contact via metal193. Therefore, the two contacts are merged into one, so that the distance between the polysilicon and the active region can be shortened to save area and reduce cost, so that this embodiment is particularly effective. The connecting junction diode and the polysilicon diode are the programming 1 and programming 0 diodes, as shown in the seventh figure c and the seventh figure d, which can be interchanged. Those skilled in the art can know that different embodiments and different types of diodes are possible in various configurations and still fall within the scope of the present invention.

The eighth figure a shows an embodiment of a three-terminal 2X2MRAM memory cell array, which uses at least one polysilicon diode 317 and 318 as a programming selector, and shows the conditions for programming 1 in a memory cell. The storage units 310-00, 310-01, 310-10, and 310-11 form a two-dimensional array. The memory cell 310-00 has an MTJ311-00, a programming 1 diode 317-00, and a programming 0 diode 318-00. One end of the MTJ311-00 is coupled to the power supply voltage V, and the other end is coupled to the N terminal of the programming 1 diode 317-00 and the P terminal of the programming 0 diode 318-00. The P terminal of the programming 1 diode 317-00 is coupled to a power supply voltage V+. The N terminal of the programming 0 diode 318-00 is coupled to a power supply voltage V-. Other storage units 310-01, 310-10, and 310-11 all have similar couplings. In the same row (column) memory cells 310-00 and 310-10 voltage V is connected to the bit line 0 (BL0). The voltage V of the memory cells 310-01 and 310-11 in the same row is connected to the bit line 1 (BL1). The voltages V+ and V- of the memory cells 310-00 and 310-01 in the same row are connected to WLOP and WLON, respectively. The voltages V+ and V- of the memory cells 310-10 and 310-11 in the same column are connected to WL1P and WL1N, respectively. In order to program 1 to memory cell 310-01, WL0P is set to high voltage, BL1 is set to low voltage, and other BL and WL are set to appropriate voltages, as shown in Figure 8a, to enable other programming 1 and programming 0 The diode is disabled. The thick black line in Figure 8a shows the direction of current flow.

The eighth figure b shows another embodiment. According to this embodiment, it shows the conditions for programming the memory cell 310-01 in a 2X2MRAM memory cell array to 1. For example, if the memory cell 310-01 needs to be programmed to 1, set BL1 and WL0P to low voltage and high voltage, respectively. If BL0 is set to high voltage in condition 1, WL0N and WL1N can be high voltage or floating, and WL1P can be low voltage or floating. The high and low voltages of MRAM in today's technology are approximately: high voltage 2-3V and low voltage 0. If BL0 is floating in condition 2, WL0N and WL1N can be high voltage, low voltage, or floating, and WL1P can be low voltage or floating. In actual implementation, the floating node is usually coupled to a fixed voltage via a very weak component to prevent leakage. An example of programming as a condition of 1 is shown in the eighth figure a, without any floating nodes.

The ninth figure a shows an embodiment of a three-terminal 2X2MRAM memory cell array, which includes MTJ311 and at least one polysilicon diode 317 and 318 as the programming selector, and shows the condition that the programming memory cell is 0. These memory cells 310-00, 310-01, 310-10, and 310-11 form a two-dimensional array. The memory cell 310-00 has an MTJ311-00, a programming 1 diode 317-00, and a programming 0 diode 318-00. One end of the MTJ311-00 is coupled to the power supply voltage V, and the other end is coupled to the N terminal of the programming 1 diode 317-00 and the P terminal of the programming 0 diode 318-00. The P terminal of the programming 1 diode 317-00 is coupled to a power supply voltage V+. The N terminal of the programming 0 diode 318-00 is coupled to a power supply voltage V-. Other storage units 310-01, 310-10, and 310-11 all have similar couplings. The voltage V of the memory cells 310-00 and 310-10 in the same column is connected to BL0. The voltage V of the memory cells 310-01 and 310-11 in the same row is connected to BL1. The voltages V+ and V- of the memory cells 310-00 and 310-01 in the same row are connected to WLOP and WLON, respectively. The voltages V+ and V- of the memory cells 310-10 and 310-11 in the same column are connected to WL1P and WL1N, respectively. In order to program 0 to memory cell 310-01, WL0N is set to low voltage, BL1 is set to high voltage, and other BL and WL are set to appropriate voltages, as shown in the ninth figure a, to make other programming 1 and programming 0 The diode is disabled. The thick black line in the ninth figure a shows the direction of current flow.

The ninth figure b shows another embodiment. According to this embodiment, it shows the conditions for programming the memory cell 310-01 in a 2X2MRAM memory cell array to 0. For example, if the memory cell 310-01 needs to be programmed to 0, set BL1 and WL0N to a high voltage and a low voltage, respectively. In condition 1, if BL0 is set to low voltage, WL0P and WL1P can be low voltage or floating, and WL1N can be high voltage or floating. The high and low voltages of MRAM in today's technology are approximately: high voltage 2-3V and low voltage 0. As in condition 2, if BL0 is floating, WL0P and WL1P can be high voltage, low voltage, or floating, and WL1N can be high voltage or floating. In actual implementation, the floating node is usually coupled to a fixed voltage via a very weak component to prevent leakage. An example of programming a condition of 0 is shown in the ninth figure a, without any floating nodes.

In the memory cells of the 2x2MRAM array in the eighth figure a, the eighth figure b, the ninth figure a and the ninth figure b, there are three-terminal memory cells, that is, the memory cells have V, V+ and V- nodes. However, if the programming voltage VDDP is less than twice the diode threshold voltage Vd, that is, VDDP<2*Vd, the V+ and V- nodes of the same memory cell can be connected together as a two-terminal memory cell. Since VD is about 0.6-0.7V at room temperature, this double-ended memory cell can work normally if the programming high voltage is lower than 1.2V and the low voltage is 0V. The common voltage configuration of MRAM array in advanced CMOS technology is to have a power supply voltage of about 1.0V. The tenth figure a and tenth figure b respectively show the circuit diagrams of programming 1 and 0 in a 2X2MRAM array with two ends.

The tenth figure a and tenth figure b show an example of programming 1 and 0, respectively, in an array of 2X2MRAM memory cells with two ends. These memory cells 310-00, 310-01, 310-10, and 310-11 form a two-dimensional array. The memory cell 310-00 has MTJ311-00, a programming 1 diode 317-00, and a programming 0 diode 318-00. At least one diode is a polysilicon diode. One end of the MTJ311-00 is coupled to the power supply voltage V, and the other end is coupled to the N terminal of the programming 1 diode 317-00 and the P terminal of the programming 0 diode 318-00. The P terminal of the programming 1 diode 317-00 is coupled to the power supply voltage V+. The N terminal of the programming 0 diode 318-00 is coupled to the other power supply voltage V-. The voltages V+ and V- are connected together at the memory cell level, if VDDP<2*Vd can be satisfied. Other storage units 310-01, 310-10, 310-11 have similar couplings. The voltage V of the memory cells 310-00 and 310-10 in the same row is connected to BL0. The voltage V of the memory cells 310-01 and 310-11 in the same row is connected to BL1. The voltages V+ and V- of the memory cells 310-00 and 310-01 in the same column are connected to WL0. The voltages V+ and V- of the memory cells 310-10 and 310-11 in the same column are connected to WL1.

In order to program 1 to memory cell 310-01, WL0 is set to high voltage, BL1 is set to low voltage, and the appropriate voltage is set to other BL and WL, as shown in the tenth figure a to make other programming 1 and programming 0 Diode disabling. The thick black line in the tenth figure a shows the direction of current flow. In order to program 0 to memory cell 310-01, WL0 is set to low voltage, BL1 is set to high voltage, and the appropriate voltage is set to other BL and WL, as shown in the tenth figure b, to make other programming 1 and programming 0 The diode is disabled. The thick black line in the tenth figure b shows the direction of current flow.

As shown in the eighth figure a to tenth figure b, the example of constructing MRAM memory cells in a 2x2 array is for illustrative purposes. Those skilled in the art know that the number of rows or columns of memory cells in a memory can be changed arbitrarily, and the rows and columns are interchangeable.

Magnetic memory (MRAM) memory cells that are magnetically parallel or anti-parallel may change the stability of the memory cells over time. However, most applications need to retain data for 10 years, from operating temperature 0 to 85°C or -40 to 125°C. In order to maintain the stability of the storage unit within the lifetime of the device and within such a wide temperature range, the magnetic memory can be read out periodically, and then the data can be written back to the same storage unit, which is an update mechanism. The update cycle may be quite long, such as more than one second (for example, minutes, hours, days, weeks, or even months). The update mechanism can be generated inside the memory or triggered from outside the memory. Long-term refresh cycle to maintain the stability of the memory cell, and can also be applied to other emerging memories, such as resistive memory (RRAM), conductive bridge random access memory (CBRAM) and phase change memory (PCM) Wait.

According to another embodiment, the programmable resistance element can be used to create a memory. The eleventh figure a shows a part of a programmable resistance memory 100, consisting of an array 101 of n columns x (m+1) columns of 3-terminal MRAM memory cells 110 and n pairs of word line drivers 150-i and 151-i, where i=0,1,...,n-1 are constructed. The memory array 101 has m normal rows and a reference row sharing a sense amplifier for differential sensing. Each memory cell 110 has a resistive element 111 coupled to the P terminal of a programming 0 diode 112 and the N terminal of a programming 1 diode 113. The programming 0 diode 112 and the programming 1 diode 113 are used as programming selectors. For those memory cells 110 in the same row, each resistance element 111 is also coupled to a bit line BLj170-j (j=0, 1, ..m-1) or reference bit line BLR0175-0. For those memory cells at 110 in the same row of the diode 112N end is coupled to a word line WLNi152-i, through the local word line LWLNi154-i, where i=0,1,...,n-1 ,. For those memory cells in the same column, the diode 113P end is coupled to a word line WLPi153-i, via the local word line LWLPi155-i, where i= 0,1,...,n-1. Each word line WLNi or WLPi is respectively coupled to at least one partial word line LWLNi or LWLPi, where i=0, 1,..., n-1. The LWLNi154-i and LWLPi155-i are generally constructed from high-resistance materials, such as N-well or polysilicon, connected to memory cells, and then coupled to WLNi or WLPi (for example, low-resistance metal WLNi or WLPi) through conductive connections, respectively Point or layer indirect point, buffer, or post-decoder 172-i or 173-i, where i=0,1,...,n-1. When using a diode as a programming selector, the buffer 172-i or post-decoder 173-i may be necessary because there is current flowing through the WLNi or WLPi, especially in some embodiments when a WLNi or WLPi driver Memory cells to program and read at the same time. The word lines WLNi and WLPi are driven by word line drivers 150-i and 151-i, respectively. For programming and reading, the power supply voltage vddi can be switched between different voltages. Each BLj170-j or BLR0175-0 is coupled to a power supply voltage VDDP via a Y-write-0 channel gate 120-j or 125 to program 0, where each BLj170-j or BLR0175-0 is programmed by YS0WBj(j =0,1,...,m-1) or YS0WRB0 to select. The Y-write-0 channel gate 120-j (j=0,1,...,m-1) or 125 can be constructed with PMOS, but NMOS, diode or bipolar devices can be used in some embodiments. Similarly, each BLj170-j or BLR0175-0 is coupled to a 0V power supply voltage via a Y-write-1 channel gate 121-j or 126 to program 1, wherein each BLj170-j or BLR0175-0 respectively It is selected by YS1Wj (j=0,1,...,m-1) or YS1WR0. The Y-write-1 channel gate 121-j or 126 can be constructed with NMOS, but PMOS, diode or bipolar devices can be used in some embodiments. Each BLj or BLR0 is coupled to the data line DLj or the reference data line DLR0 via a Y-read channel gate 130-j or 135, respectively, by YSRj (j=0,1,...,m-1) or YSRR0 Select. In this part of the memory array 101, m normal data lines DLj (j=0,1,..., m-1) is connected to an input terminal 160 of a sense amplifier 140. The reference data line DLR0 provides another input terminal 161 of the sense amplifier 140, however, a multiplexer is generally not required in the reference subsection. The output terminal of the sense amplifier 140 is Q0.

To program 0 to a memory cell, as shown in the ninth figure a or ninth figure b, specific WLNi, WLPi and BLj are selected by the word line drivers 150-i, 151-i and the Y-write-0 channel gate 120-j is selected by YS0WBj respectively, where i = 0, 1, .., n-1 and j =0,1,...,m-1, and other word lines and bit lines are also set appropriately. A high voltage is applied to VDDP. In some examples, the reference memory cell can be programmed to 0, by setting appropriate voltages to WLRNi158-i, WLRPi159-i and YS0WRB0, where i=0, 1,..., n-1. To program 1 to a memory cell, as shown in the eighth figure a or the eighth figure b, the specific WLNi, WLPi and BLj are selected by the word line drivers 150-i, 151-i, and the Y-write-1 channel Gate 121-j is selected by YS1WBj, where i=0, 1.. n-1 and j=0, 1,..., m-1, and other word lines and bit lines are also set appropriately. In some embodiments, the reference memory cell can be programmed to 1, by setting appropriate voltages to WLRNi158-i, WLRPi159-i and YS1WR0, where i=0, 1,..., n-1. To read a memory cell, a data column 160 can be opened by specific WLNi, WLPi and YSRj (where i=0,1,...,n-1, and j=0,1,...,m 1) Is selected, and a reference data line DLR0161 can be opened by turning on a specific reference memory cell, which is coupled to the sense amplifier 140 to sense and compare the resistance difference between DLj and DLR0 and ground, and at the same time enable all YS0WBj, YS0WRB0, YS1Wj and YS1WR0 are invalid, where j=0,1,...,m-1.

Another example of using two-terminal MRAM memory cells to form MRAM memory is shown in Figure eleven b. According to this embodiment, the VDDP voltage difference between the high and low states is required to be less than twice the threshold voltage Vd of the diode, that is, VDDP<2*Vd. As shown in the eleventh figure b, the two character lines WLNi152-i and WLPi153-i in each row can be combined into a character line driver WLNi152-i in the eleventh figure a, where i=0,1, ..., n-1. In addition, the local word lines LWLNi154-i and LWLP155-i in each row can be merged into a local word line LWLNi154-i in the eleventh figure a, as shown in the eleventh figure b, where i=0, 1,...,n-1. Furthermore, the two character line drivers 150-i and 151-i in the eleventh figure a can be combined into one, that is, the character line driver 150-i. The BL group and WLN group of the unselected memory cells are arranged to program the conditions of 1 and 0 appropriately, as shown in the tenth figure a and the tenth figure b, respectively. Since half of the word lines, local word lines and word line drivers can be removed in this embodiment, the area of the memory cell and the memory can be greatly reduced.

Figures twelfth a and twelfth figure b show an embodiment of a flow chart depicting the programming method S700 and the reading method S800 of the programmable resistive memory, respectively. The methods S700 and S800 describe the programming and reading of a programmable resistive memory (such as the programmable resistive memory 100 in the eleventh figure a and the eleventh figure b). In addition, although it is a one-step process, those skilled in the art know that at least some of the steps may be performed in a different order, including simultaneously or skipped.

Figure 12a depicts a flowchart of a programmable resistance memory programming method S700. According to this embodiment, in the first step S710, an appropriate power selector is selected to apply high voltage power to the word line and bit line drivers. In the second step S720, the data to be programmed is analyzed in the control logic (not shown in the eleventh figure a and the eleventh figure b) according to what type of programmable resistance element. For electrical fuse, this is a one-time programmable device (OTP), so programming usually means burning the fuse to a non-original state, and it is irreversible. The programming voltage and duration are often determined by external control signals, rather than generated from within the memory. For magnetic access memory (MRAM), the direction of current flow through the magnetic tunnel junction (MTJ) is more important than the duration. The control logic determines the appropriate power selectors for the word line and bit line and activates the control signal to ensure that the current flows in the required direction within the required time. In the third step S730, a column (group) of a memory cell is selected, so the relative partial character line can be turned on. In the fourth step S740, the sense amplifier is disabled to save power and prevent interference with the programming operation. In the fifth step S750, a row (group) of memory cells can be selected and the corresponding Y-write channel gate can be opened to couple the selected bit line to a power supply voltage. In the last step S760, the established conductive path is used to drive the required current for a period of time to complete the programming operation. For most programmable resistance memories, this conduction path is from the high-voltage power supply, through the selected bit line, resistance element, the diode as the programming selector, and the NMOS pull-down element of a local word line driver. Grounded. Especially for programming one to one MRAM, the conduction path is from the high-voltage power supply, through the PMOS pull-up element of a local word line driver, as the diode, resistance element of the programming selector, and the selected bit line to the ground.

Figure 12b depicts a flowchart of a programmable resistance memory reading method S800. In the first step S810, a suitable power selector is provided to select the power supply voltage for the local word line driver, sense amplifier and other circuits. In the second step S820, all Y-write channel gates, such as bit line programming selectors (groups), can be turned off. In the third step S830, the required local word line driver (group) can be selected so that the diode (group) as the programming selector (group) has a conductive path to the ground. In the fourth step S840, the sense amplifier is activated and the input signal to be sensed is prepared. In the fifth step S850, the data line and the reference data line are pre-charged to the V- voltage of the programmable resistance element memory cell. In the sixth step S860, the required Y-read channel gate is selected so that the required bit line (group) is coupled to an input terminal of the sense amplifier. A conductive path (group) is then established, from the bit line (group) to the resistance element of the desired memory cell, as the diode (group) of the programming selector (group) and the local word line driver (group) Pull down the component to ground. The same applies to reference branches. In the last step S870, the sense amplifier can compare the difference between the read current and the reference current to determine whether the logic output is 0 or 1 to complete the read operation.

Figure 13 shows an embodiment of a processor system 700. According to this embodiment, the processor system 700 may include a programmable resistance element 744, for example, in a memory cell array 742 in the memory 740. The processor system 700 may, for example, belong to a computer system. The computer system may include a central processing unit (CPU) 710, which communicates with various memories and peripheral devices via a common bus 715, such as input and output unit 720, hard disk drive 730, optical disc 750, memory 740, and other memoriesbody760. The other memory 760 is a traditional memory such as static memory (SRAM), dynamic memory (DRAM), or flash memory (flash), which usually communicates with the central processing unit 710 through a memory controller. The central processing unit 710 is generally a microprocessor, digital signal processor, or other programmable digital logic element. The memory 740 is preferably constructed with an integrated circuit, which includes a memory array 742 having at least a programmable resistance element 744. Generally, the memory 740 contacts the central processing unit 710 via a memory controller. If necessary, the memory 740 and the processor (such as the central processing unit 710) can be combined in a single-chip integrated circuit.

The present invention can be partially or fully implemented on an integrated circuit, a printed circuit board (PCB), or on a system. The programmable resistance element can be a fuse, an anti-fuse, or a newly emerging non-volatile memory. The fuse can be a siliconized or non-siliconized polysilicon fuse, a thermally isolated active area fuse, a metal fuse, a contact fuse, or an indirect point fuse. The anti-fuse can be a gate oxide layer breakdown anti-fuse, a dielectric in between the contact or the layer indirectly point the anti-fuse. The newly emerging non-volatile memory can be magnetic memory (MRAM), phase change memory (PCM), conductive bridge random access memory (CBRAM), or resistive random access memory (RRAM). Although the programming mechanism is different, its logic state can be distinguished by different resistance values.

However, the above are only preferred embodiments of the present invention, and should not limit the scope of implementation of the present invention, that is, all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention should still be covered by the patent of the present invention. Scope The scope of the intended protection.

<heading level="1">[Learning]</heading><p>10. . . Storage unit</p><p>11. . . Resistance element</p><p>12. . . NMOS programming selector</p><p>20,20'. . . Programmable resistance element</p><p>21,21'. . . Phase change film</p><p>twenty two. . . Bipolar transistor</p><p>twenty three. . . P+ emitter</p><p>27. . . N-type base</p><p>25. . . Collector</p><p>twenty two'. . . Diode</p><p>210. . . Storage unit</p><p>211. . . Magnetic tunnel junction</p><p>218. . . NMOS programming selector</p><p>212. . . Free stacking layer</p><p>213. . . Fixed stacked layer</p><heading level="1">[this invention]</heading><p>30. . . Memory storage unit</p><p>31. . . Resistance element</p><p>32a, 32b. . . Diode</p><p>32. . . Diode</p><p>33. . . P+ implant layer</p><p>37. . . N+ implant layer</p><p>34. . . Polysilicon</p><p>36. . . Silicide barrier</p><p>39. . . Option layer</p><p>d. . . distance</p><p>310. . . MRAM storage unit</p><p>317,318. . . Diode</p><p>311. . . MTJ</p><p>312. . . Free stacking layer</p><p>313. . . Fixed stacked layer</p><p>80,80',80",80"'. . . MRAM cell</p><p>89. . . MTJ</p><p>86,88. . . Polysilicon Diode</p><p>81. . . Polysilicon</p><p>83,83'. . . P+ implant layer</p><p>87. . . N+ implant layer</p><p>82. . . Silicide barrier</p><p>85. . . Fake MOS gate</p><p>86'. . . Junction diode</p><p>89. . . Magnetic tunnel junction</p><p>91. . . Polysilicon</p><p>92. . . Active zone</p><p>193. . . Metal</p><p>310-00, 310-01, 310-10, 310-11. . . Storage unit</p><p>317-00. . . Programming 1 diode</p><p>318-00. . . Programming 0 diode</p><p>100. . . Programmable resistance memory</p><p>101. . . Array</p><p>110. . . Memory storage unit</p><p>111. . . Resistance element</p><p>112. . . Programming 0 diode</p><p>113. . . Programming 1 diode</p><p>BLR0175-0. . . Reference bit line</p><p>150-i. . . Character line driver</p><p>BLj170-j. . . Bit line</p><p>LWLNi154-i. . . Local character line</p><p>WLPi153-i. . . Character line</p><p>LWLNi, LWLPi. . . Local character line</p><p>120-0j,125. . . Y-write-0 channel gate</p><p>121-j,126. . . Y-write-1 channel gate</p><p>140. . . Induction amplifier</p><p>160,161. . . Input</p><p>130-j,135. . . Y-read channel gate</p><p>S700-S760, S800-S870. . . step</p><p>700. . . Processor system</p><p>740. . . Memory</p><p>744. . . Programmable resistance element</p><p>742. . . Memory cell array</p><p>710. . . Central processing unit</p><p>715. . . Common bus</p><p>720. . . Input output unit</p><p>730. . . Hard disk drive</p><p>750. . . CD</p><p>740. . . Memory</p><p>760. . . Other memory</p>

The first figure shows a schematic diagram of a traditional programmable resistive memory cell.

The second figure a shows a schematic diagram of another conventional programmable resistive element used in phase change memory (PCM), which uses bipolar transistors as the programming selector.

The second figure b shows a cross-sectional view of a traditional phase change memory (PCM) that uses a diode as a programming selector.

The third figure a and the third figure b show schematic diagrams of programming a traditional magnetic memory (MRAM) memory cell into parallel (or state 0) and anti-parallel (or state 1) magnetic directions via the current direction.

The fourth figure a shows a cross section of a polysilicon diode.

The fourth diagram b shows the current-voltage characteristic diagram of the polysilicon diode as shown in the fourth diagram a.

The fifth figure shows a block diagram of a memory cell using a polysilicon diode according to the present invention.

The sixth figure a shows a top view of a programmable resistive type. This programmable resistive embodiment uses polysilicon diodes as the programming selector.

The sixth figure b shows an embodiment of the MRAM memory cell using a diode as the programming selector.

The seventh figure a shows a top view of an MRAM memory cell, which has a magnetic tunnel junction (MTJ) as a resistance element and a polysilicon diode, which is an embodiment.

The seventh figure b shows a top view of another MRAM memory cell, which has a magnetic tunnel junction (MTJ) as a resistance element and a polysilicon diode, which is another embodiment.

The seventh figure c shows a top view of another MRAM memory cell, which has a polysilicon diode and a junction diode, which is an example.

The seventh figure d shows a top view of another MRAM memory cell, which has a polysilicon diode and a junction diode abut, as an example.

The eighth figure a shows a schematic diagram of an embodiment of a three-terminal 2X2MRAM memory cell array, which uses at least one polysilicon diode as a programming selector. Moreover, according to this embodiment, the memory cell on the upper right is programmed to be a condition of 1.

The eighth figure b shows a schematic diagram of another embodiment, where the memory cell on the upper right side of the 2X2MRAM memory cell array is programmed to the condition of 1.

The ninth figure a shows a schematic diagram of an embodiment of a three-terminal 2X2MRAM memory cell array, which uses at least one polysilicon diode as a programming selector. Moreover, according to this embodiment, the condition that the memory cell on the upper right is programmed to be zero.

The ninth figure b shows a schematic diagram of another embodiment, where the memory cell on the upper right side of the 2X2MRAM memory cell array is programmed to 0.

The tenth figure a and tenth figure b show a schematic diagram of an embodiment. In a two-terminal 2X2MRAM memory cell array, the memory cells on the upper right are programmed to 1 and 0 respectively.

Figure 11a shows a partial schematic diagram of a programmable resistive memory. According to this embodiment, the MRAM array is composed of 3-terminal memory cells.

Figure eleven b shows a schematic diagram of another embodiment, in which two-terminal MRAM memory cells constitute a part of the MRAM memory.

Figure 12a depicts a flowchart of a method of programming a programmable resistive memory.

Figure 12b depicts a flowchart of a method for reading a programmable resistive memory.

Figure 13 shows a schematic diagram of an embodiment of a processor system.