Semiconductor light-emitting device

Semiconductor light-emitting element

The present disclosure relates to a semiconductor light-emitting device, in particular to a semiconductor light-emitting device, by forming a plurality of bumps (having a top surface substantially parallel to the upper surface of the substrate) on a substrate and a first conductive semiconductor layer on the substrate A protruding portion (towards the substrate between the bumps and separated from the bumps) is formed on the top, so as to scatter/diffract the light beam generated by the light-emitting structure at different angles to improve the light extraction efficiency.

Semiconductor light-emitting elements (such as light-emitting diodes) have been widely used in various traffic signs, automotive electronics, liquid crystal display backlight modules, and general lighting. The light-emitting diode basically forms an n-type semiconductor layer, a light-emitting region, and a p-type semiconductor layer in sequence on a substrate, and uses the p-type semiconductor layer and the n-type semiconductor layer to form electrodes. The holes and electrons recombine to generate a light beam on the light-emitting area, which emits a light-emitting diode through the light-transmitting electrode or substrate on the p-type semiconductor layer. Commonly used materials for the manufacture of visible light emitting diodes include various III-V compounds, including aluminum gallium indium phosphide (AlGaInP) for the manufacture of green, yellow, orange or red light emitting diodes and for the manufacture of blue light or Gallium nitride (GaN) of ultraviolet light emitting diodes, in which the gallium nitride light emitting diodes are grown on a sapphire substrate.

How to extract the light beam generated by the light-emitting layer to the outside of the light-emitting element is an important improvement problem of the current semiconductor light-emitting element. In the prior art, researchers use transparent electrodes to prevent the light beam emitted from the light-emitting layer upward from being blocked by obstacles on the path to the outside world, or to provide a reflective layer for the light beam from the light-emitting layer downward. Reflect the beam to the top. However, in addition to the upward and downward beams, the light-emitting layer also emits light beams in other directions. Part of the light beam is repeatedly reflected inside the light-emitting element due to total reflection, and is finally absorbed by the light-emitting layer itself and attenuated and eliminated, and cannot be transmitted to Outer bounds of light-emitting elements.

Taiwan Patent Publication No. 561632 discloses a light-emitting element in which at least one recess and/or bump is formed on the surface of the substrate to scatter or diffract the light generated in the light-emitting area. The recesses and/or bumps form a shape that does not cause crystal defects on the semiconductor layer. In addition, Taiwan Patent Publication No. 536841 discloses a light-emitting device, which is processed by a first layer (substrate), and a second layer having a refractive index different from that of the first layer is buried in the unevenness to grow (or become On the crystal layer of the growth base, the first crystal is grown into a concavo-convex shape, and then a second crystal having a refractive index different from that of the first crystal is grown).

The present disclosure provides a semiconductor light emitting device by forming a plurality of bumps (having a top surface substantially parallel to the upper surface of the substrate) on a substrate and forming protrusions on a first conductive semiconductor layer on the substrate (towards between the bumps) The substrate is separated from the bumps), so that the light beam generated by the light-emitting structure is scattered/diffracted at different angles to improve the light extraction efficiency.

An embodiment of the semiconductor light emitting device of the present disclosure includes a substrate, a first conductivity type semiconductor layer disposed above the substrate, a light emitting structure disposed above the first conductivity type semiconductor layer, and a light emitting structure disposed above the light emitting structure One of the second conductivity type semiconductor layer. In an embodiment of the present disclosure, the substrate includes an upper surface and a plurality of bumps disposed on the upper surface, wherein the bumps include a top surface substantially parallel to the upper surface; the first conductivity type semiconductor The layer is disposed above the substrate, and the first conductive semiconductor layer includes a plurality of first protrusions facing the substrate between the bumps, and the first protrusions are separated from the bumps.

The technical features and advantages of the present disclosure have been summarized quite extensively above, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject of the patent application of this disclosure will be described below. Those with ordinary knowledge in the technical field of the present disclosure should understand that the concepts and specific embodiments disclosed below can be used fairly easily to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which this disclosure belongs should also understand that such equivalent constructions cannot deviate from the spirit and scope of this disclosure as defined by the appended patent scope.

FIG. 1 illustrates a top view of the semiconductor light emitting device 10 of the first embodiment of the present disclosure, and FIG. 2 is a cross-sectional view taken along the section line 1-1 in FIG. 1. In an embodiment of the disclosure, the semiconductor light emitting device 10 includes a substrate 12, an N-type semiconductor layer 14 disposed above the substrate 12, a light-emitting structure 16 disposed above the N-type semiconductor layer 14, and A P-type semiconductor layer 18 above the light-emitting structure 16, a contact layer 20 disposed above the P-type semiconductor layer 18, a conductive transparent layer 22 disposed above the contact layer 20, and a conductive transparent layer 22 disposed above the N-type semiconductor layer 14. An upper first electrode 24 and a second electrode 26 disposed above the conductive transparent layer 22.

FIG. 3 illustrates a top view of the substrate 12 of the first embodiment of the disclosure, and FIG. 4 illustrates a scanning electronic image of the substrate 12 of the first embodiment of the disclosure. In an embodiment of the present disclosure, the substrate 12 includes an upper surface 12A and a plurality of bumps 30 periodically arranged on the upper surface 12A. The bumps 30 are arranged in a plurality of odd rows and a plurality of even rows , And each bump 30 in the even-numbered row is located between the two bumps 30 in the adjacent odd-numbered row. In an embodiment of the disclosure, the height of the bump 30 is between 0.5 and 5 microns, the interval is between 0.5 and 10 microns, and the width is between 0.5 and 5 microns.

In an embodiment of the disclosure, the bump 30 includes a top surface 32, three wall surfaces 34 and three inclined surfaces 36, wherein the inclined surface 36 is sandwiched between the top surface 32 and the wall surface 34. In an embodiment of the disclosure, the inclination of the wall surface 34 and the inclined surface 36 are different (that is, the included angle is different from the upper surface 12A of the substrate 12), and the two are connected and the included angle is between 90 and 180 degrees. The bump 30 includes a bottom surface 38 with three corners, and the connecting line of the corners is arc-shaped, that is, the wall surface 34 is arc-shaped.

Fig. 5 is an enlarged sectional view taken along the section line 1-1 of Fig. 1, Fig. 6 is an enlarged sectional view taken along the section line 2-2 of Fig. 1, and Fig. 7 is a scan of the enlarged area of the first embodiment of the present disclosure Pointing electronic image. In an embodiment of the disclosure, the first conductive type semiconductor layer 14 includes a plurality of first protrusions 44 facing the substrate 12 between the bumps 30. In an embodiment of the disclosure, the first conductive type semiconductor layer 14 further includes a plurality of second protrusions 42, each facing the top surface 32 of the bump 30. In an embodiment of the disclosure, the first protrusion 44 is disposed in the outer edge region 40 of the first conductivity type semiconductor layer 14 in a ring manner, and the width of the outer edge region 40 is between 5 and 10 Micrometers, as shown in Figure 1.

In an embodiment of the disclosure, the first protrusion 44 and the bump 30 are separated from each other by a gap (for example, an air gap) 46. The first protrusion 44, the second protrusion 42, the gap 46, the top surface 32, the wall surface 34, and the inclined surface 36 are configured to scatter/diffract light beams from various angles from the light emitting structure 16 To the outside of the light-emitting element 10. In this way, the light beam generated by the light-emitting structure 16 can be greatly reduced to be repeatedly reflected inside the semiconductor light-emitting element 10 (ie total internal reflection), thereby preventing the light beam from being absorbed by the light-emitting structure 16 and attenuated and eliminated, thereby improving Light extraction efficiency.

FIG. 8 is an enlarged cross-sectional view of another embodiment of the present disclosure along the section line 1-1 of FIG. 1, and FIG. 9 is an enlarged cross-sectional view of another embodiment of the present disclosure along the section line 2-2 of FIG. 1. In an embodiment of the present disclosure, the first conductive semiconductor layer 14 includes a plurality of first protrusions 44', facing the upper surface 12A of the substrate 12 between the bumps 30, and the first protrusions 44 are ringed It is arranged in the outer edge region 40 of the first conductivity type semiconductor layer 14 in a shape manner, and the width of the outer edge region 40 is between 5 and 10 microns, as shown in FIG. 1.

In an embodiment of the present disclosure, the first protrusion 44' contacts the substrate 12 between the bumps 30, and is separated from the bump 30 by a gap (for example, an air gap) 46'. The first protrusion 44', the gap 46', the top surface 32, the wall surface 34, and the inclined surface 36 are configured to scatter/diffract light beams from various angles from the light emitting structure 16 to the semiconductor light emitting element Outside of 10. In this way, the light beam generated by the light-emitting structure 16 can be greatly reduced to be repeatedly reflected inside the semiconductor light-emitting element 10 (ie total internal reflection), thereby preventing the light beam from being absorbed by the light-emitting structure 16 and attenuated and eliminated, thereby improving Light extraction efficiency.

In an embodiment of the present disclosure, after the epitaxial process of the first conductivity type semiconductor layer 14, the gap 46, 46' can be formed by a wet etching process, and the etching solution can include hydrofluoric acid, nitric acid, Phosphoric acid, an alkaline solution or a mixture of alcohols and alkalis can etch the first conductivity type semiconductor layer 14 along the interface between the bumps 30 of the substrate 12 and the first conductivity type semiconductor layer 14. In an embodiment of the disclosure, the second protrusion 42 can be removed by the wet etching process, so that the first conductive semiconductor layer 14 only has the first protrusions 44, 44' facing the substrate 12. As shown in Figure 8.

In an embodiment of the disclosure, the substrate 12 includes an insulating and light-transmitting material, such as sapphire, silicon, or silicon carbide; the N-type semiconductor layer 14, the light-emitting structure 16, and the P-type semiconductor layer 18 include III- Group V materials, such as aluminum gallium nitride, gallium nitride, indium gallium nitride, aluminum gallium indium nitride, gallium phosphide, or gallium arsenide phosphor; the contact layer 20 includes III-V materials, such as aluminum gallium nitride , Gallium nitride, indium gallium nitride, aluminum gallium indium nitride, gallium phosphide or phosphorous gallium arsenide; the conductive transparent layer 22 includes indium oxide, tin oxide or indium tin oxide; the light-emitting structure 16 may be a quantum well ( quantum well) or multi-quantum well (multi-quantum well), sandwiched between the P-type cladding layer and the N-type cladding layer. In addition, the materials of the N-type semiconductor layer 14, the light-emitting structure 16 and the P-type semiconductor layer 18 can also be II-VI, which can be selected from zinc cadmium selenide (ZnCdSe), zinc magnesium selenide (ZnMgSe), selenide Zinc barium (ZnBaSe), zinc beryllium selenide (ZnBeSe), zinc calcium selenide (ZnCaSe), zinc strontium selenide (ZnSrSe), zinc cadmium selenium sulfide (ZnCdSSe), zinc magnesium selenium sulfide (ZnMgSSe), cadmium zinc telluride (ZnCdTe), zinc magnesium telluride (ZnMgTe), zinc barium telluride (ZnBaTe), zinc beryllium telluride ZnBeTe, zinc calcium telluride (ZnCaTe), zinc strontium telluride (ZnSrTe), cadmium zinc sulfide (ZnCdSTe) and A group of zinc magnesium sulfide (ZnMgSTe). In particular, the film layer on the substrate 12 can be prepared by an epitaxial machine.

FIG. 10 illustrates a top view of the semiconductor light emitting device 60 according to the second embodiment of the present disclosure, and FIG. 11 is a cross-sectional view taken along the section line 3-3 of FIG. 10. In an embodiment of the present disclosure, the semiconductor light-emitting element 60 includes a substrate 62, an N-type semiconductor layer 64 disposed above the substrate 62, a light-emitting structure 66 disposed above the N-type semiconductor layer 64, and A P-type semiconductor layer 68 above the light-emitting structure 66, a contact layer 70 disposed above the P-type semiconductor layer 68, a crystal layer 78 disposed above the contact layer 70, and a conductive layer disposed above the crystal layer 78 The transparent layer 72, a first electrode 74 disposed on the N-type semiconductor layer 64, and a second electrode 76 disposed on the conductive transparent layer 72. In an embodiment of the disclosure, the crystalline layer 78 includes a plurality of bumps 78A to increase the brightness of the light beam generated by the light-emitting structure 66 and increase the luminous efficiency of the semiconductor light-emitting element 60.

FIG. 12 illustrates a general view of the substrate 62 of the second embodiment of the disclosure. In an embodiment of the present disclosure, the substrate 62 includes an upper surface 62A and a plurality of bumps 80 periodically arranged on the upper surface 62A. The bumps 80 are arranged in a plurality of odd rows and a plurality of even rows , And each bump 80 in the even-numbered row is located between the two bumps 80 in the adjacent odd-numbered row. In an embodiment of the disclosure, the height of the bump 80 is between 0.5 and 5 microns, the interval is between 0.5 and 60 microns, and the width is between 0.5 and 5 microns.

In an embodiment of the disclosure, the bump 80 includes a top surface 82, five wall surfaces 84 and three inclined surfaces 86, wherein the inclined surface 86 is sandwiched between the top surface 82 and the wall surface 84. The inclination of the wall surface 84 and the inclined surface 86 is different (that is, the included angle with the upper surface 62A of the substrate 62 is different), and the two are connected and the included angle is between 90 to 180 degrees. The bump 80 includes a bottom surface 88 with five corners, and the connecting line of the corners is arc-shaped, that is, the wall surface 84 is arc-shaped.

FIG. 13 is an enlarged sectional view taken along the section line 3-3 of FIG. 10, and FIG. 14 is an enlarged sectional view taken along the section line 4-4 of FIG. 10. In an embodiment of the disclosure, the first conductive semiconductor layer 64 includes a plurality of first protrusions 94 facing the substrate 62 between the bumps 80. In an embodiment of the disclosure, the first conductivity type semiconductor layer 64 further includes a plurality of second protrusions 92, each facing the top surface 82 of the bump 80. In an embodiment of the present disclosure, the first protrusion 94 is disposed in the outer edge region 90 of the first conductivity type semiconductor layer 64 in a ring manner, and the width of the outer edge region 90 is between 5 and 10 Micrometers, as shown in Figure 10.

In an embodiment of the disclosure, the first protrusion 94 and the bump 80 are separated from each other by a gap (for example, an air gap) 96. The first protrusion 94, the second protrusion 92, the gap 96, the top surface 82, the wall surface 84, and the inclined surface 86 are configured to scatter/diffract light beams from various angles from the light emitting structure 66 To the outside of the semiconductor light emitting element 60. In this way, the light beam generated by the light-emitting structure 66 can be greatly reduced to be repeatedly reflected inside the semiconductor light-emitting element 60 (ie total internal reflection), thereby preventing the light beam from being absorbed by the light-emitting structure 66 itself and attenuating and extinguishing, thereby improving Light extraction efficiency.

15 is an enlarged cross-sectional view taken along the section line 3-3 of FIG. 10 of another embodiment of the present disclosure, and FIG. 16 is an enlarged cross-sectional view taken along the section line 4-4 of FIG. 10 of another embodiment of the present disclosure. In an embodiment of the present disclosure, the first conductive semiconductor layer 64 includes a plurality of first protrusions 94', facing the upper surface 62A of the substrate 62 between the bumps 80, and the first protrusions 94 are ringed It is arranged in the outer edge region 90 of the first conductive semiconductor layer 64, and the width of the outer edge region 90 is between 5 and 10 microns, as shown in FIG. 10.

In an embodiment of the disclosure, the first protrusion 94' contacts the substrate 62 between the bumps 80, and is separated from the bump 80 by a gap (for example, an air gap) 96'. The first protrusion 94', the gap 96', the top surface 82, the wall surface 84, and the inclined surface 86 are configured to scatter/diffract light beams of various angles from the light emitting structure 66 to the semiconductor light emitting element The outside of 60. In this way, the light beam generated by the light-emitting structure 66 can be greatly reduced to be repeatedly reflected inside the semiconductor light-emitting element 60 (ie total internal reflection), thereby preventing the light beam from being absorbed by the light-emitting structure 66 itself and attenuating and extinguishing, thereby improving Light extraction efficiency.

In an embodiment of the present disclosure, after the epitaxial process of the first conductivity type semiconductor layer 64, the gap 96, 96' may be formed by a wet etching process, and the etching solution may include hydrofluoric acid, nitric acid, Phosphoric acid, alkaline solution or a mixture of alcohols and alkalis can etch the first conductive semiconductor layer 64 along the interface between the bump 80 of the substrate 62 and the first conductive semiconductor layer 64. In an embodiment of the present disclosure, the second protrusion 92 can be removed by the wet etching process, so that the first conductive semiconductor layer 64 only has the first protrusion 94, 94 facing the substrate 62.

In an embodiment of the disclosure, the substrate 62 includes an insulating and light-transmitting material, such as sapphire, silicon, or silicon carbide; the N-type semiconductor layer 64, the light-emitting structure 66, and the P-type semiconductor layer 68 include III- Group V materials, such as aluminum gallium nitride, gallium nitride, indium gallium nitride, aluminum gallium indium nitride, gallium phosphide, or gallium arsenide phosphorous; the contact layer 70 includes III-V materials, such as aluminum gallium nitride , Gallium nitride, indium gallium nitride, aluminum gallium indium nitride, gallium phosphide or phosphorous gallium arsenide; the conductive transparent layer 72 includes indium oxide, tin oxide or indium tin oxide; the light-emitting structure 66 may be a quantum well ( quantum well) or multi-quantum well (multi-quantum well), sandwiched between the P-type cladding layer and the N-type cladding layer. In addition, the materials of the N-type semiconductor layer 64, the light-emitting structure 66 and the P-type semiconductor layer 68 can also be II-VI, which can be selected from zinc cadmium selenide (ZnCdSe), zinc magnesium selenide (ZnMgSe), selenide Zinc barium (ZnBaSe), zinc beryllium selenide (ZnBeSe), zinc calcium selenide (ZnCaSe), zinc strontium selenide (ZnSrSe), zinc cadmium selenium sulfide (ZnCdSSe), zinc magnesium selenium sulfide (ZnMgSSe), cadmium zinc telluride (ZnCdTe), zinc magnesium telluride (ZnMgTe), zinc barium telluride (ZnBaTe), zinc beryllium telluride ZnBeTe, zinc calcium telluride (ZnCaTe), zinc strontium telluride (ZnSrTe), cadmium zinc sulfide (ZnCdSTe) and A group of zinc magnesium sulfide (ZnMgSTe). In particular, the film layer on the substrate 62 can be prepared by an epitaxial machine.

In an embodiment of the present disclosure, the top surface 82 is the C surface (0, 0, 1), which is substantially parallel to the upper surface 62A of the substrate 62. The manufacturing process of the bump 80 mainly includes: forming a mask with a pattern partially covering the substrate; performing an etching process to partially remove the substrate not covered by the pattern, and forming the bump 80 under the pattern. In an embodiment of the present disclosure, the etching process is a wet etching process, and the etching solution includes phosphoric acid.

FIG. 17 illustrates a top view of the semiconductor light emitting device 110 of the third embodiment of the present disclosure, and FIG. 18 is a cross-sectional view taken along the section line 5-5 of FIG. 17. In an embodiment of the disclosure, the semiconductor light-emitting element 110 includes a substrate 112, an N-type semiconductor layer 114 disposed above the substrate 112, a light-emitting structure 116 disposed above the N-type semiconductor layer 114, and A P-type semiconductor layer 118 above the light-emitting structure 116, a contact layer 120 disposed above the P-type semiconductor layer 118, a crystalline layer 128 disposed above the contact layer 120, and a conductive layer disposed above the crystalline layer 128 The transparent layer 122, a first electrode 124 disposed on the N-type semiconductor layer 114, and a second electrode 126 disposed on the conductive transparent layer 122. In an embodiment of the disclosure, the crystalline layer 128 includes a plurality of recesses 128A to increase the brightness of the light beam generated by the light-emitting structure 116 and increase the luminous efficiency of the semiconductor light-emitting device 110.

FIG. 19 illustrates a full view of the substrate 112 of the third embodiment of the disclosure, and FIG. 20 illustrates the scanning electronic image of the substrate 112 of the third embodiment of the disclosure. In an embodiment of the disclosure, the substrate 112 includes an upper surface 112A and a plurality of bumps 130 periodically arranged on the upper surface 112A, the bumps 130 are arranged in a plurality of odd rows and a plurality of even rows , And each bump 130 in the even-numbered row is located between the two bumps 130 in the adjacent odd-numbered row. In an embodiment of the disclosure, the height of the bump 130 is between 0.5 and 5 microns, the interval is between 0.5 and 110 microns, and the width is between 0.5 and 5 microns.

In an embodiment of the disclosure, the bump 130 includes a top surface 132, a ridge 140, a plurality of wall surfaces 134, and a plurality of inclined surfaces 136. The ridge 140 has a plurality of branches 142, the wall surface 134 is sandwiched between the branches 142, and the inclined surface 136 is disposed at one end of the branch 142 and adjacent to the upper surface 112A of the substrate 112. In an embodiment of the present invention, the ridge 140 includes three branches 142, and the bump 130 includes three wall surfaces 134 and three inclined surfaces 136. The top surface 132 of the bump 130 is connected to the branches 142, that is, sandwiched between the branches 142, and the top surface 132 is dart-shaped. In particular, the height of the ridge 130 is greater than the height of the wall surface 134.

The inclination of the wall surface 134 and the inclined surface 136 is different (that is, the included angle with the upper surface 112A of the substrate 112 is different), and the two are connected and the included angle is between 90 and 180 degrees. The bump 130 includes a bottom surface 138 with three corners, and the connecting line of the corners is arc-shaped, that is, the wall surface 134 is arc-shaped. The ridge 130, the wall surface 134, the inclined surface 136 and the top surface 132 are configured to reflect light beams of various angles from the light emitting structure 116 to the outside of the light emitting element 110. In this way, the light beam generated by the light-emitting structure 116 can be greatly reduced to be repeatedly reflected inside the semiconductor light-emitting element 110 (ie total internal reflection), thereby preventing the light beam from being absorbed by the light-emitting structure 116 itself and attenuated and eliminated, thereby improving Light extraction efficiency.

FIG. 21 is an enlarged sectional view taken along the section line 5-5 of FIG. 17, and FIG. 22 is an enlarged sectional view taken along the section line 6-6 of FIG. 17. In an embodiment of the disclosure, the first conductivity type semiconductor layer 114 includes a plurality of first protrusions 154 facing the substrate 112 between the bumps 130. In an embodiment of the disclosure, the first conductivity type semiconductor layer 114 further includes a plurality of second protrusions 152 facing the top surface 132 of the bump 130. In an embodiment of the present disclosure, the first protrusion 154 is disposed in the outer edge region 150 of the first conductivity type semiconductor layer 114 in a ring shape, and the width of the outer edge region 150 is between 5 and 10 Microns, as shown in Figure 17.

In an embodiment of the disclosure, the first protrusion 154 and the bump 130 are separated from each other by a gap (for example, an air gap) 156. The first protrusion 154, the second protrusion 152, the gap 156, the top surface 32, the wall surface 34, and the inclined surface 136 are configured to scatter/diffract light beams from various angles from the light emitting structure 116 To the outside of the semiconductor light emitting element 110. In this way, the light beam generated by the light-emitting structure 116 can be greatly reduced to be repeatedly reflected inside the semiconductor light-emitting element 110 (ie total internal reflection), thereby preventing the light beam from being absorbed by the light-emitting structure 116 itself and attenuated and eliminated, thereby improving Light extraction efficiency.

FIG. 23 is an enlarged cross-sectional view taken along the section line 5-5 of FIG. 17 of another embodiment of the present disclosure, and FIG. 24 is an enlarged cross-sectional view taken along the section line 6-6 of FIG. 17 of another embodiment of the present disclosure. In an embodiment of the present disclosure, the first conductive semiconductor layer 114 includes a plurality of first protrusions 154', facing the upper surface 112A of the substrate 112 between the bumps 130, and the first protrusions 154 are ringed It is arranged in the outer edge region 150 of the first conductivity type semiconductor layer 114, and the width of the outer edge region 150 is between 5 and 10 microns, as shown in FIG. 17.

In an embodiment of the disclosure, the first protrusion 154' contacts the substrate 112 between the bumps 130, and is separated from the bump 130 by a gap (for example, an air gap) 15'. The first protrusion 154', the gap 156', the top surface 32, the wall surface 34, and the inclined surface 311 are configured to scatter/diffract light beams of various angles from the light emitting structure 116 to the light emitting element 110Outside. The outside. In this way, the light beam generated by the light-emitting structure 116 can be greatly reduced to be repeatedly reflected inside the semiconductor light-emitting element 110 (ie total internal reflection), thereby preventing the light beam from being absorbed by the light-emitting structure 116 itself and attenuated and eliminated, thereby improving Light extraction efficiency.

In an embodiment of the disclosure, after the epitaxial process of the first conductivity type semiconductor layer 114, the gaps 156, 156' may be formed by a wet etching process, and the etching solution may include hydrofluoric acid, nitric acid, Phosphoric acid, an alkaline solution or a mixture of alcohols and alkalis can etch the first conductivity type semiconductor layer 114 along the interface between the bump 130 of the substrate 112 and the first conductivity type semiconductor layer 114. In an embodiment of the disclosure, the second protrusion 152 can be removed by the wet etching process, so that the first conductive semiconductor layer 114 only has the first protrusions 154 and 154 facing the substrate 112.

In an embodiment of the disclosure, the substrate 112 includes an insulating and light-transmitting material, such as sapphire, silicon, or silicon carbide; the N-type semiconductor layer 114, the light-emitting structure 116, and the P-type semiconductor layer 118 include III- Group V materials, such as aluminum gallium nitride, gallium nitride, indium gallium nitride, aluminum gallium indium nitride, gallium phosphide, or gallium arsenide phosphor; the contact layer 120 includes III-V materials, such as aluminum gallium nitride , Gallium nitride, indium gallium nitride, aluminum gallium indium nitride, gallium phosphide or phosphorous gallium arsenide; the conductive transparent layer 122 includes indium oxide, tin oxide or indium tin oxide; the light-emitting structure 116 may be a quantum well ( quantum well) or multi-quantum well (multi-quantum well), sandwiched between the P-type cladding layer and the N-type cladding layer. In addition, the materials of the N-type semiconductor layer 114, the light-emitting structure 116 and the P-type semiconductor layer 118 can also be II-VI, which can be selected from zinc cadmium selenide (ZnCdSe), zinc magnesium selenide (ZnMgSe), selenide Zinc barium (ZnBaSe), zinc beryllium selenide (ZnBeSe), zinc calcium selenide (ZnCaSe), zinc strontium selenide (ZnSrSe), zinc cadmium selenium sulfide (ZnCdSSe), zinc magnesium selenium sulfide (ZnMgSSe), cadmium zinc telluride (ZnCdTe), zinc magnesium telluride (ZnMgTe), zinc barium telluride (ZnBaTe), zinc beryllium telluride ZnBeTe, zinc calcium telluride (ZnCaTe), zinc strontium telluride (ZnSrTe), cadmium zinc sulfide (ZnCdSTe) and A group of zinc magnesium sulfide (ZnMgSTe). In particular, the film layer on the substrate 112 can be prepared using an epitaxial machine.

In an embodiment of the disclosure, the top surface 132 is the C surface (0, 0, 1), which is substantially parallel to the upper surface 112A of the substrate 112. The manufacturing process of the bump 130 mainly includes: forming a mask with a pattern partially covering the substrate; performing an etching process to partially remove the substrate not covered by the pattern, and forming the bump 130 under the pattern. In an embodiment of the present disclosure, the etching process is a wet etching process, and the etching solution includes phosphoric acid.

The technical content and technical features of the present disclosure have been disclosed as above, but those with ordinary knowledge in the technical field to which the present disclosure belongs should understand that without departing from the spirit and scope of the present disclosure defined by the scope of the attached patent application Inside, the teachings and disclosures of this disclosure can be replaced and modified in various ways. For example, many of the processes disclosed above can be implemented in different methods or replaced by other processes, or a combination of the above two methods can be used.

In addition, the scope of rights in this case is not limited to the process, machine, manufacturing, material components, devices, methods, or steps of the specific embodiments disclosed above. Those with ordinary knowledge in the technical field to which this disclosure belongs should understand that, based on the teachings and disclosures of this disclosure, the process, machine, manufacturing, and material components, devices, methods, or steps, whether it exists now or will be developed in the future, it is consistent with the embodiments of this case. The revealer performs substantially the same function in substantially the same way, and achieves substantially the same result, which can also be used in this disclosure. Therefore, the scope of the following patent applications is used to cover the components, devices, methods, or steps used in such processes, machines, manufacturing, and materials.

<p>10. . . Semiconductor light-emitting element</p><p>12. . . Substrate</p><p>12A. . . Upper surface</p><p>14. . . N-type semiconductor layer</p><p>16. . . Light-emitting structure</p><p>18. . . P-type semiconductor layer</p><p>20. . . Contact layer</p><p>twenty two. . . Conductive transparent layer</p><p>twenty four. . . First electrode</p><p>26. . . Second electrode</p><p>30. . . Convex</p><p>32. . . Top</p><p>34. . . Wall surface</p><p>36. . . Inclined plane</p><p>38. . . Underside</p><p>40. . . Outer edge zone</p><p>42. . . Second protrusion</p><p>44. . . First protrusion</p><p>44'. . . First protrusion</p><p>46. . . gap</p><p>46'. . . gap</p><p>60. . . Semiconductor light-emitting element</p><p>62. . . Substrate</p><p>62A. . . Upper surface</p><p>64. . . N-type semiconductor layer</p><p>66. . . Light-emitting structure</p><p>68. . . P-type semiconductor layer</p><p>70. . . Contact layer</p><p>72. . . Conductive transparent layer</p><p>74. . . First electrode</p><p>76. . . Second electrode</p><p>78. . . Crystalline layer</p><p>78A. . . Convex</p><p>80. . . Convex</p><p>82. . . Top</p><p>84. . . Wall surface</p><p>86. . . Inclined plane</p><p>88. . . Underside</p><p>90. . . Outer edge zone</p><p>92. . . Second protrusion</p><p>94. . . First protrusion</p><p>94'. . . First protrusion</p><p>96. . . gap</p><p>96'. . . gap</p><p>110. . . Semiconductor light-emitting element</p><p>112. . . Substrate</p><p>112A. . . Upper surface</p><p>114. . . N-type semiconductor layer</p><p>116. . . Light-emitting structure</p><p>118. . . P-type semiconductor layer</p><p>120. . . Contact layer</p><p>122. . . Conductive transparent layer</p><p>124. . . First electrode</p><p>126. . . Second electrode</p><p>128. . . Crystalline layer</p><p>128A. . . Recess</p><p>130. . . Convex</p><p>132. . . Top</p><p>134. . . Wall surface</p><p>136. . . Inclined plane</p><p>138. . . Underside</p><p>140. . . Ridge</p><p>142. . . Branch</p><p>150. . . Outer edge zone</p><p>152. . . Second protrusion</p><p>154. . . First protrusion</p><p>154'. . . First protrusion</p><p>156. . . gap</p><p>156'. . . gap</p>

By referring to the foregoing description and the following drawings, the technical features and advantages of the present disclosure can be fully understood.

FIG. 1 illustrates a top view of the semiconductor light emitting device according to the first embodiment of the disclosure;

Figure 2 is a sectional view taken along the section line 1-1 of Figure 1;

FIG. 3 illustrates a top view of the substrate of the first embodiment of the present disclosure;

4 illustrates the scanning electronic image of the substrate of the first embodiment of the disclosure;

Figure 5 is an enlarged cross-sectional view taken along the section line 1-1 of Figure 1;

Figure 6 is an enlarged cross-sectional view taken along the section line 2-2 of Figure 1;

FIG. 7 is a scanning electronic image of the enlarged area in the first embodiment of the disclosure;

FIG. 8 is an enlarged cross-sectional view of another embodiment of the present disclosure along the section line 1-1 of FIG. 1;

FIG. 9 is an enlarged cross-sectional view of another embodiment of the present disclosure along the section line 2-2 of FIG. 1;

FIG. 10 illustrates a top view of the semiconductor light emitting device according to the second embodiment of the disclosure;

Figure 11 is a sectional view taken along the section line 3-3 of Figure 10;

FIG. 12 illustrates a full view of the substrate of the second embodiment of the present disclosure;

Figure 13 is an enlarged cross-sectional view taken along the section line 3-3 of Figure 10;

Figure 14 is an enlarged cross-sectional view taken along the section line 4-4 of Figure 10;

15 is an enlarged cross-sectional view of another embodiment of the present disclosure along the section line 3-3 of FIG. 10;

FIG. 16 is an enlarged cross-sectional view of another embodiment of the present disclosure along the section line 4-4 of FIG. 10;

FIG. 17 illustrates a top view of the semiconductor light emitting device according to the third embodiment of the disclosure;

Figure 18 is a sectional view taken along the section line 5-5 of Figure 17;

FIG. 19 illustrates a full view of the substrate of the third embodiment of the present disclosure;

FIG. 20 shows the scanning electronic image of the substrate of the third embodiment of the present disclosure;

Figure 21 is an enlarged cross-sectional view taken along the section line 5-5 of Figure 17;

Figure 22 is an enlarged cross-sectional view taken along the section line 6-6 of Figure 17;

FIG. 23 is an enlarged cross-sectional view of another embodiment of the present disclosure along the section line 5-5 of FIG. 17; and

FIG. 24 is an enlarged cross-sectional view of another embodiment of the present disclosure along the section line 6-6 of FIG. 17.