Data processing apparatus and method

Data processing equipment and methods

The present invention relates to a data processing device operable to map input symbols onto subcarrier signals of Orthogonal Frequency Division Multiplexing (OFDM) symbols.

The present invention also relates to a data processing device operable to map symbols of a predetermined number of subcarrier signals received from OFDM symbols into an output symbol string.

Embodiments of the present invention may provide an OFDM transmitter/receiver.

The Digital Video Broadcasting Terrestrial Standard (DVB-T) uses Orthogonal Frequency Division Multiplexing (OFDM) to transmit data representing video images and sounds to the receiver via broadcast radio communication signals. There are two known DVB-T modes, known as 2k and 8k modes. The 2k mode provides 2048 subcarriers and the 8k mode provides 8192 subcarriers. Similarly, for the digital video broadcast handheld standard, a 4k mode has been provided, in which the number of subcarriers is 4096.

In order to improve the integrity of the data transmitted using DVB-T or DVB-H, a symbol interleaver is provided to interleave the input data symbols when these symbols are mapped onto the subcarrier signal of an OFDM symbol. This symbol interleaver includes an interleaver memory and an address generator. The interleaver generator generates one bit address for each input symbol, and each bit address indicates one of the subcarrier signals of the OFDM symbol to which the data symbol will be mapped. For 2k mode and 8k mode, a configuration has been disclosed in the DVB-T standard to generate addresses for mapping. Similarly, for the 4k mode of the DVB-H standard, a configuration for generating addresses for mapping has been provided, and an address generator for implementing this mapping has been disclosed in European Patent Application 04251667.4. The address generator includes a linear feedback shift register and a permutation circuit, and the linear feedback shift register is operable to generate a pseudo-random bit sequence. The arrangement circuit arranges the order of the contents of the linear feedback shift register to generate an address. The address provides an indication for carrying one of the OFDM subcarriers of an input data symbol stored in the interleaver memory to map the input symbol to the subcarrier signal of the OFDM symbol.

According to the further development of the digital video broadcasting terrestrial broadcasting standard (known as DVB-T2), it has been proposed to provide a further mode for transmitting data.

According to one aspect of the present invention, there is provided a data processing device that is operable to map input data symbols to be transmitted to a predetermined number of subcarrier signals of orthogonal frequency division multiplexing OFDM symbols, and the predetermined number of subcarriers The carrier signal is determined according to the complex operation mode and the input data symbols include a first group of data symbols and a second group of input data symbols. The data processing device includes a controller, an address generator, and an interleaver memory. When operating according to an even-numbered interleaving program, the controller is operable to use the read bits generated by the address generator Address and read the first set of the input data symbols from the interleaver memory to the subcarrier signal of an even-numbered OFDM symbol; and use the addresses generated by the address generator to transfer the second set of the Wait for the input data symbol to be written into the memory of the interleaver. The controller is operable according to an odd-numbered interleaving program to read the first group of input data symbols from the interleaver memory to a read address determined according to the sequence order of the first group of input data symbols On the subcarrier signal of the odd-numbered OFDM symbol, the second group of the input data symbols are written into the interleaver memory at the write address determined according to the sequence order of the input data symbols of the first group, so as to be from When the input data symbols of the first group are being read from the position in the interleaver memory, the input data symbols from the second group can be written to the position just read. The number of subcarriers that can be obtained from a current OFDM symbol is different from the number of subcarriers that can be obtained from a previous OFDM symbol; and the controller is operable to read the first input data from the interleaver memory Before the symbol, determine whether the read address can be used for the previous OFDM symbol; and before writing the second input data symbols into the interleaver memory, determine whether the write address can be used for the current OFDM symbol.

In multi-carrier modulation systems such as OFDM used in DVB-T/H[1] and DVB-T2[2], frequency or symbol interleavers are used to provide frequency diversity (especially in frequency selective channels). diversity). In both systems, the frequency interleaver works differently for odd and even OFDM symbol systems. As will be explained later, in order to minimize the amount of memory used for interleaving, the odd and even symbol interleavers operate in a complementary manner, so that the amount of memory can be minimized. DVB-T/H has only one type of OFDM symbol and DVB-T2 has at least three types of OFDM symbol. As a result, although the length of the vector of data subcarriers entering the interleaver in DVB-T/H is fixed, However, the input vector length in DVB-T2 is changed according to the type of OFDM symbol.

The embodiment of the present invention provides a configuration in which a frequency interleaver can be implemented to cope with the change in the number of subcarriers used to carry input data symbols between consecutive OFDM symbols, while at the same time reducing the required interleaver memory Minimize the amount. The frequency interleaver can be used in different modes of operation, which may need to be transferred to any of the multiple modes of operation. For example, the operation modes according to the DVB-T2 standard include 1K, 2K, 4K, 8K, 16K and 32K modes. By determining whether the read address is valid for the previous OFDM symbol before reading the first input data symbol from the interleaver memory; and before writing the second input data symbol to the interleaver memory , To determine whether the write address is valid for the current OFDM symbol, the interleaver memory size can be reduced to an amount corresponding to the maximum number of subcarriers, which are available for OFDM symbols in any operating mode of. The pattern with the maximum number of subcarriers can operate corresponding to one of the interleavers to interleave the input data symbols according to odd or even OFDM symbols. Therefore, for example, the memory size of the interleaver memory can be made equal to the number of symbols that can be carried by the subcarriers of the OFDM symbol in the mode with the maximum number of subcarriers. The example for DVB-T2 is 32k mode.

The various forms and features of the present invention are defined in the scope of the attached patent application. A further aspect of the present invention includes a data processing device operable to map symbols of a predetermined number of subcarrier signals received from Orthogonal Frequency Division Multiplexing (OFDM) symbols into an output symbol string, and a transmitter and a receiver .

The following description is provided to illustrate the operation of a symbol interleaver according to the present technology, although it should be understood that the symbol interleaver can be used in other modes and other DVB standards.

Figure 1 provides an exemplary block diagram of a coded OFDM transmitter that can be used, for example, to transmit video images and audio signals in accordance with the DVB-T2 standard. In Figure 1, a program source generates data to be transmitted by a COFDM transmitter. The video encoder 2, the audio encoder 4, and the data encoder 6 generate data to be transmitted to be fed to the program multiplexer 10. The output of the program multiplexer 10 forms a multiplexed stream with other information needed to transmit video, audio and other data. The multiplexer 10 provides a stream on the connection channel 12. There can be many such multiplexed streams fed into different branches A, B, etc. For simplicity, only branch A will be described.

As shown in FIG. 1, a COFDM transmitter 20 receives the stream in a multiplexer adaptation and energy distribution block 22. The multiplexer adaptation and energy dispersion block 22 randomizes the data and feeds the appropriate data to a forward error correction encoder 24, which performs the error correction encoding of the stream. A one-bit interleaver 26 is provided to interleave the encoded data bits, which is the output of the LDCP/BCH encoder in the example of DVB-T2. The output from the bit interleaver 26 is fed to a bit constellation mapper 28, which maps the bit group to a constellation point that will be used to transmit the encoded data bits. The output from the bit-in cluster mapper 28 is cluster point labels representing real and fictitious components. The cluster point label represents a data symbol formed from two or more bits according to the modulation technique used. These will be called cells. These data units are delivered through a time interleaver 30 whose function is to interleave data units derived from multiple LDPC code characters.

The data unit is received by a frame builder 32 via other channels 31, and the data unit is generated by branch B, etc. in FIG. 1. The frame builder 32 then forms a number of data units into a sequence to be transmitted on the COFDM symbol, where the COFDM symbol includes several data units, and each data unit is mapped to one of the subcarriers. The number of subcarriers will depend on the mode of operation of the system, which can include 1k, 2k, 4k, 8k, 16k, or 32k, which provides different numbers of subcarriers according to (for example) the following table:

<tables><img file="TW201014288A_D0001.tif" /></tables>

Therefore, in an example, the number of subcarriers in the 16k mode is 12,096, and the number of subcarriers in the 32k mode is 24,192.

Each box contains many of these COFDM symbols. The sequence of data units to be carried in each COFDM symbol is then delivered to the symbol interleaver 33. The COFDM symbol is then generated by a COFDM symbol builder block 37, which uses cluster data labels to generate the real and imaginary parts of the cluster points, and also introduces its feed from a pilot and embedded signal to form The guidance and synchronization signal of the device 36. An OFDM modulator 38 then forms OFDM symbols in the time domain, which is fed to a guard insertion processor 40 for generating guard intervals between the symbols; and then fed to a digital-to-analog converter 42 and finally to An RF amplifier in the RF front end 44 for final broadcast by the COFDM transmitter from the antenna 46.

<b>Interleaver</b>

The cluster mapper 28, the symbol interleaver 33, and the frame builder 32 are shown in more detail in FIG. 2.

The symbol interleaver provides quasi-optimal mapping of data symbols onto the OFDM subcarrier signal. According to the example technology, a symbol interleaver is provided to achieve the best mapping of input data symbols to the COFDM subcarrier signal, which has been verified by simulation analysis according to the permutation code and the generator polynomial.

As shown in FIG. 2, a more detailed example description of the bit-in cluster mapper 28 and the frame builder 32 is provided to explain an exemplary embodiment of the present technology. The data bits received from the bit interleaver 26 via a channel 62 are gathered into a group of bytes to be mapped onto a data unit, according to the number of bits per symbol provided by the modulation technique. The bit group (which forms a data character) is fed in parallel via the data channel 64 to a mapping processor 66. The mapping processor 66 then selects one of the data symbols according to the pre-specified mapping. The cluster points are represented by a real and a fictitious component, which is provided to the output channel 29 as one of a set of inputs to the frame builder 32.

The frame builder 32 receives data units from the bit into the cluster mapper 28 via channel 29, along with data units from other channels 31. After the frames of many COFDM unit sequences are established, the units of each COFDM symbol are then written into an interleaver memory 100 and read out of the interleaver memory 100 according to the write address generated by the bit address generator 102 And read the address. According to the sequence of writing and reading, the interleaving of data units is obtained by generating appropriate addresses. The operations of the address generator 102 and the interleaver memory 100 will be described in more detail with reference to FIGS. 3, 4, 5, and 6 later. The interleaved data units are then combined with the pilot and synchronization symbols received from the pilot and embedded signal former 36 and enter an OFDM symbol builder 37 to form COFDM symbols, which will be fed to the OFDM modulator 38, such as Explained above.

Figure 3 provides an example of the components of the symbol interleaver 33, which illustrates the present technique for interleaving symbols. In FIG. 3, the input data unit from the frame builder 32 is written into the interleaver memory 100. The data unit is written into the interleaver memory 100 according to the write address fed from the address generator 102 on the channel 104, and according to the read address fed from the address generator 102 on the channel 106 It is read from the interleaver memory 100. The address generator 102 generates a write address and a read address (as explained below) according to whether the relevant COFDM symbol identified by a signal fed from the channel 108 is odd or even; and according to the signal fed from the channel The selected mode identified by the 110 signal. As previously explained, the mode can be one of 1k mode, 2k mode, 4k mode, 8k mode, 16k mode, or 32k mode. As will be explained below, the write address and the read address are generated differently for odd and even symbols, as explained with reference to FIG. 4, which provides an exemplary implementation of the interleaver memory 100.

In the example shown in FIG. 4, the interleaver memory is shown to include an upper part 100 (which illustrates the operation of the interleaver memory in the transmitter) and a lower part 340 (which illustrates the deinterleaver memory in the receiver). Body operation). The interleaver 100 and the deinterleaver 340 are shown together in FIG. 4 to help understand its operation. As shown in FIG. 4, the representation of the communication between the interleaver 100 and the deinterleaver 340 via other devices and through the transmission channel has been simplified and represented as the communication between the interleaver 100 and the deinterleaver 340 Section 140. The operation of the interleaver 100 is described in the following paragraphs: Although Figure 4 provides an example of four subcarrier signals with only four data units to COFDM symbols, it should be understood that the technique shown in Figure 4 can be extended A larger number of subcarriers, such as 756 in 1k mode, 1512 in 2k mode, 3024 in 4k mode, 6048 in 8k mode, 12096 in 16k mode, and 24192 in 32k mode.

The input and output addresses of the interleaver 100 shown in FIG. 4 are shown for odd and even symbols. For even COFDM symbols, the data unit is taken from the input channel 77 and written into the interleaver memory 124.1 according to a series of addresses 120 generated by the address generator 102 for each COFDM symbol. The write address is applied to even symbols so that (as described above) interleaving is achieved by shuffling the write address. Therefore, for each interleaved symbol: y(h(q))=y'(q).

For odd symbols, the same interleaver memory 124.2 is used. However, as shown in FIG. 4, for odd symbols, the write sequence 132 is in the same address sequence used to read the previous even symbols 126. This feature allows the odd and even symbol interleaver implementation to use only one interleaver memory 100, assuming that the read operation for the existing address is performed before the write operation. The data unit written into the interleaver memory 124 during the odd symbol period is then read in a sequence 134 generated by the address generator 102 for the next even COFDM symbol, and so on. Therefore, only one address is generated for each symbol, and reading and writing of its odd/even COFDM symbols are performed simultaneously.

In general, as shown in Figure 4, once the group address H(q) of all effective subcarriers has been calculated, the input vector Y'=(y0',y1',y2',...yNmax- 1') is processed to generate an interleaved vector Y=(y0,y1,y2,...yNmax-1), which is defined as:

yH(q)=y'q for even symbols, q=0,...,N_max-1

yq=y'H(q) for odd symbols, q=0,...,N_max-1

In other words, for even-numbered OFDM symbols, input characters are written into a memory in a sequence and read back in a sequence; while for odd-numbered symbols, they are written in sequence and read back in sequence. In the above case, the arrangement H(q) is defined by the following table:

<tables><img file="TW201014288A_D0002.tif" /></tables>

As shown in FIG. 4, the deinterleaver 340 operates to reverse the interleaving applied by the interleaver 100, by applying the same set of addresses as generated by an equivalent address generator, but in reverse. Application write and read addresses. In this way, for even-numbered symbols, the write address 342 is in a sequential manner; and the read address 344 is provided by the address generator. Correspondingly, for odd symbols, the writing order 346 is determined by the set of addresses generated by the address generator; and the reading 348 is in a sequential manner.

<b>Address generation in 16k and 32K modes</b>

The schematic block diagrams of the algorithm used to generate the permutation function H(q) are shown in FIG. 5 (for the 16K mode) and FIG. 6 (for the 32K mode).

The implementation of the address generator 102 in 16K mode is shown in FIG. 5. In FIG. 5, the linear feedback shift register is formed by thirteen register stages 200 and a mutually exclusive OR gate 202, which is connected to the shift according to a generator polynomial Level of register 200. Therefore, according to the contents of the shift register 200, the lower bit of the shift register is based on the generator polynomial to match R[0], R[1], R[4], R[5] , The content of R[9], R[11] performs mutually exclusive OR operation and is provided from the output of mutually exclusive OR gate 202:

<maths><img file="TW201014288A_D0003.tif" /></maths>

According to the generator polynomial, a pseudo random bit sequence is generated from the contents of the shift register 200. However, in order to generate an address for the 16k mode (as shown in the figure), a permutation circuit 210 is provided, which effectively follows the sequence at the output of the permutation circuit 210<i>R'</i>_<i>i</i><i>[n]</i>To order<i>R</i>_<i>i</i><i>[n</i>] Arrange the order of the bits in the shift register 200. The thirteen bits from the output of the arrangement circuit 210 are then fed to a connection channel 212, and a most significant bit provided by the thixotropic circuit 218 is added via a channel 214. The fourteen-bit address is then generated on the channel 212. However, in order to ensure the authenticity of the address, the address checking circuit 216 analyzes the generated address to determine whether it exceeds a predetermined maximum value. The predetermined maximum value can correspond to the maximum number of subcarriers, which can be used for data symbols in COFDM symbols, and can be used for the mode being used. However, the interleaver in 16K mode can also be used in other modes, so by adjusting the number of maximum effective addresses accordingly, the address generator 102 can also be used in 2K mode, 4K mode, 8K mode, 16K mode, and 32K mode.

If the generated address exceeds the predetermined maximum value, a control signal is generated by the address checking circuit 216 and fed to a control unit 224 via a connection channel 220. If the generated address exceeds the predetermined maximum value, the address is rejected and a new address is reproduced for the specific symbol.

For 16K mode, define (N_r-1) Bit character R'_i, With its N_r=log₂ M_max, Where M_max=16384, using LFSR (linear feedback shift register).

The polynomial used to generate this sequence is as follows: 16k mode:<img file="TW201014288A_D0004.tif" />Where i is changed from 0 to M_max-1 once an R'has been generated_i,Character, the R'_i,The characters undergo permutation to produce the name R_iThe other character (N_r-1) Bit characters. R_iDerived from R'according to the bit arrangement provided in the table below_i：

<tables><img file="TW201014288A_D0005.tif" /></tables>

As an example, for the above permutation code, this means that for the 16k mode, R'_iThe bit number 12 is sent to R_iThe number of bit positions is 8.

The address H(q) is then derived from R through the following equation_i：

<maths><img file="TW201014288A_D0006.tif" /></maths>

Of the above equation<img file="TW201014288A_D0007.tif" />Part of it is represented by the thixotropic block T 218 in FIG. 5.

Then perform an address check on H(q) to verify that the generated address falls within the acceptable address example: if (H(q)&lt;N_max), where N in 16k mode_max=12096 in the example, the address is valid. If the address is not valid, the control unit is informed and it will try to generate a new H(q) by incrementing the index i.

The role of the thixotropic block is to ensure that it will not produce more than N twice in a row_maxThe address. In fact, if an excess value is generated, it means that the MSB (ie, the thixotropic bit) of the address H(q) is one. Therefore, the next generated value sets the other MSB to zero to ensure that a valid address is generated.

The following equation sums up the overall performance and helps to understand the loop structure of this algorithm: q=0; for (i=0;i&lt;M_max;i=i+1)

<maths><img file="TW201014288A_D0008.tif" /></maths>

if(H(q)&lt;N_max) q=q+1;}

At the same time, a search table 105 is shown in FIG. 3, which is used to receive an indication of the current operation mode on a control channel 110. As shown in Figures 5 and 6, the control unit 224 receives an indication of the current symbol (odd/even) from the control channel 108; receives an indication of the current mode from the control channel 110; and receives an indication of the current mode from the control channel 111. As indicated by the lookup table for the current number of carriers or data units, the complex symbols will be interleaved onto the OFDM symbol. The control unit 224 also outputs the control signal to the search table 105 shown in FIGS. 3, 5, and 6, to retrieve the current carrier number N from the search table 105_bwx(n).

As shown in FIGS. 5 and 6, the same control unit 224 is displayed corresponding to the same address check circuit 216 and the touch change unit 218 being displayed. Therefore, it will be understood that because the input interleaver can operate in different modes, only the feedback shift register and the permutation code need to be changed in each mode, so that the same control unit can control the interleaving in each different modeDeviceMemory.

FIG. 6 provides an example of the address generator in the 32K mode. The address generator corresponds to the address generator shown in FIG. 5, and similar components have the same reference numbers. However, for the 32K mode, the linear feedback shift register is formed by thirteen register stages 200.2, and according to a generator polynomial and the contents of the shift register 200.2, the shift register is executed according to the generator polynomial. The mutually exclusive OR operation of the contents of the bit register R[0], R[1], R[2], R[12] provides the next bit of the shift register from the output of the mutually exclusive OR gate 202.2 : 32K mode:<img file="TW201014288A_D0009.tif" />Where i is changed from 0 to M_max-1-Arrangement circuit 210.2 follows the sequence at the output of arrangement circuit 210.2<i>R'</i>_<i>i</i><i>[n]</i>To order<i>R</i>_<i>i</i><i>[n</i>] Arrange the order of the bits in the shift register 200.2 according to the bit arrangement given below:

<tables><img file="TW201014288A_D0010.tif" /></tables>

As an example, this means that for 32K mode, R'_iThe bit number of 12 is sent to R_iThe number of bit positions is 5.

The fourteen bits from the output of the arrangement circuit 210.2 are then fed to a connection channel 212.2, and a most significant bit is added to the connection channel 212.2 via the channel 214 provided by the trigger circuit 218. Therefore, a fifteen-bit address is generated on channel 212.2. The interleaver in 32K mode can also be used in other modes, so that the address generator 102 can also be used in 2K mode, 4K mode, 8K mode, 16K mode and 32K mode by adjusting the number of maximum effective addresses accordingly .

If the generated address exceeds the predetermined maximum value, a control signal is generated by the address checking unit 216 and fed to a control unit 224 via a connection channel 220. If the generated address exceeds the predetermined maximum value, the address is rejected and a new address is generated for the specific symbol.

<b>Development of symbol interleaver for multiple modes</b>

Usually, the address generator of each mode is constructed so that only in the range [0 to <i>N</i>_<i>m</i>The address is generated within -1]. Since DVB-T/H has only one symbol type, the choice of mode or<i>N</i>_<i>u</i>Also decided<i>N</i>_<i>m</i>. This makes the concept of the odd-even frequency interleaver intuitive, because during the interleaving, the range and sequence of the write address of the symbol 2n (even) are the same as the range of the read address of the symbol 2n-1 (odd) and sequence. By operating in this way, the memory required to implement the odd-even interleaver can only have the subcarriers in each OFDM symbol<i>N</i>_<i>m</i>The number, not double it. Therefore, for the 32K mode (the interleaver address generation is shown in Figure 6), the channel interleaver or deinterleaver (on the receiver) required on the transmitter only needs to have 24192 positions instead of that number. double.

DVB-T2 combines 1K, K, K, K, 16K and 32K FFT sizes or modes, which<i>N</i>_<i>u</i>Individually are 1024, 2048, 4096, 8192, 16384, 32768. The DVB-T2 physical layer is organized into so-called physical layer boxes, and each box is composed of several symbols. Each box starts with a preamble (P1), and then starts with one or more preamble (P2) symbols. Several data carrying (Pd) symbols are then followed by the box being selectively closed and a box closed (FC) symbol. Although the P1 symbol does not carry payload data and therefore does not need to be frequency interleaved, the remaining symbol types do carry payload data and therefore need to be interleaved. For a given symbol, the number of data units it carries depends on the distributed navigation type (SISO/MISO) extended bandwidth, and usually depends on the specific combination of parameters that have been selected for the transmitter (system configuration). However, for a given configuration, the number of cells carried by any OFDM symbol depends on the symbol type. Therefore, P2 symbols usually carry fewer data units than Pd symbols; FC symbols carry fewer data units than P2 symbols.

Consider (assuming) the transmission of the symbol 2n-1 (odd number) and the symbol 2n (even number) for the connection of the 32K system as described above. Imagine the symbol 2n-1 is the P2 symbol and the symbol 2n is the Pd symbol. Then the range of the write address of the symbol 2n will exceed the range of the read address of the symbol 2n-1, because the Pd symbol has more data units than the P2 symbol. Because the addresses are generated pseudo-randomly, another consequence of the above situation is that the order of the write and read addresses is also different. This means that implementing odd-even interleaving with a single memory is no longer a worthless task. So it can be implemented using two separate memories: each size N_maxLocation, where N_maxIt is the maximum number of data units that can be carried by any type of symbol in the bandwidth extension mode, but this will require twice the amount of memory 2 N_max. Note N_maxIt depends on the selected FFT size or OFDM mode.

As will be explained later, the present invention provides a configuration whereby the frequency interleaving can still only use size N_maxOne memory location is implemented.

<b>The best use of odd interleaver</b>

As shown in Figure 4, two symbol interleaving procedures (one for even COFDM symbols and one for odd COFDM symbols) allow to reduce the amount of memory used during interleaving. In the example shown in Figure 4, the writing sequence of odd symbols is the same as the reading sequence of even symbols. Therefore, when the odd symbols are being read from the memory, the even symbols can be written to just read. After that, when the even-numbered symbol is read from the memory, the next odd-numbered symbol can be written to the position just read.

As disclosed in the United Kingdom (UK) patent application number 0722728.3 under the joint examination of the applicant in this case, it has been discovered that the exchange designed for the 2k and 8k symbol interleaver of DVB-T and the 4k symbol interleaver of DVB-H The technique works better for odd symbols than for even symbols. This is because the average distance on the interleaver output of adjacent subcarriers at the input of the interleaver is greater for the interleaver for odd symbols than for the interleaver for even symbols.

It will be understood that the amount of interleaver memory required to implement a symbol interleaver depends on the number of data symbols to be mapped onto the COFDM carrier symbol. Therefore, the 16k mode symbol interleaver requires only half of the memory required to implement the 32k mode symbol interleaver, and similarly, the amount of memory required to implement the 8k symbol interleaver is the amount of memory required to implement the 16k interleaver. Half. Therefore, for a transmitter or receiver that can implement a symbol interleaver of a predetermined pattern, the receiver or transmitter will include enough memory to implement two odd-numbered exchange procedures for half of the predetermined pattern or less. For example, a receiver or transmitter that includes a 32K interleaver will have enough memory to accommodate two 16K odd-numbered interleaving programs each with its own 16K memory.

Therefore, in order to solve the fact that the even-numbered interleaving process is not as good as the odd-numbered interleaving process, a symbol interleaver that can accommodate multiple modulation modes can be configured, so that if it is in a mode that contains half or less of the number of carriers in the maximum mode At this time, only an odd-numbered symbol interleaving program is used. For example, in a transmitter/receiver capable of performing 32K mode, when operating in a mode with fewer carriers (ie, 16K, 8K, 4K, or 1K), separate odd and even interleaving procedures are not used. Two odd interleavers will be used. As disclosed in the UK Patent Application No. 0722728.3, the performance of an interleaver using two odd-numbered interleavers will be further improved by using a sequence of odd-numbered interleavers instead of a single odd-numbered interleaver, so that the input to the interleaver Any data bit of the device will not always modulate the same carrier in the OFDM symbol. This effect can be achieved by adding a compensation to the modulus of the interleaver address and the number of data carriers, or using permutation sequences in the interleaver. Adding a compensation to the modulus of the interleaver address and the number of data carriers effectively offsets and surrounds the OFDM symbol so that any data bit input to the interleaver will not always modulate the same carrier in the OFDM symbol.

Furthermore, the compensation may be a random sequence, which may be generated by another address generator from an OFDM symbol interleaver, or may be generated in some other way. In addition to the above, the UK Patent Application No. 0722728.3, which is also under review, discloses the use of an arrangement sequence in the interleaver to increase any data bits input to the interleaver will not always modulate the same carrier in the OFDM symbol Possibility.

As explained above, in DVB-T2, there are two types of frequency interleaver operation. The choice of form is determined by the choice of FFT size or OFDM mode. Therefore, in the modes 1K, 2K, 4K, 8K, and 16K, the frequency interleaver can operate in its only odd-numbered form; and in the 32K mode, it can operate in the odd-even form as described above. In only odd form, the interleaver equation can be modified as follows:

yq=xH₀(q) For q=0,...,N_m-1 even sign

yq=xH₁(q) For q=0,...,N_m-1 odd sign

Where H₀(q) is the pseudo-random address generated for even symbol carrier q, and H₁(q) is the pseudo-random address generated for the odd-numbered carrier q. These are address generators with separate effects for odd and even symbols. These address generator circuit pairs for each FFT size are described in the draft DVB-T2 recommendation. Although only the odd-numbered interleaver conceptually requires two separate memories of the size of each Nbwx position, it is envisaged that the actual implementation of the DVB-T2 transmitter and/or receiver will have to support all FFT sizes. Therefore, in these implementations, there will be enough memory to implement 32K odd-even interleaving. This memory has enough capacity to support two 16K, four 8K, eight 4K, sixteen 2K and 32 1K frequency interleavers. As a result, only odd-numbered interleaving does not require additional memory, because the large memory that can already be used for 32K odd-even-numbered interleaving can be divided into two memory blocks, which is only available for the smaller FFT size in odd-numbered interleaving. needs. The technology thus provides a method to implement 32K odd-even interleaving using the smallest memory.

<b>Minimum memory requirement</b>

This technology provides a configuration that allows the smallest amount of memory to be used in 32K mode. As explained above, according to the present technology of the maximum memory size operation mode (32K mode in this example), the odd-even interleaving method requires a minimum amount of memory. Furthermore, as explained above, the number of data units or subcarriers will vary from symbol to symbol, so that in the symbol-by-symbol-based 32K mode, in order to reduce the amount of memory required, this technology allows only a single memory to be used. The symbols of the maximum 32k mode are interleaved, and the range of the write address and the read address is changed to consecutive odd and even symbols.

An example of this technology is illustrated in the flowchart shown in FIG. 7, which illustrates the operation of the control unit 224 in the odd/even mode (32k mode in this example) of the largest available memory size. . The 32K odd-even frequency interleaver depicted in the flowchart in Figure 7 uses the following terms:

N_bwx(n) represents the number of data carriers in symbol n

Addr is the pseudo-random address generated by the equivalent in Figure 1 for 32K

Input is the data unit input to the frequency interleaver and stored in InCell

CellOut (cell output) is the data cell output from the frequency interleaver.

RAM is N_maxPosition frequency interleaver memory, where N_maxIs the maximum number of data units covering all symbol types including extended bandwidth, that is, N_max=max(N_bwx)。

M is the counter of data unit per OFDM symbol.

Function Calc(N_bwx(n)) is a lookup table: given the number of symbols in a DVB-T2 physical layer frame, the type of symbol n can be determined in conjunction with other system configuration parameters. Once the type of symbol is known, then N_bwxIt can be found from the appropriate table in the DVB-T2 specification.

According to the present technology, as shown in FIG. 7, the data unit is read from the input only when the generated address is valid for the current symbol; otherwise, the input is not read. Likewise, the data unit is written to the output of the interleaver only when the generated address is valid for the previous symbol. The operation of the control unit 224 will now be explained, as represented by the flow chart shown in FIG. 7: In step S1, the variables represented in the flow chart are initialized. Therefore, the counter of the number of data units per OFDM symbol is initialized (m=0), the count of symbol n is initialized (n=1), the even symbol flag is initialized to true (even=1), and the symbol (N_bwx(n)) and the symbol (N_bwx(n-1)) The number of carriers is initialized to be equal to each other and the input-enable flag is set to 1 (true).

S2: In step S2, an address is generated by the address generator from the output of the address bus 212.2, and is read from the address check circuit 216 into the control unit 220.

S4: At a decision point S4, the input enable flag is checked and if yes, a data unit is input to the frequency interleaver and a buffer input unit is stored. If otherwise, the process proceeds to step S8.

S8: If in step S8, the even-numbered symbol flag is set to true, that is, the symbol is an even-numbered symbol, then in step S10 the output-enable flag is based on whether the generated address is less than the (n-1)th OFDM The total number of data carriers in the symbol is set. The OFDM symbol is set by using the function N_bwx(n-1) The previous OFDM symbol obtained by accessing the lookup table 105. If the symbol is an odd number, proceed to step S12, and the output flag is based on whether the current counter of the data unit of the OFDM symbol is less than the available N_bwx(n-1) The total number of carriers of the previous OFDM symbol (n-1) is set (as performed for even symbols).

S14, S16: The output enable flag (output-enable) is tested to determine whether it is true (yes) or false (no), and then branches for odd and even symbols. If the output enable flag is true (yes), the process proceeds to step S18 and step S20 for even and odd symbols individually.

S18: If the output enable flag from step S14 is true, the data symbol at the generated address is read from the memory and output from the interleaver memory (unit output).

S20: If the output enable flag from step S16 is true, the data symbol on the memory address of the counter m for this symbol is output from the interleaver (unit output).

If the output enable flags from decision points S14 and S16 are false, the processing is performed from steps S22 and S24 for even and odd symbols.

S22: The input-enable flag is set in step S22, based on whether the generated address (in step S2) is less than the number of data symbols available in the current symbol, as in the search table function N_bwx(n) The judged.

S24: The input enable flag is based on whether the current count m of data symbols of the OFDM symbol is less than the current OFDM symbol N_bwx(n) is set by the total number of carriers.

Separately in steps S26 and S28, processing is then performed for even and odd branches.

S26: If the input-enable flag is set to yes, the received unit (input unit) is written into the interleaver memory at the address generated by the address generator in step S2.

S28: If the input enable flag is yes, the received data unit is written into the memory at its address indicated by the current counter m of the data unit.

If the input-enable flag is false when determining steps S26 and S28, the process proceeds to step S34, where the counter m is incremented. The process then proceeds to step S36.

S36: At decision point S36, the current counted number of data units of the current OFDM symbol is tested to determine whether it is equal to the maximum number of data units (the number of subcarriers) that can be executed in the current OFDM symbol. If it is true, the process proceeds to step S38. If it is false, the process loops back to step S2, where the next address is generated to the address generator circuit, as shown in FIG. 5.

S38: If the counter m for the number of subcarriers of the current OFDM symbol has reached (as determined in step S36), the even symbol flag is toggled, and the counter for the number of data symbols of the current OFDM symbol is reset Is zero (m=0) and the number of symbols is incremented. At the same time, the input-enable flag is set to yes and the lookup table is used to retrieve the number of data units that can be mapped to the current OFDM symbol from the lookup table 105.

The implementation method of the odd-numbered frequency interleaver for FFT sizes other than 32K is illustrated in the flowchart of FIG. 8. In addition to the variables defined for the above odd-even situations, it also has:

Addr0 is a pseudo-random address H₀(q).

Addr1 is a pseudo-random address H₁(q)[2].

Individually reading from the interleaver input and writing to the output is also filtered by the validity of the generated address. The data units read into the interleaver memory are stored as follows: data units from even symbols are stored in positions 0 to N_max-1, and the data unit from the odd symbol is stored in position N_maxTo N_max-1。

The flowchart shown in FIG. 8 is summarized as follows: S50: In step S50, the variables of the procedure are initialized so that the counter of the current data symbol of the current OFDM unit is initialized to zero (n=0). The even sign flag is set to 1 (true) and the operation Calc(N_bwx(n)) The maximum number of generated addresses in the current mode, by retrieving this value from the lookup table 105. The maximum number of data units that can be mapped to the previous OFDM symbol (n-1) is set equal to the maximum number of the current OFDM symbol. The input enable flag is also set to true.

S52: At decision point S52, the input enable flag is tested to determine whether it is currently true (yes). If it is true, the process proceeds to step S54 and the current data symbol is input and stored in the variable buffer "input-unit". If not true (no), the process proceeds to step S56.

S56: In step S56, according to whether the current symbol is an even-numbered OFDM symbol or an odd-numbered OFDM symbol (Addr1 and Addr0 respectively), the address generator circuit generates an address, such as the one shown in FIG. 6.

S58: At the decision point S58, it is judged whether the current OFDM symbol is an odd symbol or an even symbol. If the current symbol is an even-numbered symbol, the process proceeds to step S60, and if it is an odd-numbered symbol, the process proceeds to step S62.

S60: The output enable flag is based on whether the even address (Addr1) is smaller than the previous OFDM symbol N_bwx(n-1) The maximum number of available carriers is set to true or false.

S62: If the current symbol is an odd symbol, the output enable flag is based on whether the address (Addr0) is smaller than the previous OFDM symbol N_bwxThe maximum number of subcarriers available in (n-1) is set to true or false.

Then, the process performs even and odd branches according to the decision points S64 and S66 individually.

At decision point S64, it is judged whether the output enable flag is true. If it is true, the process proceeds to step S68, and the data symbol is at position N_maxPlus the even number generated address (Addr1) is retrieved from the interleaver memory and stored in the output unit buffer (unit output) for output from the interleaver.

S70: If the output enable flag is true for the odd-numbered OFDM symbol, the data symbol is captured at the odd-numbered generation address (Addr0) and stored in the unit-output data buffer (unit output) for output from the interleaver.

If the decision points S64 and S66 are both false (that is, the output is not enabled), the processing proceeds to S72 and S74 of the even and odd branches individually.

S72: In step S72, the enabling flag is input based on whether the current OFDM symbol is smaller than the current OFDM symbol N_bwx(n) The maximum number of data symbols that can be carried is set to true or false.

S74: For the corresponding operation of the odd-numbered OFDM symbol branch, the input enable flag is based on whether the current count m of the data symbol of the current OFDM symbol n is less than the current OFDM symbol N_bwx(n) The number of available data symbols is set to true or false, which provides the corresponding operation performed in step S72.

The processing then follows the decision points in steps S76 and S78 to perform odd and even OFDM symbol branching.

S76: At the decision point S76, the input enable flag (Inenable) is analyzed, and if it is true, the data symbol in the input cell buffer (InCell) is written into the interleaver memory, and in step S80, The memory address identified by the counter.

S78: For the corresponding operation of odd-numbered OFDM symbols, the received data symbols in the input buffer (InCell) are written into the interleaver memory, and the address N in step S82 is determined_max+n.

Otherwise, from decision points S76 and S78, the counter for the number of data symbols of the OFDM symbol is incremented to step S84 and the process passes to decision point S86.

S86: At decision point S86, it is judged whether the counter of the current number of data symbols received for the current OFDM symbol is equal to that it can be mapped to the current OFDM symbol (e.g. from the search table 105 N_bwx(n) The maximum number of symbols to be extracted. If the maximum number of data symbols has been mapped to the current OFDM symbol, the process passes to step S88. Otherwise, the process passes back to step S52.

S88: If the current OFDM symbol has reached the maximum number of its data symbols (which can be carried), the even symbol flag is toggled, the number of OFDM symbols is incremented, and the counter for the number of data symbols of the current OFDM symbol is changed Reset to zero (m=0) and the input enable flag is set to true. Then search for it in the search table 105 which can be mapped to subsequent OFDM symbols n, N_bwx(n) The maximum number of data symbols on the above.

<b>receiver</b>

Figure 9 provides an example of a receiver that can be used with this technology. As shown in FIG. 9, the COFDM signal is received by the antenna 300 and detected by the tuner 302; and is converted into a digital form by the analog-to-digital converter 304. Before recovering data from the COFDM symbol, a guard interval removal processor 306 removes the guard interval from the received COFDM symbol. The recovered data uses a fast Fourier transform (FFT) processor 308 and a cooperating embedded signal decoding unit 311 The channel estimator and correction 310 is based on known techniques. The demodulated data is recovered from a mapper 312 and fed to a symbol deinterleaver 314, which operates to perform reverse mapping of the received data symbols to regenerate an output data string from which the data has been deinterleaved.

The symbol deinterleaver 314 (as shown in FIG. 9) is formed from a data processing device having an interleaver memory 340 and an address generator 342. The interleaver memory system is shown in FIG. 7 and (as explained above) is operated to perform deinterleaving by using multiple sets of addresses generated by the address generator 342. The address generator 342 is shown in FIG. 8 and is configured to generate a corresponding address to map the data symbols recovered from each COFDM subcarrier signal into an output data string.

The remaining part of the COFDM receiver shown in FIG. 9 is provided to cause the error correction decoding 318 to correct the error and restore the estimated value of the source data.

One advantage of the receiver and transmitter provided by this technology is that the symbol interleaver and symbol deinterleaver in the receiver and transmitter can be switched between 1k, 2k, and 2k by changing the generator polynomial and arrangement order. Between 4k, 8k, 16k and 32k modes. Therefore, the address generator 342 shown in FIG. 10 includes an input 344 (which provides an indication of the mode) and an input 346 (which indicates whether there are odd/even COFDM symbols). This provides a flexible implementation, because the symbol interleaver and deinterleaver can be formed as shown in FIGS. 3 and 4, with the address generator shown in either FIG. 5 or FIG. 6. The address generator can therefore be adapted to different modes by changing to the generator polynomial and arrangement order indicated for each mode. For example, it can be done using software changes. On the other hand, in other embodiments, the embedded signal indicating the mode of DVB-T2 transmission can be detected in the receiver embedded in the signal processing unit 311 and used to automatically configure the symbol according to the detected mode Deinterleaver.

Examples of address generators and corresponding interleavers for 2k, 4k, and 8k modes are disclosed in European Patent Application No. 04251667.4, the content of which is incorporated herein for reference. The address generator in 0.5k mode is disclosed in the UK patent application number 0722553.5 under review.

Various modifications can be made to the above-mentioned embodiments without departing from the scope of the present invention. In particular, the examples of generator polynomials and arrangement order that have been used to represent the form of the present invention are not limitative, and can be extended to generator polynomials and arrangement orders of the same form.

It should be understood that the transmitters and receivers shown in FIGS. 1 and 9 are only provided for convenience of explanation and not limitation. For example, it should be understood that the position of the symbol interleaver and deinterleaver relative to, for example, the bit interleaver and mapper can be changed. It should be understood that the effects of the interleaver and deinterleaver will not change due to their relative positions, although the interleaver can interleave I/Q symbols instead of v-bit vectors. Corresponding changes can also be made in the receiver. Therefore, the interleaver and the deinterleaver can be operated in different data types and positioned at positions different from those described in the exemplary embodiment.

As mentioned above, the permutation code and generator polynomial of the interleaver described with reference to the specific mode implementation can be equally applied to other modes, by changing the predetermined maximum allowable address according to the number of carriers of the mode.

As described above, the embodiments of the present invention find the application of DVB standards (such as DVB-T and DVB-H), which are incorporated herein for reference. For example, the embodiments of the present invention can be used in transmitters or receivers operating in accordance with the DVB-H standard in handheld mobile terminals. Mobile terminals can be integrated with (for example) mobile phones (whether second, third or higher generation) or personal digital assistants or tablet personal computers. These mobile terminals can receive DVB-H or DVB-T compatible signals inside buildings or, for example, moving in cars or trains (even at extremely high speeds). The mobile terminal can, for example, be powered by a battery, main power, or low-voltage DC supply; or be powered by a car battery. The services that can be provided by DVB-H include audio, messaging, Internet browsing, radio, static and/or dynamic video images, TV services, interactive services, on-demand video or near video, and other options. These services can be operated in conjunction with each other. It should be understood that the present invention is not limited to the application of DVB but can be extended to other standards including both fixed and mobile transmission and reception.

<p>2. . . Video encoder</p><p>4. . . Audio encoder</p><p>6. . . Data encoder</p><p>10. . . Program multiplexer</p><p>12. . . Connect channel</p><p>20. . . COFDM transmitter</p><p>twenty two. . . Multiplexer adaptation and energy distribution block</p><p>twenty four. . . Forward error correction encoder</p><p>26. . . Bit interleaver</p><p>28. . . Bit-in-cluster mapper</p><p>29. . . Output channel</p><p>30. . . Time interleaver</p><p>31. . . Channel</p><p>32. . . Frame builder</p><p>33. . . Symbol interleaver</p><p>36. . . Guiding and embedding signal former</p><p>37. . . OFDM symbol builder</p><p>38. . . OFDM modulator</p><p>40. . . Protection plug-in processor</p><p>42. . . Digital to analog converter</p><p>44. . . RF front end</p><p>46. . . antenna</p><p>62. . . Channel</p><p>64. . . Data channel</p><p>66. . . Mapping processor</p><p>100. . . Interleaver memory</p><p>102. . . Address generator</p><p>104. . . Channel</p><p>105. . . Lookup table</p><p>106. . . Channel</p><p>108. . . Channel</p><p>110. . . Channel</p><p>111. . . Control channel</p><p>140. . . Section</p><p>200. . . Register level</p><p>202. . . Mutually exclusive or gate</p><p>210. . . Arrange the circuit</p><p>212. . . Connect channel</p><p>214. . . Channel</p><p>216. . . Address check circuit</p><p>218. . . Thixotropic circuit</p><p>220. . . Connect channel</p><p>224. . . control unit</p><p>300. . . antenna</p><p>302. . . tuner</p><p>304. . . Analog to digital converter</p><p>306. . . Guard interval remove processor</p><p>308. . . Fast Fourier Transform (FFT) processor</p><p>310. . . Channel estimator and correction</p><p>311. . . Embedded signal decoding unit</p><p>312. . . Mapper</p><p>314. . . Symbol deinterleaver</p><p>316. . . Bit deinterleaver</p><p>318. . . Error correction decoding</p><p>340. . . Interleaver memory</p><p>342. . . Address generator</p><p>344. . . enter</p><p>346. . . enter</p>

The embodiments of the present invention will now be described by way of example only with reference to the following drawings, in which similar components are provided with corresponding reference numerals, and among them:

Figure 1 is a schematic block diagram of a coded OFDM transmitter that can be used (for example) in the DVB-T2 standard;

Figure 2 is a schematic block diagram of the components of the transmitter shown in Figure 1, in which a symbol mapper and a frame builder illustrate the operation of the interleaver;

Figure 3 is a schematic block diagram of the symbol interleaver shown in Figure 2;

4 is a schematic block diagram of the interleaver memory shown in FIG. 3 and the corresponding symbol de-interleaver in the receiver;

Figure 5 is a schematic block diagram of the address generator shown in Figure 3 for 16k mode;

Figure 6 is a schematic block diagram of the address generator shown in Figure 3 for 32k mode;

Figure 7 is a flowchart illustrating the operation of the interleaver shown in Figure 3 in odd-even mode, for example for the 32K model;

Fig. 8 is a flowchart illustrating the operation of the interleaver shown in Fig. 3 only in odd mode, for example, for the 16K model;

Figure 9 is a schematic block diagram of a coded OFDM receiver that can be used, for example, in the DVB-T2 standard; and

FIG. 10 is a schematic block diagram of the symbol deinterleaver appearing in FIG. 9.