Broadband pilot channel estimation using a reduced order FFT and a hardware interpolator

Broadband pilot channel estimation using reduced-order FFT and hardware interpolator

Cross-references to related applications

According to the provisions of the Patent Law, this application requires the rights and interests of the provisional application with serial number 61/040,449 filed on March 28, 2008, which is expressly incorporated herein by reference.

The present disclosure relates to channel estimation in communication systems.

In wireless communication systems, the transmitter usually encodes, interleaves, and modulates traffic data (ie, symbol mapping) to obtain data symbols. For a coherent system, the transmitter multiplexes the pilot frequency symbol and the data symbol, processes the multiplexed pilot frequency and data symbol to generate a modulated signal, and sends the signal through a wireless channel. The channel response of the channel distorts the transmitted signal, and the noise and interference in the channel further deteriorate the signal. The transmitted signal reaches the receiver through multiple transmission paths. The characteristics of the propagation path usually change over time due to a variety of factors. The subbands of different frequencies used for communication experience different channel conditions and have different signal-to-noise ratios (SNR). Therefore, in order to effectively transmit data, it is usually necessary to accurately estimate the channel response between the transmitter and the receiver.

The receiver receives pilot frequency modulation symbols and processes the received pilot frequency modulation symbols to obtain channel response estimates. Since the pilot frequency modulation symbol has some values known by the receiver, the receiver can estimate the channel response based on the received pilot frequency symbol value and the transmitted pilot frequency symbol value known by the receiver. Once the channel is estimated, the receiver uses the channel estimation to determine from the received data modulation symbols what the data modulation symbol was originally sent. Subsequently, the receiver performs symbol demapping, deinterleaving, and decoding on the recovered data modulation symbols according to the coding and modulation scheme used for the traffic data.

There are several different methods of performing channel estimation. In one method, only a small tile of the entire frequency-time frame of the modulation symbol value is demodulated. This fragment only includes a relatively small number of pilot frequency modulation symbol values. These pilot frequency values are called "narrow frequency" or "dedicated" pilot frequency values. The receiver uses interpolation techniques to interpolate the channel characteristics between points of known channel characteristics given by the pilot frequency value. The resulting channel estimate is used to determine the value of the data symbol originally sent from the value of the received data symbol.

In the second method, more so-called "broadband" or "common" pilot frequency modulation symbol values are distributed throughout the frequency-time frame. Use the inverse fast Fourier transform (IFFT) function to convert the received pilot frequency value into the time domain. Identify the strongest pilot frequencies in the time domain, and then zero out these strongest pilot frequencies. The zero-padding time domain result is converted to the frequency domain through the Fast Fourier Transform (FFT) function to generate a larger set of channel estimates, and each channel estimate corresponds to each modulation symbol value in the frequency-time frame. In some environments and applications, the channel estimation operation performed by the receiver consumes a large amount of processing power, requires the receiver to include a large amount of dedicated hardware, and/or causes the receiver to consume a large amount of power, which is undesirable .

In the receiver, one channel estimation mechanism includes a hardware interposer. In the first mode, the narrowband pilot frequency modulation symbol value is analyzed to generate channel parameters, and the channel parameters are provided to the hardware interpolator so that the hardware interpolator generates the channel estimation value used in demodulation. For example, the channel estimation value can be used for the fragments of the demodulated frame, where the fragments include narrow-band pilot frequency values.

In the second mode, the broadband pilot frequency modulation symbol value is provided to the inverse fast Fourier transform (IFFT) function block to generate the time domain value. After time-domain processing such as threshold and tap selection and zero padding, the Fast Fourier Transform (FFT) function is used to generate intermediate channel estimates. These intermediate values are analyzed to determine the channel parameters, and the channel parameters are provided to the hardware interpolator, so that the hardware interpolator generates a large number of channel estimates for demodulating the frame. The use of a hardware interpolator in this way introduces a time offset that is different for each frequency of multiple values. Therefore, the phase adjustment coefficient is calculated for each frequency, and the hardware interpolator uses the phase adjustment coefficient to perform time offset correction in the frequency domain by multiplying each post-FFT (post-FFT) band by the respective phase adjustment coefficient, This effectively converts the signal in the time domain back to the situation it should be in when no time shift occurs. Using the hardware interpolator in the broadband pilot channel estimation mode makes the FFT used in this mode have a relatively small order, and therefore makes the entire channel estimation mechanism consume less power and/or consume less processing resource.

The above is a summary of the content of the invention, and therefore inevitably includes simplifications, generalizations and omissions of details; therefore, those skilled in the art should realize that the summary is merely illustrative and is not intended to be limiting in any way. In the non-limiting detailed description herein, other aspects, inventive features, and advantages of the devices and/or processes described herein, which are only limited by the scope of the patent application, will become apparent.

FIG. 1 is a simplified high-level block diagram of an example of a wireless communication device 100. The wireless communication device 100 includes an antenna 101, a radio frequency (RF) integrated circuit 102, and a digital baseband integrated circuit 103 in addition to other components not shown.

FIG. 2 is a more detailed block diagram of the antenna 101 and the RF transceiver integrated circuit 102 in FIG. 1. The RF transceiver integrated circuit 102 includes a receiving chain 104 and a transmitting chain 105. The input transmission 106 is received at the antenna 101 and enters the receiving chain 104 through the duplexer 107 and the matching network 108. After down-conversion is performed in the receiving chain 104, the received signal is transmitted to an analog-to-digital converter (ADC) 109 in the digital baseband integrated circuit 103. ADC 109 converts the signal into digital samples for further processing. If the wireless communication device 100 is to transmit, a digital analog converter (DAC) 110 in the digital baseband integrated circuit 103 converts the digital information into an analog form. Subsequently, the transmit chain 105 of the RF transceiver integrated circuit 102 up-converts the obtained analog signal, and the power amplifier PA 111 amplifies the obtained RF signal. The amplified signal is transmitted to the antenna 101 via the duplexer 107 to be transmitted as an output transmission 112.

FIG. 3 is a more detailed block diagram of the digital baseband integrated circuit 103 of FIG. 2. The digital baseband integrated circuit 103 includes: ADC 109, receiving channel 113, transmitting channel 114, DAC 110, processing circuit 115, multiple memories 116, multiple high-speed memories 117, data mover engine 118 , The first bus 119, the second bus 120 and the elapsed time timer 121. The receiving channel 113 in turn includes a set of processing modules 122-125, which are referred to herein as the wireless communication system data machine sub-circuit (WCSMSC), which is incorporated into the chain to process the input data stream. These WCSMSCs include a front-end WCSMSC 122, a fast Fourier transform (FFT) WCSMSC 123, a demodulation (DEMOD) WCSMSC 124, and a demapping/deinterlacing/decoding (DDE) WCSMSC 125. DDE WCSMSC 125 sequentially includes a demapper part, an LLR buffer 129, and a decoder module. The data streams of each WCSMSC passing through the receiving channel 113 are buffered by the buffers 126-130, which include a sample buffer 126, a symbol buffer 127, a slice buffer 128, an LLR buffer 129, and a decoding output bufferDevice130. The general path for receiving channel data is from left to right through the circuits 109, 122, 126, 123, 127, 124, 128, 125, 130 to the second bus 120 in FIG. Similarly, the transmitting channel 114 includes a corresponding set of WCSMSC 131-134 and buffers 135-138. The general path of transmitting channel data is from the second bus 120 to 135, 131, 136, 132, 137, 133, 138, 134, and 110 from right to left in FIG. 3.

In this example, the processing circuit 115 includes multiple processors, including a digital signal processor (DSP) and a general-purpose processor. DSP can perform fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) operations and other signal processing functions with software. The processing circuit 115 executes a program 139 of processor-executable instructions stored in the memory 116. The high-speed memory 117, the first bus 119, and the processing circuit 115 together form a tightly coupled memory (TCM) system. The processing circuit 115 can read from or write to the high-speed memory 117 via the first bus 119. In the following discussion, the DSP and the general-purpose processor are collectively referred to as the processing circuit 115.

In the example of FIG. 3, the processing circuit 115 uses a so-called "task list" to control the respective sub-circuits 122-125 and 131-134 of the receiving and transmitting channels. The task list includes one or more task instructions. In the figure, four task lists TL1, TL2, TL3, and TL4 stored in the memory 117 are shown. The task list TL1 includes the task instructions of the transmission channel 114. The task list TL2 includes the task instructions of the FFT WCSMSC 123. The task list TL3 includes DEMOD WCSMSC 124 task instructions. Task list TL4 includes DDE WCSMSC 125 mission instructions. Each task list includes a task instruction sequence, which is executed by an associated sub-circuit. The sub-circuit includes a task manager circuit associated with the second bus 120, and also includes a plurality of dedicated function circuits for performing data processing operations of the circuit. The task manager reads the task instructions from its associated task list, interprets the operation codes and various fields of the task instructions, and then controls the associated hardware of the dedicated function circuit to perform the operations indicated by the task instructions. By placing appropriate task instructions into the task list of a specific sub-circuit, the processing circuit 115 can cause the dedicated function circuit of the specific sub-circuit to perform a specific operation specified by the processing circuit. The processing circuit 115 can write task instructions into these task lists through the first bus 119 as desired, modify the task lists, delete the task lists, and maintain the task lists. Each task list is stored in the memory 117 in the circular buffer. The task manager of DEMOD WCSMSC 124 in FIG. 3 is identified by reference numeral 140. The associated dedicated function circuits controlled by the task manager 140 include a minimum mean square error estimation (MMSE) demodulator 204A, a maximum ratio combining (MRC) demodulator 204B, and a channel estimation (CE) circuit 257.

FIG. 4 is a schematic diagram showing input time-domain samples received from the ADC 109. These time domain samples pass through the front end 122 and into the sampling buffer 126. The digits 1, 2, 3, etc. above the horizontally extending dot stream shown in FIG. 4 are the indexes of the corresponding samples in the sampled input stream. The dot represents the sample itself. Each sample includes an I value and a Q value. In the example shown, a sequence of 1024 time-domain samples is received, followed by multiple samples of the loop prefix. After that, after looping the prefix, another set of 1024 time-domain samples is received, and so on. The sampling in FIG. 4 is a sampling corresponding to a part of a frame. The FFT WCSMSC 123 (see FIG. 3) processes each successive sample group with 1024 samples, and generates a corresponding group of 1024 values, which collectively represent an OFDM symbol. The loop prefix sampling is not processed by FFT WCSMSC 123, but is ignored. The arrow 200 indicates that the sample values 0-1023 in the symbol buffer 127 constitute a single OFDM symbol.

FIG. 5 is a schematic diagram showing a two-dimensional frame 201 of sample values processed in the symbol buffer 127. Consider the vertical dimension in Figure 5 as the frequency axis. Thus, the values in different rows have different frequencies. Different frequencies are also called different "tones" in the art. The integer index "f" is defined as a frequency index, indicating one of multiple frequency rows. For example, "f" with a value of "0" indicates the bottom row in FIG. 5. For example, "f" with a value of "1" indicates the second highest row in Figure 5, and so on.

Consider the horizontal dimension in Figure 5 as the time axis, with time extending from left to right. In the example of Figure 5, there are 8 OFDM symbols in a frame, and each OFDM symbol in the frame includes 1024 sample values, where each sample value in turn includes an I value part and a Q Value part. One of the 1024 sample values is also called the modulation symbol value.

The frame 201 includes two kinds of sampling values, a "pilot frequency" sampling value and a "data" sampling value. In FIG. 5, the pilot frequency sampling value is represented by a dot symbol, and the data sampling value is represented by an "X" symbol. In the type of wireless communication system described in this article, a base station communicates with multiple mobile communication devices. The base station may periodically transmit a type of transmission having the frame structure shown in FIG. 5, in which each mobile communication device receives and demodulates all sample values of the frame. This frame is called a broadcast frame. The broadcast frame is filled with control data values and guide frequency values. Data values are interspersed among the pilot frequency values called "common pilot frequency" or "broadband pilot frequency", and these data values are distributed in most of the frequency range of the frame in a conventionally known pattern. The transmitter in the base station transmits the pilot frequency, and the frequency-time position of the pilot frequency in the frame of FIG. 5 is known by the receiving mobile communication device. The value of the pilot frequency is also known to the receiving mobile communication device. Receive the sampled value of the frame received by the receiver in the mobile communication device, and identify the pilot frequency value at the known frequency-time position. The pilot frequency is disturbed by the wireless channel between the transmitting base station and the receiving mobile communication device, as well as by noise and interference. The receiver estimates the effect of this scrambling on each data value in the frequency-time grid of Fig. 5, and this process is usually called channel estimation. By applying the channel estimation value to the corresponding received data value, the demodulator can eliminate the channel's adverse effect on the transmitted data value. In the frame of FIG. 5, there are multiple broadband pilot frequencies distributed throughout most of the grid. The first channel estimation method is called the "wideband pilot frequency channel estimation and demodulation" method in the text. As described in detail below, this method is used for channel estimation for a frame with multiple such broadband pilot frequencies.

FIG. 6 is a schematic diagram showing another type of frame 202. Different from the broadcast frame 201 of FIG. 5, the frame 202 of FIG. 6 only includes a pilot frequency in a relatively small frequency-time "segment" 203. This piece 203 includes user information to be sent to a mobile communication device. The pilot frequency in this fragment 203 is usually called "dedicated pilot frequency" or "narrow frequency pilot frequency". They are narrow frequency because they do not cover the frequency range of the frame. The receiver in the mobile communication device does not need to try to demodulate and use values outside the fragment, because those values will not be transmitted to a specific mobile communication device. Since the fragment 203 has a smaller number of narrow-band pilot frequencies compared with a large number of wide-band pilot frequencies in the frame 201, the first channel estimation method cannot be used. The second channel estimation method is referred to herein as the "plane estimation and interpolation" method. As described in detail below, this method is used to perform channels on the fragments of FIG. 6 including a smaller number of narrow-band pilot frequencies. estimate.

Figure 7 is a schematic diagram showing the "common pilot channel estimation and demodulation" method. The FFT module 123 and the symbol buffer module 127 at the bottom left of FIG. 7 represent the FFT WCSMSC 123 and the symbol buffer 127 of FIG. 3. The 1024 values of the symbol in the example of FIG. 5 are passed from the symbol buffer 127 to the right to the MMSE or MRC demodulator module 204. The MMSE demodulator 204A and the MRC demodulator 204B depicted in FIG. 3 are located in the MMSE or MRC demodulator module 204 in FIG. 7. Each symbol value (I, Q) passed into the MMSE or MRC demodulator module 204 from the symbol buffer 127 is multiplied by a different "channel estimation value" to generate the demodulated symbol value (I, Q) and signal noise Then, the demodulated symbol value (I, Q) and the signal-to-noise ratio (SNR) value are written into the chip buffer 128. The slice buffer 128 in the lower right part of FIG. 7 is the slice buffer 128 in FIG. 3.

Since the frame is stored in the symbol buffer 127, the processing circuit 115 (see FIG. 3) knows the position of the broadband pilot frequency in the frame. The processing circuit 115 implements the channel estimation function of the modules 206, 207, 209, 210, and 211 in the form of firmware or software. Therefore, the processing circuit 115 places the symbol buffer push task instruction in the task list TL3 of the demodulator WCSMSC 124 in FIG. 3. The task manager 140 of the demodulator WCSMSC 124 retrieves the symbol buffer push task instruction via the second bus 120 and interprets the task instruction. The symbol buffer push task instruction includes a field indicating all positions of all wideband pilot frequency values in the frame of the symbol buffer 127. The execution of the demodulation push task command causes these broadband pilot frequency values to be pushed to the high-speed memory 117 for further processing by the processing circuit 115.

Fig. 8 is a schematic diagram of a symbol buffer push task instruction. In Figure 7, the push of broadband pilot frequency is represented by line 205. If the pilot frequency is scrambled, the descrambling operation is performed first. Subsequently, the descrambled 256 broadband pilot frequency values pass through the 256-point inverse fast Fourier transform (IFFT) function block 206 to generate 256 time-domain sample values, which represent the impulse response of the channel. Each of these 256 time-domain sampled values includes an I part and a Q part. The function block 207 performs threshold adjustment on the 256 time-domain sample values output by the IFFT function block 206, so as to identify the 16 strongest pilot frequencies. This is achieved by moving the 16-junction tall window (or "sliding" the window) upwards across the entire 256 time-domain samples one junction at a time to find the window position corresponding to the maximum output energy. In one example, adaptive junction threshold processing is performed by detecting the distribution of interference power and actual junction values to determine the number of identified time-domain junction samples to pass. In the example of FIG. 7, subsequently, the 16 time-domain joint sample values 208 identified using the above-mentioned sliding window and threshold processing are provided to the zero pad function block 208. k_STARTThe value is an integer index used to identify the position of the bottom contact of the sliding window when the final position of the sliding window is determined. k_CThe value is an index used to identify one of the contact positions in the window, and the contact position identifies the center position of the average combined energy of all the contact values in the sliding window when the sliding window is in its final position. The zero pad function block 208 adds zero values to the 16 time domain contact sample values, so as to generate a complete set of 1024 zero pad time domain samples. The 1024-point FFT function block 109 transforms these time-domain joint samples back to the frequency domain to generate 1024 "channel estimates" values. Line 213 indicates that 1024 channel estimates are provided to the MMSE or MCR demodulator module 204. Referring back to FIG. 7, the noise estimator function block 211 uses the 16 time-domain joint sample values 208 to generate a single noise estimation value of the frame. The MMSE or MRC demodulation module 204 demodulates the data symbol value (I, Q) of the frame into the demodulated symbol value (I, Q and SNR) written into the chip buffer 128 using the channel estimation and noise estimation value .

Fig. 10 is a schematic diagram showing the "plane estimation and interpolation" method. The processing circuit 115 implements the channel estimation function of the functional modules 300 and 301. However, the modules 302, 303, and 204 are implemented in hardware. The hardware of the modules 302 and 303 are located in the channel estimation (CE) module 257 of the DEMOD WCSMSC 124 in FIG. 3.

The processing circuit 115 knows the position of the narrow-band pilot frequency value because the narrow-band pilot frequency value is stored in the symbol buffer 127. Thus, the processing circuit 115 puts the symbol buffer push task instruction into the task list TL3 of the demodulator WCSMSC 124 in FIG. 3. The task manager 140 of the demodulator WCSMSC 124 retrieves the symbol buffer to push the task instruction through the second bus 120, interprets the task instruction, and pushes the dedicated pilot frequency value to the high-speed memory 117 (see FIG. 3). In FIG. 9, the push of the narrow-band pilot frequency is represented by the line 304. The narrow-band pilot frequency is analyzed by the collecting pilot frequency and channel parameter estimation function block 300 to determine the three channel parameter values 305: 1) the channel average (CA) value, 2) the time coefficient representing the slope of the channel over time or Time slope (Delta T), and 3) the frequency coefficient or frequency slope (Delta F) representing the slope of the channel changing with frequency. In one example, the CA value is determined by averaging all the narrowband pilot frequency values in the fragment and then applying a scaling factor. In one example, the Delta T value is determined by the following method: respectively averaging the pilot frequency value of each symbol time (the value in each of the eight columns in Fig. 6), and then by comparing an average value with the following An average value is compared to compare these average values in order to determine how the average value changes over time. Each user segment has such a Delta T value. Similarly, in an example, the Delta F value is determined by averaging the pilot frequency value of a tone (a frequency) in all 8 symbol times. When calculating such averages for each tone, compare these averages by comparing one average to the next in order to determine the slope value of how the average changes with increasing frequency. There is such a Delta F value for each user fragment. The discussion on how to obtain these three values is simplified, and, in practice, these values can also be scaled. The processing circuit 115 provides the three determined parameter channel values 305 to the planar interpolator hardware 302.

9 is a schematic diagram of the DEMOD MMSE task command. If the MMSE demodulator is used, the DEMOD MMSE task command is used to provide the channel parameter value 305 from the processing circuit 115 to the MMSE demodulator (in the DEMOD WCSMSC 124). If an MRC demodulator is used, a similar DEMOD MRC task command (not shown) is used. The hardware plane interpolator hardware 302 calculates CA+y*(Delta F)+x*(Delta T) to determine the channel estimate of the tone at the frame coordinates (x, y), where x is the number of symbols (Time offset), and where y is the pitch number (index "f"). Therefore, the channel estimation value in the lower left corner of the fragment is CA. Therefore, the channel estimation value of the next position in the fragment upward along the left edge of the fragment is CA+(1*Delta F). The channel estimation value of the next position upward along the left edge of the fragment is CA+(2*Delta F). Similarly, along the time dimension (horizontal dimension), the channel estimate in the lower left corner of the fragment is CA. The channel estimate of the next position to the right along the bottom edge of the fragment is CA+(1*Delta T). The channel estimate of the next position to the right along the bottom edge of the fragment is CA+(2*Delta T). Therefore, it can be considered that the three channel parameters 305 define a plane in the three-dimensional space. The plane has a slope in the frequency dimension, and the plane has a slope in the time dimension.

In FIG. 10, the obtained 1024 determined channel estimation values are identified by reference numeral 306. The eight groups of these values 306 are buffered in the buffer 303. These channel estimation values 306 are provided to the MMSE or MRC demodulator module 204 as groups of 1024 channel estimation values 307. Line 308 indicates that 1024 channel estimates 307 are provided to the MMSE or MRC demodulator module 204. In this example, the modules 302, 303, and 204 are implemented by hardware in DEMOD WCSMSC 124 in Figure 3, and each value is transmitted from one of these modules to the next through a dedicated signal wire in DEMOD WCSMSC 124 to realise. The noise estimator function block 301 is implemented as firmware. The noise estimator function block 301 uses the narrowband pilot frequency to determine the estimated noise value of the frame, and provides this estimated noise value to the MMSE or MRC demodulator module 204. Subsequently, the MMSE or MRC demodulator 204 demodulates the data symbol values (I, Q) in the user chip (see the user chip 203 in FIG. 6) into demodulated symbols written into the chip buffer 128 Value (I, Q) and SNR value.

Figures 11A-11B collectively make up Figure 11. Figure 11 is a schematic diagram showing the novel method and demodulator WCSMSC 124, where the novel method and demodulator WCSMSC 124 can perform the channel estimation in the case of the "wideband pilot frequency" shown in Figure 5 and the channel estimation shown in Figure 6. The channel estimation in the case of the "narrowband pilot frequency" shown, but does not include the undesirably large 1024-point FFT 210 in FIG. 7. The demodulator WCSMSC 124 can operate according to the novel hybrid mode (wideband pilot frequency mode) and plane estimation and interpolation mode (narrowband pilot frequency) of FIG. 9. The functions of FIGS. 7 and 9 are not implemented by the digital baseband integrated circuit 103, and the new function of FIG. 11 is implemented by the digital baseband integrated circuit 103.

The operation of the demodulator in FIG. 11 in the plane estimation and interpolation mode is similar to the operation of the plane estimation and interpolation method and circuit described above in conjunction with FIG. 9. As shown by the line 400, the narrow-band pilot frequency value of the user segment is pushed to the processing circuit 115. The modules 300, 301, 302, 303, and 204 in FIG. 11 are the same modules as the modules 300, 301, 303, and 204 in FIG. The multiplexer function block 401 is controlled to provide the CA value, time coefficient or time slope value (Delta T) and the frequency coefficient or frequency slope value (Delta F) generated by the function module 300 to the planar interpolator hardwarebody302. The multiplexer function block 402 is controlled to provide the noise estimate from the noise estimator 301 to the MMSE or MRC demodulator 204.

However, the demodulator of Figure 11 can also operate in the novel "hybrid mode." Running in a mixed mode uses most of the functional processing of the broadband pilot channel estimation and demodulation method and circuit described above in conjunction with Figure 7, except for the use of the planar interpolator hardware 302, which eliminates the need for 1024 in Figure 7 The bigger one is the FFT function block 210 with strong processing capability. In FIG. 11, as shown by the line 403, the broadband pilot frequency value is pushed to the processing circuit 115. This includes using DEMOD push task instructions as described above in conjunction with Figure 7. The processing of the functional modules 206, 207, and 211 of FIG. 11 is the same as the processing of the functional modules 206, 207, and 211 of FIG. 7 described above. Process 207 output value k from time domain_STARTIndicates the position of the bottom of the 16-contact sliding window when the sliding window is in its final position. As described above in conjunction with FIG. 7, the value k output from the time domain processing 207_CIndicates the position of the energy center in the sliding window. However, the zero pad function module 404 extends multiple zero values in order to expand the 16 time domain contact sample values 208 into a smaller set of 64 time domain values, instead of expanding to the larger one in the case of FIG. 7 A set of 1024 time domain values. Subsequently, the smaller 64-point FFT function block 405 operates on the set of 64 time-domain joint sample values to generate 64 intermediate channel estimation values 406. However, the MMSE or MCR demodulator 204 requires 1024 channel estimates.

The existing planar interpolator hardware 302 is used to expand the 64 intermediate channel estimation values output by the 64-point FFT 405 into 1024 channel estimation values. The intermediate channel estimation value 406 is stored in a buffer 407 referred to herein as a channel estimation buffer. Unlike in the plane estimation mode and the interpolation mode, the functional module 300 collects the pilot frequencies and estimates the channel parameters of the pilot frequencies extracted from the symbol buffer 127. In the hybrid mode, the functional module 408 collects the pilot frequencies and performs Analyze and determine the channel parameters used by the planar interpolator hardware 302 to obtain a two-dimensional interpolation result. In this example, the function module 408 analyzes the middle channel estimation value from the channel estimation buffer 407, and calculates three channel parameter values 305 (channel average (CA), time coefficient or time slope value (Delta T) and frequency Coefficient or frequency slope value (Delta F)). The three channel parameter values 305 are determined by the processing represented by the function module 408 herein. In contrast to providing channel parameters from the function module 300, the multiplexing function module 401 indicates that the three determined parameters are provided to the hardware plane interpolator 302. By placing the calculated parameters into the DEMOD MMSE task instruction, the DEMOD WCSMSC The task manager 140 of 124 reads the task instruction and provides the channel parameters to the hardware interposer 302 to transmit the parameters. Similarly, in the hybrid mode, the multiplexer function block 402 is controlled so that the noise estimate from the noise estimator 301 is coupled to the noise input of the MMSE or MRC demodulator 204.

In addition, as shown by the arrow 409 in FIG. 11B, the processing circuit 115 determines the phase ramp parameter<i>k</i>_<i>C</i>and<i>k</i>_<i>START</i>. These parameters can be used to define the phase slope used to compensate for the time offset of a given block of OFDM data. Determine the time offset for each block of OFDM information (denoted as τ_d), and calculate the respective phase adjustment coefficient (phase correction coefficient) for each frequency in the OFDM module according to formula (1),

D_k=exp(-j 2πf_kτ_d) Formula 1)

Where f_kIt can be a subcarrier of any frequency in the OFDM signal. Subsequently, by multiplying each frequency band of the post FFT signal by D_k^-1, That is, the reciprocal of the above-mentioned phase adjustment coefficient, the time offset is corrected in the frequency domain, so as to effectively convert the signal in the time domain back to what it should have when there is no offset. See the following formula (13) for details.

<b>Formula-based hybrid mode description:</b>

Channel frequency impulse response<i>N</i>_<i>FFT</i>The 1024-point FFT is given by the following formula (2):

<maths><img file="TW201014283A_D0001.tif" /></maths>

The symbols used in the text,<i>N</i>_<i>FFT</i>Is the number of tones in the preamble signal. The indexes of these tones are 0, 1,...,<i>N</i>_<i>FFT</i>-1。<img file="TW201014283A_D0002.tif" />The value is the estimated value of the time domain channel, where<i>k</i>=0、1、...、<i>N</i>_<i>p</i>-1. The "a" value is the antenna index. If there is only one antenna as shown in this example, the index "a" has only one value and can be ignored.<i>N</i>_<i>p</i>Is the number of pilot frequencies in each F-PPICH OFDM symbol. Due to the FFT window position, the time-domain channel estimate has an unspecified phase slope. The actual phase-adjusted channel estimation is achieved by<img file="TW201014283A_D0003.tif" />The value is multiplied by the following quantity:

<maths><img file="TW201014283A_D0004.tif" /></maths>

In formula (3),<i>I</i>_<i>p</i>Is the absolute index of the first preamble signal tone. For this tone, the pilot frequency tone index is zero. "P" is not a digitized index, which is different from<i>I</i>_<i>s</i>"S" in.<i>I</i>_<i>s</i>It is determined by F-PPICH OFDM symbol s (s=0, 1) in F-PPICH (with<i>N</i>_<i>FFT</i>Index method) the smallest preamble signal tone occupied. Therefore, the F-PPICH occupancy index in F-PPICH OFDM symbol s is<i>k</i>Δ+<i>I</i>_<i>s</i>The pitch of k=0, 1,...,<i>N</i>_<i>p</i>-1. Noticed<i>I</i>_<i>s</i>The value of is 0, 1,..., Δ-1, and<i>I</i>₁=(<i>I</i>₀+(Δ/2))modΔ. The symbol Δ is the pilot frequency spacing in the tone and is equal to<i>N</i>_<i>FFT</i>/<i>N</i>_<i>P</i>, And the value 2 in this example. if<i>N</i>_<i>TILE</i>=<i>N</i>_<i>FFT</i>/<i>N</i>_<i>W</i>=16, the frequency pulse can be responded to<i>N</i>_<i>FFT</i>Expressed as the following formulas (4)-(6), where<i>N</i>_<i>TILE</i>Is the number of tones in the fragment.

<maths><img file="TW201014283A_D0005.tif" /></maths>

<maths><img file="TW201014283A_D0006.tif" /></maths>

<maths><img file="TW201014283A_D0007.tif" /></maths>

if<i>m</i>=<i>l</i>/<i>N</i>_<i>TILE</i>, Then the following formulas (7)-(8) are given:

<maths><img file="TW201014283A_D0008.tif" /></maths>

<maths><img file="TW201014283A_D0009.tif" /></maths>

Therefore, the 64-channel estimation value 406 output by the 64-point FFT 405 in FIG. 11 is given by the following formula (9), where the value of "m" ranges from 0 to 63.

<maths><img file="TW201014283A_D0010.tif" /></maths>

These 64 channel estimates 406 are used to obtain frequency coefficients (or frequency slope or Delta F) and time coefficients (or time slope or Delta T), where<img file="TW201014283A_D0011.tif" />Used to calculate the final slope.<i>k</i>_<i>C</i>The value is an integer index as described above, and<i>k</i>_<i>C</i>The value is such a digit, which ideally is small (<i>N</i>_<i>w</i>) In the FFT window (relative to the current<i>k</i>_<i>START</i>Value given<i>k</i>_<i>C</i>) The center position of the DC component, which is determined to minimize the error introduced by the linear interpolation represented by the frequency of the channel, which is represented by the contact point processed by the post-threshold in time. Separate the phase rotation introduced by the offset in time from the linear interpolation.

According to the following formulas (10), (11) and (12), determine the m-th 16-tone segment (ie, the segment with the pitch index from 16m to 16m+15,<i>m</i>=0,...,<i>N</i>_<i>W</i>) The three channel parameter values are 305. Equation (10) describes how to calculate the channel average (CA) component. Equation (11) describes how to calculate the frequency coefficient (or frequency slope or Delta F). Equation (12) shows how to calculate the time coefficient (or time slope or Delta T). "M" is an integer index that identifies the fragment in the frame. Therefore, a different set of three parameter values is calculated for each fragment indicated by the "m" index value. In this example, the time coefficient is set to zero, but in other embodiments, the time coefficient is determined in a manner similar to the frequency coefficient determined in formula (11), so that the time coefficient is determined at time (Figures 5 and 6). Interpolation is performed in the two dimensions of the horizontal dimension in the illustration) and the frequency (the vertical dimension in the illustration of FIG. 5 and FIG. 6).

<maths><img file="TW201014283A_D0012.tif" /></maths>

<maths><img file="TW201014283A_D0013.tif" /></maths>

<maths><img file="TW201014283A_D0014.tif" /></maths>

In the above formulas (10), (11) and (12), the calculated three channel parameter values are phase adjusted. In formula (10), the index value is the phase adjustment coefficient. In formula (11), the first index value is the phase adjustment coefficient.

<maths><img file="TW201014283A_D0015.tif" /></maths>

The above formula (13) is a formula for calculating the phase adjustment coefficient Φ(f). In the formula, the "f" value is an integer frequency (pitch) index indicating the frequency (pitch) in the chip for which the phase adjustment coefficient Φ(f) is calculated.<i>N</i>_<i>TILE</i>The value is the number of tones for which the channel value is calculated by the linear interpolator. In other words, there is (<i>N</i>_<i>TILE</i>-1) Tones, the channel values for these tones are unknown and calculated by the interpolator. In the example in Figure 11,<i>N</i>_<i>TILE</i>It is 16, because there are 64 values provided to the planar interpolator 302, and the interpolator outputs 1024 values. For example, to determine the phase adjustment coefficient Φ(f) of the third tone (data value) between the known channel values at tones 0 and 16, the "f" value is 3, and<i>N</i>_<i>FFT</i>The value is 1024.

Conceptually, the processing circuit 115 of FIG. 3 executes a program of processor-executable instructions 139 (see FIG. 3), thereby performing the calculations of formulas (10), (11), (12), and (13). Subsequently, the processing circuit 115 uses the DEMOD MMSE task command or the DEMOD MRC task command to provide the obtained three channel parameter values 305 to the DEMOD WCSMSC 124 in the plane interposer hardware 302. The planar interpolator 302 uses the three parameters 305 to perform the last step of the interpolation function to generate a two-dimensional array of channel estimates. The vertical dimension of the array represents frequency, and the horizontal dimension represents time. In addition to calculating the three parameters 305, the processing circuit 115 also uses formula (13) to calculate a set of phase adjustment coefficients, where as "f" increases from 0, a phase adjustment coefficient Φ is calculated for each frequency index value "f" (f). The processing circuit 115 writes the calculated phase adjustment coefficient Φ(f) (one Φ(f) for each value of ``f'') into the hardware plane interpolator 302 by directly passing through the second bus 120 (see FIG. 3) These phase adjustment coefficients are provided to the plane interpolator 302 in the register of (as shown by the arrow 410 in FIG. 11). Subsequently, the planar interpolator 302 uses the phase adjustment coefficient to multiply all the channel estimation values of the row corresponding to the frequency index value "f" in the two-dimensional array by the same phase adjustment coefficient. Similarly, in the two-dimensional array, all the channel estimation values in the next row corresponding to the second highest frequency index value "f" are multiplied by the same next phase adjustment coefficient. The result of multiplying each row of the two-dimensional array of channel estimation values by the corresponding phase adjustment coefficient is a two-dimensional array of phase-adjusted channel estimation values. The phase-adjusted channel estimates of this array are output from the planar interpolator 302, buffered, and provided to the demodulator 204 for demodulation. The flow of the phase-adjusted channel estimation value from the planar interpolator 302 to the buffer 303 and the MMSE or MRC demodulator 204 is realized through a dedicated hardware wire in the DEMOD WCSMSC 124.

FIG. 12 is a flowchart of the mixed mode operation 500 of FIG. 11. The wideband pilot frequency value is provided to the IFFT, thereby generating a first time domain value (step 501).

Time-domain processing is performed on the first time-domain value, thereby generating a second time-domain value (step 502). In one example, the time domain processing includes the functions 207 and 404 of FIG. 11. FFT processing is performed, thereby generating intermediate channel estimation values (step 503). In an example, these intermediate channel estimates are buffered 407. The estimated value of the intermediate channel is analyzed to generate channel parameters (step 504). In one example, the analysis is represented by the function module 408, and the channel parameters include channel average (CA), frequency coefficient (Delta F), and time coefficient (Delta T). The channel parameters are provided to the hardware interposer so that the hardware interposer generates a channel estimate (step 505). In an example, the processing circuit 115 will be based on the sliding window value k_CAnd k_STARTThe determined additional phase adjustment coefficient Φ(f) is provided to the hardware interpolator, so that the hardware interpolator also performs phase adjustment on the channel estimation. Use the obtained phase-adjusted channel estimation value to demodulate the data symbol value (I, Q) of the frame (step 506). The channel parameters vary from fragment to fragment of a frame, but the phase adjustment coefficient only varies from frame to frame. In FIG. 11, the data symbol value from the symbol buffer 127 is identified by the arrow labeled "I and Q symbol". The demodulated data symbol value entering the chip buffer 128 is identified by an arrow labeled "I and Q demodulated symbol SNR value".

FIG. 13 is a flowchart of the plane estimation mode operation 600 of FIG. 11. The narrowband pilot frequency value is analyzed to generate channel parameters (step 601). In one example, this analysis is represented by the function module 300 in FIG. 11, and the channel parameters include channel average (CA), frequency coefficient (Delta F), and time coefficient (Delta T). The channel parameters are provided to the hardware interposer, and the hardware interposer generates channel estimates accordingly (step 602). The channel estimation value is used to demodulate the data symbol value (I, Q) of the frame (step 603). In FIG. 11, the data symbol value from the symbol buffer 127 is identified by the arrow labeled "I and Q symbol". The demodulated data symbol value entering the chip buffer 128 is identified by an arrow labeled "I and Q demodulated symbol SNR value".

The various techniques described herein can be implemented in a variety of ways. In one or more exemplary embodiments, the described functions may be implemented as hardware, software, firmware, or any combination thereof. When implemented in software, this function can be stored as one or more instructions or codes on a computer readable medium or transmitted through one or more instructions or codes on a computer readable medium. Computer readable media include computer storage media and communication media. Communication media includes any media that facilitates the transfer of computer programs from one place to another. The storage medium can be any available medium that the computer can access. For example, but not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk memory, disk storage or other disk storage devices, or can be used to command or Any other medium that can be accessed by a computer in the form of a data structure that carries or stores the required code. Moreover, any connection can be appropriately referred to as a computer-readable medium. For example, if you use coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave to transmit software from a website, server, or other remote source, the coaxial cable , Fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio, and microwave are also included in the definition of media. The magnetic discs and discs used in this application include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVD), floppy discs and Blu-ray discs. The discs usually reproduce data magnetically, while the discs are optically Reproduce the information. The above combination should also be included in the scope of computer readable media.

Although the specific embodiments described above are for instructional purposes, the teachings of this patent document still have general applicability and are not limited to the specific embodiments described above. In some examples, the hardware interpolator can perform linear interpolation, and in other examples, the hardware interpolator can perform non-linear interpolation. In the above specific embodiment, although some of the functions represented by the functional modules are implemented by firmware/software, and other functions are implemented by dedicated hardware, which functions are implemented by hardware and which functions are implemented by firmware/software The way of dividing may be different in different embodiments. Therefore, without departing from the scope of the patent application proposed below, various modifications, adjustments, and combinations can be made to the various features of the specific embodiments described.

<p>101. . . antenna</p><p>102. . . RF transceiver integrated circuit</p><p>103. . . Digital baseband integrated circuit</p><p>104. . . Receiving chain</p><p>105. . . Launch chain</p><p>106. . . Input transmission</p><p>107. . . Diplexer</p><p>108. . . Matching network</p><p>109. . . Analog-to-digital converter</p><p>110. . . Digital-to-analog converter</p><p>111. . . Power amplifier</p><p>112. . . Output transmission</p><p>113. . . RX channel</p><p>114. . . TX channel</p><p>115. . . processor</p><p>116. . . Memory</p><p>117. . . High-speed memory</p><p>118. . . Data mover</p><p>119. . . First bus</p><p>120. . . Second bus</p><p>121. . . Elapsed time timer</p><p>122. . . front end</p><p>123. . . FFT</p><p>124. . . demodulation</p><p>125. . . DDE</p><p>126. . . Sample buffer</p><p>127. . . Symbol buffer</p><p>128. . . Fragment buffer</p><p>129. . . LLR buffer</p><p>130. . . Decode output buffer</p><p>131. . . Encoder module</p><p>132. . . Modulator</p><p>133. . . IFFT</p><p>134. . . Window and add</p><p>135. . . buffer</p><p>136. . . buffer</p><p>137. . . buffer</p><p>138. . . buffer</p><p>139. . . Program</p><p>140. . . Task manager</p>

FIG. 1 is a simplified high-level block diagram of a mobile communication device 100 according to a novel aspect.

FIG. 2 is a more detailed block diagram of the RF transceiver integrated circuit 102 of the mobile communication device of FIG. 1.

FIG. 3 is a more detailed schematic diagram of the digital baseband integrated circuit 103 of the mobile communication device of FIG. 1.

FIG. 4 is a schematic diagram showing OFDM symbols generated by the FFT WCSMSC 140 of FIG. 3.

FIG. 5 is a schematic diagram showing a frame including a "broadband" pilot frequency modulation symbol value.

Fig. 6 is a schematic diagram showing a frame including a "narrowband" pilot frequency modulation symbol value.

Figure 7 is a schematic diagram of the method and circuit of "Broadband Pilot Frequency Channel Estimation and Demodulation".

Figure 8 is a schematic diagram of a symbol buffer push task instruction.

Figure 9 is a schematic diagram of the DEMOD MMSE task instruction.

Figure 10 is a schematic diagram of the "planar estimation and interpolation" method and circuit.

Figures 11A and 11B together form a schematic diagram illustrating a novel method and novel demodulator WCSMSC 124, where the method and demodulator WCSMSC 124 can perform channel estimation in the case of "wideband pilot frequency" shown in Figure 5 , And the channel estimation in the case of the "narrow frequency pilot frequency" shown in FIG. 6, but the larger 1024-point FFT 210 in FIG. 7 is not required.

FIG. 12 is a simplified flowchart showing the operation of the hybrid mode of FIG. 11.

FIG. 13 is a simplified flowchart showing the operation of the plane estimation and interpolation mode in FIG. 11.