Digital-to-analog converter

Digital to analog converter

The subject matter of this manual is generally about digital-to-analog converters.

A digital-to-analog converter (DAC) is a device used to convert a digital program code into an analog signal. For example, a DAC can convert an 8-bit digital signal into an output voltage or current having an amplitude representing a digital code. Two common examples of DAC are "R-string" DAC and "R-2R trapezoidal" DAC. Another example is the shunt resistor architecture (RRA) DAC. The advantages of PRA-DAC over "R-string" DAC and "R-2R trapezoidal" DAC include: Compared with "R-2R trapezoidal" DAC, PRA-DAC has a constant output impedance and inherent monotonicity.

When an input (for example, a digital program code) changes, the output of a DAC (for example, an analog signal) stabilizes to a value after a delay called a stabilization time. The settling time depends on the output resistance Rout of the DAC and a capacitive load CL at the output of the DAC. Specifically, the settling time depends on a time constant that can be defined by the product of Rout and CL. The stabilization time can limit the conversion speed of one of the DACs.

The present invention discloses a PRA-DAC. The PRA-DAC can be operated to increase its conversion speed.

One of the advantages of the PRA-DAC is that its conversion speed can be increased without (i) not affecting resistor matching, thereby maintaining the linearity of the PRA-DAC; and (ii) not increasing the power consumption during a fine stabilization period.

Example PRA-DAC

Figure 1 illustrates a schematic circuit diagram of an exemplary PRA-DAC 100. In this example, the PRA-DAC 100 receives a digital input D with one of N bits (for example, d₀, D₁,..., d_N-1) An N-bit DAC. Based on a received D, the PRA-DAC 100 generates an analog voltage output Vout. In one example, Vout can increase monotonically with D. For example, if D₁>D₂, Then Vout_D1>Vout_D2。

The PRA-DAC 100 includes a resistor network. The resistor network contains 2^NSet the resistance element 110 in parallel. In some implementations, a capacitive load CL can be coupled to the resistor network at the output of PRA-DAC 100. In this example, each of the sets of parallel resistance elements 110 includes a resistance element RA and a resistance element RB. The groups of parallel resistance elements 110 have substantially the same resistance R=RA+RB. One of the groups of parallel resistance elements 110a is connected to the ground GND. 2 of these groups of parallel resistance elements^NThe -1 110b is coupled to a first switching network. The first switch network includes switches S1, S2,..., S2^N-1. S1 to S2^N-1 can control the 2 to be connected to a reference voltage Vref or to GND^N-1 set of parallel resistance elements 110b.

S1 to S2^N-1 is based on a control word generated by a decoder 120 to connect the sets of parallel resistance elements 110b. For example, S1 to S2^N-1 can be configured such that: if a control signal representing a logic 1 is received, a switch connects a connected resistor to Vref; and if a control signal representing a logic 0 is received, the switch will The connected resistor is connected to GND. Other reference levels can also be used. In some implementations, a switch can be a transistor that is biased to function as a switch. There may be other implementation options.

The decoder 120 generates a 2 based on the received D^N-1 bit control word. In some embodiments, each control bit in the control word corresponds to switches S1 to S2^NOne of -1. Based on the corresponding control bit, S1 to S2^N-1 can connect these groups of parallel resistance elements 110b to Vref or GND. In some implementations, the control word can be a decoded representation of one of D. For a given D (for example, D is 0 and 2^NAn integer between -1), 2^N-1 D of the control bits can be at logic 1 and 2 of these control bits^N-D can be at logic 0. In some embodiments, since the decoder 120 is configured to generate 2^N-1 of the control signals are at logic 1 D, so the D of the groups of parallel resistance elements 110 is connected to Vref and 2^N-D resistors are connected to GND.

Therefore, the PRA-DAC 100 can generate Vout based on a divided voltage between the sets of parallel resistance elements 110 connected to Vref and the sets of parallel resistance elements 110 connected to GND. In some embodiments, the equivalent resistance between Vref and Vout is approximately<img file="TW201014197A_D0001.tif" />, And the equivalent resistance between Vout and GND is approximately<img file="TW201014197A_D0002.tif" />. PRA-DAC 100 can generate Vout based on D(Vout(D)) according to the following equation:

<maths><img file="TW201014197A_D0003.tif" /></maths>

The PRA-DAC 100 can generate Vout(D) that is substantially monotonic with respect to D. For example, when D is incremented by 1 (for example, from D to D+1), an additional resistance element is connected to Vref. Therefore, Vout(D) is less than Vout(D+1). In some implementations, the monotonic nature of the PRA-DAC 100 is substantially independent of the matching quality of the sets of parallel resistance elements 110. For example, if the sets of parallel resistance elements 110 are poorly matched, resulting in a resistance that crosses the height of the sets of parallel resistance elements 110, the monotonic nature of the PRA-DAC 100 can be maintained roughly because there is still More resistors are connected to Vref.

As shown, the PRA-DAC 100 draws a reference current Iref from Vref. In this example, Iref first flows from a node at Vref through the group D parallel resistance element 110 to a node at Vout, and then from Vout through 2^N-D group of parallel resistance elements 110 flow to GND. Looking at D, Iref(D) can be expressed as:

<maths><img file="TW201014197A_D0004.tif" /></maths>

According to the above equation, Iref(D) can be expressed as:

<maths><img file="TW201014197A_D0005.tif" /></maths>

By rearranging the above equation, Iref(D) can be expressed as:

<maths><img file="TW201014197A_D0006.tif" /></maths>

Note that Iref(D) is dependent on a second-order polynomial of D. Iref(D) has a minimum value when D=0. The minimum value of Iref(D) is:

<i>I</i>_min=<i>Iref</i>(<i>D</i>=0)=0

In the middle scale (2^N-1), Iref(D) increases to a maximum value. The maximum value of Iref(D) is:

<maths><img file="TW201014197A_D0007.tif" /></maths>

After the middle scale, Iref(D) decreases symmetrically to:

<maths><img file="TW201014197A_D0008.tif" /></maths>

The output resistance (Rout(D)) of PRA-DAC 100 at D includes and<img file="TW201014197A_D0009.tif" />Parallel resistance<img file="TW201014197A_D0010.tif" />. Solving the equivalent resistance, Rout(D) can be expressed as<img file="TW201014197A_D0011.tif" />, Where Rout is independent of D.

Settling time and conversion speed

When D changes, Vout(D) is called stable time t_SETTLEOne of them stabilizes to a value (for example, a final value) after a delay. For example, when Vout(D) and<img file="TW201014197A_D0012.tif" />The difference is less than<img file="TW201014197A_D0013.tif" />(E.g,<img file="TW201014197A_D0014.tif" />), Vout(D) can be regarded as stable to its final value.

As one of the PRA-DAC 100 conversion speed f_S(For example, the rate of change of D) depends on t_SETTLE, Therefore f_SWill not be greater than<img file="TW201014197A_D0015.tif" />. For example, depending on the rate of change of D,<img file="TW201014197A_D0016.tif" />(For example, one cycle of D) Vout(D) can be compared with<img file="TW201014197A_D0017.tif" />The difference is greater than<img file="TW201014197A_D0018.tif" />(E.g,<img file="TW201014197A_D0019.tif" />. Therefore, f_SOne of the maximum values can be expressed as:

<maths><img file="TW201014197A_D0020.tif" /></maths>

As explained earlier, t_SETTLEDependent on τ_DAC. τ_DACCan be expressed as:

<maths><img file="TW201014197A_D0021.tif" /></maths>

For a first-order system, Vout(D) is exponentially stable and can be expressed as:

<maths><img file="TW201014197A_D0022.tif" /></maths>

<i>t</i>=τ_<i>DAC</i>The time Vout(t) can be expressed as: Expression [1]<img file="TW201014197A_D0023.tif" />By simplifying,<i>Vout</i>(<i>t</i>=τ_<i>DAC</i>) Can be expressed as:

<maths><img file="TW201014197A_D0024.tif" /></maths>

For a first-order system, t_SETTLEWith τ_<i>DAC</i>The relationship between can also depend on N. Similarly, when Vout(D) and<img file="TW201014197A_D0025.tif" />The difference is less than<img file="TW201014197A_D0026.tif" />At this time, Vout(D) can be considered to have stabilized to its final value. This condition can also be expressed as: expression [2]

<maths><img file="TW201014197A_D0027.tif" /></maths>

Generally speaking,<i>Vout</i>(<i>t</i>=0)=0 and<i>Vout</i>(<i>t</i>=0)=0. By using expression [1], Vout(t) can be expressed as: expression [3]

<maths><img file="TW201014197A_D0028.tif" /></maths>

By using expression [3] and expression [2], the condition can be expressed as:

<maths><img file="TW201014197A_D0029.tif" /></maths>

By using the Neperian logarithm, the condition can be expressed as:

<maths><img file="TW201014197A_D0030.tif" /></maths>

<maths><img file="TW201014197A_D0031.tif" /></maths>

Therefore, the condition can be expressed as:

t_SETTLE&gt;(<i>N</i>+1)ln(2)τ_<i>DAC</i>,

t_SETTLE&gt;(<i>N</i>+1)ln(2)<i>Rout</i>‧<i>CL</i>,or

<maths><img file="TW201014197A_D0032.tif" /></maths>

Example PRA-DAC conversion speed

As discussed earlier, f_SDepends on t_SETTLE, T_SETTLEDependent on τ_DAC, And τ_DACDepends on Rout. Therefore, t can be reduced by reducing the Rout of PRA-DAC 100_SETTLE. Permanently reducing Rout can result in increased power consumption that can be proportional to the reduction in Rout. In addition, for example, reducing the resistance of the resistance element in the PRA-DAC can reduce the resistance matching (for example, matching the actual resistance values of the sets of parallel resistance elements 110, including the actual resistance values of RA and RB). quality. For example, in various embodiments, the actual resistance value of the resistor RA (eg, RA coupled to S1, RA coupled to S2, RA coupled to S3, etc.) should be matched or approximately the same value. As another example, the actual resistance value of the resistor RB (for example, RB coupled to S1', RB coupled to S2', RB coupled to S3', etc.) should be matched or approximately the same value.

If the resistance of the resistance elements decreases, the resistor matching can become, for example, more susceptible to parasitic resistance (e.g., the parasitic resistance of the switch between the resistors and the metal wiring). Since the actual resistances of the sets of parallel resistance elements 110 may not be approximately the same value, for example, the voltage division between the sets of parallel resistance elements 110 connected to Vref can be changed, thereby affecting Vout. Since the linearity of the PRA-DAC 100 depends on the resistor matching, the linearity can be reduced.

Referring to FIG. 1, the PRA-DAC 100 is operable to temporarily reduce Rout. When receiving a first input signal PHI1 (for example, a clock signal) at the decoder 120, f_S. The resistance element RA in the groups of parallel resistance elements 110 can be coupled to a second switching network. The second switch network includes switches S0', S1', S2',..., S(2^N-1)'. The second switching network is operable to short-circuit the resistance element RA in response to a second input signal PHI2. For example, when PHI2 is high (for example, represented by logic 1), the second switching network can short-circuit the resistance element RA. Another option is that when PHI2 is low (for example, represented by a logic 0), the second switching network is turned off. Other reference levels can be used.

When the second switch network is disconnected, the groups of parallel resistance elements 110 have a resistance R=RA+RB. Short-circuiting the resistance element RA causes the groups of parallel resistance elements 110 to have a resistance R=RB. due to<img file="TW201014197A_D0033.tif" />, So Rout decreases. Therefore, τ_DACAnd t_SETTLEDecrease, and f_SCan be increased.

FIG. 2 is a diagram 200 including an exemplary resistance value of the adjustable resistance element in the PRA-DAC of FIG. 1. The diagram 200 also includes operations (for example, disconnection and conduction) S1 to S2 of FIG. 1^NOne of -1 control signal S. As shown in Figure 2, PHI1 can be used to temporarily reduce Rout.

PHI2 can depend on PHI1. In particular, PHI2 can be high in the first part of a clock cycle of PHI1. The first part may correspond to a rough stable period, where R=B. During the rough stabilization period, Vout(t) corresponds to the time constant due to<img file="TW201014197A_D0034.tif" />And stable. The first part of PHI2 can be followed by a second part of the clock cycle of PHI1, where PHI2 is low. The second part corresponds to a fine stabilization period, where R=RA+RB. During the fine stabilization period, Vout(t) corresponds to the time constant<img file="TW201014197A_D0035.tif" />And stable.

Since Rout temporarily decreases during the first part of the clock cycle of PHI1, τ_DACAnd t_SETTLEIt can be decreased during the first part of the clock cycle of PHI1. In addition, since R can be equal to (RA+RB) during the second part of the clock cycle of PHI1, the linearity of the PRA-DAC 100 can be maintained during the second part of the clock cycle of PHI1. In addition, the increased power consumption of the PRA-DAC 100 can be limited to the first part of the clock cycle of PHI1.

FIG. 3 is a diagram 300 illustrating one of example stabilization times. Specifically, Figure 3 illustrates<img file="TW201014197A_D0036.tif" />One example of PRA-DAC stabilization time. therefore,<img file="TW201014197A_D0037.tif" />. When Rout decreases temporarily, Vout is<i>t</i>=τ_DACTime stabilizes to approximately 63% of a final value (e.g., as illustrated by curve 310), and this ratio is not temporarily reduced when Rout (e.g., as shown by curve 320 at<i>t</i>=τ_DACIllustrated at the time) is about three times faster. In addition, when Rout decreases temporarily, t_SETTLE1&lt;t_SETTLE2。

In this example, PHI2 has been configured so that a rough settling period is equal to τ_DAC. After coarse stabilization, the following fine stabilization period corresponds to τ_DAC. In some embodiments, PHI2 can be generated so that PHI2 is high during the entire clock cycle of PHI1. There may also be other configurations.

Although one implementation of a PRA-DAC is described (for example, PRA-DAC 100 of FIG. 1), other implementations are possible. For example, the PRA-DAC may include other structures that allow the PRA-DAC to temporarily reduce Rout. For example, other types of resistance elements (e.g., transistors) can be used. As another example, the resistance element of the PRA-DAC can be an adjustable resistance element (for example, a variable resistor). As another example, the sets of parallel resistance elements 110 of FIG. 1 may alternatively include switching resistors connected in parallel.

Several embodiments of the invention have been described herein. However, it will be understood that various modifications can be made without departing from the spirit and scope of the invention. Therefore, other implementation schemes also fall within the scope of the following patent applications.

<p>100. . . PRA-DAC</p><p>110a. . . Resistance element</p><p>110b. . . Resistance element</p><p>120. . . decoder</p>

Figure 1 illustrates a schematic circuit diagram of an exemplary PRA-DAC;

FIG. 2 is a diagram containing an exemplary resistance value of the adjustable resistance element in the PRA-DAC of FIG. 1; and

Figure 3 is a diagram illustrating an exemplary settling time.

In the drawings, similar reference signs indicate similar elements.