Track and hold amplifiers and analog to digital converters

Track and hold amplifiers and analog-to-digital converters

The present invention relates to a track and hold amplifier, and more specifically, to an analog to digital converter with a front-end track and hold amplifier.

At present, analog to digital (Analog to Digital, A/D) converters are widely used in various applications, such as medical systems, audio systems, test and measurement equipment, communication systems, and image and video systems.

The track and hold amplifier is often used as the front end of the A/D converter, tracking an analog input signal and holding the analog input signal at its output at a specific time until the maintained analog input signal is received by other circuits of the A/D converter. So that the A/D converter can correctly convert the analog input signal into a digital signal. However, in fact, the inherent nonlinearity of the amplifier or the buffer used in the track-and-hold amplifier will reduce the resolution of the A/D converter, so that the digital signal cannot accurately represent the analog input signal. .

Therefore, it is necessary to correct the non-linearity of the tracking and holding amplifier in the A/D converter.

Since the inherent nonlinearity of the amplifier or the buffer used in the track-and-hold amplifier in the prior art will reduce the resolution of the A/D converter, the digital signal cannot accurately represent the analog signal. In view of this, the object of the present invention One is to provide a track-and-hold amplifier and analog-to-digital converter.

The present invention provides a track and hold amplifier, which includes: an input node that receives an analog signal; a buffer coupled between a first node and an output node; a first switch coupled to the input node and Between the first node; a plurality of switching circuits, each of the switching circuits includes a capacitor coupled between the first node and a second node; and a voltage generating unit to the capacitors of the plurality of switching circuits A common signal and a reference signal are selectively provided, wherein the reference signal is independent of the analog signal and the common signal.

The present invention also provides an analog-to-digital converter for converting an input signal into an output signal, comprising: a track and hold amplifier for receiving the input signal and generating a sampling signal, including: an input node for receiving the input Signal; a buffer, coupled between a first node and an output node; a first switch, coupled between the input node and the first node; a plurality of switching circuits, each of the switching circuits includes: A capacitor coupled between the first node and a second node; a second switch coupled between the second node and a common node; and a third switch coupled to the second node, Wherein when the first switch is turned on, the second switch is turned on, the third switch is turned off, when the third switch is turned on, the first switch and the second switch are turned off; and a voltage is generated Unit, coupled to the third switch of each of the switching circuits, and selectively providing a common signal and a reference signal to the third switch of the switching circuit, wherein the reference signal is independent of the input signal and the common Signal; a quantizer to quantize the sampled signal to generate a quantized signal; and a correction processor to correct the quantized signal to generate the output signal.

Another track and hold amplifier of the present invention includes: an input node receiving an analog signal; an amplifier having a non-inverting input node, an inverting input node, and an output node, wherein the non-inverting input node is coupled to a A common node; a first switch, coupled between the inverting input node and the common node; a plurality of switching circuits, each of the switching circuits includes: a capacitor coupled to the inverting input node and a first Between nodes; a second switch, coupled between the first node and the input node; a third switch, coupled to the first node; and a fourth switch, coupled to the first node and Between the output nodes, the third switch and the fourth switch are synchronized, and when the first switch is turned on, the second switch is turned on, and the third switch is turned off. When the device is turned on, the first switch and the second switch are turned off; and a voltage generating unit, coupled to each of the third switches of the switching circuit, is selective to the third switch of the switching circuit The ground provides a common signal and a reference signal, wherein the reference signal is independent of the analog signal and the common signal.

Another type of ratio-to-digital converter of the present invention is used to convert an input signal into an output signal. It includes: a track and hold amplifier for receiving the input signal and generating a sampling signal, including; an input node for receiving the input signal An amplifier having a non-inverting input node, an inverting input node and an output node, wherein the non-inverting input node is coupled to a common node; a first switch is coupled to the inverting input node and the A plurality of switching circuits, each of the switching circuits includes: a capacitor, coupled between a first node and the inverting input node; a second switch, coupled to the first node and the input Between nodes; a third switch, coupled to the first node; a fourth switch, coupled between the first node and the output node, wherein the third switch and the fourth switch are synchronized, when When the first switch is turned on, the second switch is turned on, and the third switch is turned off. When the third switch is turned on, the first switch and the second switch are turned off; and a voltage generating unit, The third switch coupled to each of the switching circuits selectively provides a common signal and a reference signal to the third switch of the switching circuit, wherein the reference signal is independent of the input signal and the common signal A quantizer to quantize the sampled signal to generate a quantized signal; and a correction processor to correct the quantized signal to generate the output signal.

The invention can reduce the inherent nonlinearity of the tracking and holding amplifier, improve the resolution of the A/D converter, and make the output digital signal more accurate.

In order to make the objectives, features, and advantages of the present invention more comprehensible, preferred embodiments are described below in detail. The examples are used to illustrate the present invention, but not to limit the present invention. The protection scope of the present invention is subject to the scope of the attached patent application.

FIG. 1 is a schematic diagram of a simple track and hold amplifier 100. The track and hold amplifier 100 includes a switch 110, a buffer 120, and a capacitor 130. The switch 110 is composed of a signal Φ₁control. During the track mode (ie, the switch 110 is turned on), the input of the track and hold amplifier 100 receives the analog input signal x, and transmits the x signal to the capacitor 130, which is coupled to the input of the buffer 120. During the hold mode (ie, the switch 110 is off), the capacitor 130 is de-coupled from the input of the track and hold amplifier 100, so that a charging voltage is maintained on the capacitor 130. Then, an output signal y of the buffer 120 is transmitted to the subsequent circuit of the A/D converter. In Figure 1, the capacitance value of capacitor 130 is C_S。

FIG. 2 is a schematic diagram of an A/D converter 200 according to an embodiment of the invention. The A/D converter 200 includes a track and hold amplifier 210, an N-bit quantizer 250, and a correction processor 260. The track and hold amplifier 210 tracks and holds an analog input signal x to generate a sampled signal y. Then, the N-bit quantizer 250 quantizes the sampled signal y to generate an N-bit digital signal D_y. Finally, the correction processor 260 receives the quantized signal D_y, And correct the quantized signal D caused by the track and hold amplifier 210_yNonlinearity to generate a digital output signal<img file="TW201014195A_D0001.tif" />。

As shown in Figure 2, the track and hold amplifier 210 is an open-loop circuit, including a switch SW1 and a plurality of switching circuits 220₁-220_n, The buffer 230 and the voltage generating unit 240. The switch SW1 is determined by the signal Φ₁Control, coupled to input node N_inAnd node N₁From the input node N_inReceive analog input signal x. Buffer 230 is coupled to node N₁And an output node N_outbetween. In some embodiments, the buffer 230 is a gain amplifier. Switching circuit 220₁-220_nEach of them is coupled to node N₁And the voltage generating unit 240. Switching circuit 220₁-220_nThere are similar architectures, and each switching circuit can contain a capacitor and two switches. To switch circuit 220₁As an example, the switching circuit 220₁Contains capacitor C₁, Switch SW2 and switch SW3, in which capacitor C₁Coupled to node N₁And node N₂In the meantime, the switch SW2 is coupled to the node N₂And a public node V_com1In the meantime, the switch SW3 is coupled to the node N₂And the voltage generating unit 240. Voltage generating unit 240 to switching circuit 220₁-220_nSelectively provide common signal V_comAnd reference signal V_ref, Where the reference signal V_refIt can be irrelevant to the analog input signal X and the common signal V_comAny signal. And, the common signal V_comThe voltage can be compared with the common node V_com1The voltages provided are equal or not equal. Furthermore, in the track and hold amplifier 210, each switch SW2 is determined by the signal Φ_1aEach switch SW3 is controlled by the signal Φ₂Control, where the switch SW2 and the switch SW3 are turned on non-simultaneously. Figures 3A and 3B show the signal Φ₁, Φ_1aAnd Φ₂Waveform diagrams of different embodiments of the phase relationship between the two, in which the Φ shown in Figure 3B_1aAnd Φ₂It is a non-overlapping clock signal.

Refer to Figure 2 and Figure 3A, when the signal Φ₁When it is a high level voltage (tracking mode), the switches SW1 and SW2 are turned on and the switch SW3 is turned off. In tracking mode, node N₁Signal X_rIt is equal to the analog input signal X. When the signal Φ₂When it is a high level voltage (hold mode), the switches SW1 and SW2 are turned off and the switch SW3 is turned on. As shown in Figure 2, during the holding mode, the voltage generating unit 240 provides a reference voltage V_refTo switching circuit 220_i, And provide a common signal V_comTo other switching circuits (i.e. except switching circuit 220_iOther switching circuit 220₁-220_n). The signal x can be calculated by the following equation (1)_r：

<maths><img file="TW201014195A_D0002.tif" /></maths>

Then signal x_rIt can be written as the following equation (2):

<maths><img file="TW201014195A_D0003.tif" /></maths>

Where q₁Is a sequence that has nothing to do with the analog input signal x, the sequence can be a binary sequence, R is a predetermined value and<img file="TW201014195A_D0004.tif" />. And, in the present invention, the sum of capacitor values<img file="TW201014195A_D0005.tif" />And the value C of capacitor 130 shown in Figure 1_Sequal. In one embodiment, the capacitor C₁-C_nCan have unequal capacitance values to obtain randomness to correct non-linearity. For example, the value of each capacitor can be the unit capacitance value C_unitOr C_unitTo the 2n power (n is any integer greater than 0), namely C_unit, C_unit², C_unit⁴Wait. Next, the buffer 230 receives the signal x_r, Generate sampling signal y. Due to the non-linearity of the buffer 230, the sampling signal y can be expressed as a polynomial as shown in the following equation (3):

<maths><img file="TW201014195A_D0006.tif" /></maths>

If the input and output characteristics of the buffer 230 are monotonic, the signal x_rIt can be expressed as the following equation (4):

<i>x</i>_<i>r</i>=<i>b</i>₀+<i>b</i>₁×<i>y</i>+<i>b</i>₂×<i>y</i>²+<i>b</i>₃×<i>y</i>³+…　(4)

Then, the N-bit quantizer 250 quantizes the sampled signal y to generate an N-bit digital signal D_y, And the correction processor 260 corrects the N-bit digital signal D_yTo generate digital output signals<img file="TW201014195A_D0007.tif" />, Where the digital output signal<img file="TW201014195A_D0008.tif" />Is signal x_rThe estimation in the digital domain can be expressed as the following equation (5):

<maths><img file="TW201014195A_D0009.tif" /></maths>

Because the digital output signal<img file="TW201014195A_D0010.tif" />Highly approximate signal x_r, According to equations (4) and (5) the signal x_rIt can be expressed as the following equation (6):

<maths><img file="TW201014195A_D0011.tif" /></maths>

Then, the expected values related to the q value on both sides of equation (6) can be calculated by the following equation (7):

<maths><img file="TW201014195A_D0012.tif" /></maths>

Where q₂Can be the same as q₁A sequence of zero-mean binary values with the same waveform. After that, equation (7) can be written as the following equation (8):

<maths><img file="TW201014195A_D0013.tif" /></maths>

And, suppose that in the holding mode, the voltage generating unit 240 provides the reference signal V_refTo switching circuit 220_j(Not shown in the figure) instead of switching circuit 220_i,Provide common signal V_comTo other switching circuits (i.e. except switching circuit 220_jSwitching circuits other than 2201-220_n), R_jIt can be calculated and expressed as the following equation (9):

<maths><img file="TW201014195A_D0014.tif" /></maths>

And, suppose that in the holding mode, the voltage generating unit 240 provides the reference signal V_refTo switching circuit 220_jAnd switching circuit 220_i, And provide a common signal V_comTo other switching circuits (i.e. except switching circuit 220_jAnd 220_iOther switching circuit 220₁-220_n), R_tIt can be calculated and expressed as the following equation (10):

<maths><img file="TW201014195A_D0015.tif" /></maths>

Due to linear characteristics and according to equations (8), (9) and (10), equation (11) can be calculated as follows:

<maths><img file="TW201014195A_D0016.tif" /></maths>

As mentioned above, any R_tBy switching circuit 220₁-220_nSelect two different switching circuits to obtain. Then, by solving the couplet differential equation (11), the correction processor 260 can obtain the differential value Δb to correct the non-linearity caused by the buffer 230. For example, solve two difference equations (11) to obtain Δb₂And Δb₃, So the nonlinearity caused by the second-order and third-order factors of the above equation can be compensated.

In addition, the voltage generating unit 240 provides the reference signal V according to a predetermined sequence (specific sequence)_refTo switching circuit 220₁-220_n. In an embodiment, the voltage generating unit 240 may sequentially provide the reference signal V during the time period T_refTo switching circuit 220₁-220_n, Where the time period T contains multiple sub-time periods. For example, the voltage generating unit 240 can be used in the sub-time period t₁Provide reference signal V_refTo switching circuit 220₁, And provide the common signal V_comTo switching circuit 220₂-220_n, Where the sub-period t₁Contains the signal Φ as shown in Figure 3A or 3B₂Multiple clock cycles. Next, the voltage generating unit 240 operates in the sub-time period t₂Provide reference signal V_refTo switching circuit 220₂, In the sub-period t₃Provide reference signal V_refTo switching circuit 220₃Etc., where the sub-period t₁To t_nThe length can be the same. In another embodiment, the voltage generating unit 240 provides the reference signal V during the time period T_refTo switching circuit 220₁-220_n. For example, the voltage generating unit 240 is in the sub-time period t₁Provide reference signal V_refTo switching circuit 220₃, In the sub-period t₂Provide reference signal V_refTo switching circuit 220_n, In the sub-period t₃Provide reference signal V_refTo switching circuit 220₁. In another embodiment, the voltage generating unit 240 can simultaneously provide the reference signal V_refTo multiple switching circuits. For example, the voltage generating unit 240 is in the sub-time period t₁Provide reference signal V_refTo switching circuit 220₁And 220₂, In the sub-period t₂Provide reference signal V_refTo switching circuit 220₃And 220₄。

In the present invention, the reference signal V provided to the switching circuit of the tracking and holding amplifier_refThe order or number of the A/D converters can be the same or different, and can be determined and adjusted according to the design and accuracy of the A/D converter. And, the reference signal V_refThe period, duty cycle or amplitude can be the same or different, and can also be determined and adjusted according to the design and accuracy of the A/D converter. Moreover, in an embodiment, the values of all capacitors of the tracking and holding amplifier may be the same or different.

FIG. 4 is a schematic diagram of a track and hold amplifier 400 according to another embodiment of the present invention. The track and hold amplifier 400 is a closed-loop circuit, and includes a switch SW1, a plurality of switching circuits, an amplifier 420, and a voltage generating unit 430. The switch SW1 is coupled to a public node V_com1And the inverting input node of the amplifier 420, and the signal Φ as shown in Fig. 3A or Fig. 3B₁control. Each switching circuit is coupled to node N_inAnd the inverting input node of the amplifier 420, where the slave node N_inReceive analog input signal x. The structure of the switching circuit can be similar, and each switching circuit can include a capacitor and three switches. To switch circuit 410₁As an example, the switching circuit 410₁Contains capacitor C₁, Switch SW2, switch SW3 and switch SW4, in which capacitor C₁Coupled to node N₃And the inverting input node of the amplifier 420, the switch SW2 is coupled to the node N_inAnd node N₃In the meantime, the switch SW3 is coupled to the node N₃And the voltage generating unit 430, the switch SW4 is coupled to the output node N_outAnd node N₃between.

In the track-and-hold amplifier 400, each switch SW2 can be generated by the signal Φ shown in Fig. 3A or Fig. 3B_1aEach switch SW3 and SW4 can be controlled by the signal Φ shown in Figure 3A or Figure 3B.₂Control, so the switches SW3 and SW4 can be synchronous (synchronous). Moreover, the non-inverting input node of the amplifier 420 is coupled to the common node V_com1, The output of the amplifier 420 is coupled to the output node N_out. Similarly, the voltage generating unit 430 selectively provides the common signal V to the switching circuit_comAnd reference signal V_ref, And can provide the reference signal V to the switching circuit according to the preset sequence as described above_ref. Common signal V_comThe voltage can be compared with the common node V_com1The voltages provided are equal or not equal.

FIG. 5 is a schematic diagram of a track and hold amplifier 500 according to another embodiment of the present invention. The track and hold amplifier is a closed loop circuit, including two switches SW1, multiple switching circuits, amplifier 520, and two voltage generating units 530A and 530B. Compared with the amplifier 420 shown in FIG. 4, the amplifier 520 is a fully differential amplifier. To switch circuit 510A₁And 510B₁As an example, the switching circuit 510A₁Coupled to node N_in+And the reverse input node of amplifier 520, from node N_in+Receive analog input signal x, switch circuit 510B₁Coupled to node N_in-And the non-inverting input node of amplifier 520, from node N_in-Receive analog input signal x. In addition, the non-inverting output node and the inverting output node of the amplifier 520 are respectively coupled to the output node N_out+And N_out-. The voltage generating unit 530A is coupled to the node N_in+The switching circuit selectively provides the common signal V_comAnd reference signal V_rp, The voltage generating unit 530B is coupled to the node N_in-The switching circuit selectively provides the common signal V_comAnd reference signal V_rn. In this embodiment, the track and hold amplifier can track and hold the analog input signal x, and generate two sampling signals y+ and y-. Then, as described above, a successional quantizer (not shown in the figure) can quantize the sampled signal y+ or y- to generate a digital signal D_y。

Although the present invention has been disclosed as above in the preferred embodiment, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

<p>100. . . Track and hold amplifier</p><p>110. . . Switcher</p><p>120. . . buffer</p><p>130. . . Capacitor</p><p>200. . . A/D converter</p><p>210. . . Track and hold amplifier</p><p>230. . . buffer</p><p>240. . . Voltage generating unit</p><p>250. . . N-bit quantizer</p><p>260. . . Correction processor</p><p>SW1, SW2, SW3, SW4. . . Switcher</p><p>220₁-220_n. . . Switching circuit</p><p>C₁-C_n. . . Capacitor</p><p>400, 500. . . Track and hold amplifier</p><p>420. . . Amplifier</p><p>410₁. . . Switching circuit</p><p>430. . . Voltage generating unit</p><p>510A₁, 510B₁. . . Switching circuit</p><p>520. . . Amplifier</p><p>530A, 530B. . . Voltage generating unit</p>

Figure 1 is a simple schematic diagram of a track and hold amplifier;

Figure 2 is a schematic diagram of an A/D converter according to an embodiment of the invention;

Figures 3A and 3B show the signal Φ₁, Φ_1aAnd Φ₂S waveform;

Figure 4 is a schematic diagram of a track and hold amplifier according to another embodiment of the present invention;

Figure 5 is a schematic diagram of a track and hold amplifier according to another embodiment of the present invention.