Multiple port SRAM cells and devices

Multi-port static random access memory unit and device

The present invention relates to an integrated circuit (IC) design, in particular to a multi-port static random access with balanced read and write speeds and improved noise margin Memory (static random access memory, SRAM) unit structure.

For high-speed communication devices, image processing devices, and other system on chip (SOC) products, it is becoming more and more common to use SRAM devices as data storage units. SRAM devices traditionally include a logic circuit part and a memory cell part, which include a plurality of cells arranged in one or more arrays. SRAM cells can be classified into single-port cells, two-port cells, dual-port cells, and multi-port cells according to their structure. SRAM devices composed of two-port, dual-port, and multi-port units are becoming more and more popular because they are particularly suitable for parallel operations.

FIG. 1A shows a conventional two-port SRAM cell 100 composed of eight transistors. The traditional two-port SRAM cell 100 includes two P-type metal oxide semiconductor (MOS) transistors 102, 104 and six N-type metal oxide semiconductor (NMOS) transistors 106, 108, 110, 112, 114, 116 . P-type metal oxide semiconductor (PMOS) transistors 102 and 104 are pull up devices, and NMOS transistors 106 and 108 are pull down devices. NMOS transistors 110 and 112 are used as pass gates for read or write operations. gate) element. The sources of the PMOS transistors 102 and 104 are all coupled to the supply voltage Vcc, and the sources of the NMOS transistors 106 and 108 are all coupled to the complementary supply voltage, such as the ground terminal or the voltage Vss. The gates of the PMOS transistor 102 and the NMOS transistor 106 are both coupled to the node 118, and the drains of the two transistors 102 and 106 are both coupled to the node 120. The gates of the PMOS transistor 104 and the NMOS transistor 108 are commonly coupled to the node 120, and the drains of the two transistors 104 and 108 are both coupled to the node 118. The node 118 is coupled to the complementary bit line of the read/write port via the NMOS transistor 112, wherein the NMOS transistor 112 is controlled by the read/write word line. The node 120 is coupled to the read/write port bit line through the NMOS transistor 110, wherein the NMOS transistor 110 is also controlled by the read/write word line. In some special cases, the read/write port can only be used as a write port without a read function.

The read port portion of the conventional two-port SRAM cell 100 includes an NMOS transistor 114 as a pull-down element and an NMOS transistor 116 as a turn-on gate element. The gate of the NMOS transistor 114 is coupled to the node 120 (or node 118), and the source thereof is coupled to a complementary supply voltage, such as the ground terminal or the voltage Vss. When the high level signal of the read word line turns on the NMOS transistor 116, the high level signal at the node 120 (or node 118) can turn on the NMOS transistor 114 to ground the read port bit line.

FIG. 1B shows the layout 122 of the metal routing of the conventional two-port SRAM cell 100 in FIG. 1A. The layout diagram 122 shows the metal windings used as many interconnections in the conventional two-port SRAM cell 100 in FIG. 1A. These interconnections include several power lines, such as a supply voltage line 124, a complementary supply voltage line 128, another complementary supply voltage line's landing pad 126 (not shown), and several bit lines and characters. Wire. The bit lines shown in FIG. 1B are read/write port bit lines 130, read/write port complementary bit lines 132, and read port bit lines 134. The read/write word line 136 is parallel to the read word line 138 and is located on the same metal layer, which is higher than the supply voltage line 124, the complementary supply voltage line 128, the landing pad 126, and the read/write port The bit line 130, the complementary bit line 132 of the read/write port, and the metal layer of the bit line 134 of the read port are arranged. The three landing pads 140, 142, and 144 are also parallel to the aforementioned bit line and located on the same metal layer. The landing pads 140 and 142 are used to establish a connection with the read/write character line 136, and the landing pads 144 are used to establish a connection with the read character line 138.

The disadvantage of the traditional two-port SRAM cell 100 is that the layout structure is asymmetric. The read/write port bit line 130 is inserted between the landing pad 140 and the supply voltage line 124. However, the read/write port complementary bit line 132 is inserted between the supply voltage line 124 and the complementary supply voltage line 128. The asymmetrical layout may cause an imbalance in coupling capacitance between the read/write port bit line 130 and the read/write port complementary bit line 132. Therefore, unnecessary coupling capacitors and noise will cause the SRAM cell 100 to suffer inconsistency between read and write operations.

Figure 2A shows a conventional dual-port SRAM cell 200 composed of eight transistors. The conventional dual-port SRAM cell 200 includes two PMOS transistors 202 and 204 and six NMOS transistors 206, 208, 210, 212, 214, and 216. The dual-port SRAM cell 200 uses two sets of bit lines and complementary bit lines to respectively serve as the A port (first read/write port) and the B port (second read/write port). The sources of the PMOS transistors 202 and 204 are all coupled to the supply voltage Vcc, and the sources of the NMOS transistors 206 and 208 are all coupled to the complementary supply voltage, such as the ground terminal or the voltage VSS. The gates of the PMOS transistor 202 and the NMOS transistor 206 are both coupled to the node 218, and the drains of the two transistors 202 and 206 are both coupled to the node 220. The gates of the PMOS transistor 204 and the NMOS transistor 208 are coupled to the node 220 together, and the drains of the two transistors 204 and 208 are both coupled to the node 218. The node 218 is coupled to the complementary bit line of port A (first read/write port) through the NMOS transistor 212, and is coupled to the complementary bit of port B (second read/write port) through the NMOS transistor 216 Yuan line. The NMOS transistor 212 is controlled by the A-port word line, and the NMOS transistor 216 is controlled by the B-port word line. The node 220 is coupled to the A port bit line through the NMOS transistor 210 and is coupled to the B port bit line through the NMOS transistor 214. The NMOS transistor 210 is controlled by the A-port word line, and the NMOS transistor 214 is controlled by the B-port word line.

FIG. 2B shows the layout diagram 222 of the metal windings of the conventional dual-port SRAM cell 200 in FIG. 2A. The layout diagram 222 shows the interconnection of several supply lines (for example, supply voltage line 224 and two complementary supply voltage lines 226 and 228) and several bit lines and word lines. The bit lines shown in FIG. 2B are A port bit lines 230, A port complementary bit lines 232, B port bit lines 234, and B port complementary bit lines 236. The A port character line 238 is parallel to the B port character line 240. The two landing pads 242 and 244 are also parallel to the above-mentioned bit line and the supply voltage line. The landing pad 242 is used to establish a connection with the A-port character line 238, and the landing pad 244 is used to establish a connection with the B-port character line 240.

Although the conventional dual-port SRAM cell 200 provides a symmetrical layout structure, it still has a balance problem caused by the coupling capacitance on the bit line. For example, the configuration of the bit line 230 of port A between the complementary supply voltage line 226 and the landing pad 242 and the configuration of the bit line 232 of the complementary write port between the complementary supply voltage line 226 and the supply voltage line 224 may result in inconsistencies. Balanced coupling capacitors. Because the port B bit line 234 is arranged between the complementary supply voltage line 228 and the landing pad 244, and the port B complementary bit line 236 is arranged between the complementary supply voltage line 228 and the supply voltage line 224, the bit line of the B port For the line 234 and the complementary bit line 236 of the port B, the same problem of unbalanced coupling capacitance may occur. The imbalance between the coupling capacitances of the interconnection lines may cause unnecessary noise tolerance levels, thereby hindering the operating speed of the unit.

Therefore, in the design of integrated circuits, a new SRAM cell structure with balanced read and write speeds and improved noise tolerance is required.

The invention discloses a multi-port static random access memory unit. An embodiment of the present invention discloses a multi-port static random access memory cell, which includes: a latch having a first node and a second node for retaining a value and a complementary value respectively; and a first NMOS The transistor is coupled between the first node and a read/write port bit line, the gate of the first NMOS transistor is controlled by a read/write word line; a second The NMOS transistor is coupled between the second node and a complementary bit line of a read/write port, and the gate of the second NMOS transistor is controlled by the read/write word line; The third NMOS transistor has a gate coupled to the second node and a source coupled to a complementary supply voltage; a fourth NMOS transistor has a drain coupled to the third NMOS transistor The source of, the drain coupled to a read port bit line, and the gate coupled to a read word line; a fifth NMOS transistor has a gate coupled to the first node , And a source coupled to the complementary supply voltage; and a sixth NMOS transistor having a source coupled to the drain of the fifth NMOS transistor, coupled to a read port complementary bit line The drain and the gate coupled to the read word line, wherein, in the layout view of the multi-port static random access memory cell, the read port bit line and the read port complementary bit The line, the read/write port bit line, and the read/write port complementary bit line are connected by at least one supply voltage line, one or more complementary supply voltage lines, and one or more word lines Separated by the mat.

In order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments, in conjunction with the accompanying drawings, to describe in detail as follows:

Examples:

The present invention relates to a multi-port static random access memory cell with a symmetrical layout structure, which can achieve balanced read and write speeds and improved noise tolerance. The following only lists different embodiments of the present invention to explain the principle of the present invention. Those who are familiar with this art can make some changes and modifications without departing from the spirit and scope of the present invention.

FIG. 3A is a circuit diagram of a two-port SRAM cell 300 composed of ten transistors according to an embodiment of the present invention. The two-port SRAM cell 300 includes two PMOS transistors 302 and 304 and eight NMOS transistors 306, 308, 310, 312, 314, 316, 318, and 320. In the read/write port portion of the two-port SRAM cell 300, PMOS transistors 302 and 304 are used as pull-up elements, NMOS transistors 306 and 308 are used as pull-down elements, and NMOS transistors 310 and 312 are used as conduction The gate element is used. The sources of the PMOS transistors 302 and 304 are all coupled to the supply voltage Vcc, and the sources of the NMOS transistors 306 and 308 are all coupled to the complementary supply voltage, such as the ground terminal or the voltage Vss. The gates of the PMOS transistor 302 and the NMOS transistor 306 are both coupled to the node 322, and the drains of the two transistors 302 and 306 are both coupled to the node 324. The gates of the PMOS transistor 304 and the NMOS transistor 308 are coupled to the node 324 together, and the drains of the two transistors 304 and 308 are both coupled to the node 322. The node 322 is coupled to the complementary bit line of the read/write port via the NMOS transistor 312, wherein the gate of the NMOS transistor 312 is controlled by the read/write word line. The node 324 is coupled to the read/write port bit line through the NMOS transistor 310, wherein the gate of the NMOS transistor 310 is also controlled by the read/write word line. The combination of transistors 302, 304, 306, 308, 310, and 312 can be additionally regarded as a latch, and a value and its complementary value can be written into the latch.

The read port portion of the two-port SRAM cell 300 includes NMOS transistors 314, 316, 318, and 320. NMOS transistors 314 and 318 are used as pull-down elements, and NMOS transistors 316 and 320 are used as turn-on gate elements. Transistors 314 and 316 can be regarded as a read port coupled to the bit line of the read port, and transistors 318 and 320 can be regarded as another read port coupled to the complementary bit line of the read port. . The gate of the NMOS transistor 314 is coupled to the node 322, and the source thereof is coupled to the complementary supply voltage Vss. When the high level signal of the read word line turns on the NMOS transistor 316, the high level signal at the node 322 can turn on the NMOS transistor 314 and ground the read port bit line. The gate of the NMOS transistor 318 is coupled to the node 324, and its source is coupled to the complementary supply voltage Vss. When the high level signal of the read word line turns on the NMOS transistor 320, the high level signal at the node 324 can turn on the NMOS transistor 318 and ground the complementary bit line of the read port.

Before the write operation of the read/write port, precharge the read/write port bit line (to the high level state) and pre-discharge the read/write port complementary bit line (to the low level state) ). According to the value written into the SRAM cell, the logic state on the bit line and the complementary bit line can be reversed. Then, the read/write word line is pulled to a high level to turn on the NMOS transistors 310 and 312 to allow data to be written to the SRAM cell.

The read/write port can also be used for data read. During the read operation, the read/write port bit line and the read/write port complementary bit line are pre-charged. Next, the read/write word line is pulled to a high level to turn on the NMOS transistors 310 and 312 to allow data to be read by a sensing circuit. The bit cell data can also be read from the read port. During the sensing operation of the read port, the read word line is pulled to a high level to turn on the NMOS transistors 316 and 320. When the node 324 is a high-level signal and the node 322 is a low-level signal, the NMOS transistor 318 is turned on to pull the complementary bit line of the readout port to ground, and the NMOS transistor 314 remains in the off state to maintain the readout port. The element line is high level.

FIG. 3B shows the layout 326 of the metal winding of the two-port SRAM cell 300 in FIG. 3A according to an embodiment of the present invention. The layout diagram 326 shows many interconnected metal wires used in the two-port SRAM cell 300 in FIG. 3A. These interconnections include several power lines, such as a supply voltage line 328, two complementary supply voltage lines 330, 332 and word line landing pads 346, 348, 350, 352, and several bit lines and word lines. The bit lines shown in FIG. 3B include read/write port bit lines 334, read/write port complementary bit lines 336, read port bit lines 338, and read port complementary bit lines 340. The read word line 342 is parallel to the read/write word line 344. The four landing pads 346, 348, 350, and 352 are also parallel to the aforementioned bit line and supply line. The landing pads 346 and 348 are used to establish a connection with the read/write character line 344, and the landing pads 350 and 352 are used to establish a connection with the read character line 342. With this structure, for a high-speed SRAM device, the ratio of the length of the bit line to the word line can be less than about 1/4.

In order to avoid unbalanced coupling capacitance, the bit lines are designed to be separated by land bonding pads or supply lines, such as the supply voltage line 328 or the complementary supply voltage line 330 or the complementary supply voltage line 332. The metal configuration in the layout structure is also completely symmetrical, so that the cell current and the resistance-capacitance delay (RC delay) balance performance can be provided between the bit line and the complementary bit line. In other words, the wire group including the read port bit line 338, the read port complementary bit line 340, the read/write port bit line 334, and the read/write port complementary bit line 336 are comprised of complementary The supply voltage lines 330, 332, the supply voltage lines 328, and the landing pads 346, 348, 350, 352 are separated from each other by separate groups.

It must be noted that the layout direction of the N-type well area and the P-type well area (not shown) is parallel to the bit line along the shortest side of the SRAM cell, and each SRAM cell has a space between the two P-type well areas. An N-type well area. The word lines (for example, the read word line 342 and the read/write word line 344) are arranged in a direction orthogonal to the bit line.

FIG. 3C is a layout diagram 354 of the metal winding of the two-port SRAM cell 300 in FIG. 3A according to another embodiment of the present invention. The layout diagram 354 is similar to the layout diagram 326 shown in FIG. 3B, and the same interconnections used in the layout diagram 326 are also used in the layout diagram 354. The difference between the layout drawing 326 and the layout drawing 354 is the configuration of four metal windings. The configuration of the complementary supply voltage line 330 is changed to the configuration of the landing pad 346, and the configuration of the complementary supply voltage line 332 is changed to the configuration of the landing pad 348.

Similar to the layout diagram 326 in Figure 3B, the individual cell lines in the structure are designed to be separated by landing pads or supply lines, and the metal configuration in the layout structure is also completely symmetrical. Therefore, a balance between the cell current and the resistance-capacitance delay is provided between the bit line and the complementary bit line.

FIG. 4A is a circuit diagram of a multi-port SRAM cell 400 composed of fourteen transistors according to another embodiment of the present invention. By implementing multiple ports for the SRAM cell, more read ports can be generated to increase the read/write operation speed. The multi-port SRAM cell 400 includes two PMOS transistors 402, 404 and twelve NMOS transistors 406, 408, 410, 412, 414, 416, 418, 420, 422, 424, 426, 428. In the read/write port portion of the multi-port SRAM cell 400, PMOS transistors 402 and 404 are used as pull-up elements, while NMOS transistors 406 and 408 are used as pull-down elements, and NMOS transistors 410 and 412 are used as pull-down elements. The turn-on gate element is used. The sources of the PMOS transistors 402 and 404 are all coupled to the supply voltage Vcc, and the sources of the NMOS transistors 406 and 408 are all coupled to the complementary supply voltage Vss. The gates of the PMOS transistor 402 and the NMOS transistor 406 are both coupled to the node 430, and the drains of the two transistors 402 and 406 are both coupled to the node 432. The gates of the PMOS transistor 404 and the NMOS transistor 408 are coupled to the node 432 together, and the drains of the two transistors 404 and 408 are both coupled to the node 430. The node 430 is coupled to the complementary bit line of the read/write port via the NMOS transistor 412, wherein the gate of the NMOS transistor 412 is controlled by the read/write word line. The node 432 is coupled to the read/write port bit line via the NMOS transistor 410, wherein the gate of the NMOS transistor 410 is also controlled by the read/write word line. The combination of transistors 402, 404, 406, 408, 410, 412 can be additionally regarded as a latch, and a value and its complementary value can be written into the latch

Because the multi-port SRAM cell 400 has multiple readout ports, the number of transistors in the readout port portion is relatively high. The first read port portion of the multi-port SRAM cell 400 includes four NMOS transistors 414, 416, 418, 420, and the second read port portion of the multi-port SRAM cell 400 includes four NMOS transistors 422, 424 , 426, 428. For the first readout port, NMOS transistors 414 and 418 are used as pull-down elements, and NMOS transistors 416 and 420 are used as turn-on gate elements. For the second readout port, NMOS transistors 422 and 426 are used as pull-down elements, and NMOS transistors 424 and 428 are used as turn-on gate elements. The gates of the NMOS transistors 414 and 422 are all coupled to the node 430, and the sources of the NMOS transistors 414 and 422 are all coupled to the complementary supply voltage Vss. When the high level signal of the read word line turns on the NMOS transistors 416, 424, the high level signal at the node 430 will turn on the NMOS transistors 414, 422 to allow the first read port bit line and the second read The port bit line is pulled down to ground. The gates of the NMOS transistors 418 and 426 are all coupled to the node 432, and the sources of the NMOS transistors 418 and 426 are all coupled to the complementary supply voltage Vss. When the high level signal of the read word line turns on the NMOS transistors 420 and 428, the high level signal at the node 432 will turn on the NMOS transistors 418, 426 to allow the complementary bit line of the first read port and the second read The outbound complementary bit line is pulled down to ground.

Before the write operation, pre-charge the read/write port bit line (to a high level state) and pre-discharge the read/write port complementary bit line (to a low level state). According to the value written into the SRAM cell, the logic state on the bit line and the complementary bit line can be reversed. Then, the read/write word line is pulled to a high level to turn on the NMOS transistors 410 and 412 to allow data to be written to the SRAM cell.

During the sensing operation, the read word lines of the first read port and the second read port are pulled to a high level to turn on the NMOS transistors 416, 420, 424, and 428. When the node 432 is a high-level signal and the node 430 is a low-level signal, the NMOS transistors 418 and 426 are turned on, and the complementary bit line of the first readout port and the complementary bit line of the second readout port are pulled down to ground; The NMOS transistors 414 and 422 remain in the off state, so the bit line of the first read port and the bit line of the second read port are maintained at a high level.

Those skilled in the art can understand that the number of read ports does not need to be limited to the two read ports in Figure 4A, and the number of read ports can be increased without departing from the spirit of the present invention.

FIG. 4B is a layout diagram 434 of the metal winding of the multi-port SRAM cell 400 in FIG. 4A according to another embodiment of the present invention.

The layout diagram 434 shows the many interconnected metal wires used in the multi-port SRAM cell 400 in Figure 4A. These interconnections include several power lines, such as a supply voltage line 436, two complementary supply voltage lines 438, 440, and several bit lines and word lines. The bit lines shown in Figure 4B include read/write port bit lines 442, read/write port complementary bit lines 444, first read port bit lines 446, first read port complementary bits The cell line 448, the second read port bit line 450, and the second read port complementary bit line 452. The read word line 454 is parallel to the read/write word line 456. The six landing pads 458, 460, 462, 464, 466, and 468 are also parallel to the aforementioned bit line and supply line. The landing pads 458 and 460 are used to establish a connection with the read/write character line 456, and the landing pads 462, 464, 466, and 468 are used to establish a connection with the read character line 454.

Similar to the examples in FIGS. 3B and 3C, the metal configuration in the layout diagram 434 is also completely symmetrical, thus providing a balanced performance of read and write operations. With this structure, for a high-speed SRAM device, the ratio of the length of the bit line to the word line in the layout structure can be less than about 1/5.

It must be noted that the layout direction of the N-type well area and the P-type well area (not shown) is parallel to the bit line along the shortest side of the SRAM cell, and each SRAM cell has a space between the two P-type well areas. An N-type well area. The word lines (for example, read word line 454 and read/write word line 456) are arranged in a direction orthogonal to the bit line.

By implementing a symmetrical layout structure for SRAM cells, stable and high-speed two-port or multi-port SRAM devices can be produced. The symmetry of the present invention provides a high-speed and completely average-speed SRAM cell structure between the read cycle and the write cycle. The metal winding proposed in the present invention also provides complete noise shielding to avoid the imbalance of the coupling capacitance between the interconnections, thereby improving the noise tolerance.

Although the present invention is disclosed as above in a preferred embodiment, it is not intended to limit the scope of the present invention. Anyone who is familiar with the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

<p>100. . . Traditional two-port SRAM cell</p><p>102, 104, 202, 204, 302, 304, 402, 404. . . PMOS transistor</p><p>106, 108, 110, 112, 114, 116, 206, 208, 210, 212, 214, 216, 306, 308, 310, 312, 314, 316, 318, 320, 406, 408, 410, 412, 414, 416, 418, 420, 422, 424, 426, 428. . . NMOS transistor</p><p>122, 222, 326, 434. . . Layout</p><p>124, 224, 328, 436. . . Supply voltage line</p><p>126, 140, 142, 144, 242, 244, 458, 460, 462, 464, 466, 468. . . Landing pad</p><p>128, 226, 228, 330, 332, 438, 440. . . Complementary supply voltage line</p><p>130, 334, 442. . . Read/write port bit line</p><p>132, 336, 444. . . Complementary bit line for read/write port</p><p>134, 338. . . Read port bit line</p><p>136, 344, 456. . . Read/write character line</p><p>138, 342, 454. . . Read character line</p><p>200. . . Traditional dual-port SRAM cell</p><p>230. . . Port A bit line</p><p>232. . . Complementary bit line of port A</p><p>234. . . Port B bit line</p><p>236. . . Complementary bit line of port B</p><p>238. . . A port character line</p><p>240. . . B port character line</p><p>300. . . Two-port SRAM cell</p><p>340. . . Complementary bit line of read port</p><p>346, 348, 350, 352. . . Character line landing pad</p><p>400. . . Multi-port SRAM cell</p><p>446. . . First read port bit line</p><p>448. . . Complementary bit line of the first readout port</p><p>450. . . Second read port bit line</p><p>452. . . Complementary bit line of the second readout port</p><p>Vcc. . . Supply voltage</p><p>Vss. . . Complementary supply voltage</p>

Figure 1A shows the traditional two-port SRAM cell composed of eight transistors; Figure 1B shows the layout of the metal windings of the traditional two-port SRAM cell in Figure 1A; Figure 2A shows the layout of the traditional two-port SRAM cell with eight transistors. A traditional dual-port SRAM cell composed of crystals; Figure 2B shows the layout of the metal windings of the traditional dual-port SRAM cell in Figure 1A; Figure 3A shows the ten transistors according to an embodiment of the present invention Figure 3B and Figure 3C show the layout of the metal windings of the two-port SRAM cell in Figure 3A according to different embodiments of the present invention; Figure 4A shows another According to an embodiment, a multi-port SRAM cell composed of fourteen transistors; and FIG. 4B shows the layout of the metal winding of the multi-port SRAM cell in FIG. 4A according to another embodiment of the present invention.