Method and systems for repairing an integrated circuit device

Method and system for repairing faults on integrated circuit

The present invention mainly relates to integrated circuits, in particular to a method and system for repairing integrated circuits using auxiliary integrated circuits.

An integrated circuit (IC) is designed to include active and passive components interconnected in a predetermined pattern, such as transistors, diodes, resistors, and capacitors, to perform desired functions. Integrated circuits and components are becoming more and more complex. In logic circuits, the number of logic cells and interconnections of integrated circuits on a wafer of a given size has substantially increased, which reflects the improvement of semiconductor processing technology. Integrated circuits may include, for example, powerful application-specific integrated circuit (ASIC) devices designed to provide high-level functions for specific devices or types of applications.

Manufacturing ASICs are logic chips designed to perform specific functions to meet specific requirements of specific applications. These designs are implemented in a single silicon wafer by mapping functions to a series of pre-designed and pre-verified logic circuits provided by ASIC suppliers. These circuits add from simple functions such as inverters, NAND, NOR, flip-flops and latches to more complex structures such as memory arrays, adders, counters, and phase-locked loops.

The integrated circuit may also include a gate array with transistors arranged in rows and columns on each wafer. The standard procedure for manufacturing this structure includes manufacturing up to 500,000 transistors, which includes 250,000 gates on each wafer. Each transistor is provided with conductive contact points that can also be arranged in rows and columns. After performing subsequent processing steps including, for example, adding a conductive layer, the completed wafer is tested. In some cases, if any device on the wafer is defective, the wafer will fail the exhaustive test and will be discarded. Instead, perform active repair by using conductive materials or redundant gates to reconnect inactive logic circuits or reprocess the wafer by adding all the additional semiconductors and conductive layers needed to replace or repair the inactive parts . All these methods will consume a lot of time and financial resources.

Therefore, there are currently unmentioned needs in the industry to solve this and other shortcomings and deficiencies.

One embodiment of the present invention provides a system and method for repairing integrated circuit devices. Briefly, one of the many embodiments of the above system can be implemented as a system for repairing integrated circuit devices. This system includes a detection logic circuit configured to locate defective parts of the integrated circuit device; the configuration is successful An auxiliary integrated circuit component capable of replacing the defective part; and a discrimination logic circuit configured to discriminate the position of the interface.

Another embodiment of the present invention can also be regarded as providing a method for repairing an integrated circuit device. In this regard, one of the many embodiments of this method can be broadly summarized by the following steps: using a plurality of factors to identify a defective part of an integrated circuit device to determine the location of the defective part, the plurality of factors including: storage A function range data in a function range database; a code range stored in a code range database; and a routing data stored in a routing database; using at least one of the plurality of factors Identifying at least one isolation point configured to isolate the defective part from the integrated circuit device; using at least one of the plurality of factors to identify the plurality of connection points configured to be electrically connected to the field-effect programmable gate array; and Attach the field-effect programmable gate array to the integrated circuit device.

Another embodiment of the present invention can also be regarded as providing a system for repairing an integrated circuit device. The system includes: a mechanism for identifying defective parts of an integrated circuit device; The cut-off point is a mechanism for isolating the defective part; and a mechanism for judging a plurality of connection points on the integrated circuit device to connect auxiliary integrated circuit components.

This embodiment can be further regarded as providing a system for repairing an integrated circuit device. The system includes: a detection logic circuit configured to locate a defective part of the integrated circuit device; and configured to functionally replace the defective part Auxiliary integrated circuit components; and a discrimination logic circuit configured to discriminate the position of the interface.

Another embodiment of the present invention can be further regarded as providing a method for repairing an integrated circuit device, the method includes identifying defective parts of the integrated circuit device; cutting off the existing circuit components; and adding auxiliary integrated circuit components To the integrated circuit device.

Other systems, methods, features, and advantages of the present invention will be obvious to those familiar with the art after examining the following drawings and detailed descriptions. All such additional systems, methods, features, and advantages should be included in this specification and within the scope of this disclosure, and are protected by the attached patent application scope.

Various aspects of the present invention have been summarized, and in the following, reference will be made to the description of the present invention illustrated in the drawings in detail. Although the invention will be described in conjunction with these figures, it is by no means intended to limit it to the embodiment or embodiments of the invention herein. On the contrary, the purpose of the present invention is to cover all substitutions, changes and equivalents included in the spirit and scope of the disclosure defined by the scope of the patent.

Refer to Figure 1, which is a schematic top view of an exemplary integrated circuit (IC) semiconductor wafer used in the method and system. The IC wafer 100 includes a substrate 101 on which a plurality of digital logic circuit components 104 are arranged. The probe pad 106 is disposed on the IC wafer 100 so that the total number of digital logic circuit components 104 will not be reduced at all or minimized due to the existence of the probe pad 106. The conductive pad 102, which may be in the form of a conductive trace, is connected between the probe pad 106 and the contact 105 of the digital logic circuit component 104.

Refer to Figure 2, which is a block diagram of an exemplary embodiment of the system. The system 120 for repairing IC devices includes a detection logic circuit 122 configured to locate defective part(s) of the IC device. The detection logic circuit 122 can use a variety of factors, including, for example, function range data, code range data, routing data, power consumption data, and so on. The function scope data generally refers to the functions of the operation designed in the IC device. For example, a part of an IC device that includes a logic circuit for performing a disproportionately large number of operations relative to other parts of the IC device is considered to have a high range of functions. For example, a circuit analysis device or multiple assertion commands can be used to provide functional range data. In this way, the area with a high percentage of functions is regarded as having a high range of functions.

Generally, the code range data is judged by testing the program or checking the effectiveness of the code line. For example, consider the following four-line case (CASE) statement: always @(instruction)case(instruction) 2'b00: decode=2'b000 2'b01: decode=2'b001 2'b10: decode=2' b010 2'b11: decode=2'b011 endcase

The input on the instruction is only three cases: 00, 01, and 10, and the fourth case 11 is not applicable. It is judged that the valid code range in this CASE is three-quarters, or seventy-five percent (75%).

The routing description provides the additional steps required for increased accessibility without creating additional performance issues related to timing and signal integrity. For example, the wire is extended so that the antifuse can be properly connected between different conductor layers. Perform routing to ensure that the anti-fuse layer makes proper contact with the wires. However, the extension typically does not exceed ten percent (10%) of the total length. The routing data is usually defined in a database or similar data file.

Determine the power consumption data at the wafer or system level by measuring the voltage and current directly into the device. Electronic design automation (EDA) tools can also be used by wafer suppliers to determine power consumption data. In this machine, the power consumption data can be judged by monitoring the toggling device and measuring the exchange current in the device. Other EDA tools can also be used to perform power consumption analysis on circuits with corresponding routes.

The system 120 further includes an auxiliary IC component 124 configured to functionally replace the defective part. In addition, the system 120 includes an identification logic circuit 126 for identifying the location of the interface, which is configured to identify the location where the auxiliary IC component on the IC device is integrated into the IC device. In addition, the location of the interface can identify where the defective part of the IC device should be isolated. The system 120 may further include a database containing performance information corresponding to the integrated circuit device.

Refer to Figure 3, which is a partial cross-sectional perspective view of an example integrated circuit semiconductor wafer using anti-fuse technology together with the method and system disclosed herein. The IC wafer 140 includes a large number of semiconductor gates 144. One or more anti-fuse layers 148 (such as those required to use anti-fuse technology) are included on the semiconductor gate 144. The field-effect programmable gate array (FPGA) 142 is placed on the IC wafer 140 and integrated into the logic circuit of the IC wafer 140 by using the through hole 146 and the anti-fuse material 148. The FPGA 142 can then be programmed to replace the function of the defective part of the IC wafer 140. The anti-fuse material is configured to provide a short circuit to create an electrical connection at a specified point. Although FIG. 3 only describes a single connection, FPGA 142 is connected to various gates 144 and IC wafer 140 to replace defective parts of the IC wafer.

In addition to using the anti-fuse technology to create a short circuit to create an electrical connection, it may also be necessary to isolate the defective part of the logic circuit from the circuit of the IC wafer 140. One or more fuses shown in Fig. 4A and Fig. 4B can be used to perform isolation of the defective part. Figures 4A and 4B depict top views of example fusible link regions in the closed state and the open state, respectively. The example fuse 160 includes terminals 162 and 163 connected via a link 164. As shown in FIG. 4A, the link 164 remains as it is and creates a closed circuit between the terminals 162 and 163. When it is necessary to isolate between the terminals 162 and 163 to isolate one or more defective parts of the IC wafer, a part of the link 164 may be damaged and the gap 166 may be generated. The gap 166 generates an electrical open circuit, so the terminals 162 and 163 are electrically isolated. Various methods can be used to break the link 164, including, but not limited to, current generated by voltage potential, laser or anti-fuse related technologies, and so on.

Refer to FIG. 5, which is a block diagram describing an example interface between the integrated circuit wafer and the auxiliary integrated circuit. The IC wafer 180 includes a logic circuit 184 synchronized with a clock signal 182 generated by a clock 186. The auxiliary IC 190, which is shown as a field-effect programmable gate array (FPGA), includes a logic circuit 194 and has an interconnect 198 connecting the logic circuit 184 of the IC wafer 180. Since the logic circuit 194 of the auxiliary IC component 190 is interconnected with the logic circuit 184 of the IC wafer 180, they should be properly synchronized for proper operation to avoid system timing issues. Synchronization can be achieved by receiving the clock signal 196 in the digital phase locked loop (DPLL) 188 provided in the auxiliary IC 190. The digital phase lock loop 188 then generates the auxiliary clock signal 192 received by the logic circuit 194. In this way, the logic circuit 194 is properly synchronized with the logic circuit 184 to prevent timing related issues.

Refer to FIG. 6, which is a block diagram describing an example of a method for preparing an integrated circuit wafer. The method first identifies the defective part of the IC wafer in block 200. Use multiple factors such as function range data, code range data, routing data, and power consumption data to identify bad parts. Those who are familiar with the art will recognize that a variety of data can be used to determine the location of the defective part. In block 202, if necessary, cut off the existing circuit components corresponding to the defective part. A logic map potentially combined with one or more factors can be used to determine a feasible cut-off point. In block 204, auxiliary IC components are added to the IC wafer to replace the function of the defective part. In an exemplary embodiment, the auxiliary IC component is a field-effect programmable gate array (FPGA), which is added and programmed to replace the lost function in the defective part.

The main principle of IC wafer repair includes cutting off the existing defective logic circuit (also called dicing), and connecting the replacement logic component of the auxiliary IC component, such as FPGA. Because the cost of placing FPGA components on the entire wafer is too high, it is useful to identify specific parameters that can determine or predict possible malfunctions on the IC wafer. Various factors that can be used to determine the possible location of the FPGA to repair the IC wafer include but are not limited to the code range, function range, routing data, and, in some cases, power consumption, etc.

The combination of these factors can be optimally used in the form of a bad analysis image. Refer to Figure 7, which describes an example defect analysis image. The failure analysis image 220 uses a multi-axis configuration, where each axis can represent one of the factors. For example, one axis is for the code range 226, one axis is for the function range 222, and one axis is for the routing data 224. It also shows the image areas 228-232 represented by A, B, C, D, and E, which are based on the analysis of various factors combined with the probability of failure on the IC wafer to better define possible results. Together with the defect analysis map in Figure 7, refer to Figure 8, which is a block diagram showing the table corresponding to the defect analysis map in Figure 7. The table 250 contains area rows 252, which list each image area identified on the bad analysis image 220. The code range line 254 identifies the general code range value of each identified image area. Although the code range value shown is limited to the resolution of two points, the range value can be defined with a larger resolution within the scope and spirit of this invention. The function range row 256 identifies the general function range value of each identified image area. The routing data row 258 identifies the general routing data corresponding to each identified image area. Similar to the code range value, the function range and routing data value can also be defined at a greater resolution than shown. The bad probability row 260 identifies the bad probability of each identified image area according to the combination of the code range, the function range, and the routing data factor.

The judgment of multiple factor values can be achieved through multiple technologies. For example, a special configuration logic description set configured to utilize a wafer logic circuit can be used to generate code range data. Specially configured branch conditional instruction sets can be executed in multiple arrays to find the code range related to specific functional areas of IC wafers. You can use, for example, specially designed judgments or use verification logic languages and monitors to capture the range of functions. The routing data can be judged by analyzing the logical image, and when in use, electrical, electromagnetic, capacitive or thermal monitoring technologies can be used to judge the power consumption.

In the analysis of individual areas, area A has low code range, low function range, and low routing data value. The combination of these factors represents a higher probability of possible failure, because this combination may imply that this part of the wafer is a low or non-actor. Zone B, which presents a low code range, a low functional range, and a high routing data value, can reflect the area with the probability of bad clock logic. Area C, which has a low code range and a high function range, is not an effective area because meaningful functions cannot exist without support codes. Another possible meaning of this area is that this situation may imply that the information derived from one or more factors is incorrect. Area D, which presents a high code range and a low functional range, has a low probability of possible failure because of the correlation between the code range and the functional range. The E area, which presents a high code range and a high function range, has a very low probability of representing a bad part regardless of the routing data value, because the high function range in the high code range area is logically related to normal operation. Positions of integrated circuit devices with a high probability of including defective parts include integrated circuits corresponding to code ranges that are low relative to other main integrated circuit devices and functional ranges that are low relative to other main integrated circuit devices. The part of the device.

Refer to FIG. 9, which shows a block diagram of another exemplary embodiment of a method for repairing an integrated circuit wafer. The method 300 first uses multiple factors in block 302 to identify the defective portion of the IC wafer. The data corresponding to multiple factors can be judged by accessing the integrated circuit configuration data. As shown in block 310, the factors include, but are not limited to, function range data, code range data, and routing data. These factors can be analyzed individually or, for example, using a bad analysis image in combination. After identifying the defective part of the IC wafer, one or more isolation points are identified in block 304. The isolation point is used to isolate the defective area of the IC wafer from the remaining functional parts. The identification of the isolation point can also rely on information related to the factors used to identify the bad part. In addition, a logical image can be generated for the defective part identified in the block 302 to correctly know the "cut" of the metal layer to isolate the defective part of the IC wafer. Identify multiple connection points in block 306 so that the FPGA can be attached to the IC wafer in block 308. The identification of multiple connection points can also depend on the factors used to identify the bad part and the logical image produced.

Technologies including but not limited to anti-fuse technology can be used to connect the FPGA to the IC wafer at the connection point. The related fuse technology, for example, can be used to cut the metal layer at the position identified as the isolation point in the block 304. Other types of bad logic circuits can also be repaired functionally using FPGAs in this way. For example, the method and system used here can integrate FPGA to bypass bad logic circuits related to the program, such as stuck-at-1 and stuck-at-0. In this way, scan chains in the chip can also be used to point out defective areas and, if possible, integrate points. In addition, the fuse and anti-fuse technology embedded in the IC wafer at a predetermined position can be used to perform bonding or cutting through software.

Refer to FIG. 10, which shows a block diagram of another exemplary embodiment of a system for repairing integrated circuit wafers. The system 330 includes a mechanism for identifying defective parts of the IC wafer in block 332. The system 330 also includes a mechanism for determining the cutting point on the IC wafer in block 334. Depending on the interconnection of the defective part, it may be necessary to identify more than one point on the IC wafer to isolate the defective part. The system 330 also includes a mechanism for determining multiple connection points of auxiliary IC components in block 336. The connection point is used to functionally integrate the logic circuit of the auxiliary IC component to the logic circuit of the IC wafer to replace the lost function in the defective part. The auxiliary IC component may be, for example, an FPGA.

The embodiments of the present invention can be implemented in hardware, software, firmware, or a combination thereof. Some embodiments can be implemented in software or firmware that is stored in memory and executed by an appropriate command execution system. If implemented in hardware, alternative embodiments can be implemented by the following technologies or any or a combination of them, which are well known in the art: discrete logic circuits with logic gates for implementing logic functions based on data signals, with appropriate combinations The special application of logic gate is integrated circuit (ASIC), programmable gate array (PGA), field effect programmable gate array (PGA) and so on.

Any program description and block in the flowchart should be recognized as a module, section, or part of the program code, which contains one or more executable instructions to implement specific logic functions or steps in the program, and replace The embodiments are included in the scope of the embodiments of the present invention, in which functions can be performed in an order different from the order shown or discussed, including substantially simultaneous or reverse order depending on the functions involved. This is for The art of invention can be understood by those with general knowledge.

The method and system can also include a sequential list of executable instructions for performing logical functions, which can be implemented in any computer readable medium used by or in conjunction with the instruction execution system, device, or device. The instruction execution system, The equipment or device is, for example, a computer application system, a processor-containing system, or other systems that can obtain instructions from an instruction execution system, equipment, or device and execute the instructions. In the context of this document, a "computer-readable medium" can be any mechanism that can contain, store, communicate, transmit, or transport programs used by or in conjunction with instruction execution systems, equipment, or devices. Computer readable media can be, for example, but not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, equipment, devices, or conductive media. More specific examples (non-exhaustive list) of computer-readable media may include the following: electrical connections with one or more wires (electronics), portable computer discs (magnetic), random access memory (RAM) ) (Electronics), read-only memory (ROM) (electronics), erasable programmable read-only memory (EPROM or flash memory) (electronics), optical fiber (optical), and portable optical disc read-only memory (CDROM) (optical). Note that the computer-readable media can even be paper or other suitable media on which the program can be printed, because the program can be captured electronically by scanning the paper or other media optically, and then compiling, translating, or using it if necessary Other than that, it is processed in an appropriate manner and then stored in the computer memory. In addition, the scope of the present invention includes embodying the functions of the illustrated embodiments of the present invention in logic circuits implemented in hardware or software-configured media.

It should be emphasized that this embodiment of the present invention, especially any shown embodiment, is only a possible example of implementation, and is only presented to promote a clear understanding of the principles of the present invention. Many variations and modifications can be made to the embodiment of the invention without substantially departing from the spirit and principle of the invention. All such changes and variations shall be included in the scope of this invention and the present invention, and shall be protected by the scope of the following patent applications.

<p>100. . . Integrated Circuit Wafer</p><p>101. . . Base</p><p>102. . . Conductive pad</p><p>104. . . Digital logic circuit components</p><p>105. . . get in touch with</p><p>106. . . Probe pad</p><p>120. . . system</p><p>122. . . Detection logic circuit</p><p>124. . . Auxiliary IC component</p><p>126. . . Discrimination logic circuit for discerning interface position</p><p>140. . . IC wafer</p><p>142. . . Field Effect Programmable Gate Array (FPGA)</p><p>144. . . Semiconductor gate</p><p>146. . . Through hole</p><p>148. . . Antifuse layer</p><p>160. . . Fuse</p><p>162, 163. . . Terminal</p><p>164. . . link</p><p>166. . . gap</p><p>180. . . IC wafer</p><p>182. . . Clock signal</p><p>184. . . Logic circuit</p><p>186. . . clock</p><p>188. . . Digital Phase Locked Loop (DPLL)</p><p>190. . . Auxiliary IC</p><p>192. . . Auxiliary clock signal</p><p>194. . . Logic circuit</p><p>196. . . Clock signal</p><p>198. . . interconnection</p><p>200,202,204. . . Block</p><p>220. . . Bad analysis image</p><p>222,224,226. . . axis</p><p>228-232. . . Image area</p><p>250. . . surface</p><p>252. . . District line</p><p>254. . . Code range line</p><p>256. . . Functional scope line</p><p>258. . . Routing information line</p><p>260. . . Bad Probability</p><p>300. . . method</p><p>302-310. . . Block</p><p>330. . . system</p><p>332-336. . . Block</p>

Many aspects of this invention can be better understood with reference to the drawings. The components in the figure are not drawn absolutely to scale, and the focus is to clearly describe the principle of the present invention. In addition, in the figures, similar component symbols denote corresponding components in several figures.

Figure 1 is a schematic top view of an exemplary integrated circuit semiconductor wafer used in the method and system.

Figure 2 is a block diagram of an exemplary embodiment of the system of the invention.

Figure 3 is a partial cross-sectional perspective view of an example integrated circuit semiconductor wafer using anti-fuse technology together with the method and system invented herein.

FIG. 4A and FIG. 4B are top views of example fusible link regions described in the closed state and the open state, respectively.

Figure 5 is a block diagram describing an example interface between the integrated circuit wafer and the auxiliary integrated circuit.

FIG. 6 is a block diagram describing an example of a method for preparing an integrated circuit wafer.

Figure 7 is a diagram depicting the example defect analysis image.

Fig. 8 is a block diagram showing the table corresponding to the failure analysis diagram of Fig. 7.

FIG. 9 is a block diagram showing another exemplary embodiment of a method for repairing an integrated circuit wafer.

FIG. 10 is a block diagram showing another exemplary embodiment of a system for repairing integrated circuit wafers.