Wafer bonded epitaxial templates for silicon heterostructures

Wafer bonded epitaxial board for silicon heterostructure

The present invention relates to the field of thin-film semiconductor processing, and particularly to the processing of non-silicon thin films.

The optoelectronics, optoelectronics, telecommunications, and light-emitting diode (LED) industries need a substrate technology that allows them to use low-cost, easily available substrates (such as Si) as optical material films on which devices can be fabricated Mechanical support. Some obvious advantages are improved mechanical strength and higher thermal conductivity relative to the surface body optoelectronic materials.

In the prior art, the III-V semiconductor layered structure grown on the surface body Ge substrate is used to generate a high-efficiency three-junction solar cell with an efficiency exceeding 30%. However, these are extremely expensive for the general public and are only limited to space applications, because Ge substrates make up most of this cost.

The optoelectronics, optoelectronics, telecommunications, and light-emitting diode industries will automatically adopt a low-cost, easily available substrate (such as Si) as a mechanical support substrate for the optoelectronic non-silicon film used to manufacture devices on it. Benefit from technology. Some obvious advantages are improved mechanical strength and higher thermal conductivity relative to the surface body optoelectronic materials.

The present invention is an improvement to a method of epitaxially growing a heterostructure on a virtual substrate composed of an optoelectronic device substrate and a processing substrate. The method includes the step of starting to bond the device substrate to the processing substrate. The device substrate includes materials suitable for manufacturing optoelectronic devices here, and the processing substrate includes inexpensive materials suitable for providing mechanical support. The mechanical strength of the bond between the Bond Berween device substrate and the processing substrate is improved. The device substrate is thinned by, for example, peeling off the device film from the device substrate, leaving a single crystal film. The upper part of the device film that has fallen off the device substrate is removed to provide a smoother and less defective inclined surface for subsequent optoelectronic device manufacturing. The heterostructure grows epitaxially on a smooth surface.

In the illustrated embodiment, the device substrate is InP/Si, and the step of epitaxially growing a heterostructure on a smooth surface includes epitaxially growing a photoluminescent InP/InGaAs/InP double heterostructure on the smooth surface.

The step of removing the upper portion of the device film that has fallen off from the device substrate includes chemically polishing the upper portion using damage selective etching, or mechanically polishing the upper portion.

Where the device substrate and the processing substrate present the InP/Si interface, the use of damage selective etching to chemically polish the upper part includes the use of HCl: H₃PO₄: H₂O₂Carry out the etching step with a ratio of 1:2:2 or 1:2:4.

In other embodiments, the step of mechanically grinding the upper part includes using a colloidal silica slurry in a sodium hypochlorite solution.

The present invention can also be defined as an improvement of a heterostructure device layer that is epitaxially grown on a virtual substrate. The improvement includes a device substrate and a processing substrate forming a virtual substrate. The device substrate is combined with the processing substrate and the device substrate includes a material suitable for manufacturing optoelectronic devices. The processing substrate contains materials suitable for providing mechanical support. The mechanical strength of the bond between the Bond Berween device substrate and the processing substrate is improved, and the device substrate is thinned by, for example, peeling off the device film from the device substrate, leaving a single crystal film on the virtual substrate. The upper part of the device film peeled off from the device substrate is removed to provide the optoelectronic device with a smoother and less defective inclined surface. The heterostructure grows epitaxially on the smooth surface where optoelectronic devices can be manufactured.

Although functional descriptions have been or will be used to describe devices and methods for the sake of grammatical fluency, it should be clearly understood that the scope of patent application of the present invention cannot be understood as being affected by "methods" or Any restriction on the structure of "steps" should be understood to be consistent with the definition provided in the scope of the patent application under the judicial regulations and the equivalent, and in the scope of the patent application under 35 USC 112, the formula is specially used Under the stated circumstances, it should be understood as completely consistent with the legal equivalent under 35 USC 112. The present invention can be better realized by referring to the following drawings, in which the same elements are represented by the same numbers.

As illustrated graphically in the block diagram of FIG. 1, the manufacturing 104 of the virtual wafer bonded substrate may require two possible steps. These steps are as shown in block diagram 100 before the functional substrate is manufactured by combining the thin device film and the body substrate, or as shown in block diagram 102 after manufacturing the functional logic device in the processing substrate and/or in the optoelectronic device After the functional optoelectronic substrate is manufactured in the substrate, the device film can be transferred to the processing substrate.

This description summarizes many examples of optoelectronic virtual substrate manufacturing. We first outline the generally used technology and device structure that can use virtual substrate products. Second, more material processing steps will be described in the order in which they appear during the manufacturing process.

Process and product overview

For illustrative purposes, the term "device substrate" 10 is the optoelectronic substrate from which the film 12 is to be removed. In the description, the term "processing substrate" 14 is defined as a substrate used to provide mechanical support for the device substrate 12, that is, the remainder of the device substrate after the film 12 is removed. The term "virtual substrate" 16 is defined as the completed structure of the thin device film 12 on the processing substrate 14.

As shown in the diagram in Figure 2, the available materials for the device substrate 10 discussed below can be considered to be all materials related to the thin film materials of the wafer-bonded virtual substrate device used in the manufacture of optoelectronics and high-gain devices. These materials Including (but not limited to): III/V group compound semiconductors (i.e. GaAs, InP, GaN, etc.), group II/VI semiconductors (i.e. CdTe, etc.), group IV semiconductors (i.e. Ge for the growth of the GsAs group) and optical The important ferroelectric oxide (ie, LiNbO₄,BaTiO₄Wait).

The processing substrate 14 is generally Si that can be obtained in large quantities and has the required electrical, mechanical, and thermal properties. Therefore, the Si heterostructure can be made of any of the materials mentioned above according to the teaching and spirit of the present invention. However, a low-cost insulating substrate (ie, glass, sapphire, etc.) can also be used as the processing substrate 14.

The general process for manufacturing the virtual substrates 16 includes the following steps:

1) The device substrate 10 and the processing substrate 14 may need to be pre-bonded to allow the removal of the thin film 12 (ie, ion implantation into the device substrate 10 as shown by the number 11 in the diagram in FIG. 3a).

2) Clean the device substrate 10 and/or put it in a passivated state to facilitate the bonding process.

3) As shown in the diagram in Figure 4a, start the combination process.

4) Strengthen the combination to improve the mechanical strength of the device substrate 10 and the processing substrate 14.

5) As shown in FIG. 4b, the device substrate 10 is thinned to leave a single crystal thin film 12 on the completed virtual substrate 16 for ion implantation of the substrate.

6) As shown in Figures 5a and 5b, in the case of layer shedding caused by ion implantation, the device substrate 10 producing the device film 12 can be reprocessed by surface grinding to allow the substrate to be used again to transfer another device film.

Considering the concept used for manufacturing the optoelectronic virtual substrate 16, these steps will be listed in the order in which they appear in the above-mentioned general processing.

Processing steps:

1) Ion implantation

As shown in the diagram in Figure 3a, prior to the bonding process, ion implantation of the device substrate 10 is performed to implant the necessary amount of gas species in the substrate to form an internal passivation surface and to peel off a layer from the substrate during annealing. Necessary internal pressure. Figure 3a illustrates the use of ion beam 11 to perform ion implantation of device substrate 10 before bonding; it produces a modified structure including device film 12 as shown in Figure 3b, and an ion damage layer for film transfer. 13, and the surface body of the device substrate 10, which is now referred to as the most unaffected processing substrate 14.

The treatment generally uses H⁺Or H⁺With He⁺The combination of implementation. However, other gas types can be used to produce an in-substrate etching process that facilitates layer shedding. For a given device substrate material, there is a minimum implantation temperature and a required implantation temperature to avoid amorphism, that is, the minimum required dose relationship for this process.

a) H⁺Implantation-implant a sufficient dose of H⁺In order to allow the film to fall off during annealing, this dose is a function of the following factors: Implant energy. Implantation temperature. Device substrate material. Film peeling annealing temperature

b)H⁺/He⁺Co-implantation-implant a sufficient dose of H⁺/He⁺To allow the film to fall off during annealing. The concept of this method is that H plays a chemical role to make the inner surface in a passivated state, and the chemically inert He effectively moves to the inner surface to provide pressure, and compared with H, each implanted ion can cause greater damage. This improves the inner surface density. The necessary dose is a function of the following factors: Implant energy. Implantation temperature. H/He ratio. Device substrate material. Film peeling annealing temperature

c) Etchant implantation-except H⁺In addition to or instead of implanting H⁺Implantation can be used to implant chemical species known to etch a given material to produce volatile internal trapped chemical species, and cause detachment during annealing. The selected chemical type will be a specific material selected based on known etchant characteristics or experimental experience.

2) Surface passivation

After the implantation and before the bonding process, a passivation process needs to be performed on the surfaces of the device substrate 10 and the processing substrate 14 to allow the hydrophobic wafer bonding. This specific chemical treatment requires a specific device substrate. The purpose of this step is to create a close covalent bond between the device film 12 in the completed virtual substrate and the processing substrate 14 to allow the possibility of ohmic and low-resistance interface electrical properties. The necessary step to make it possible to obtain the completed device structure is to eliminate the absorbed water by low-temperature baking in an inert atmosphere or in a vacuum. Baking should reach a temperature such that the vapor pressure of water at this temperature is much higher than the partial pressure of water in the surrounding environment.

a. Group IV passivation-the use of diluted HF etching process to make the IV element semiconductor (specifically Ge) hydrophobic. This leaves the hydride-based termination surface.

b. III/V group passivation-by using a specific composition chemical treatment to make the III/V group composition semiconductor hydrophobic, so as to leave a hydrophobic passivation surface for bonding.

c. II/VI group passivation-by using a specific composition chemical treatment to make the II/VI group composition semiconductor hydrophobic, so as to leave a hydrophobic passivation surface for bonding.

d. Ferroelectric oxides-the application of ferroelectric oxides is essentially different from the application of optoelectronic materials in terms of element and composition semiconductors. For this reason, the substrate material to be processed will be selected according to its electrical and refractive properties, but it is usually not necessary to try hydrophobic wafer bonding of the insulating ferroelectric film. Therefore, surface passivation will generally focus on the formation of thin oxides on the device and processing substrates 10, 14.

3) Surface modification

As shown in FIGS. 6a and 6b, using any thickness of the deposited surface modifying layer 40 to change the physical interaction properties between the substrates 10 and 14 is another useful technique for extending this process to a wider range of optoelectronic materials. This can be achieved in one of three ways, where X represents any type of composition compatible with the disclosed method.

a. Depositing a layer 40 of material X on the device substrate 10 makes X-process material bonding possible.

b. Depositing a layer 40 of material X on the processing substrate 14 makes X-device material bonding possible.

c. Depositing a layer 40 of material X on the two substrates makes it possible to bond XX materials.

This technology controls the bonding process by using materials that are compatible with the disclosed process or can be modified, making it possible to combine a wide range of optoelectronic materials. At this time, the material is only referred to as material X. The general processing is illustrated in Figure 6a and Figure 6b. FIG. 6a illustrates the modification of an implanted device substrate in which a crystal or amorphous film 40 having the same chemical composition as the processing substrate 14 has been implanted. 6b illustrates the use of this technology to demonstrate the wafer bonding substrate stack of the device substrate 10, the damaged area 13 of ion implantation, the device film 12, the deposited bonding adjustment film 40, the bonding interface 42, and the processing substrate 14.

More specific applications of this technology are:

d. Epitaxial Si bonding layer-This technique involves epitaxially growing a strained Si film on the device substrate material. In this embodiment, the material X is a strained thin film Si. This growth can ensure that there is a tight and super-strength bond between the device material and the Si epitaxial layer. The device substrate 10 with strained Si epitaxy is implanted by an epitaxial layer (not shown) in preparation for wafer bonding and layer shedding. For material systems that use Si to process the substrate 14, this allows the use of established passivation techniques to directly perform Si-Si wafer bonding processing.

e. Amorphous Si bonding layer-This technique involves depositing a thin layer of amorphous Si on the device substrate 10 under low temperature conditions, enabling the use of typical Si surface preparation chemistry. In this embodiment, the substance X is amorphous Si. This processing can be performed before or after ion implantation of the device substrate 10. For the material system using Si to process the substrate 14, this allows the Si-Si wafer bonding process using the mature passivation technology.

4) Particle removal

After the surface passivation, it may be necessary to remove residual particle contamination on the bonding surface of the device substrate 10 and the processing substrate 14. As shown in Figures 4a and 4b, this can be effectively accomplished by performing cleaning with carbon dioxide particle jets. FIG. 4a is a diagram of the stack of the device substrate 10 and the processing substrate 14 after ion implantation and initial bonding, which illustrates the undamaged surface body device substrate 10, the ion-implanted damaged layer 13, the device film 12, the crystal Circular bonding device/processing interface 42 and processing substrate 14. 4b is a diagram illustrating the wafer-bonded dummy substrate 16 after annealing and layer peeling, and it illustrates the undamaged body device substrate 10 having the ion-implanted damaged surface area 13. The wafer bonding virtual substrate including the device film 12 ion implantation damaged surface area 13, the undamaged transferred device film 12, the wafer bonding interface 42 and the processing substrate 14 are also described. Hold the device substrate 10 and/or the processing substrate 14 at a high temperature, and the CO₂The throttled gas/particle jet hits the surfaces of the substrates 10 and 14, thereby removing the particles under the combined physical and thermophoretic lifting effect.

In application CO₂During this period, the substrate is maintained at a temperature greater than 50°C. This technology has been described for Si, Ge, and InP.

5) High temperature bonding begins

When combining different materials, there is generally a thermal expansion mismatch coefficient between the two materials, which results in a temperature-dependent strain state of the device film 12 in the virtual substrate 16, which is determined by the equation:<maths><img file="TW200529459A_D0001.tif" /></maths>

Where α(T) is the difference between the thermal expansion coefficients of the two substrates as a function of temperature T, and where<i>T</i>_<i>0</i>It is the temperature under the condition of zero strain, which is generally considered to be the starting temperature of bonding. Therefore, by controlling the temperature when the two substrates are in contact, the strain state at the desired temperature can be adjusted. This is very beneficial for improving the performance of the substrate in the high temperature process, or the operating temperature strain of the device can be adjusted to adjust the key device characteristics such as energy band gap and carrier mobility. The following describes as<i>α(T)</i>The general type of achievable strain temperature-strain dependence of the function of the sign of.

α(T)=α_handle(T)-α_device(T)

The positive value of strain here indicates the film under tension, and the secondary value of strain indicates the film under pressure.

a.α<i>(T)</i>&gt;0

1. Bonding at room temperature-In this case, the film 12 will be under tension at higher processing temperatures. This will lead to changes in the lattice matching in the heteroepitaxial on the virtual substrate 16 and the tendency of the concave substrate to bend.

2. High temperature bonding-In this case, the film will have a zero strain condition at the bonding temperature, so that the tensile strain and concave wafer bending will be reduced at higher processing temperatures. Likewise, at room temperature and possibly at the operating temperature of the device, the thin film 12 will cause the convex wafer to bend under compressive strain. This can change the operation of the device and make it possible to design a novel device based on the strain control of material parameters.

b.α<i>(T)</i>&lt;0

1. Room temperature bonding-In this case, the film 12 will be under pressure at high temperatures. This will lead to changes in lattice matching in heteroepitaxial on the virtual substrate and bending of the convex substrate.

2. High temperature bonding--In this case, the film 12 will have a zero strain condition at the bonding temperature, so that the compressive strain and convex wafer bending will be reduced at high processing temperatures. Likewise, at room temperature and possibly at the operating temperature of the device, the thin film 12 will cause the concave wafer to bend under compressive strain. This can change the operation of the device and make it possible to design a novel device based on the strain control of material parameters. Most of the materials suitable for the wafer bonding virtual substrate 16 belong to this category.

a. Ge/Si combination--Figure 7 illustrates the predicted strain in Ge/Si combination as the substrate at different T₀The value of the combined temperature as a function of the graph. At high temperatures, the pressure of the film can be₀Initially combined and reduced.

b. InP/Si combination--Figure 8 illustrates the predicted strain in the InP/Si combination as the substrate at different T₀The value of the combined temperature as a function of the graph. Same as above, the film pressure at high temperature can be reduced by the higher temperature T₀Initially combined and reduced.

c. GaAs/Si--Figure 9 illustrates the predicted strain in the GaAs/Si combination as the substrate at different T₀The value is a graph of the combined temperature as a function. Same as above, the film pressure at high temperature can be reduced by the higher temperature T₀Initially combined and reduced.

6) Combination of different temperatures starts

For some desired adjusted strain states, a single high temperature combined temperature will not be able to complete the manufacture of the device. Similarly, for materials with the same thermal expansion coefficient, strain adjustment will be more difficult. To further enable strain control at the desired temperature, the bonding between the substrates can be started at different temperatures. In this way, the thermo-mechanical strain state can be controlled more freely or manually built in the completed structure. In this case, the temperature-dependent strain state is given by:<maths><img file="TW200529459A_D0002.tif" /></maths>

Where the value γ₀Is the strain built into the bond structure at the beginning of the bond and it is given by:<maths><img file="TW200529459A_D0003.tif" /></maths>

In this expression,<i>T</i>_<i>d</i>and<i>T</i>_<i>h</i>These are the temperatures of the device substrate 10 and the device 14 at the moment when the combination starts. temperature<i>T</i>_<i>0</i>Start temperature for effective combination. The different temperatures of the substrate at the beginning of bonding make this factor difficult to determine.<i>T</i>_<i>o</i>Must have in T_dWith T_hOne of the values between, and it will depend on the experimental equipment used in the virtual substrate manufacturing, and can be determined through experiments. The built-in strain is close to<maths><img file="TW200529459A_D0004.tif" /></maths>

For the device substrate 10 and the processing substrate 14 having very similar linear expansion coefficients. Under the following circumstances, the combination at different wafer temperatures can be performed.

a.α<i>(T)</i>&gt;0：

1. <i>T</i>_<i>d</i>&gt;<i>T</i>_<i>h</i>-These conditions make it possible to add normal strain components that cause the substrate film to be exposed to increased pressure at high temperatures.

2. <i>T</i>_<i>d</i>&lt;<i>T</i>_<i>h</i>- Under these conditions, it is possible to add negative strain components that reduce high temperature tensile strain, but lower temperature compressive strain is produced.

b.α<i>(T)</i>&lt;0：

1. <i>T</i>_<i>d</i>&gt;<i>T</i>_<i>h</i>-These conditions make it possible to add a normal strain component that has reduced the compressive strain level by causing the substrate film to be at a high temperature.

2. <i>T</i>_<i>d</i>&lt;<i>T</i>_<i>h</i>-Under these conditions, it is possible to add negative strain components to improve the high-temperature tensile strain, but the low-temperature tensile strain has been reduced.

c.α<i>(T)</i>=0：

1. <i>T</i>_<i>d</i>&gt;<i>T</i>_<i>h</i>--The tensile strain that is not affected by temperature can be applied to the device film in this way.

2. <i>T</i>_<i>d</i>&lt;<i>T</i>_<i>h</i>--Compressive strain that is not affected by temperature can be added to the device film.

7) Annealing under high pressure to enhance bonding and peel off the device layer

After the device substrate 10 and the processing substrate 14 are combined, a thermal cycle is required to improve the bonding strength and activate the ion implantation layer transfer process. Performing this cycle under pressure, the combined surface body substrate stack can accommodate thermal-mechanical strain. In addition, bonding is strengthened by improved substrate-to-substrate contact. A combined treatment using multiple pressure-temperature steps or even a continuously changing pressure-temperature curve can be used to optimize the pressure effectiveness in this treatment.

Specifically, under the low temperature condition before the peeling, higher pressure can be used to ensure better substrate contact, but the pressure will inhibit the peeling at the high temperature. By reducing the pressure to a lower level before annealing to a high temperature, the shedding will not be restricted.

a. Variable pressure cycle-a possible embodiment is to independently use varying pressure and temperature to optimize the combined treatment. At low temperatures, high pressure is applied to strengthen the bond. Then reduce the pressure at high temperature to avoid the suppression of layer shedding in the device substrate. A representative process is illustrated in the graph of FIG. 10, which illustrates the wafer bonding temperature-pressure curve as a function of time in the bonding annealing process.

b. Single pressure cycle-for the long-lasting annealing, it is also possible to improve the bonding process by applying uniaxial load to the bonding pair. In this treatment, the load should be small enough without suppressing foaming.

8) Modification of the device layer

After the transfer of the device film in the layer transfer process caused by ion implantation, the near surface area of the device film 12 is rough and full of defects. As shown in Figures 11a and 11b, this layer should be removed in a controlled manner to leave a useful surface for the subsequent processing of manufacturing optoelectronic devices. Depending on the device layer 10, this can be accomplished by:

a. Wet chemical polishing-this method uses the etching of the device film to controllably remove the damaged layer 13 on the wafer bonded virtual substrate 16 caused by ion implantation, while smoothing the surface of the transferred layer . The etching of special materials is listed as follows:

1. Ge/Si

i. HF: H₂O₂: H₂O--This etching can be performed at different temperatures with different dilution ratios x:y:z.

ii. HF: HNO₃: C₂H₄O₂: H₂O--This etching can be performed at different temperatures with different dilution ratios w:x:y:z.

iii. H₂O₂: H₂O--This etching can be performed at different temperatures with different dilution ratios y:z.

2. InP/Si

i. HCl: H₃PO₄: H₂O₂--Successfully used this etching solution in the ratio of 1:2:2 and 1:2:4. H₂O₂Acting as an oxidant and HCl and H₃PO₄The mixture etches the oxide. The combination of oxidation and subsequent etching produces a smooth surface and removes implant damage. Figure 12a illustrates the roughness of two surfaces as a function of time for different etching dilutions. Figures 12b and 12c illustrate the photoluminescence intensity of InP/InGaAs/InP double heterostructures epitaxially grown on InP/Si virtual substrates exposed to 1:2:2 and 1:2:4 etching dilutions, respectively spectrum. The relative improvement in the luminescence intensity of the chemically treated structure indicates that the treatment produced an improved surface for epitaxial growth. The spectrum corresponding to the epitaxially prepared InP substrate in FIG. 12b is taken from the double heterostructure grown on the epitaxially prepared InP substrate provided by the surface body substrate manufacturer. The 45-second watch body InP spectrum is taken from a double heterostructure grown on an epitaxially prepared InP substrate that has been exposed to chemical treatment for 45 seconds. The 45-second InP/Si spectrum was taken from a double heterostructure grown on a wafer bonded virtual InP/Si sample that was chemically treated for 45 seconds after the layer transfer. The transferred InP/Si spectrum is taken from the double heterostructure grown on the wafer bonding structure of InP/Si without surface treatment after the layer is peeled off. In FIG. 12c, the spectrum corresponding to the epitaxially prepared InP is taken from the double heterostructure grown on the epitaxially prepared InP substrate provided by the surface body substrate manufacturer. The 60-second watch body InP spectrum is taken from a double heterostructure grown on an epitaxially prepared InP substrate that has been exposed to chemical treatment for 60 seconds. The 60-second InP/Si spectrum was taken from a double heterostructure grown on a wafer bonded virtual InP/Si sample that was chemically treated for 60 seconds after the layer was removed.

b. Chemical and physical polishing-This uses chemical and mechanical polishing slurry to etch implant damage and leave a smooth surface.

1. Ge/Si--The colloidal silica slurry in KOH chemistry can be used to grind the substrate.

2. InP/Si--shows that colloidal silica slurry in sodium hypochlorite solution can be used to smooth the surface of these virtual substrate materials. Figure 12d shows the photoluminescence spectrum of an InP/InGaAs/InP double heterostructure epitaxially grown on an InP/Si substrate after chemical and mechanical polishing. In FIG. 12d, the spectrum corresponding to the epitaxially prepared InP is taken from the double heterostructure grown on the epitaxially prepared InP substrate provided by the surface body substrate manufacturer. The 5-minute surface body InP spectrum is taken from the double heterostructure grown on the epitaxially prepared InP substrate that has been exposed to the polishing process for 5 minutes. The 30-second InP/Si spectrum is taken from a double heterostructure grown on a wafer bonded virtual InP/Si sample that has been polished for 30 seconds after the layer transfer. The improvement of the photoluminescence intensity of the polished virtual substrate relative to the unpolished substrate indicates an improved surface for epitaxial growth. In this treatment, the surface roughness is reduced to about 3 nm rms, and the scanning image of the atomic force microscope is shown in Figure 12e.

Homogeneous epitaxy smoothing--even in the case where chemical etching removes implant damage but does not leave the best smooth plane for subsequent hetero epitaxy, homogeneous epitaxy of the device thin film material on the etched sample has been demonstrated, To reduce the surface roughness. This can be used as the first step of growing heteroepitaxial structures on wafer bonded virtual substrates.

9) Growth of epitaxial heterostructures

The completed virtual substrate 16 is used as a template for the growth of optoelectronic devices performed by heteroepitaxial. With careful modification of the device layer, a wide range of optoelectronic devices becomes possible. A representative image of this structure is shown in Figures 13a and 13b. FIG. 13a is a diagram showing the completed wafer bonding virtual substrate 16 including the device film 12, the wafer bonding interface 42 and the processing substrate 14. As shown in FIG. FIG. 13b is a diagram showing a wafer-bonded virtual substrate 16 with a device 50 for fabricating epitaxial growth on the device film 12.

10) Strain compensation layer

In device manufacturing, standard processes such as MOCVD, diffusion, implantation, and lithography techniques are used to construct wafer-bonded substrates in or on the transfer layer. One of the potential challenges is due to the existence of strain caused by thermal expansion in the transfer layer. The possibility of wafer bending. As shown in FIG. 14, one practical method to reduce this effect is to deposit a strain compensation layer on the back surface of the processing substrate 14. 14 is a diagram schematically showing an optoelectronic structure 50 grown on a wafer-bonded virtual substrate including a device film 12, a bonding interface 42, a processing substrate 14, and a strain compensation layer 18 deposited on the back surface of the substrate.

This concept will be implemented by depositing a thin film 18 on the back surface of the processing substrate 14 before or after the device layer 10 is transferred to the processing substrate 14. The strain compensation layer 18 must have the same Δα sign as the device film 12 relative to the processing substrate. The zero bending state is not a zero strain state, but in the absence of other driving forces to deform the substrate, the strain energy of the device film 12 matches the strain energy of the strain compensation layer completely. The materials and deposition techniques can be selected to minimize the manufacturing costs associated with this processing step. The substrate diameter, film strain, and film thickness are used to increase the strain energy associated with the film 12. The zero-bending processing temperature can be adjusted by selecting the strain compensation layer 18, the deposition temperature and the thickness. The following are examples of how to perform strain compensation for some material systems:

a. Ge/Si--The simplest case is to deposit a thin film of Ge on the back surface of the Si-treated substrate.

b. InP/Si--It is not necessary to deposit InP on the back surface of the substrate to be processed, but a Ge thin film can be used because the deposition of the Ge thin film is relatively simple.

c. GaAs/Si--Similar to the situation of InP/Si, Ge can produce a good strain compensation layer.

d. Other materials--For all the systems mentioned above, under the condition that the sign of α is appropriate, low-cost materials that are easy to deposit are suitable strain compensation layers.

Those skilled in the art can make many changes and modifications without departing from the spirit and scope of the present invention. Therefore, it should be understood that the illustrated embodiments are only for illustrative purposes and should not be regarded as a limitation of the present invention defined by the scope of the patent application. For example, despite the fact that the elements of the patent application are listed in the following specific combinations, it should be understood that the present invention includes other combinations of fewer, more or different elements, which are disclosed above or even not This is the first application in this combination.

The vocabulary used to describe the present invention and its various embodiments in this specification should not only be understood in terms of the general definition of the vocabulary, but should also be included in the structure of this specification, the special definition of materials or the scope of the meaning beyond the general definition. Therefore, if an element can be understood as including more than one word meaning in this specification, its use in the scope of patent application should be understood as belonging to all possible meanings supported by the specification and the vocabulary itself.

Therefore, the definitions of the vocabulary and the elements within the scope of the following patent applications are defined in this specification as not only the combination of the elements stated verbatim, but also all equivalent structures, materials or used to perform substantially the same in substantially the same way. Function to obtain substantially the same result. Therefore, in this sense, it should be understood that equivalent substitutes of two or more elements can replace any element in the scope of the following patent applications, or a single element can replace two or more elements in the scope of patent applications. . Although the above-mentioned elements are regarded as a specific combination and even for the first time, it should be understood that one or more elements in the claimed combination may be excluded from the combination in some cases, and the claimed combination may refer to A variant of a combination or sub-combination.

Those who are skilled in this technology should clearly understand that insubstantial changes (now known or made in the future) of the claimed subject matter are equally within the scope of the patent application. Therefore, obvious alternatives known to or later known by the ordinary skilled in the art should be defined as within the defined elements.

Therefore, the scope of patent application should be understood to include everything that is specifically illustrated and described above, is conceptually equivalent, obviously replaceable, and essentially incorporates the essential viewpoints of the present invention.

<p>10Device base board</p><p>11Ion beam</p><p>12Film</p><p>13 Damaged area/layer</p><p>14Processing substrate</p><p>16Virtual substrate</p><p>40Deposited surface modification layer</p><p>42Wafer bonding interface</p><p>50Optical electronic structure</p>

Figure 1 is a block diagram illustrating two alternative virtual substrate manufacturing strategies.

Figure 2 is a block diagram illustrating a thin film race for a virtual substrate according to the present invention.

3A and 3B are diagrams respectively illustrating ion implantation in the device substrate and the resulting structure.

4A and 4B are diagrams respectively illustrating the stacking of the device and the processing substrate after ion implantation and initial bonding, and the wafer bonding virtual substrate after annealing and layer peeling.

5A and 5B are diagrams respectively illustrating a back-layer transfer device substrate including a near-surface ion implantation damaged layer and an undamaged surface body, wherein the removal of damage by etching from the surface body device substrate allows the process to be repeated.

FIGS. 6A and 6B do not respectively illustrate the surface modification of the implanted device substrate by using any thin film of the same chemical composition as the processing substrate and the diagram showing the wafer-bonded substrate stack of the device substrate using this technology.

FIG. 7 is a graph of temperature as a function of the strain state of the Ge/Si wafer combined with the virtual substrate.

FIG. 8 is a graph showing the temperature as a function of the strain state of the InP/Si wafer combined with the virtual substrate.

FIG. 9 is a graph showing the temperature as a function of the strain state of the GaAs/Si wafer combined with the virtual substrate.

Figure 10 is a graph of the wafer bonding temperature-pressure curve as a function of the time used in the bonding annealing process.

11A and 11B do not respectively illustrate the wafer-bonded virtual substrate after annealing and layer exfoliation, and the wafer-bonded virtual substrate after damage removal, etching, grinding, and epitaxial growth on the device film.

Figure 12A shows the rms surface roughness of the transferred InP device film as HCl: H₃PO₄: H₂O₂A graph showing a function of the time used in the etching chemistry diluted in the ratio of 1:2:2, 1:2:4 and 1:2:5.

Figure 12B shows that the ratio of 1:2:2 of HCl:H which is usually provided for epi-ready InP for epi-ready growth is 1:2:2.₃PO₄: H₂O₂A graph of the photoluminescence intensity (PL) of the InP/InGaAs/InP double heterostructure on the InP/Si heterostructure etched in a wet chemical etchant, and the surface body InP grinding for 45 seconds, and InP/Si grinding for 45 seconds and as The transferred InP is the wafer bonding structure after the layer transfer and before any surface modification. The improved mechanical strength of the polishing of the InP/Si virtual substrate illustrates the improved surface quality of the processed structure.

Figure 12C shows that the ratio of 1:2:4 HCl:H for preparing InP for epitaxial growth is usually provided for epitaxial growth.₃PO₄: H₂O₂A graph of the photoluminescence intensity (PL) of the InP/InGaAs/InP double heterostructure on the InP/Si heterostructure etched in a wet chemical etchant, and the surface body InP is polished for 60 seconds, and InP/Si is polished for 60 seconds. The improved mechanical strength of the polishing of the InP/Si virtual substrate illustrates the improved surface quality of the processed structure.

Figure 12D shows the photoluminescence intensity (PL) of the InP/InGaAs/InP double heterostructure grown on the InP/Si heterostructure treated by the sodium hypochlorite chemical mechanical polishing method for preparing epitaxial InP, which is usually provided for epitaxial growth. , And the surface body InP grinding for 5 minutes, and InP/Si grinding for 30 seconds. The improved mechanical strength of the polishing of the InP/Si virtual substrate illustrates the improved surface quality of the processed structure.

FIG. 12E is an atomic force lithography image of the transferred InP substrate film surface after 30 seconds of chemical mechanical polishing method treatment.

FIGS. 13A and 13B are diagrams respectively illustrating the completed wafer bonding virtual substrate and the wafer bonding virtual substrate having an epitaxial growth device fabricated on the device film.

Figure 14 shows an optoelectronic structure grown on a wafer bonded virtual substrate, which includes a device film, a bonding interface, a processing substrate, and a strain compensation layer deposited on the back of the substrate.

The present invention and its various embodiments can be better understood by referring to the above detailed description of the preferred embodiments, which are presented as illustrative examples defined in the scope of the patent application of the present invention. It should be understood that the present invention as defined in the scope of the patent application can be broader than the illustrative embodiments described above.