Device and methodology for reducing effective dielectric constant in semiconductor device

Apparatus and method for reducing effective dielectric constant of semiconductor device

The present invention generally relates to a semiconductor device and a manufacturing method thereof, and more particularly to a manufacturing method of sub-lithographic features in a semiconductor device and a dielectric material for reducing the effective dielectric constant of the dielectric material.

In order to manufacture microelectronic devices such as integrated circuits (IC), a variety of different metal layers and insulating layers need to be selectively deposited on silicon wafers. The insulating layer may be silicon dioxide, silicon oxynitride, fluorinated silicon glass (FSG) and the like. These insulating layers, such as inner dielectric layers (ILD), are deposited between metal layers, and serve as electrical insulation between metal layers or have other conventional functions. These layers are deposited by conventional techniques such as enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD) or other processes.

The insulating layer between the metal layers is etched to form vias and metallized to connect the metal layers. These internal connections are located in the dielectric (insulating) layer. To achieve this goal, the stacked layers of metal and insulation undergo a lithography process to provide a pattern impedance with a predetermined IC design. For example, the top layer of this structure may cover the photoresist layer of the photoactive composite material to be patterned by masking. After that, the photolithography process uses visible light or ultraviolet light to pass through the mask to the photoresist layer to expose it to the mask pattern. It is possible to use an anti-reflective coating (ARC) on the top of the wafer substrate to minimize light reflection to the photoresistance layer and provide a consistent processing procedure. The etching performed may be anisotropic or isotropic and wet or dry etching, depending on the physical and chemical properties of the material. Regardless of the manufacturing process, in order to maximize the integration of the device components in the super-large integrated circuit, the density of the components must be increased.

Although silicon dioxide has been used as an insulating material due to its thermal stability and mechanical strength, a low-k (low-k) material has been discovered in recent years to achieve better device performance. By using a low dielectric constant material, the capacitance of the structure can be reduced and the device speed can be increased. However, compared to typical dielectric materials (such as silicon dioxide), the use of organic low-dielectric constant materials (such as SiLK, manufactured by Dow Chemical Co., Midland, M1) tends to have lower mechanical strength. In some applications, it is found that the following materials combined with other materials in the device have a specific effective dielectric constant, for example: (i) undoped silicon glass (USG) with K of 4.1 and Keff of approximately 4.3; (ii) Double layer of USG and fluorinated silicon glass (FSG) (K=3.6), with Keff of about 3.8; (iii) Organosilicon glass (OSG), with K of 2.9 and Keff of about 3.0, and (iv ) Porous OSG, with a double layer of porous OSG and OSG, Keff is about 2.4.

By building devices with low-k dielectric or mixed low-k dielectric stacks, the large inner line-to-line components of line capacitive coupling will be reduced, thus maximizing the positive advantages of low-k materials, and at the same time Improve the overall solidity and credibility of the final structure. Compared with the "all low-k" dielectric material stack, the mixed oxide/low-k dielectric stack structure is more solid, and the thermal cycle due to the high CTE (coefficient of thermal expansion) of organic and semi-organic low-k materials Stress, the known mixed oxide/low-k dielectric stack structure is relatively more sensitive to the degradation of the via resistance and the delamination of the via. However, at low dielectric constants, the overall strength of the dielectric material is significantly reduced.

Even with low dielectric constant materials, such as a mixed oxide/low dielectric stack structure, voided channels can be formed in the dielectric material between interconnects and vias to reduce the effective K of the multilayer structure. (Keff) or K of the dielectric material to further improve the electronic characteristics of the device. These channels are vacuum filled and have a dielectric constant of approximately 1. With these channels, higher dielectric constant materials can be used to increase the overall strength of the structure without reducing the electronic properties.

In known systems, sub-resolution lithography processes can be used to establish such channels. The lithography process typically includes some new processes and machine settings, which will increase the overall cost of manufacturing semiconductor devices. In the sub-resolution lithography process, it is also necessary to etch a wide trench in an empty space, which cannot be reduced by ILDPECVD afterwards. Furthermore, although these channels establish low line-to-line capacitance, for wide lines, there is a high layer-to-layer capacitance. Of course, this will affect the overall electronic characteristics of the device. Air gaps may also occur from high layers and near via holes, which will cause the risk of plating tanks and metal filling these areas. Recently, in the known manufacturing process, there is also a need to provide isotropic etching, but it may etch the bottom of the interconnection, making it unsupported or floating, thereby reducing the overall structure and electronic performance of the device.

The present invention intends to solve these and other problems.

One aspect of the present invention is a method of manufacturing a structure, which includes providing a structure with an insulating layer and forming a primary lithography template mask on the insulating layer, and the insulating layer has at least one interconnection. The insulating layer is etched by masking the sub-lithographic template and using a selective etching to form sub-lithographic features spanning one of the sidewalls of the at least one interconnection.

In another aspect of the present invention, the method includes providing a structure having an insulating layer, and forming a barrier structure on the insulating layer, the insulating layer having a plurality of interconnections. The method further includes forming a sub-lithographic template mask on the barrier structure, the sub-lithographic template mask has sub-lithographic features, and the barrier structure and the insulating layer are selectively etched by the sub-lithographic template mask to form the insulating layer The formation of sub-lithographic features.

In another aspect of the present invention, a semiconductor device includes an insulating layer having at least one slit formed therein and the slit spans a minimum gap larger than an interconnection.

The present invention relates to a semiconductor device and a manufacturing method that provide channels (or holes) in dielectric (insulating) materials to improve the overall device performance. The method of the present invention does not require new process steps or machine settings, nor does it require new introductions. The materials in the final construction, and further avoid the shortcomings of the sub-resolution lithography process.

Furthermore, the method of the present invention is easy to use with any material, whether it is a mixed structure or a material with a high dielectric constant. On the one hand, the present invention avoids the floating of the interconnection line and reduces the effective dielectric constant Keff to maintain the layer-to-layer vertical capacitance of the interconnection line. It is also possible to maintain the overall device strength using the method of the present invention.

FIG. 1 shows a structure generally used for manufacturing a semiconductor device. This structure, marked with a symbol 100, is a single-level structure, that is, a wiring layer, and is used to illustrate the purpose of the present invention. However, it is well known by those skilled in the art that the structure disclosed or described herein may be a multi-level structure with multiple different layers. The manufacturing method described here is also suitable for describing such a multi-stage structure.

The structure 100 of FIG. 1 includes a substrate 110, which can be any suitable conventional material (such as silicon). This substrate may be built as an integrated circuit of the line level. The insulating layer 120 is deposited on the substrate 110 using any conventional method, such as plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD) or other processes. The insulating layer 120 may be (i) undoped silicon glass (USG), (ii) USG and fluorinated silicon glass (FSG), (iii) organic silicon glass (OSG), (iV) porous OSG and OSG, ( v) Compositions containing these materials or other conventional dielectric materials. The insulating layer 120, in an embodiment, is preferably a layer structure of OSG or OSG and porous-OSG. The diffusion barrier layer 135, which may be SiC, SiN, or other known materials described herein, may be deposited on the insulating layer 120 to protect the interconnection 130. The diffusion insulating layer 135 may additionally serve as an etching mask for subsequent processes. The diffusion barrier layer 135 may have a thickness ranging from 250 angstroms to 500 angstroms, or other thicknesses, depending on its application.

Figure 2 shows the first step of the method of the present invention. In this step, a blockout patterned resistance 140 (upper lithographic resistance) is deposited or formed on the diffusion barrier layer 135. The barrier patterned resistance 140 has a thickness of 2000 angstroms to 1 micrometer in one embodiment, and is deposited by conventional means. The hindering patterning impedance may be any conventional photoresist material. The hindering patterning resistance 140 includes holes or features larger than the minimum resolution feature, that is, in one embodiment, the hindering patterning resistance 140 is larger than the gap between the interconnections 130.

Figure 3 shows the second step of the present invention. In FIG. 3, a block copolymer nanotemplate 150 is formed on the barrier patterned resistance 140 and part of the diffusion barrier layer 135. The bulk copolymer nano-template 150 is a thin layer and has characteristics of less than the minimum resolution. That is, in one embodiment, the characteristic of the bulk copolymer nanotemplate 150 is smaller than the gap between the interconnections 130. The material of the bulk copolymer nano-template 150 may be self-assembled into substantially uniform shapes and interstitial holes or features. For example, the bulk copolymer nano template 150 may be a self-assembled single-layer templated porous or permeable film. The bulk copolymer nano template 150 may be cured by electron beam, ultraviolet light, or heat. It can be further confirmed that in an embodiment, the patterned resistance 140 may be formed on the bulk copolymer nanotemplate 150.

In one embodiment, the diameter of the holes of the bulk copolymer nanotemplate 150 is about 20 nm, and the distance between the holes is about 20 nm. In other embodiments, the range of features and spacing may be from less than 5nm to 100nm. The thickness of the bulk copolymer nano-template 150 is about 20 nm in one embodiment, and it is composed of an organic material matrix with meshes or holes. It can be understood that the thickness of the bulk copolymer nano-template 150 (and the barrier resistance) will depend on the thickness of the insulating layer, the required feature resolution and other factors, all of which can be referred to by those skilled in the art. And ok.

Figure 4 shows an etching step of the present invention. Now the bulk copolymer nano-template 150 and the diblock patterned resistor 140 are formed on the substrate. In one embodiment, RIE etching is used to form a channel 160 or a nanometer between the interconnections 130. Meter string. In this step, when the insulator 120 is etched between the holes of the bulk copolymer nano-template 150, the insulating layer 120 may be intentionally eroded to form one or more nanometer columns between adjacent interconnections. In other embodiments, the insulating layer 120 may be eroded to the substrate or lower levels. In this step, because an etching step cannot be selected indefinitely, the bulk copolymer nano-template 150 may also begin to be corroded. However, the characteristics of the bulk copolymer nano-template 150 have been transferred to the diffusion barrier layer 135. It will then be used as a mask with a transfer pattern. It is also possible to form an undercut under the interconnection.

As shown in FIG. 4, the small holes 135a are approximately equal to the channels 160 and exist on the surface of the insulating material 120. They basically correspond to the characteristic size of the bulk copolymer nano-template 150. For example, the diameter of the small holes 135a Approximately in the order of 20 angstroms to 200 angstroms. Furthermore, during the etching, the insulating material 120a may be etched from the sidewalls of the interconnection 130, but then deposited again in a further deposition step. In one embodiment, the thickness of the sidewall etching insulating material 120a ranges from 5 angstroms to 200 angstroms, and has thicker sidewalls near the bulk copolymer nanotemplate 150 or the diffusion barrier layer 135. What those skilled in the art know is that in order to control the pattern, the masks 130, 150 and the etching steps may be adjusted, thus eliminating the possibility of close to via land gaps and the like. Similarly, by adjusting the etching process, the channel 160 may partially or completely extend through the insulating layer 120, or the insulating layer close to the interconnection may be completely or substantially completely eroded. In the latter case, in the subsequent steps of forming a higher interconnection layer, insulating material may be deposited near the sidewalls.

RIE is an anisotropic etching, which mainly etches vertically downward to form the channel 160 by etching the insulator. It is possible to perform a wet clean after RIE to remove any polymer residues produced by the etching step. This cleaning step may include an etchant to continuously anisotropically etch the insulating layer to form an undercut under the interconnection (Figure 5). If diluted hydrofluoric acid (DHF) is used to etch the insulating layer containing USG or FSG, the speed is relatively slow. For example, in H₂When the ratio of O:HF is 200:15, the etching rate may be 10 to 20 angstroms per minute.

On the other hand, the use of DHF to etch OSG has a very low chemical etching rate, which is almost impossible to measure. In the OSG embodiment, RIE is used with plasma O₂, By oxidizing or "damaging" the exposed OSG surface to provide a more complete etching capability. Afterwards, this damaged layer may be quickly etched with DHF. However, when using plasma O₂, It may damage the OSG insulating layer or diffusion layer, but this damage can be corrected by providing other etching on the damaged part.

Figure 5 shows that in addition to providing a channel formed by an undercut, the nanotube column is enlarged by isotropic etching to a single larger column 160a. The single larger column 160a is larger than the original bulk copolymer nanotemplate 150 Hollow. In this step, by adding such O₂To change RIE. In this step, the undercut 160b is formed by isotropic etching, but it should not etch the entire area at the bottom of the interconnection. Third, the etching can be adjusted to provide a more extreme undercut, which will depend on the expected performance of the overall device. However, this undercut preferably does not include the entire area of the bottom of the interconnect 130. In one embodiment, this undercut will reduce the vertical capacitance of the wide line.

6 shows other manufacturing steps of the present invention. For example, after the undercut is formed, the bulk copolymer nano-template 150 and the barrier step patterned resistor 140 are etched or peeled off, leaving small holes 135a. These masks may have been partially or completely eroded during the etching process, thus leaving the diffusion barrier layer 135 as a mask. The wet etching process can also be used together with the solvent DHF or other acids that can etch any of the aforementioned dielectric materials. In one embodiment, the concentration of DHF is about 1000:1 to 10:1 H₂O: HF. In another aspect of the present invention, by widening the channel 160, materials with different dielectric constants and other properties, such as high ductility, high fracture toughness, etc., are then backfilled in the channel.

Still referring to FIG. 6, the second insulating layer 170 is deposited on the formed structure by a general deposition method, such as PECVD. The second insulating layer may include a cap. After depositing some on the interconnect 130 (such as copper wires) and the diffusion barrier layer 135, the cap will not only seal the channel, but also form a reduced area 165 . In one embodiment, this cover will minimize the topography. These reductions may minimize any step-to-step capacitance problems between adjacent layers.

During the initial deposition of the insulating material, the small-sized hole 135a substantially eliminates the need for a sufficiently thick material to be deposited on the pipe string. The material of the second insulating layer 170 may be (i) undoped silicon glass (USG), (ii) USG and fluorinated silicon glass (FSG), (iii) organic silicon glass (OSG), (iv) porous OSG And OSG, (v) a composition containing these materials or other conventional dielectric materials. In one embodiment, the second insulating layer 170 is preferably a layer structure of OSG or porous OSG and OSG, and this layer structure uses OSG as a cover for sealing the pipe string.

Figure 7 shows a top view of a structure formed in accordance with the present invention. In this figure, the barrier impedance pattern 175 may be formed by using the barrier patterned resistor 140, and the barrier impedance pattern 175 may be used to additionally strengthen the structure formed at other locations outside the channel. In an exemplary method, the barrier resistance pattern 175 may be formed on the scribe line or via to provide additional strength and prevent pores in the vicinity of the sawing operation. What needs to be recognized is that the channels on the cutting path may cause serious failure due to the breakage of fragile materials. When extreme cutting occurs at the same time, the hindering impedance pattern 175 may also strengthen the dielectric and avoid or prevent the formation of gaps in adjacent vias.

It can be understood that as mentioned above, the steps and devices of the present invention may be repeated on higher-level insulating layers. Therefore, as shown in FIG. 7, it is possible to use the method of the present invention to form a multilayer insulating layer with vias, interconnects and channels. It can also be understood that by providing channels, the effective dielectric constant of the insulating material can be reduced without significantly affecting the integrity, robustness, and strength of the entire device. In fact, by having a Keff of 2.77 or greater, the method of the present invention can achieve a Keff of 2.0 or less. Furthermore, by using the method of the present invention, the use of porous materials in the insulating layer can be avoided. Therefore, by increasing the mechanical strength and thermal performance of the device, the heat can be transferred downward to the substrate. This structure can be formed by other methods described here.

Figures 9 to 14 show another embodiment of the present invention. FIG. 9 is a schematic diagram of a structure having two insulating layers 200 and 210 of any of the aforementioned types. For example, the insulating layer can be SiO₂, FSG, SiCOH, SiLK or other materials. The insulating layer 200 includes an interconnect 220, and the insulating layer includes a via 230 and a plurality of interconnects 240. A dielectric cover, such as SiN, SiC, SiCOH, etc. (diffusion layer) 252 is deposited on the insulating layer 210 and the interconnection. In one embodiment, the thickness of the cover ranges from 5 nanometers to 50 nanometers. If the internal wiring, such as copper wire, is covered by a cover, SiO is provided₂As a cover. Multiple layers of these materials or any combination may be used with the present invention.

Now referring to Figures 10 to 14, after the deposition layer of Au, Ag, In, Sn or Ga with a thickness of 5 nm to 50 nm, SiO₂The blanket deposition layer 260 is provided on the cover 250. It can be understood that the hindering patterning resistance may be deposited between the deposition layers 260 and 270, or may also be on the deposition layer 270. In the foregoing embodiment, the hindering patterning resistance should be an upper lithography mask to prevent the formation of a wide range of gaps in the device. It can be easily dissolved in acids, acid salts and lye. For example, Sn or In may be used in the present invention to make it easier to remove in subsequent steps. However, other metals can also be used together in the present invention. For example, the layer 270 is tempered to produce agglomeration (ie, beading) to form sub-lithographic features ranging from 1 nm to 50 nm. In this approach, a nano island 270a is formed from the layer 270 as a mask for further processing steps. The layer 270 has a thickness between 1 nm and 50 nm, and in one embodiment, has a thickness between 5 nm and 20 nm.

In Figure 11, the pores in layer 150 are etched. This etching can generally be performed by RIE. The nano-island 270a is peeled off by wet or etching, and the RIE etching continues to the layer 250. The lower layer hard mask, such as the cover 250, is used to protect the lower layer structure during the removal of the metal island 270a. RIE etching forms channels or pores 250a (Figure 12). The etching continues to the silicon dioxide layer 210 to form pores or nanochannels 210a, which are substantially the same size as the secondary lithographic features of layer 270, ranging from 1 nm to 50 nm. In one embodiment, RIE is anisotropic etching.

The dielectric cap layer 280 deposited on the insulating layer 210 is deposited by PECVD or any conventional method to deposit silicon dioxide for sealing the channel 250a (FIG. 14). In one aspect of the present invention, the dielectric cap layer 280 may have a thickness ranging from 5 nm to 50 nm (of course, other thicknesses of materials that can be used for this should also be considered). The dielectric cover 280 can also be made of other materials, such as SiC, SiCOH, or SiN. In an embodiment, the nanochannel can be filled with a strong dielectric material before being sealed by the cover dielectric layer. The reduced portion may be formed in the cover dielectric layer 280.

In one aspect of this embodiment, irregular hole patterns in impedance may be formed using electron beam, X-ray or EUV lithography. In this example, this impedance will leave the area mask of the dielectric layer, and vertical pores or pillars are etched into the dielectric layer. When the dielectric is an organic material, a mask such as silicide may be used under the impedance.

In a further embodiment, random hole patterns in a two-dimensional polymer mask with porogen may be used to form pores. In order to manufacture this mask, a polymer is used and then hardened at a high temperature or with a solvent, or the pore former is removed by conventional techniques. The formation of sub-lithographic holes for further processing will eliminate the need for optical lithography exposure for this or other processes. These vertical pores or nanotube columns will then be etched by the above-mentioned methods.

A spin-coated film with fine metal particles such as metal sol (sol) may also be used to form the required holes, represented by layer 270. In this process, a single layer of fine metal particles from the sol may be deposited by the surfactant pretreatment layer 260. The surfactant forms a single layer on the surface and attracts the sol particles to the surface to form a single layer of sol particles. . In other words, this layer will be burned off, leaving metal particles on the surface, which will then be used as a mask. A phase separation spinning solution, such as a block copolymer, can also be used as a mask. In addition, in this embodiment, a selective mask can be used to selectively increase the robustness of critical areas of the wafer, as discussed with reference to FIG. 7.

Although the present invention has been discussed in the previous embodiments, those skilled in the art will be able to understand the possible variants of the present invention without departing from the spirit and scope of the present invention.

<p>100. . . structure</p><p>110. . . Substrate</p><p>120, 200, 210. . . Insulation</p><p>130, 220, 240. . . Inline</p><p>135. . . Diffusion barrier</p><p>140, 175. . . Hinder patterned impedance</p><p>150. . . Block copolymer nano template</p><p>160. . . aisle</p><p>135a. . . Small holes</p><p>160a. . . Larger string</p><p>160b. . . Undercut</p><p>170. . . Second insulating layer</p><p>230. . . Via hole</p><p>252, 280. . . Dielectric cover layer</p><p>260, 270. . . Sedimentary layer</p><p>270a. . . Nano island</p><p>250a. . . Pores</p>

Figure 1 is a schematic diagram of the initial structure used in the present invention; Figure 2 is a schematic diagram of the process steps according to the present invention; Figure 3 is a schematic diagram of the process steps according to the present invention; Figure 4 is a schematic diagram of the process steps according to the present invention; Figure 5 Fig. 6 is a schematic diagram of the process steps according to the present invention (and the structure formed); Fig. 7 is a top view of the structure formed according to the present invention; Fig. 8 is a schematic view of the process steps according to the present invention Figure 9 is a schematic diagram of the process steps according to the present invention; Figure 10 is a schematic diagram of the process steps according to the present invention; Figure 11 is a schematic diagram of the process steps according to the present invention; Figure 12 is a schematic view of the process steps according to the present invention; The schematic diagram of the process steps of the invention; FIG. 13 is a schematic diagram of the process steps according to the present invention; FIG. 14 is a schematic diagram of the process steps according to the present invention (and the structure formed).