Fabrication method of semiconductor device

Manufacturing method of semiconductor device

The present invention relates to a manufacturing technology of a semiconductor device, and more particularly to a technology that is effectively applicable to a testing technology in a semiconductor device containing a semiconductor memory.

Regarding the burn-in test device, there is, for example, Japanese Patent Laid-Open No. 06-283657 (Patent Document 1), which is a burn-in test device that performs a good or bad evaluation of a semiconductor device as a device under test in a burn-in test. As shown in the disclosure of Patent Document 1, the burn-in test device is based on batch processing.

In addition, as for the test technology in the burn-in test device, there is the following technique: divide the burn-in test substrate into each test group, and supply a signal to each test group to implement the burn-in test technology. Japanese Patent Publication 2003-57292 Publication (Patent Document 2); A technique for dividing semiconductor devices into a plurality of groups and performing quality judgments on the basis of the semiconductor device units belonging to them, Japanese Patent Laid-Open No. 2000-40390 (Patent Document 3); or In a constant-temperature bath, semiconductor devices are transported in a state where voltage is continuously applied, and electrical tests are performed at each semiconductor device test station. Japanese Patent Laid-Open No. 05-55328 (Patent Document 4), etc.

[Patent Document 1] Japanese Patent Laid-Open No. 06-283657 [Patent Document 2] Japanese Patent Laid-Open No. 2003-57292 [Patent Document 3] Japanese Patent Laid-Open No. 2000-40390 [Patent Document 4] Japanese Patent Kaiping No. 05-55328 Bulletin

[The problem to be solved by the invention]

The semiconductor device tested by the burn-in test device, for example, contains SiP (System in Package). The semiconductor device is a product that can be stored in a package by superimposing a plurality of semiconductor chips such as logic or semiconductor memory such as microcomputers and the like.

In the future, it can be predicted that SiP will have a significant and important development. After discussing shortening the test time of the semiconductor memory part in order to improve production efficiency, it is expected to omit the aging test or shorten the time of the memory test.

As a result, the test time can be greatly shortened. However, even if the test time is deliberately shortened in the batch mode, there is still a problem that the production capacity can hardly be improved due to the influence of the loading and unloading of the semiconductor device or the step time.

In addition, although a large number of test substrates for testing semiconductor devices can be prepared to reduce the impact of the loading and unloading of the semiconductor device or the step time, the test substrate is equipped with high-density sockets and FPGAs containing semiconductor devices. Field Programmable Gate Array (Field Programmable Gate Array), SRAM (Static Random Access Memory, Static Random Access Memory), buffers and other peripheral circuits, and by preparing a large number of test substrates, the test cost can be very high. High probability.

Furthermore, as a method for performing memory testing in SiP other than the batch method, a general memory testing machine and processor can be considered, but this method is only based on a test time of a few minutes at best, so it can be measured at the same time. The maximum number is only about 256, so there is a possibility of deteriorating efficiency.

An object of the present invention is to shorten the test time of a semiconductor device.

An object of the present invention is to greatly reduce the testing cost of semiconductor devices.

An object of the present invention is to provide a testing method suitable for testing semiconductor devices with an intermediate test time.

An object of the present invention is to provide a testing technique that can perform memory testing in a semiconductor device including semiconductor memory at low cost and efficiently.

The above-mentioned and other objects and novel features of the present invention can be understood from the description of this specification and the accompanying drawings.

Among the inventions disclosed in this application, a brief description of the outline of the representative invention is as follows.

The manufacturing method of the semiconductor device of the present invention includes the following steps: a step of introducing a plurality of test substrates equipped with a plurality of semiconductor devices into a constant temperature bath to perform a test, and taking out a test substrate after the test; The step of removing a plurality of semiconductor devices from the test substrate; the step of mounting a plurality of semiconductor devices to be tested on the test substrate from which the semiconductor device has been removed; and introducing the test substrate with the plurality of semiconductor devices into a thermostat , The steps to implement the test.

In addition, it simply shows the summary of other inventions of this application.

The manufacturing method of the semiconductor device according to the present invention has the following steps: a step of mounting a semiconductor device including SiP products on a plurality of test substrates, and the SiP product combines a plurality of semiconductor chips such as logic or semiconductor memory Those stored in a package; and put a plurality of test substrates into a constant temperature bath, and perform the steps of memory test together.

In addition, the manufacturing method of the semiconductor device according to the present invention has the following steps, and the temperature of the first channel and the second channel of the thermostatic bath are different: to introduce a plurality of test substrates equipped with a plurality of semiconductor devices to the constant temperature The step of taking out a test substrate after the test is finished; the step of removing a plurality of semiconductor devices from the test substrate; the step of mounting a plurality of semiconductor devices to be tested on the test substrate from which the semiconductor device has been removed Steps; and the steps of introducing a test substrate equipped with a plurality of semiconductor devices into a constant temperature bath to implement the test.

Furthermore, the method for manufacturing a semiconductor device according to the present invention includes the following steps, and the temperature of the first channel and the second channel of the thermostatic bath are different: to introduce a plurality of test substrates equipped with a plurality of semiconductor devices to The state of performing the test in a constant temperature bath, the process of removing a test substrate from the end of the test by the processor; the process of removing a plurality of semiconductor devices from the removed test substrate; and the process of cooling the test substrate according to the test result by the processor The semiconductor device performs the steps of sorting and storing; on the test substrate from which the semiconductor device is removed, the processor mounts the steps of performing the test of a plurality of semiconductor devices; and the processor introduces the test substrate with the plurality of semiconductor devices into the thermostat Steps to implement the test.

In addition, the manufacturing method of the semiconductor device of the present invention has the following steps: the test substrates equipped with a plurality of semiconductor devices are introduced into the thermostat to perform the memory test, and the memory test is taken out and the test is finished A step of testing a substrate; a step of removing a plurality of semiconductor devices from the test substrate; a step of mounting a plurality of semiconductor devices for performing a memory test on the test substrate from which the semiconductor device is removed; and a step of mounting a plurality of semiconductor devices The test substrate of the semiconductor device is introduced into the constant temperature bath to perform the steps of memory test.

Furthermore, the method for manufacturing a semiconductor device of the present invention has the following steps: to introduce a plurality of test substrates equipped with a plurality of semiconductor devices into a constant temperature bath to perform the test, and take out the two-piece test after the test is completed The step of substrate; the step of removing a plurality of semiconductor devices from the two test substrates; the step of mounting a plurality of semiconductor devices to be tested on the two test substrates for removing the semiconductor device; and the step of mounting a plurality of semiconductors The two test substrates of the device are introduced into the constant temperature bath, and the test steps are carried out.

In addition, if the other outlines of the invention of this application are separately disclosed, it is as follows.

That is, 1. A method of manufacturing a semiconductor device, comprising the following steps; (a) A plurality of test substrates equipped with a plurality of semiconductor devices are stored in a storage groove of the test device to implement the above-mentioned plurality of semiconductor devices In the state of the test, the step of taking out one piece of the above-mentioned test substrate after the test; (b) the step of removing the plurality of semiconductor devices from the taken-out test substrate; (c) on the above-mentioned test substrate from which the semiconductor device is removed , A step of mounting a plurality of semiconductor devices for testing; (d) a step of storing the test substrate mounted with the plurality of semiconductor devices in the storage slot, and testing the introduced test substrate.

<p>Among the inventions disclosed in the present application, the effects obtained by representative ones are briefly described as follows.</p><p>By loading, starting, ending, and taking out the test device to the test device by taking the test device related to a plurality of devices on a plurality of substrates as a unit, the test cost can be reduced.</p>

Hereinafter, embodiments of the present invention will be described in detail based on the drawings. In addition, in all the drawings for explaining the embodiment, as a principle, the same components are given the same symbols, and their repeated descriptions are omitted.

In the following embodiments, except for particularly necessary circumstances, in principle, the same or identical parts are not described repeatedly.

Furthermore, in the following embodiments, if it is necessary to explain for convenience, they can be divided into a plurality of regions or embodiments for description. However, unless otherwise specified, these are not unrelated to each other. One party is part or all of the modification, detailed explanation, supplementary explanation, etc. of the other party.

In addition, in the following embodiments, when the number of elements (including number, numerical value, range, etc.) is involved, it is not limited to a specific number except for the case where it is specifically stated and the case where the principle is clearly limited to a specific number. The number may be greater than or less than a specific number.

Furthermore, in the following embodiments, the constituent elements (including the element steps, etc.) are not limited to the specific number, except for the case where it is specifically indicated, and may be greater than or less than the specific number.

Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of the constituent elements, etc., except for the cases that are specifically stated and in principle, it can be clearly considered that this is not the case, etc., may be set to include substantially similar or similar Its shape, etc. This situation is the same for the above-mentioned numerical value and range.

Fig. 1 is a block diagram of a burn-in test device used in one embodiment of the present invention, Fig. 2 is an explanatory diagram of a processor in one embodiment of the present invention, and Fig. 3 shows the test performed in the burn-in test device of Fig. 1 A plan view of an example of the semiconductor device. Figures 4 and 5 are cross-sectional views of other examples of the semiconductor device tested in the burn-in test device of Fig. 1, and Fig. 6 shows the shape of the test substrate connected to the burn-in test device of Fig. 1 An explanatory diagram of an example. FIG. 7 is a block diagram showing the structure of the test substrate in FIG. 6, FIG. 8 is a block diagram showing the circuit structure of the substrate and the power supply substrate after the burn-in test device of FIG. 1 is installed, and FIG. 9 shows the diagrams respectively. 1 is an explanatory diagram of the aging test device and the outline of the specifications in the processor in Figure 2, Figure 10 is an explanatory diagram showing the outline of the tester's function in the aging test device of Figure 1, and Figure 11 is an explanatory diagram of the aging test device in Figure 1 An explanatory diagram of the summary of the implemented memory test. Fig. 12 is a timing diagram showing the test sequence in the burn-in test device of Fig. 1, and Figs. 13-20 are detailed flow charts of the memory test using the burn-in test device and the processor. , Figure 21 is a flow chart of the memory test steps implemented by the burn-in test device of Figure 1, Figure 22 is a flow chart of the memory test steps implemented by the batch process discussed earlier by the inventor, and Figure 23 is a comparison An explanatory diagram of the comparison between the memory test performed by the burn-in test device of Fig. 1 and the memory test performed by the batch process of Fig. 22. Fig. 24 shows the relationship between the test time and the number of measurements in various test systems Fig. 25 is an explanatory diagram comparing the effects of the burn-in test device of Fig. 1 and the batch process burn-in test device previously discussed in Fig. 22.

In this embodiment, the burn-in test device (inspection device, test system) 1 has a general burn-in test function, that is, stores a plurality of test substrates in a test substrate storage tank, controls them to a specific temperature, and supplies power and input signals To each substrate, the quality judgment result of the device under test mounted on the substrate is output by the signal output from it, and according to the program, the continuity or discontinuity is implemented in sequence including voltage, signal pattern, and temperature (the temperature is sometimes single) Combine multiple tests, and store the results in the test function of the memory device. For example, in addition to semiconductor devices with inherent defects or semiconductor devices that cause failures that depend on time and stress due to inhomogeneities in manufacturing, devices that have the following functions: implement the burn-in test function of the selection test, and implement the semiconductor device The function of testing in the memory section implements the function of judging the quality of the semiconductor device and even implementing classification according to the test result.

On the other hand, as a tester for similar concepts. The processor system can perform the same tester for a single test substrate. The present invention is not limited to those who use the above-mentioned aging test device, of course, the tester can also be modified. The processor and so on are thus implemented. In addition, it is not necessary to have the original aging test function (heating test).

FIG. 1 is a block diagram showing the structure of the burn-in test device 1. As shown in the figure, a main board 2 is provided in the burn-in test device 1.

For example, about 24 slots 3 are provided on the main board 2. Each channel 3 is connected with a test substrate 4 respectively. The test substrate 4 is, for example, mounted with about 10 semiconductor devices as devices to be tested.

In the main board 2, about 24 rear boards (test control parts) 5 and about 24 power boards (power source parts) 6 of the same number are respectively mounted in a manner corresponding to each channel 3. A fixed DC power supply 7 is mounted on the main board 2. The power substrate 6 is a power source supplied from a fixed DC power source 7, for example, about three kinds of power supply voltages are generated, and they are respectively supplied to the test substrate 4 and the rear substrate 5.

Each rear substrate 5 is connected to a control terminal (test controller) 9 via a hub 8. The control terminal 9 includes, for example, a personal computer, etc., and executes the tester function and the control processor (test system) 10 (FIG. 2) provided in the BIST (Built-In Self Test) of the semiconductor device. The rear substrate 5 generates a test control signal for the test substrate 4 according to the control of the control terminal 9 and processes the judgment result from the test substrate 4.

FIG. 2 is a configuration diagram illustrating the outline of the processor 10.

In the plan view on the right side of FIG. 2, a substrate holder 11 is provided below. An elevator 12 is arranged above the substrate frame 11, and a loader/unloader 13 is arranged above the elevator 12.

An elevator 14 is arranged above the loader/unloader 13, and on the left side of the loader/unloader 13, from above to below, there are respectively a buffer tray 15, a loading tray 16, a good product tray 17, a defective product tray 18, and Unchecked product tray 19.

The substrate rack 11 stores a plurality of test substrates 4 before testing. The elevator 12 lifts the test substrate 4 stored in the substrate rack 11 to a specific position, and when other test substrates 4 are being processed in the loader/unloader 13, it becomes the test substrate 4 until the loader/unloader 13 is emptied. Standby buffer.

The loader/unloader 13 mounts the semiconductor device to be tested on the test substrate 4 and unloads the semiconductor device after the test. The elevator 14 lifts the T test substrate 4 equipped with the semiconductor device 20 to a specific position, and when the channel of the burn-in test device 1 is full, it becomes a buffer for the test substrate 4 to wait until the channel is emptied.

The buffer tray 15 stores empty trays. The loading tray 16 stores the semiconductor device under test. The good product tray 17 stores semiconductor devices determined to be good products after the test, and the defective product tray 18 stores semiconductor devices determined to be defective products. The uninspected product tray 19 stores uninspected semiconductor devices. The so-called uninspected refers to the removal of the semiconductor device 20 that cannot be tested due to poor contact with the measurement socket 4b (FIG. 6) mounted on the semiconductor device 20 and the test substrate, etc., and thus becomes the category of re-inspection. Object.

3 is a plan view showing an example of the semiconductor device 20 tested by the burn-in test device 1, and FIGS. 4 and 5 are cross-sectional views of other examples of the semiconductor device 20 tested by the burn-in test device 1.

The semiconductor device 20 shown in FIG. 3 includes a so-called flat SiP, and is configured as follows: a microcomputer and flash memory or SDRAM (Synchronous Dynamic RAM) are mounted on a printed wiring board 21 Wait for a plurality of semiconductor chips 22-25 such as heterogeneous semiconductor memory.

On the wafer mounting surface of the printed wiring board 21, connection electrodes and wiring patterns are formed, and the connection electrodes and the electrode portions provided on the semiconductor wafers 22 to 25 are connected to each other via bumps or the like.

On the back surface of the printed wiring board 21, bump electrodes and wiring patterns are formed, and the bump electrodes and the electrode portions of the semiconductor wafers 22-25 are electrically connected to each other through the wiring patterns and through holes, respectively.

The bump electrodes are formed in an array at a predetermined pitch, and the bump electrodes are respectively formed with solder bumps containing spherical solder that becomes an external connection terminal.

In addition, the semiconductor device 20 in FIG. 4 includes a stacked SiP, and the stacked SiP is stacked with two semiconductor chips 26 and 27 including semiconductor memory such as a microcomputer and a flash memory.

In this case, the semiconductor device 20 of FIG. 4 includes a BGA (Ball Grid Array, a ball grid array package) which is a type of surface-mounted CSP. A semiconductor chip 26 is mounted on the center of the chip mounting surface of the printed wiring board 28.

A connection electrode 29 is formed in the center portion of the wafer mounting surface of the printed wiring board 28, and the connection electrode 29 and the electrode portion provided on the back surface of the semiconductor wafer 26 are connected to each other via bumps 30 and the like.

In this semiconductor wafer 26, a semiconductor wafer 27 is laminated, and an adhesive material, such as an insulating resin, is adhered and fixed. On the chip mounting surface of the printed wiring board 28, solder electrodes and wiring patterns are formed in the vicinity of the peripheral portions of the opposite sides of the semiconductor chip 26. The soldering electrode provided on the printed wiring board 28 is connected to the electrode portion formed on the peripheral portion of the main surface of the semiconductor wafer 27 via the soldering wire 31.

On the back surface of the printed wiring board 28, a plurality of bump electrodes are formed in an array shape, and solder bumps 32 containing spherical solder are respectively formed in the bump electrodes.

In addition, the periphery of the welding electrodes of the semiconductor chips 26 and 27 and the printed wiring board 28 and the bonding wires 31 are sealed by the sealing resin 33 to form a package.

Furthermore, the semiconductor device 20 in FIG. 5 includes a QFP (Quad Flat Package) type. In this case, the die holders 34 and 35 located in the center of the semiconductor device 20 are equipped with, for example, two semiconductor chips 36 and 37 including a microcomputer and a flash memory.

In the vicinity of the four peripheral portions of the semiconductor chips 36 and 37, there are a plurality of inner leads 38, and the electrode portions provided on the main surfaces of the semiconductor chips 36 and 37 and the inner leads 38 are connected to each other via bonding wires 39.

The semiconductor chips 36 and 37, the inner leads 38 and the bonding wires 39 are sealed by the sealing resin 40 to form a package. Protruding from the four sides of the package, there are substantially L-shaped outer leads 41 extending and formed with inner leads 38.

FIG. 6 is an explanatory diagram showing an example of the shape of the test substrate 4.

As shown in FIG. 6, on the lower edge of the test substrate 4, a substrate edge connector 4a is provided. The substrate edge connector 4a is a connector connected to the channel 3 provided on the main board 2.

For example, about ten measuring sockets 4b for mounting the semiconductor device 20 are mounted on the test substrate 4, and peripheral circuits 4c are respectively provided below each measuring socket 4b in a manner corresponding to the measuring socket 4b.

FIG. 7 is a block diagram showing the structure of the test substrate 4 in FIG. 6.

FIG. 7 shows a semiconductor device 20 mounted on a measurement socket 4b in the test substrate 4, and a peripheral circuit 4c corresponding to the semiconductor device 20. As shown in FIG.

In the peripheral circuit 4c, via the board edge connector 4a, the test signal output from the rear board 5 and various power supply voltages generated by the power board 6 can be supplied. Various power supply voltages generated by the power supply substrate 6 can also be supplied to the semiconductor device 20 via the substrate edge connector 4a. The peripheral circuit 4c saves voltage level conversion or test instructions, and results at the end of the test.

The semiconductor device 20 includes a CPU 20a, an SDRAM 20b, and a flash memory 20c as a microcomputer, and can test the SDRAM 20b and the flash memory 20c by the BIST of the CPU 20a based on test signals output and input via the peripheral circuit 4c.

FIG. 8 is a block diagram showing the circuit configuration of the rear substrate 5 and the power supply substrate 6.

On the rear substrate 5, a CPU module 5a and an FPGA 5b are mounted.

The CPU module 5a includes a LAN interface 42, SDRAM 43, flash memory 44, CPU 45, CF slot 46, bus interface 47 and so on.

The LAN interface 42, SDRAM 43, flash memory 44, CPU 45, CF slot 46, and bus interface 47 are connected to each other through address bus AB and data bus DB, respectively.

The LAN interface 42 is an interface with the control terminal 9 (FIG. 1) as a host. SDRAM43 is the working area of CPU45.

The flash memory 44 stores startup programs and the like. The CF slot 46 is used for a CF (Compact Flash) card slot, and stores a program for starting the flash memory 44.

The CPU 45 controls the test substrate 4 corresponding to the program stored in the flash memory 44. The bus interface 47 is the interface of the external bus connected with FPGA5b.

The FPGA5b includes a driver 48 connected to the input pins and I/O pins of the substrate edge connector 4a, a buffer 49 and a power control unit 50 connected to the driver, and so on. The power supply control unit 50 controls the power supply voltage generated by the power supply board 6 according to instructions from the control terminal.

Four power generation units 51 to 54 are provided on the power supply board 6. The power generation unit 51 generates a power supply voltage to be supplied to the driver of the FPGA 5b. The power generation units 52 to 54 respectively generate three different power supply voltages to be supplied to the semiconductor device 20 and the like.

The power generation units 51 to 54 are respectively provided with a D/A (Digital/Analog) converter, a regulator, and an overcurrent detection unit. The D/A converter converts the control signal output from the power control unit 50 into an analog value. The regulator generates an arbitrary power supply voltage based on the analog ratio output from the D/A converter. The overcurrent detection unit outputs a detection signal when detecting overcurrent.

Next, the test technique implemented by the burn-in test device 1 in this embodiment will be described.

First, the operation of the processor 10 in FIG. 2 will be described.

FIG. 9 is a schematic diagram showing the specifications of the burn-in test device 1 and the processor 10, respectively.

Figure 9 shows the setting temperature of the constant temperature bath, temperature accuracy, temperature scale, tray classification, channel spacing, cooling method of the test substrate 4, constant temperature bath composition, minimum test time, supply method of uninspected products, and ID of the test substrate 4 Summary of various specifications in identification.

First, the semiconductor device 20 is placed in a tray and then supplied, and the semiconductor device 20 is mounted on the test substrate 4 by the loader/unloader 13. The test substrate 4 on which the semiconductor device 20 is mounted is supplied to the empty part of the constant temperature chamber in the burn-in test device 1 via the elevator 14 each piece.

The test substrate 4 with the semiconductor device 20 is reinstalled. Because other test substrates 4 enter and exit the test, it becomes the following composition: In the burn-in test device 1, the entrance and exit of the test substrate 4 are opened according to each channel. . In addition, it is also possible to prepare only the number of throttle valves required for the thermostatic bath corresponding to one test substrate 4.

Each test substrate 4 after the test is cooled and recovered by the elevator. Then, according to the test results, the loader/unloader 13 classifies each semiconductor device 20 to be classified as good, defective, and uninspected, and stored in the good tray 17, defective tray 18, or uninspected tray 19 Any of them.

In this example, although the loader and the unloader are the same to improve the space efficiency, the loader and the unloader may be configured separately. Furthermore, the test substrate 4 is provided with an ID based on a barcode, for example, to check the test results by the loader/unloader 13 for classification, and can also be used for a specific measurement socket that holds a specific test substrate 4 in the device. It is information such as defectiveness, and is used for the purpose of not containing products, etc. in the measuring socket.

Next, the structure of the burn-in test device 1 shown in FIG. 1 will be described.

As the main test content of the burn-in test device 1, there are the following content: A memory test performed by BIST using a semiconductor memory (SDRAM, flash memory, etc.) of a microcomputer mounted in the semiconductor device 20 , Write customer data to flash memory, and implement burn-in tests on microcomputers and memory units.

In addition, the function of the tester is set exclusively for BIST, and signals are generated to the test substrate 4 in units of each rear substrate 5, and the determination result from the test substrate 4 is processed. Furthermore, there is no need to be equipped with a dedicated ALPG (ALgorithmic Pattern Generator) or TG (Timing Generator) and address breaker, etc., and the test program can be created in C language.

The clock signal (about 66 MHz) of the actual operation of the semiconductor device 20 is implemented by the BIST of the semiconductor device 20, and the BIST tester is only transmitted according to the program. As a result, it is determined that the timing accuracy is about 1 MHz without worrying about the timing accuracy.

FIG. 10 is an explanatory diagram showing the outline of the function of the tester in the burn-in test device 1.

In FIG. 10, the upper part of the item column indicates the functions implemented by the CPU module 5 a mounted on the rear substrate 5, and the lower part of the item column indicates the functions implemented by the control terminal 9.

Next, the memory testing technology implemented by the burn-in testing device 1 will be described.

FIG. 11 is an explanatory diagram showing the outline of the memory test performed by the burn-in test device 1.

The test substrate 4 on which the semiconductor device 20 is mounted is sequentially introduced into the constant temperature chamber, and after reaching a certain temperature, the memory test is started. The test time of the memory test is, for example, about ten minutes to about tens of minutes.

After the memory test is finished, the test substrate 4 is cooled, and then according to the test result, the processor 10 is classified into PASS, FAIL, and unchecked and then taken out. The number of test substrates stored in the constant temperature bath is about 24, for example. The test substrate 4 enters and exits into the constant temperature bath in units of one piece.

The temperature of the constant temperature bath can be set from low temperature to normal temperature to high temperature. The low temperature setting range is, for example, about -50°C to about 0°C, and more widely, about -55°C to about 10°C. In this low temperature, for example, semiconductor devices used in electronic systems for automobiles, etc. can be tested.

In addition, the temperature setting of the test at room temperature is implemented at room temperature of about 25°C, and the wider setting range is about 15°C to about 40°C. The test temperature setting at high temperature is about 125°C, and the wider setting range is about 90°C~150°C.

FIG. 12 is a timing chart showing the test sequence in the burn-in test device 1.

First, in the measuring socket 4b of the first test substrate 4, for example, about 10 semiconductor devices 20 are mounted (inserted). When the mounting of the semiconductor device 20 is completed, the test substrate 4 will be introduced into the thermostat. And, after the thermostat reaches a certain temperature (temperature), the memory test starts (selection).

Then, if the memory test is over, the test substrate 4 can be cooled. With the processor 10, the semiconductor device 20 is unplugged from the measurement socket 4b, and the measurement sockets of the test substrate 4 can be reinstalled again. 4b The tested semiconductor device 20 (plug-in). After that, the test substrate 4 is introduced into a constant temperature bath, and after reaching a specific temperature (temperature), a memory test (selection) is performed.

Furthermore, in the second test substrate 4, when the semiconductor device 20 is mounted until the first test substrate 4 is completed, the semiconductor device 20 is then mounted (inserted). If the second test substrate 4 also ends the mounting of the semiconductor device 20 in the same way, it is introduced into the thermostat and reaches a specific temperature (temperature), and then the memory test (selection) is started.

If the memory test is finished, after cooling the test substrate 4, the processor 10 removes the semiconductor device 20 from the measuring socket, and the semiconductor device 20 tested by the test substrate 4 can be mounted (plugged in) again. Hereinafter, in the test substrates 4 from the third to the twenty-fourth, the memory test can be performed by the same cycle.

Thereby, it becomes the following so-called single-chip processing sequence: 24 test substrates 4 are processed sequentially with a time difference, and each test substrate 4 is cycled in a unit of one. The test starts from the test substrate 4 of the semiconductor device 20 after the semiconductor device 20 is inserted, and the self-test ends. The test substrate 4 takes out the semiconductor device 20. Here, the so-called single-chip processing refers to a processing in which each test substrate 4 is subjected to a memory test separately. However, the test itself should pay attention to the situation where multiple pieces can be processed at the same time. That is, the introduction to the test device, the start, end, and take-out of the test are implemented in a single piece. Moreover, this situation is not for the convenience of the device, and excludes the simultaneous introduction of two or more pieces.

Next, using the flowcharts in Figs. 13-20, the test steps in the burn-in test device 1 are described in detail. Here, although the description focuses on a certain channel in the burn-in test device 1, in other channels, the test steps described below are also implemented separately.

13 and 14 are flowcharts showing an example of the test procedure when the number of channels of the burn-in test device 1 and the number of test substrates 4 are the same.

First, it will be explained using FIG. 13. FIG. 13 is a test procedure in a case where the elevator 12 is used as a buffer and the test substrate 4 is on standby until the loader/unloader 13 is emptied.

First, open the door of the channel after the test is completed (step S101), pull out the test substrate 4 from the channel (step S102), and close the door of the channel (step S103).

Next, the test substrate 4 is on standby in the elevator 12, and after the loader/unloader 13 is emptied (step S104), the processor 10 unloads the semiconductor device 20 from the test substrate 4, and performs classification according to the test result (step S105).

After the semiconductor device 20 is removed, the semiconductor device 20 to be tested again is mounted on the test substrate 4 (step S106), and the loader/unloader 13 enters a standby state (step S107).

After that, the door of the channel pulled out in the process of step 102 is opened (step S108), the test substrate 4 is introduced into the channel (step S109), and the door of the channel is closed (step S110).

Then, it waits until the temperature of the test substrate 4 introduced in the process of step S109 reaches the set temperature (step S111), and when the temperature reaches the set temperature, the memory test is performed (step S112).

In the memory test, test 1 to test N are performed in parallel in each of the M semiconductor devices 20 mounted on the test substrate 4. In addition, if all the tests are completed, the self-test board 4 can output a flag indicating the end of the test. The rear substrate 5 detects the end of the test based on the mark, and then informs the control terminal 9 of it. After that, the processing of steps S101 to S112 is repeated again.

In addition, the memory test time in the processing of step S112 may be larger according to the difference in the write/delete time of the memory portion due to the manufacturing unevenness of the semiconductor device 20, etc., or the number of semiconductor devices that have become poorly tested. different.

For example, as long as there is a semiconductor device 20 with a very long write/delete time, the test time will be restricted by the semiconductor device 20 and become longer. In addition, when all the semiconductor devices 20 mounted on the test substrate 4 are judged to be defective in the first test 1, the test ends at that time, so the test time can be greatly reduced.

In this way, since the test time is different according to the test substrate 4 introduced into each channel, the processing of the above steps S101 to S112 can be implemented separately in each channel.

Next, the test procedure shown in Figure 14 will be explained. Fig. 14 is a test when a temperature-independent test is performed during the period when the elevator 12 is used as a buffer until the loader/unloader 13 is emptied and the test substrate 4 stands by, and until the temperature of the test substrate 4 in the tank stabilizes Step example.

First, open the door of the channel after the test is completed (step S201), and after pulling out the test substrate 4 from the channel (step S202), close the door of the channel (step S203). Next, the test substrate 4 is on standby in the elevator 12, waiting for the loader/unloader 13 to be emptied (step S204), the processor 10 pulls out the semiconductor device 20 from the test substrate 4, and classifies according to the test results (step S205) .

After that, the semiconductor device 20 for re-testing is mounted on the test substrate 4 (step S206), and then it stands by in the loader/unloader 13 (step S207). Thereafter, the door of the channel in the process of step 202 is opened (step S208), and after the test substrate 4 is introduced into the channel (step S209), the door of the channel is closed (step S210).

Then, after waiting until the channel into which the test substrate 4 is introduced reaches the set temperature, the memory test is performed (step S211). In the process of this step S211, temperature setting is started, and a temperature-independent test is performed during the period until the set temperature is stabilized. In this way, the test can be carried out more efficiently.

In addition, if the memory test ends, the self-test board 4 can output a flag indicating the end of the test. The rear board 5 detects the end of the test based on the mark, and informs the control terminal 9 of it. After that, the processing of steps S201 to S211 is repeated again.

15-20 are flowcharts illustrating examples of the test steps when the number of test substrates 4 is more than the number of channels of the burn-in test device 1 by one or two.

First, it will be explained using FIG. 15. Fig. 15 uses the elevator 12 as the buffer 1, and uses the standby part (not shown) provided between the loader/unloader 13 and the elevator 14 as the buffer 2, until the loader/unloader 13 is emptied for testing The test procedure for the case where the substrate 4 is on standby. Thereby, the test substrate 4 for re-testing can be efficiently prepared, and the test efficiency can be further improved.

First, open the door of the channel after the test is completed (step S301), and after pulling out the test substrate 4 from the channel (step S302), close the door of the channel (step S303).

Next, the test substrate 4 is on standby in the elevator 12 and waits for the loader/unloader 13 to be emptied (step S304). The processor 10 pulls out the semiconductor device 20 from the test substrate 4, and performs classification according to the test results (step S305). ).

After that, after the semiconductor device 20 for re-testing is mounted on the test substrate 4 (step S306), it waits in the standby section (step S307), and waits for the channel to be cleared.

If the slot is empty, the slot door is opened (step S308), and after the test substrate 4 is introduced into the slot (step S309), the slot door is closed (step S310).

Then, it waits until the temperature of the test substrate 4 introduced in the process of step S309 reaches the set temperature (step S311), and when the temperature reaches the set temperature, the memory test is performed (step S312).

Next, the test procedure shown in Figure 16 will be described. In FIG. 16, only the standby part is used as a buffer, and another example of the test procedure in the case where the test substrate 4 is on standby until the loader/unloader 13 is emptied.

First, open the door of the channel after the test is completed (step S401), and after pulling out the test substrate 4 from the channel (step S402), close the door of the channel (step S403).

Next, the processor 10 pulls out the semiconductor device 20 from the test substrate 4, and performs classification according to the test result (step S404). After that, after the semiconductor device 20 for re-testing is mounted on the test substrate 4 (step S405), it waits in the standby section (step S406), and waits for the channel to be cleared.

If the slot is empty, the slot door is opened (step S407), and after the test substrate 4 is introduced into the slot (step S408), the slot door is closed (step S409).

Then, it waits until the temperature of the test substrate 4 introduced in the process of step S408 reaches the set temperature (step S410), and when the temperature reaches the set temperature, the memory test is performed (step S411).

Next, the test procedure shown in Figure 17 will be described. Figure 17 is the case where the elevator 12 is not used and the standby part is used as a buffer. When the loader/unloader 13 is not emptied, the test substrate 4 is on standby in the slot, and when the slot is not emptied, the loader/unloader 13 An example of the test procedure in the case where the test substrate 4 is put on standby.

First, open the door of the channel after the test is completed (step S501), and after pulling out the test substrate 4 from the channel (step S502), close the door of the channel (step S503).

Next, the processor 10 pulls out the semiconductor device 20 from the test substrate 4, and performs classification according to the test result (step S504). Next, the semiconductor device 20 to be tested again is mounted on the test substrate 4 (step S505), and after waiting in the loader/unloader 13 (step S506), the channel door is opened (step S507), and the test substrate 4 is introduced After reaching the slot (step S508), the slot door is closed (step S509).

Then, it waits until the temperature of the test substrate 4 introduced in the process of step S508 reaches the set temperature (step S510), and when the temperature reaches the set temperature, the memory test is performed (step S511).

Next, the test procedure shown in Figure 18 will be described. Fig. 18 uses the elevator 12 and the standby part as a buffer to make the test substrate 4 stand by until the loader/unloader 13 is emptied, and until the temperature of the test substrate 4 in the tank is stabilized, a situation independent of temperature is implemented Examples of test steps.

First, open the door of the channel after the test is completed (step S601), and after pulling out the test substrate 4 from the channel (step S602), close the door of the channel (step S603).

After that, stand by in the elevator 12 (step S604), wait for the loader/unloader 13 to be emptied, and pull out the semiconductor device 20 from the test substrate 4 by the processor 10, and perform classification according to the test result (step S605).

Next, after the semiconductor device 20 to be re-tested is mounted on the test substrate 4 (step S606), it stands by in the standby section and waits for the channel to be cleared (step S607).

If the slot is empty, the slot door is opened (step S608), the test substrate 4 is introduced into the slot (step S609), and the slot door is closed (step S610).

Then, the temperature of the test substrate 4 introduced in the process of step S609 is set to start, and the memory test is performed after reaching the set temperature (step S611). Here, in the process of step S611, the temperature setting is started, and a temperature-independent test is performed until the temperature setting is stabilized. In this way, the test can be carried out more efficiently.

Next, the test procedure shown in Figure 19 will be described. Figure 19 uses only the standby part as a buffer, and when the loader/unloader 13 is not emptied, the test substrate 4 is put on standby in the tank until the channel is emptied. During the period until the temperature of the test substrate 4 in the test board 4 stabilizes, an example of the test procedure in the case of performing a temperature-independent test.

First, open the door of the channel after the test is completed (step S701), and after pulling out the test substrate 4 from the channel (step S702), close the door of the channel (step S703).

Next, the processor 10 pulls out the semiconductor device 20 from the test substrate 4, and performs classification based on the test results (step S704), and then mounts the semiconductor device 20 to be tested again on the test substrate 4 (step S705), and is placed in the standby section In standby, waiting for the channel to be cleared (step S706).

If the slot is empty, the slot door is opened (step S707), the test substrate 4 is introduced into the slot (step S708), and the slot door is closed (step S709).

In addition, the temperature of the test substrate 4 introduced in the process of step S708 is set to be the set temperature and the memory test is performed, and the test substrate 4 after the test is completed waits in the tank (step S710).

In this case, in the process of step S710, the temperature setting can be started, and a temperature-independent test can be performed until the temperature is stabilized. In this way, the test can be carried out more efficiently.

Next, the test procedure shown in Figure 20 will be described. Fig. 20 is the case where the elevator 12 is not used and the standby part is used as a buffer. When the loader/unloader 13 is not emptied, the test substrate 4 is on standby in the tank, and when the tank is not emptied, the loader/unloader 13 is used. During the period when the test substrate 4 is put on standby and the temperature of the test substrate 4 in the tank stabilizes, the test procedure example in the case of performing a temperature-independent test.

First, open the door of the channel after the test is completed (step S801), pull out the test substrate 4 from the channel (step S802), and close the door of the channel (step S803).

Next, the processor 10 pulls out the semiconductor device 20 from the test substrate 4, performs classification according to the test result (step S804), mounts the retested semiconductor device 20 on the test substrate 4 (step S805), and installs the semiconductor device 20 on the test substrate 4 (step S805). The unloader 13 stands by (step S806), and waits for the channel to be cleared.

If the channel is empty, the channel door is opened (step S807), the test substrate 4 is introduced into the channel (step S808), and the channel door is closed (step S809).

In addition, the temperature of the test substrate 4 introduced in the process of step S808 is set to start, and the memory test is performed after reaching the set temperature. The test substrate 4 after the test is completed and waits in the tank (step S810).

In this case, the temperature setting can also be started in the processing of step S810, and a temperature-independent test can be performed until the setting temperature is stabilized. In this way, the test can be carried out more efficiently.

Above, in the memory test shown in FIGS. 14-20, in the same manner as in FIG. 13, test 1 to test N are performed in parallel in each semiconductor device 20. In addition, if all the tests are completed, the self-test board 4 can output a flag indicating the end of the test. The rear substrate 5 detects the end of the test according to the mark, and then informs the control terminal 9 of it. After that, repeat the implementation again from the initial step processing.

In addition, in the memory test of FIGS. 14-20, the time of the memory test is based on, for example, the difference in the write/delete time of the memory due to the manufacturing unevenness of the semiconductor device 20, or the semiconductor that has become poorly tested. The number of devices is quite different.

Furthermore, in FIGS. 13-20, the situation where each test substrate 4 is introduced into the channel separately is disclosed, but the test substrate 4 can also be a so-called two-single method, etc., and two (or more than three) ) Is introduced into the channel, and two pieces (more than three pieces) can be taken out from the channel at the same time. However, the larger the number of sheets, the more likely it is to reduce the cost-cutting effect of the substrate and increase the burden on the processor used to transport the substrate. Therefore, the monolithic approach, that is, a monolithic approach, has advantages in terms of processor cost. The upper limit of N slices can be considered as N=4, but it is preferably less than two single slices.

Furthermore, the insertion sequence of the substrates can also be from the top (or from the bottom) in the initial stage, but of course it is not limited to this. For example, it can also be inserted randomly.

In this case, the larger the number of test substrates 4 imported at the same time, the more the load of the processor 10 will increase, and the disadvantages of increasing the test waiting time will occur.

FIG. 21 is a flowchart of the memory test performed by the burn-in test device 1.

In FIG. 21, for example, the situation of performing a normal temperature memory test (normal temperature selection) and a high temperature memory test (high temperature selection) is disclosed. In FIG. 21, when the burn-in test is carried out, it is carried out in other steps, for example, before the processing of step S901 described below.

When the room temperature selection and the high temperature selection are implemented by the burn-in test device 1, the memory test by the room temperature is first performed (step S901). Then, after performing a high-temperature memory test (step S902), the logic tester can measure the logic function and electrical characteristics of the CPU 20a of the semiconductor device 20 (step S903).

Here, in the processing of steps S901 and S902, after the memory test is completed in the test sequence illustrated in FIG. 12 in the processing of step S901, the processing of step S902 is performed again in the processing illustrated in FIG. 12 Memory test performed in the test sequence. That is, a separate memory test is performed for the room temperature selection and the high temperature selection.

Furthermore, the test technology in non-volatile memory such as flash memory cards is disclosed in detail in the specification and drawings of Japanese Patent Application No. 2002-141267.

FIG. 22 is a flowchart of the memory test steps implemented by the batch processing discussed previously by the inventors.

The batch processing system prepares a large number (for example, about 72) test substrates, and simultaneously performs a memory test of a large number (for example, about 1,000) of semiconductor devices.

In this case, a semiconductor device for performing the test is mounted on all the test substrates (step S1001), and the burn-in test and the memory test are performed together (step S1002). And, if the memory test is over, all the semiconductor devices mounted on the test substrate are removed (step S1003), and the test performed by the logic tester is implemented (step S1004).

FIG. 23 is an explanatory diagram for comparing the processing comparison between the memory test performed by the burn-in test device 1 and the memory test performed by the batch process discussed by the inventor.

In FIG. 23, the upper section shows the relationship between the processing time of the memory test performed by batch processing and the number of substrates, and the lower section shows the processing time of the memory test performed by the single-chip processing of the burn-in test device 1 The relationship with the number of substrates. In addition, the test condition is that the test time is 30 minutes, and by high-temperature sorting, for example, about 1000 semiconductor devices are tested.

As shown in the figure, in batch processing, for example, when 72 test substrates are used, the time required for the insertion step of mounting semiconductor devices on all test substrates is about one hour. After that, the 72 test substrates were introduced into the constant temperature bath until the temperature setting, the memory test, and the cooling of the test substrate were completed, which took about 1.2 hours.

After the memory test is finished, the step of removing the semiconductor device from each test substrate again takes about 1 hour, so the total processing time of the memory test is about 3.2 hours.

In this way, in the insertion step of the batch process, since the semiconductor devices are mounted on the test substrates one by one, the other 71 test substrates are in a waiting state. Moreover, in the temperature setting of the constant temperature bath, since all the test substrates are introduced and the constant temperature bath is heated together, it takes time to raise and lower the temperature.

On the other hand, in the single-chip processing performed by the burn-in test device 1, about 24 test substrates are used, and the memory test is performed in the order illustrated in FIG. 21, thereby completing the test in about 2.3 hours. All memory tests.

In this way, in the single-chip processing, the number of test substrates 4 used can be reduced, and the test time can be shortened.

Figure 24 is a graph showing the relationship between the test time and the number of measurements in a general test system.

For example, in a logic tester, the number of measurements is about one to four, and the test time is about several seconds. In addition, in a memory tester that does not have a burn-in test function, the number of measurement is about 128 to about 128, and the test time is about ten seconds to ten minutes. Furthermore, in a batch-type aging test device, the number of test pieces is from about 500 to 10,000, and the test time is from about 8 hours to about 100 hours.

In this way, there is no test system that can efficiently test 128 to 512 semiconductor devices in the so-called test time of about ten minutes to tens of minutes (the hatched area in the figure), as it can reasonably correspond to such a test. It takes less time and less test substrates to obtain a test system with a production capacity equal to or higher than that of the burn-in test device for batch processing, preferably the burn-in test device 1 (or only the burn-in test device).

FIG. 25 is an explanatory diagram comparing the effects of the burn-in test device 1 of single-chip processing and the burn-in test device of batch processing discussed earlier.

In Figure 25, compare the number of test substrates and the cost of the memory test when the memory test of the semiconductor device is performed in a specific number every month. The cost calculation of the memory test is set as a hypothetical cost model ( The relative comparison of the cost for testing the substrate, the repayment cost of the device investment, the operator's cost, the utility cost of electricity, etc., and the memory test yield).

In the figure, the bar-shaped curve represented by hatching represents the number of test substrates (relative value) required for each test condition in batch processing, and the bar-shaped curve represented by white part represents each test condition in single-chip processing The number of test substrates required (relative value).

In addition, the broken line curve represented by a solid line represents the test cost (relative value) of each test condition in batch processing, and the broken line curve represented by a broken line represents the test cost (relative value) of each test condition in single chip processing.

In this case, as shown in FIG. 25, with less test time (including aging test), especially under any test condition of no aging test and high temperature or normal temperature, the test cost can be greatly reduced.

On the other hand, under test conditions that include burn-in testing and both room temperature selection and high temperature selection coexist, regardless of the increase in the number of test substrates, the cost of memory testing performed by batch processing can also be less than that of single chip processing.

According to the results, when the memory test time of the semiconductor device is short, the monolithic type is used, while the memory test time is long (especially when the burn-in test is performed). The implemented memory test method can be used flexibly, which can further greatly improve the test efficiency.

Therefore, according to the present embodiment, the number of test substrates 4 used can be reduced, the memory test time can be greatly shortened, and the manufacturing cost of the semiconductor device 20 can be reduced.

As mentioned above, the invention made by the present inventors has been specifically described based on the embodiments, but the present invention is not limited to the above-mentioned embodiments, and of course various changes can be made without departing from the gist of the invention.

In the above embodiment, the memory test in the semiconductor device of the SiP product is disclosed. However, if the memory test is a product that can perform memory test by a test substrate, it can also be a semiconductor device other than SiP.

For example, it can be a microcomputer (CPU) that does not include MCP (Multi Chip Package), but a product that includes multiple semiconductor memories such as flash memory, SRAM, DRAM, and so on. SoC (System on Chip) products where the main functions of, chipset, video chip, etc. are integrated on a semiconductor chip, or in addition, a large-capacity flash memory with BIST introduced so that multiple memory tests can be performed at the same time Semiconductor devices, such as memory testers such as memory products, or processors, which require a long test time for testing.

In addition, not only the above-mentioned semiconductor devices, but also memory card products or memory module products that require a long test time for testing with memory testers/processors such as multimedia cards.

[Industrial availability]

The testing method of the semiconductor device of the present invention is suitable for efficiently and at low cost to implement the memory test in the semiconductor device including the semiconductor memory.

<p>1Aging test device (inspection device, test system)</p><p>2Motherboard</p><p>3Slot</p><p>4Test board</p><p>4aSubstrate edge connector</p><p>4bMeasuring socket</p><p>4cperipheral circuit</p><p>5Back board (test control department)</p><p>5aCPU Module</p><p>5bFPGA</p><p>6Power Board (Power Section)</p><p>7Fixed DC power supply</p><p>8 Hub</p><p>9Control terminal (test controller)</p><p>10Processor (test system)</p><p>11Substrate rack</p><p>12Lift</p><p>13Loader/Unloader</p><p>14Lift</p><p>15Buffer tray</p><p>16Load Pallet</p><p>17Good product tray</p><p>18Defective product tray</p><p>19Unchecked product tray</p><p>20Semiconductor device</p><p>20aCPU</p><p>20bSDRAM</p><p>20cFlash memory</p><p>21Printed Wiring Board</p><p>22~25Semiconductor chip</p><p>26, 27Semiconductor chip</p><p>28Printed Wiring Board</p><p>29Connecting electrode</p><p>30 bump</p><p>31Welding line</p><p>32Solder bump</p><p>33Sealing resin</p><p>34, 35Die holder</p><p>36,37Semiconductor chip</p><p>38Internal lead</p><p>39Welding line</p><p>40Sealing resin</p><p>41External lead</p><p>42LAN interface</p><p>43SDRAM</p><p>44Flash memory</p><p>45CPU</p><p>46CF slot</p><p>47Bus Interface</p><p>48Drive</p><p>49Buffer</p><p>50Power Control Department</p><p>51~54Power Generation Unit</p><p>ABAddress Bus</p><p>DBData Bus</p>

Fig. 1 is a block diagram of a burn-in test device according to an embodiment of the present invention.

Fig. 2 is an explanatory diagram of a processor according to an embodiment of the present invention.

FIG. 3 is a plan view showing an example of a semiconductor device used for testing in the burn-in test device of FIG. 1. FIG.

4 is a cross-sectional view showing another example of the semiconductor device used for testing in the burn-in test device of FIG. 1.

FIG. 5 is a cross-sectional view showing an example of a semiconductor device used for testing in the burn-in test device of FIG. 1.

Fig. 6 is an explanatory diagram showing an example of the shape of a test substrate connected to the burn-in test device of Fig. 1.

FIG. 7 is a block diagram showing the structure of the test substrate of FIG. 6.

FIG. 8 is a block diagram showing the circuit configuration of the substrate and the power supply substrate after being installed in the burn-in test device of FIG. 1.

Fig. 9 is an explanatory diagram showing the outline of the specifications of the burn-in test device of Fig. 1 and the processor of Fig. 2 respectively.

Fig. 10 is a schematic explanatory diagram showing the function of the tester in the burn-in test device of Fig. 1.

FIG. 11 is a schematic explanatory diagram showing a memory test performed by the burn-in test device of FIG. 1. FIG.

FIG. 12 is a timing diagram showing the test sequence in the burn-in test device of FIG. 1.

FIG. 13 shows a detailed flow chart of an example of a memory test using a burn-in test device and a processor.

Figure 14 shows a detailed flow chart of other examples of memory testing using a burn-in test device and a processor.

FIG. 15 shows a detailed flow chart of an example of a memory test using a burn-in test device and a processor.

FIG. 16 shows a detailed flow chart of other examples of memory testing using a burn-in test device and a processor.

FIG. 17 shows a detailed flow chart of an example of a memory test using a burn-in test device and a processor.

Figure 18 shows a detailed flow chart of other examples of memory testing using a burn-in test device and a processor.

Figure 19 shows a detailed flow chart of an example of memory testing using a burn-in testing device and a processor.

FIG. 20 shows a detailed flow chart of other examples of memory testing using a burn-in test device and a processor.

FIG. 21 is a flowchart of a memory test performed by the burn-in test device of FIG. 1.

FIG. 22 is a flowchart of the memory test steps implemented by the batch processing discussed previously by the inventors.

FIG. 23 is an explanatory diagram for comparing the processing comparison between the memory test implemented by the burn-in test device of FIG. 1 and the memory test implemented by the batch processing of FIG. 22.

Figure 24 is a graph showing the relationship between the test time and the number of measurements in various test systems.

FIG. 25 is an explanatory diagram comparing the effects of the burn-in test device of FIG. 1 and the burn-in test device of batch processing previously discussed by the inventor of FIG. 22.