System and method for stress free conductor removal

System and method for removing conductor without stress

The present invention relates to a dual-damascene semiconductor manufacturing process, and more particularly to a method and system for planarizing features and layers in a semiconductor manufacturing process.

Single and dual damascene manufacturing processes have become more and more common in semiconductor manufacturing. In a typical dual damascene manufacturing process, one or more conductive materials are deposited in the pre-patterned trenches and vias formed in the semiconductor substrate or in the thin film formed on the semiconductor substrate, In order to form the required circuit interconnection. This often results in excessive conductive material or a covering of conductive material. The conductive material covering is unnecessary and unexpected, so it must be removed in order to produce metal inlaid features and provide a uniform and flat surface for subsequent processing.

Typically, the covering of the conductive material is removed from the semiconductor substrate by a combination of chemical mechanical polishing (CMP) and electrochemical polishing (ECP) (eg, etching) treatments and CMP and ECP treatments. Each of these treatments has serious shortcomings. For example, ECP typically has relatively small throughput, poor uniformity, and ineffective removal of non-conductive materials.

CMP requires material contact treatment, which typically will leave conductive residues, cause corrosion of various materials, or cause uneven removal, and cannot properly planarize interconnects and interlayer dielectric (ILD) tops. noodle. CMP also causes stress-related damage (such as inner layer separation, peeling), leaving interconnects and ILD structures remaining. The stress damage caused by CMP will be further aggravated by the extremely poor inner layer adhesion characteristics of the materials used recently. Reducing the actual stress by reducing the actual force of the CMP process often results in unacceptably small throughput and other poor processing performance parameters.

In view of this, there is a need for an improved planarization system and method to uniformly and substantially remove the covering material with minimal actual stress on the remaining features. The improved planarization system and method must be suitable for semiconductor manufacturing and must be suitable for processes such as dual damascene processing or other semiconductor manufacturing processes.

In summary, the present invention satisfies the above needs by providing an improved formation system and method for semiconductors in a dual damascene structure. We must understand that the present invention can be implemented in various forms, including, for example, processing, equipment, systems, computer-readable media, or devices. Various innovative embodiments of the present invention will be described below.

One of the embodiments provides a method for forming a semiconductor with a dual damascene structure, including: receiving a patterned semiconductor substrate. The semiconductor substrate has a first conductive interconnect material that fills up one of the multiple features in the pattern. The first conductive interconnect material has a covering part. Flatten the covering. During the planarization process, the covering portion is substantially completely removed. A mask layer is reduced and a subsequent dielectric layer is formed on the planarized covering portion. A mask is formed on the subsequent dielectric layer. One or more features are formed in the subsequent dielectric layer and the features are filled with a second conductive interconnect material.

The flattening cover includes a small downward force CMP process. The flattening covering part includes a flattening treatment that does not generate stress.

The mask layer includes two or more mask layers. Shrinking the mask layer includes removing at least a part of one of the two or more mask layers. Shrinking the mask layer includes removing at least one layer of two or more mask layers. At least one of the two or more mask layers includes a conductive material.

Shrinking the mask layer includes removing the mask layer. Shrinking the mask layer includes removing a part of the first conductive filling material that is substantially flush with the remaining part of the mask layer. Shrinking the mask layer includes etching the mask layer.

Forming a subsequent dielectric layer on the planarized covering portion includes coating one or more subsequent dielectric layers. The subsequent dielectric layer includes a low-k dielectric material.

The formation of the subsequent dielectric layer on the planarized covering portion includes the subsequent planarized dielectric layer. The planarization of the subsequent dielectric layer includes confirming the unevenness in the subsequent dielectric layer, forming a second dielectric layer on the entire subsequent dielectric layer, and planarizing the second dielectric layer. The second dielectric layer is a substantially flat material. The second dielectric layer is a spin-on glass. The subsequent dielectric layer is a low-k dielectric material.

Another embodiment provides a method for forming a semiconductor in a dual damascene structure, including: receiving a patterned semiconductor substrate. The patterned semiconductor substrate has a first conductive interconnecting material that fills up a plurality of features in the pattern. The first conductive interconnect material has a covering part. Flatten the covering. During the planarization process, the covering portion is substantially completely removed. Remove a mask layer. A subsequent dielectric layer is formed on the planarized covering part. A mask is formed on the subsequent dielectric layer. One or more features are formed in the subsequent dielectric layer and one or more features are filled with a second conductive interconnect material. Removing the mask layer includes etching the mask layer.

Another embodiment is to provide a method for forming a semiconductor with a dual damascene structure, including: receiving a patterned semiconductor substrate. The patterned semiconductor substrate has a first conductive interconnecting material that fills up a plurality of features in the pattern. The first conductive interconnect material has a covering part. The covering part is flattened, wherein the covering part is substantially completely removed during the flattening process. A mask layer is reduced and a subsequent dielectric layer is formed on the planarized covering portion. Forming the subsequent dielectric layer includes confirming unevenness in the subsequent dielectric layer, forming a second dielectric layer on the entire subsequent dielectric layer, and planarizing the second dielectric layer. A mask is formed on the subsequent dielectric layer. One or more features are formed in the subsequent dielectric layer. Fill one or more features with a second conductive interconnect material. Planarizing the second dielectric layer includes etching the second dielectric layer.

The invention provides the advantages of improved flatness and more accurate mask application. In addition, by substantially eliminating non-low-k dielectric materials from the dielectric stack, the overall k value of the dielectric stack can be reduced.

Other aspects and advantages of the present invention can be more clearly understood with reference to the following detailed description and the accompanying drawings showing the principle of the present invention.

Reference will be made to the accompanying drawings to illustrate the present invention. In the illustration, similar reference signs indicate similar elements.

Several exemplary embodiments of the improved planarization system and method are described below. Those familiar with this art should clearly understand that the present invention can still be implemented without some or all of the specific details described herein.

An embodiment of the improved planarization system and method is to provide improved local planarization uniformity throughout the semiconductor substrate. The improved local flattening uniformity substantially eliminates the local unevenness caused by changes in the features of the underlying layer and the deposition process. Another embodiment is to provide improved overall planarization uniformity throughout the entire substrate (eg, edge uniformity compared to center uniformity).

FIG. 1 shows a patterned semiconductor substrate 100 in a dual damascene process according to an embodiment of the present invention. In part of the semiconductor manufacturing process, such as the dual damascene manufacturing process, the substrate 100 has been patterned. The substrate 100 is patterned using a mask. The substrate 100 includes large and somewhat isolated features 102 (such as trenches, vias, etc.), smaller and somewhat isolated features 104, and several features 106, and these features are arranged closely together . It also includes a barrier layer 110. Typically, the barrier layer 110 is a different material from the substrate 100 or the conductive interconnect material 120. The conductive interconnect material 120 is copper or copper alloy or other conductive materials.

The cover 112 of the conductive interconnect material 120 extends above the features 102, 104, and 106 and has relatively local variations 114, 116, 118 in the thickness of the cover 112. As shown in the figure, compared to the smaller feature 104, it has a slightly smaller variation in the thickness of the covering portion 112, and the larger feature 102 has a relatively larger thickness in the covering portion 112. Reduce the amount. The densely arranged features 106 have a covering portion 112 with a somewhat larger thickness.

The typical etching process etches the covering portion 112 of the conductive interconnect material 120 over the entire wafer area at a fairly uniform rate, so the typical etching process exposes the second portion of the barrier layer 110 near the closely spaced features 106 Before, the first part of the barrier layer 110 near the large feature 102 will be exposed. In short, a typical etching process cannot planarize the covering portion 112 of the conductive interconnect material and compensates for the unevenness.

Figure 2 shows an additional layer 202 added in accordance with an embodiment of the present invention. An additional layer 202 is formed above the covering portion 112. The additional layer 202 is a substantially flat filling material (such as spin-on glass (SOG), polysilicon, polymer photoresist, double layer, UV or heat curable material, or other flowable to form a flat surface and has appropriate etching characteristics) s material). There may also be an arbitrary and relatively thin conformal layer 204 between the additional layer 202 and the covering portion 112 (for example, a thickness of about 25 to 100 nm). The conformal layer 204 is a barrier layer or an adhesive layer. The conformal layer 204 allows more materials to be used as the additional layer 202.

The additional layer 202 and the covering portion 112 have an etching selectivity of substantially 1:1, so that subsequent etching processes (such as plasma or gas etching processes) can etch both the additional layer 202 and the covering portion 112 at substantially the same rate .

FIG. 3 shows a substantially flat covering portion 112' according to an embodiment of the present invention. Since the extra layer 202 above the stack of layers 100, 110, 112, 202 is formed as a substantially flat surface, the first etching process can uniformly etch the extra layer 202 and the covering portion 112 over the entire area until the remaining covering portion 112' is substantially flat, and the local variation 114, 116, 118 is substantially eliminated.

A typical formulation involves the following conditions, that is, a 1:1 etch selectivity between the additional layer 202 and the cover 112 is provided. For example, if the additional layer 202 is SOG and the covering portion 112 is copper, the halogen-based (such as Cl, F, Br, I) chemical substances have etching rate control on both SOG and copper, allowing all The 1:1 selectivity is required for adjustment. Although any plasma feed gas that generates reactive halogen radicals can be used, CF₄, Cl₂, And HCl, HBr are typical examples. Various processing parameters can be adjusted to control the etching rate, selectivity, uniformity, and reduce changes due to processing variables such as substrate temperature and one or more additives (such as Ar, H₂, Cl, O₂, CH₃X(X=F, Cl, Br, I), CH₂F₂, And CH₄) Corrosion caused by the content.

Another method involves the use of Ar or other passivation gases such as He, Xe, Ne, Kr and other passive gases to dominate the etching by sputtering. Other additives are used as the main etchant for the copper covering 112 to provide the etching of the additional layer 202. Rate control and passivation of the top surface of the remaining copper 112. Other additives include, for example, H₂And/or CF₄. Each of these treatments is available at 75^oC and 400^oOperate in a large temperature range between C.

The first etching process is an etching process designed to make the remaining covering portion 112 substantially locally flat, in which the local variations 114, 116, and 118 are substantially eliminated. One or more subsequent etching processes will remove most or most of the covering portion 112'. A final etching process may be applied to continue the etching process to the end point of removing the cover 112' from the barrier 110. The general etching process may also include a final etching process. The final processing system comprising subsequent selective barrier removal and blunt after etching of the remaining portion of the conductive material 120, serve to prevent corrosion and provide stability required for further processing. The additional operations after the final etching can be designed not only to remove any material in a large amount, but also to passivate the remaining conductive material 120, so as to prevent corrosion and provide stability required for further processing.

FIG. 4A shows a substrate 100 that has undergone a second etching process according to an embodiment of the present invention. The second etching process continues to the end point, so the barrier layer 110 at all positions will be exposed substantially at the same time and only the conductive material (such as copper, copper-containing alloys and combinations thereof, and other conductive materials) in the part 120 will remain, and It fills the features 102, 104, 106.

The first etching process and the second etching process may be substantially similar or completely different. For example, the first etching process is an etching process to improve the covering portion with local unevenness 114, 116, 118 (for example, caused by the position and size of the features 102, 104, 106, and the concentration of the underlying layer) 112 local flatness. The entire additional layer 202 and part of the covering portion 112 can be removed in the first etching process. In comparison, the second etching process is a more selective etching process, which removes most of the remaining and flat covering portion 112 to reach the end point (that is, when the barrier layer 110 is exposed).

FIG. 4B shows a substrate that has undergone barrier removal processing according to an embodiment of the present invention. A part of the barrier layer 110 is removed to expose the mask layer 402 below. Only part of the barrier layer 110 formed in the features 102, 104, 106 remains. The typical second etching process removes most of the covering portion 112 at a high speed and preferably has a high selectivity to the barrier layer 110. For example, if the covering portion 112 is copper, a halogen-based chemical substance (such as Cl₂, CF₄, HCl, HBr, BCl₃) Can be effectively used for the second etching treatment. In another method, an etching treatment dominated by physical properties such as Ar (or other inert gas or passivation gas)-based sputtering treatment can be used. Various processing parameters can be adjusted to control the etching rate and selectivity. Various processing parameters include adjusting the substrate temperature balance such as reactive substances and one or more additives (such as H₂, O₂, Ar, He, Xe, Ne, Kr, etc.) content and other processing variables.

FIG. 5 is a flowchart 500 of the operation of the method for performing local planarization according to an embodiment of the present invention. In operation 505, an additional layer 202 is attached above the conductive covering portion 112. In operation 510, a first etching process is applied to remove most of the additional layer 202 and the conductive cover 112. In operation 515, a second etching process is applied to remove the remaining covering portion 112' to the end point.

In another embodiment, operation 515 also includes the final etching process described above. The subsequent processing after the final etching includes selective barrier removal and passivation of the remaining conductive material 120 to prevent corrosion and provide stability required for further processing. The additional operations after the final etching process can be designed not only to remove any material in a large amount, but also to passivate the remaining conductive material 120, so as to prevent corrosion and provide stability required for further processing.

6A to 6D show a series of chemical conversion and etch-back treatments applied to the substrate 600 to improve local uniformity according to an embodiment of the present invention. FIG. 7 is a flowchart 700 of a method for applying chemical conversion and etch-back processing to a substrate 600 to improve local uniformity according to an embodiment of the present invention. As shown in FIG. 6A, similar to the substrate 100 shown in FIG.

Referring to FIGS. 6B and 7 below, in operation 705, an additional layer 604 is formed above the covering portion 602. An additional layer 604 is deposited or formed on the cover 602. For example, the additional layer 604 is formed by chemical conversion at the uppermost end of the covering portion 602. If the covering portion 602 is made of copper or copper alloy, the copper reactant layer 604 can be formed by controlling the size of its exposure to gas. One example is halogen gas, which can form a copper halide layer 604. The copper reactant layer 604 diffuses into the surface of the copper covering portion 602 and transforms into the top end of the copper covering portion 602. The chemical conversion of copper is a known technique, as published by Nagrej S. Kalukani and Robert T. Dehav in 2002, in the Journal of the Electrochemical Society, Vol. 149(11), pages G620 to G632 "Application for low temperature, dry etching, and flattening of copper."

In another example, an additional layer 604 may be deposited on the cover 602. The deposition layer 604 includes a polymer layer or an oxide layer deposited on the covering portion 602.

Hereinafter, referring to operation 710 and FIG. 6C, an etch-back process is applied to remove the additional layer 604. Part of the cover 602 is also removed. Removal of the additional layer 604 will result in further softening (ie, flattening) of the outline of the covering portion 602 to become the outline 606'. The copper halide substantially softens the outer shape of the covering portion 602. The copper halide also maintains an etch-back selectivity of substantially 1:1 with the copper covering portion 602. Operations 705 and 710 can be repeated multiple times to substantially flatten the covering portion 602 to the subsequent contours 606' and 606", so as shown in FIG. 6D, until the final contour is substantially flat.

The chemical conversion of the copper covering portion 602 formed by the compound is typically achieved by oxidizing the copper at the interface of the Cu reactive material. The copper oxidation system in this case includes a copper compound in which elemental copper undergoes chemical conversion to become copper in a positively oxidized state. For example, at lower temperatures (such as less than 200^oC) In the chlorine plasma, the copper will be oxidized and become copper chloride or copper dichloride (CuCl or CuCl) on the surface₂）。

The etch-back treatment involves the reduction of the copper compound into another chemical compound that can be volatilized, so that it will detach from the surface of the remaining covering portion 602' at a fixed substrate temperature. For example, in reactive hydrogen species (such as H₂In the presence of plasma), there will be CuCl₂Reduced to volatile Cu₃Cl₃. Alternately performing the shape-related conversion followed by the etchback of the conversion part results in the substantial removal of the copper covering 602 while simultaneously flattening the shape (eg, contour) of the copper covering 602.

In operation 715, if the covering portion 602 is substantially flattened, the method operation ends. Moreover, if the covering portion 602 is not substantially flattened in operation 715, the method operation continues to the above-mentioned operation 705. In one of the embodiments, operations 705 to 715 are performed on-site in a single etching chamber. In another embodiment, operation 710 can be performed offline and includes ECD or small downward force CMP processing to achieve a substantially flat covering portion 602' as shown in FIG. 6D.

The method operation shown in FIGS. 6A to 7 can be used as a general flat removal process, which performs both the flattening of the uneven covering portion 602 and the removal of most of the covering portion 602.

The local thickness of the substrates 100 and 600 can be determined by any of one or more layer thickness mapping techniques of known techniques. For example, the eddy current sensor can reflect the thickness of the covering portions 112, 112', such as US Patent Application No. 10/328,912, filed on December 23, 2002, jointly owned by Gertis et al. The case is titled "Signal separation system, method and equipment for thin film substrates using eddy current", and US Patent Application No. 10/251,033, filed on September 19, 2002, jointly owned by Gertis and others. It is named "Detection and Mapping System and Method of Metal Residues in a Multi-Step Sequence" and so on.

The methods and systems shown in FIGS. 1 to 7 described above illustrate that various methods can substantially eliminate local and pattern-related non-uniformities in the covering portion. However, the methods and systems shown in FIGS. 1 to 7 are not directly aimed at correcting the overall unevenness. The overall non-uniformity includes the non-uniformity of the material removal rate at the center of the substrate compared to the variation at the edge of the substrate and other non-local phenomena.

FIG. 8 is a flowchart of a method operation 800 for correcting overall unevenness according to an embodiment of the present invention. In operation 805, a substrate with local non-uniformities such as non-uniformities related to the feature pattern in its covering portion is received. In operation 810, the local unevenness is substantially eliminated by CMP, ECP, the method and system shown in FIGS. 1 to 7 or any other known methods. As shown in FIG. 3 above, substantially removing the local unevenness will form a substantially and locally planarized covering portion, such as the planarized covering portion 112'.

FIG. 9 shows a substantially removed and flattened cover 902 according to an embodiment of the present invention. The substantially removed and flattened covering portion 902 is a relatively thin covering portion, such as a thickness of several hundred angstroms.

In operation 815, any overall non-uniformity in the flattened coating is confirmed and quantified by mapping the substrate with the flattened coating. The covering portion can be flattened by mapping any one of the above-mentioned one or more known layer thickness mapping techniques. The mapping can be performed on-site (in the current processing room) or offline (outside the current processing room). The on-site mapping processing is also dynamic processing and allows the subsequent processing to be dynamically adjusted while the subsequent processing is in progress.

In operation 820, the etching process is adjusted and controlled to meet the specific requirements of the overall non-uniformity detected in the final etching process, and the process that can substantially mechanically generate no stress is removed from the process determined in operation 815. The location and size of the overall unevenness. For example, if the remaining covering portion 902 is about 500 angstroms thick at the center and 300 angstroms thick at the edges, the formula can be adjusted to compensate for the unevenness from the center to the edge, so that the entire barrier layer 110 At the same time exposed. Since no mechanical force is applied to the substrate during the etch-back process, a process that does not generate stress can avoid the above-mentioned CMP problem.

The selected recipe (for example, the value of the selected process variable) is selective to the barrier layer 110 (that is, the barrier will be etched at a lower rate than the recipe for etching copper, for example, the copper etching in these processes The typical selectivity range beyond barrier etching is greater than 1 but less than 3) and it minimizes any depression (for example, excessive removal of conductive material 120 in features 102, 104, 106).

The final etching has a relatively small etching rate for both the remaining copper of the covering portion 902 and the barrier layer 110, so that any recess of the smallest feature portion 102, 104, 106 can be blocked with respect to the residual height of the barrier layer 110 Is the smallest. Therefore, the final etching will not have extremely high selectivity to etching copper.

It can also have the final etch-back treatment. The final etch-back treatment includes the etch-back of the mask material and/or ILD material with appropriate selectivity and uniformity control, so that the final result is: can provide with the least loss of copper and ILD Substantially overall uniform and substantially flat features (for example, at the end of the final etching and barrier removal process, any copper recesses are overall uniform throughout the substrate 100). In this case, the final etching includes a homogenization process that can etch back the mask material with high selectivity, so as to minimize copper loss and minimize copper pits. For example, the halogen concentration is low and the substrate temperature is low (for example, less than about 200^oC) The halogen-based treatment will maintain a small copper etching rate, while still fully chemically etching the mask material. Can use halogen-containing reactive substances (such as CF₄, C₂F₆, C₄F₆) Any plasma feed gas. Etching rate control additives include Ar, O₂, CH₂F₂And can also include other additives.

At the end of the final etching and the final etch-back process, if the overall copper recess and/or mask/ILD loss is uneven across the substrate, additional changes must be made to the formulation to correct the overall unevenness . For example, a typical situation is that the result of etching non-uniformity can be explained as an etching rate with a faster center or a faster edge. In each of these situations, copper pits and/or mask/ILD losses will vary throughout the substrate. During the final etch-back of the mask/ILD material, the use of appropriate uniformity and selectivity control will be able to compensate and offset this change, so that the overall flatness can be obtained with the least loss of copper and mask The characteristic part. In the case of a faster final etching process at the center of the substrate with a larger copper recess, the final etch-back process that selectively etches the edges of the mask material is faster to compensate, in order to achieve and characteristic The copper in the parts 102, 104, and 106 has the same height. The typical selectivity obtained in this treatment is greater than 2. In order to provide uniformity control, the recipe changes include pressure, temperature fluctuations throughout the substrate, ion flux uniformity control, gas concentration, and processing chamber wall temperature. The control selectivity changes include the concentration of reactive halogen species, substrate temperature, and bias power.

10-11C illustrate the method operation of the dual damascene processing according to an embodiment of the present invention. FIG. 10 is a flowchart of a method operation 1000 according to an embodiment of the present invention. In operation 1002, a patterned and filled semiconductor substrate 1100 is provided. FIG. 11A shows a patterned and filled semiconductor substrate 1100 in a dual damascene process according to an embodiment of the present invention. The lower substrate layer 1102 includes an exemplary large feature portion 1106, an exemplary middle feature portion 1109, and a plurality of exemplary small feature portions 1108. The substrate layer 1102 includes a low-k dielectric material.

A liner layer 1104 (for example, tantalum, tantalum nitride, tantalum nitride stack, ruthenium, tungsten, platinum, iridium, titanium silicon nitride, etc.) is formed on the inner side of each of the features 1106, 1108, and 1109. A mask layer 1110 may also be included. The mask layer 1110 is typically an oxide layer, a carbonized layer, or a nitride layer for the purpose of masking the previous etching patterning operation. The present invention is also applicable to the case where the mask layer is regarded as equivalent to the material of the dielectric substrate. As described in more detail below, the mask layer 1110 may also be a metal and/or conductive material. The mask layer 1110 typically has a higher k dielectric value (eg, greater than about 3) than other low-k dielectric materials used in semiconductor manufacturing processes. For the purpose of protection (for example, to protect the low-k material from physical and chemical damage during subsequent processing), a mask layer 1110 is often formed on the low-k dielectric layer. The mask layer 1110 includes a plurality of layers which will be described in detail below.

The features 1106, 1108, and 1109 are filled with conductive filler material 1120 (for example, copper, copper alloy or other conductive materials). Similar to the above-mentioned FIG. 1, the conductive filling material 1120 has uneven covering portions formed above the features 1106, 1108, and 1109.

In operation 1004, the semiconductor substrate 1100 is planarized. FIG. 11B shows a patterned, filled and planarized semiconductor substrate 1100 in a dual damascene process according to an embodiment of the present invention. In the general removal and planarization process shown in FIGS. 1 to 9 above, the uneven covering portion of the conductive filling material 1120 has been substantially removed. A CMP process (for example, a small downward force CMP process) can also be used to remove most of the covering portion of the conductive filling material 1120 and planarize the conductive filling material 1120. After the general removal and planarization process, a substantially flat covering portion of the conductive filling material 1120' will remain.

In operation 1006, the remaining conductive filler material 1120' and the liner layer 1104 are removed to the desired end point (for example, substantially all the materials expected to be removed have been removed). This operation can be accomplished by one or more of the aforementioned steps. FIG. 11C shows an etched semiconductor substrate 1100 in a dual damascene process according to an embodiment of the present invention. The end point of this partial etching is typically when the upper surface of the mask layer 1110 is exposed and the upper surface of the conductive material 1120' is uniform or slightly dish-shaped with respect to the upper surface of the mask layer. The etching process and chemical substances are selective to the mask 1110, so the mask is not substantially removed and the conductive filling material 1120' is removed. Therefore, the remaining conductive material 1120' is removed by etching until the mask layer 1110 is not substantially covered.

In a typical conventional semiconductor manufacturing process, operation 1006 is performed by a CMP process and the mask layer 1110 is used as a CMP stop layer. Therefore, the typical mask layer 1110 must be as thick as 1000 Angstroms or more. Since the CMP process typically cannot achieve a selectivity of about 10:1 between the liner layer 1104 and the substrate dielectric layer 1102, the mask layer 1110 must be used as a CMP stop layer. Therefore, in a typical CMP operation, the liner layer 1104 below the upper surface of the mask layer 1110 and the conductive filling material 1120' are often removed, and an unexpected channel is formed between the mask layer and the conductive material 1120' Ditch or rounded edge transition zone. In addition, a typical CMP operation will cause unintended sores, local unevenness, and separation between various layers of materials. The shear stress imparted to the semiconductor substrate 1100 by a typical CMP process will cause separation. However, a relatively small downward force CMP, such as a downward force less than about 5 psi, will not give severe shear stress to the semiconductor substrate 1102 during the removal of the conductive filler material. Many low-k materials have relatively small adhesion properties, so the transition zone between low-k materials and other materials is particularly easy to separate.

However, the etching process described herein can achieve an etching selectivity of approximately 10:1 for the liner layer 1104 to the mask layer 1110 without applying shear stress to the semiconductor substrate 1102. The etching process will therefore more accurately etch the pad layer relative to the mask layer. In this way, the removal (ie, etching) of the liner layer 1104 can be more accurately controlled and a steeper edge transition area between the mask layer 1110 and the conductive material 1120' can be achieved. In addition, since it is no longer necessary to use the mask layer 1110 as a CMP stop layer, the mask layer can be thinner (that is, less than 250 angstroms) or completely eliminated. Also, additional materials can be used to replace traditional CMP stop materials. For example, the mask layer 1110 includes a layer (multi-layer) of a low-k organosilicate glass material, which contains silicon, carbon, oxygen and hydrogen (Si, C, O, H), Or dielectric materials with or without silicon based polymer, such as cross-linked polyphenylene ether polymers, methyl silicates, hydrosilicates, and many porous types of these films. The requirements for such a mask/covering layer 1110 and its exact thickness depend on the inlay pattern scheme, photolithography and pattern etching processing conditions. Compared with the above-mentioned CMP, the present invention can have a thinner film in all cases.

In operation 1008, a subsequent dielectric layer is formed over the etched semiconductor substrate 1100. FIG. 11D shows a semiconductor substrate 1100 with a subsequent dielectric layer 1130 according to an embodiment of the invention. The subsequent dielectric layer 1130 includes one or more barrier layers 1122. The subsequent dielectric layer 1130 includes a low-k dielectric material. The subsequent dielectric layer 1130 is also planarized as shown in FIGS. 13 and 14A to 14C.

In operation 1010, as shown in FIG. 11E, a mask layer 1132 is formed on the subsequent dielectric layer 1130. FIG. 11E shows a semiconductor substrate 1100 having a mask layer 1132 formed on a subsequent dielectric layer 1130 according to an embodiment of the present invention. The mask layer 1130 allows the dielectric layer 1130 to be patterned for subsequent device formation processing.

In operation 1012, the dielectric layer 1130 is etched to form features 1134, 1136, and 1138. FIG. 11F shows a semiconductor substrate 1100 having features 1134, 1136, and 1138 formed in a dielectric layer 1130 according to an embodiment of the present invention. As described above, the features 1134, 1136, and 1138 can be interconnected by the lower conductive filler material 1120' among the lower features 1106, 1108, and 1109.

In operation 1014, the features 1134, 1136, and 1138 are also filled with conductive filling materials. Filling the features 1134, 1136, and 1138 with conductive filler material also includes coating a suitable liner layer 1140 on the inner surface of the features. Then, the method operation system ends or the method operation can continue to operation 1002 described above.

Hereinafter, referring to FIG. 11G and FIGS. 12A to 12D, the process of removing to the end in operation 1006 of FIG. 10 will be described in more detail. FIG. 11G is a flowchart of a method operation 1006 for removing the remaining conductive filling material 1120 to a desired end point according to an embodiment of the present invention. 12A to 12D show detailed views of the region 1200 of the mask layer 1110 and the conductive material 1120' in various embodiments of the process of removing to the end point.

As shown in FIGS. 12A and 12B, the mask layer 1110 includes a plurality of layers 1110A and 1110B. As described above, in the conventional CMP operation, the mask layers (multiple mask layers) 1110, 1110A, and 1110B will typically remain between the material stacks during implementation. However, since the mask layer (multiple mask layers) has a larger k value, it is expected that the mask layer will have a minimum thickness. FIG. 12A shows that the conductive filling material 1120' and the liner layer 1104 are slightly dish-shaped compared to the upper surface of the mask layer 1110A. The conductive filling material 1120' has a dish depth of Δh below the upper surface of the mask layer 1110A. Typically, the mask layers 1110A and 1110B have a total thickness of 500 to 1000 angstroms or more and a typical Δh range is between 250 and 500 angstroms. Since it is no longer necessary to use the mask layers 1110A and 1110B as the CMP stop layer, but can still be removed by etching, it can provide the metal damascene chip designer with greater flexibility and can use other materials for other functions. For example, the upper mask layer 1110A is still a nitride or oxide with a relatively large k value, which meets the requirements of its strength or resistance to chemical substances. The nitride layer and oxide layer have better deposition and adhesion properties and can be etched easily and accurately. Alternatively, the mask is a low-k material or omitted as described above.

FIG. 12A shows a detailed view of a region 1200 at the end of the substrate 1100 according to an embodiment of the present invention. FIG. 12B shows another detailed view of the region 1200 at the end of the substrate 1100 according to an embodiment of the present invention. The etching chemistry has more precise selectivity than the CMP process, so the upper mask layer 1110A can be etched without affecting the liner 1104 and the conductive material 1120'. As shown in FIG. 12B, the upper mask layer 1110A can be etched until it is substantially uniform with the liner 1104 and the conductive material 1120' (that is, the dish depth Δh is close to zero). In addition, a small downward force CMP polishing wheel can also be used to remove at least a part of the upper mask layer 1110A. One of the advantages of this method is that since at least part of the upper mask layer 1110A is removed, the mask layer can be made much thicker than (for example, about greater than 1000 Angstroms) Typical users.

FIG. 12C shows another detailed view of the region 1200 at the end of the substrate 1100 according to an embodiment of the present invention. As shown in FIG. 12C, the upper mask layer 1110A can be completely removed by etching treatment chemicals that are selective to the lower mask layer 1110B. The etching treatment is plasma etching treatment or wet etching treatment. Since the upper mask layer 1110A is completely removed, the upper surface of the remaining mask layer 1110B below the upper surface of the gasket 1104 and the conductive material 1120' has a depth of Δh' which is slightly dish-shaped. Therefore, the depth Δh' of the dish shape will be much smaller than the Δh shown in FIG. 12A.

The stress-free etching process shown in FIG. 1 to FIG. 9 removes the entire upper mask layer 1110A, so the upper barrier layer has an initial thickness greater than 1000 angstroms or more. Moreover, since the upper mask layer 1110A is completely removed, the conductive material can be used as the upper barrier layer without short-circuiting the filled features 1106, 1108, and 1109 together. The lower mask layer 1110B is extremely thin (for example, less than 5 angstroms). It is also possible to omit the lower mask layer 1110B (that is, the lower barrier layer is made of the same material as the substrate 1102), and the selective etching process for the substrate material can completely remove the upper mask layer 1110A to make the lower substrate The material is exposed. If the semiconductor substrate is already in the plasma etching processing chamber, this plasma etching treatment can be easily applied, so that the general removal and planarization operation without stress can be performed as shown in FIG. 10 above.

FIG. 12D shows still another detailed view of the region 1200 at the end of the substrate 1100 according to an embodiment of the present invention. As shown in FIG. 12D, etching the liner 1104 and the conductive filling material 1120' to make the dish depth h", compared to h', is more significantly reduced. In this way, the dish depth h" is less than 250 angstroms.

FIG. 13 is a flowchart of a method operation 1008 of coating a subsequent dielectric layer 1130 according to an embodiment of the present invention. In operation 1302, the semiconductor substrate 1100 is coated with a dielectric layer 1130. FIG. 14A shows a plurality of dielectric layers 1410 and 1412 constituting the dielectric layer 1130 according to an embodiment of the present invention.

In operation 1304, the unevenness 1414 of one or more of the dielectric layers 1410 and 1412 is confirmed. As shown in the above operation 1010 in FIG. 10, the flatness of the upper dielectric layer 1412 is extremely important to whether the correct photolithography operation can be performed (that is, the mask and the subsequent etching). In a typical conventional process, the total thickness of the dielectric layers 1410, 1412 must be relatively thin (for example, less than about 1000 angstroms). However, as described in the detailed description below, the dielectric layers 1410, 1412 will have a total thickness much greater than 1000 angstroms (for example, about 4000 angstroms or more). For example, the dielectric layers 1410 and 1412 are spin on glass (SOG). When coating each layer, the unevenness 1414 will be reduced and substantially eliminated.

In another example, the first dielectric layer 1410 is a low-k dielectric material, and the second dielectric layer 1412 is SOG or other substantially flat dielectric materials. For example, SOG can reduce the unevenness of each layer of SOG by about 50%.

In operation 1306, another dielectric layer is attached to the semiconductor substrate 1100. FIG. 14B shows the third dielectric layer 1420 on the semiconductor substrate 1100 according to an embodiment of the present invention. A third dielectric layer 1420 (or a subsequent dielectric layer) may be attached to further reduce the unevenness 1414. As shown in the figure, the unevenness 1416 is substantially smaller than the unevenness 1414.

In operation 1310, the dielectric layers 1410, 1412, and 1420 are planarized. FIG. 14C shows a planarized third dielectric layer 1420 according to an embodiment of the invention. After the planarization operation, a planar portion of the third dielectric layer 1420' remains. The flattening operation is any suitable flattening process (for example, CMP, small downward force CMP, flattening without stress, etc.).

In addition, we should clearly understand that it is not necessary to perform the instructions represented by the operation shown in any of the above figures in the described order, and it is not necessary to operate all the processing represented by the operation to implement the present invention. In addition, the processing shown in any of the above figures can also be implemented as software stored in any one of RAM, ROM, or a computer's hard disk drive or a microprocessor control system (such as a processing control system) or a combination thereof.

Although various embodiments of the present invention are described by the above and the drawings, the scope of the present invention is not limited to the above embodiments. As long as the spirit of the present invention is not deviated from, the present invention can be implemented by any modification. invention. Therefore, each embodiment is illustrative and not restrictive, and the scope of the present invention is not limited to the content of each embodiment. Therefore, the scope of the present invention includes the above-mentioned embodiments and their variations.

<p>100, 1100, 1102, 600. . . Semiconductor substrate (or layer)</p><p>102, 104, 106, 1106, 1106', 1106", 1108, 1109, 1134, 1136, 1138... Features</p><p>110, 1122. . . Barrier layer</p><p>112, 112', 602, 602', 902. . . Covering part (or remaining copper)</p><p>114, 116, 118. . . Local inhomogeneity (or local change)</p><p>120. . . Conductive interconnect material</p><p>1002, 1004, 1006, 1008, 1010, 1012, 1014, 1150, 1152, 1302, 1304, 1306, 1310, 505, 510, 515, 705, 710, 715, 805, 810, 815, 820. . . operate</p><p>1110, 1110A, 1110A', 1110B, 1132, 402. . . Mask layer</p><p>1104, 1140. . . Cushion layer</p><p>1120, 1120'. . . Filler</p><p>1130, 1410, 1412, 1420, 1420'. . . Dielectric layer</p><p>1200, 1200', 1200", 1200'''...area</p><p>1414, 1416. . . Unevenness</p><p>202, 604. . . Extra layer</p><p>204. . . Conformal layer</p><p>606, 606', 606"... outline</p><p>800, 1000, 1006, 1008. . . Method operation</p><p>h, h', h"...thickness (or depth)</p>

FIG. 1 shows a patterned semiconductor substrate according to an embodiment of the invention.

Figure 2 shows an additional layer added in accordance with an embodiment of the present invention.

Figure 3 shows a substantially flat covering portion according to an embodiment of the invention.

FIG. 4A shows a substrate that has undergone a second etching process according to an embodiment of the present invention.

FIG. 4B shows a substrate that has undergone barrier removal processing according to an embodiment of the present invention.

FIG. 5 is a flow chart of the operation of the method for local flattening according to an embodiment of the present invention.

6A to 6D show a series of chemical conversion and etch-back treatments applied to the substrate to improve local uniformity according to an embodiment of the present invention.

FIG. 7 is a flowchart of the method operation of chemical conversion and etch-back processing applied to a substrate to improve local uniformity according to an embodiment of the present invention.

FIG. 8 is a flowchart of the operation of the method for correcting overall unevenness according to an embodiment of the present invention.

Figure 9 shows a substantially removed and flattened cover according to an embodiment of the invention.

Fig. 10 is a flowchart of the method operation according to an embodiment of the present invention.

FIG. 11A shows a patterned and filled semiconductor substrate in a dual damascene process according to an embodiment of the present invention.

FIG. 11B shows a patterned, filled and planarized semiconductor substrate in a dual damascene process according to an embodiment of the present invention.

FIG. 11C shows an etched semiconductor substrate in a dual damascene process according to an embodiment of the present invention.

FIG. 11D shows a semiconductor substrate with a subsequent dielectric layer according to an embodiment of the present invention.

FIG. 11E shows a semiconductor substrate with a mask layer formed above the subsequent dielectric layer according to an embodiment of the present invention.

FIG. 11F shows a semiconductor substrate having features formed in a dielectric layer according to an embodiment of the present invention.

FIG. 11G is a flow chart of the operation of the method for removing the remaining conductive filler material to the expected end point according to an embodiment of the present invention.

12A to 12D show detailed views of the area of the mask layer and the conductive material in various embodiments of the removal-to-terminal processing.

FIG. 13 is a flowchart of the operation of the method for coating a subsequent dielectric layer according to an embodiment of the present invention.

FIG. 14A shows a plurality of dielectric layers constituting a dielectric layer according to an embodiment of the present invention.

FIG. 14B shows the third dielectric layer on the semiconductor substrate according to an embodiment of the present invention.

FIG. 14C shows a planarized third dielectric layer according to an embodiment of the invention.