Ultra low dielectric materials based on hybrid system of linear silicon precursor and organic porogen by plasma-enhanced chemical vapor deposition (PECVD)
Abstract
A method for depositing a low dielectric constant film is provided by reacting a gas mixture including one or more linear, oxygen-free organosilicon compounds, one or more oxygen-free hydrocarbon compounds comprising one ring and one or two carbon-carbon double bonds in the ring, and one or more oxidizing gases. Optionally, the low dielectric constant film is post-treated after it is deposited. In one aspect, the post treatment is an electron beam treatment.
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20 claims: 13 independent, 7 dependent
- 1一種用以沉積一低介電常數膜的方法,其至少包含:在足以沉積一低k膜層於一基材表面上的沉積條件下,傳送一氣體混合物至該基材表面,該氣體混合物包括一或多種直鏈、不含氧的有機矽化物,一或多種不含氧的碳氫化物其係包含一環及一或二個碳-碳雙鍵於該環上,及一或多種氧化氣體。
- 2如申請專利範圍第1項所述之方法,其中該一或多種直鏈、不含氧的有機矽化物包含一烷基矽烷。
- 3如申請專利範圍第1項所述之方法,其中該一或多種直鏈、不含氧的有機矽化物包含選自下列之一成員,包括甲基甲矽烷、二甲基甲矽烷、三甲基甲矽烷、四甲基甲矽烷、乙基甲矽烷、二甲矽烷基甲烷、雙(甲基甲矽烷基)甲烷、1,2-二甲矽烷基乙烷、1,2-雙(甲基甲矽烷基)乙烷、2,2-二甲矽烷基丙烷、二乙基甲矽烷、丙基甲矽烷、乙烯基甲基甲矽烷、1,1,2,2-四甲基乙矽烷(1,1,2,2-tetramethyldisilane)、六甲基乙矽烷(hexamethyldisilane)、1,1,2,3,3-五甲基丙矽烷(1,1,2,2,3,3-pentamethyltrisilane)、1,3-雙(甲基矽甲烷基)丙烷(1,3-bis(methylsilano)propane)、1,2-雙(二甲基矽甲烷基)乙烷(1,2-bis(dimethylsilano)ethane)、1,3-雙(二甲基矽甲烷基)丙烷(1,3-bis(dimethylsilano)propane)及其之組合。
- 4如申請專利範圍第1項所述之方法,其中該環包含5或6個碳原子。
- 5如申請專利範圍第4項所述之方法,其中該環包含6個碳原子。
- 6如申請專利範圍第1項所述之方法,其中該一或多種氧化氣體係選自由臭氧、氧氣、二氧化碳、一氧化碳、水、氧化二氮、2,3-丁二酮及其之組合所構成的群組中。
- 7如申請專利範圍第1項所述之方法,其中該一或多種氧化氣體係由二氧化碳和氧氣所組成。
- 8如申請專利範圍第1項所述之方法,更包含對該低介電常數膜層施以後-處理的步驟。
- 9如申請專利範圍第1項所述之方法,其中該一或多種直鏈、不含氧的有機矽化物包含三甲基甲矽烷且該一或多種不含氧的碳氫化物包含α-萜品烯。
- 10如申請專利範圍第9項所述之方法,其中該一或多種氧化氣體係由二氧化碳和氧氣所組成。
- 11一種用以沉積一低介電常數膜的方法,其至少包含:在足以沉積一低k膜層於一基材表面上的沉積條件下,傳送一氣體混合物至該基材表面,該氣體混合物包括一或多種直鏈、不含氧的有機矽化物,一或多種氧化氣體及一或多種包含下列結構之不含氧的碳氫化物 其中R係由具有1至5個碳原子的直鏈烷基團中選出。
- 12如申請專利範圍第11項所述之方法,其中該一或多種不含氧的碳氫化物包含α-萜品烯。
- 13如申請專利範圍第11項所述之方法,其中該一或多種直鏈、不含氧的有機矽化物包含選自下列之一成員,包括甲基甲矽烷、二甲基甲矽烷、三甲基甲矽烷、四甲基甲矽烷、乙基甲矽烷、二甲矽烷基甲烷、雙(甲基甲矽烷基)甲烷、1,2-二甲矽烷基乙烷、1,2-雙(甲基甲矽烷基)乙烷、2,2-二甲矽烷基丙烷、二乙基甲矽烷、丙基甲矽烷、乙烯基甲基甲矽烷、1,1,2,2-四甲基乙矽烷(1,1,2,2-tetramethyldisilane)、六甲基乙矽烷(hexamethyldisilane)、1,1,2,3,3-五甲基丙矽烷(1,1,2,2,3,3-pentamethyltrisilane)、1,3-雙(甲基矽甲烷基)丙烷(1,3-bis(methylsilano)propane)、1,2-雙(二甲基矽甲烷基)乙烷(1,2-bis(dimethylsilano)ethane)、1,3-雙(二甲基矽甲烷基)丙烷(1,3-bis(dimethylsilano)propane)及其之組合。
- 14如申請專利範圍第11項所述之方法,其中該具有1至5個碳原子的直鏈烷基團係選自由甲基、乙基、丙基及異丙基所組成的群組中。
- 15如申請專利範圍第11項所述之方法,其中該該一或多種氧化氣體係選自由臭氧、氧氣、二氧化碳、一氧化碳、水、氧化二氮、2,3-丁二酮及其之組合所構成的群組中。
- 16如申請專利範圍第11項所述之方法,更包含對該低介電常數膜層施以一電子束處理的步驟。
- 17一種用以沉積一低介電常數膜的方法,其至少包含:在足以沉積一低k膜層於一基材表面上的沉積條件下,傳送一氣體混合物至該基材表面,該氣體混合物包含:一或多種直鏈、不含氧的有機矽化物;一或多種不含氧的碳氫化物其係包含一環及一或二個碳-碳雙鍵於該環上;及一或多種氧化氣體;以一電子束來處理該低介電常數膜層。
- 18如申請專利範圍第17項所述之方法,其中該一或多種直鏈、不含氧的有機矽化物包含選自下列之一成員,包括甲基甲矽烷、二甲基甲矽烷、三甲基甲矽烷、四甲基甲矽烷、乙基甲矽烷、二甲矽烷基甲烷、雙(甲基甲矽烷基)甲烷、1,2-二甲矽烷基乙烷、1,2-雙(甲基甲矽烷基)乙烷、2,2-二甲矽烷基丙烷、二乙基甲矽烷、丙基甲矽烷、乙烯基甲基甲矽烷、1,1,2,2-四甲基乙矽烷(1,1,2,2-tetramethyldisilane)、六甲基乙矽烷(hexamethyldisilane)、1,1,2,3,3-五甲基丙矽烷(1,1,2,2,3,3-pentamethyltrisilane)、1,3-雙(甲基矽甲烷基)丙烷(1,3-bis(methylsilano)propane)、1,2-雙(二甲基矽甲烷基)乙烷(1,2-bis(dimethylsilano)ethane)、1,3-雙(二甲基矽甲烷基)丙烷(1,3-bis(dimethylsilano)propane)及其之組合。
- 19如申請專利範圍第17項所述之方法,其中該一或多種不含氧的碳氫化物包含α-萜品烯。
- 20如申請專利範圍第19項所述之方法,該一或多種直鏈、不含氧的有機矽化物包含三甲基甲矽烷且該一或多種不含氧的碳氫化物包含α-萜品烯。
Independent claims20
85 paragraphs, as filed
Ultra-low-K dielectric material using PECVD linear silicon precursor and organic porogen hybrid system
The embodiment of the present invention generally relates to the manufacture of integrated circuits, and in detail, relates to a method of depositing a dielectric layer on a substrate and a structure including the dielectric layer.
Since semiconductor components were first introduced decades ago, the size of semiconductor components has roughly followed Moore's Law, that is, the rule of reducing a size by half every two years is evolving, that is, the number of components that can be accommodated on a chip is every two. The annual rate of doubling is increasing. At present, manufacturers can routinely produce components of 0.13 micrometers or even 0.1 micrometers, and it is expected that components of smaller sizes will be produced in the future.
In order to further reduce the size of the components on the integrated circuit, low-resistance conductive materials and low-dielectric constant (k) insulating layers must be used to reduce the capacitive coupling between adjacent metal lines. One example of such low-k materials is spin-on glass, for example, undoped silica glass (USG) or fluorine-doped silica glass (FSG), which can be used as a gap fill layer in a semiconductor process. Other examples of low-k materials include carbon-doped silicon dioxide and polytetrafluoroethylene. However, the continuous reduction of component size has also increased the industry's demand for materials with lower k values.
Recently, the research and development of low-k materials has mostly focused on the technology of incorporating silicon, carbon and oxygen atoms into the deposited layer. A challenge in this field is to develop a material with low-k properties, containing silicon, carbon and oxygen atoms, while also exhibiting the desired thermal and mechanical properties. More commonly, a film with a low-k value and composed of a network of silicon, carbon and oxygen atoms usually has very poor mechanical strength and is easily damaged by etching chemicals and subsequent plasma treatments, leading to failure of integrated circuits.
Therefore, there is a need for a method for preparing low-k materials that can improve the speed and efficiency of the components on the integrated circuit, as well as the durability and mechanical strength of the integrated circuit.
The embodiment of the present invention generally relates to a method for depositing a low-k film. In one embodiment, the method of the present invention includes delivering a gas mixture to the surface of a substrate under deposition conditions sufficient to deposit a low-k film layer on the surface of the substrate. The gas mixture includes one or more linear and non-linear materials. Oxygen-containing organosilicon compounds, one or more oxygen-free hydrocarbons which contain a ring and one or two carbon-carbon double bonds on the ring, and one or more oxidizing gases. Alternatively, the low-k film layer is post-treated. In one aspect, the low-k film is post-processed with an electron beam.
In another embodiment, the method for depositing a low-k film layer of the present invention includes delivering a gas mixture to the surface of a substrate under deposition conditions sufficient to deposit a low-k film layer on the surface of the substrate, the The gas mixture includes one or more linear, oxygen-free organosilicon compounds, and one or more oxygen-free hydrocarbons have the following structure:<chemistry general="n"><img file="TW200529250A_D0001.tif" /></chemistry>And one or more oxidizing gases. Alternatively, the low-k film layer is post-treated. In one aspect, the low-k film is post-processed with an electron beam.
The detailed description is disclosed below.
The present invention includes a method for depositing a low-k film including silicon, oxygen, and carbon by allowing one or more linear, oxygen-free organosilicides, one or more oxygen-free Hydrocarbons include a ring and one or two carbon-carbon double bonds on the ring, and one or more oxidizing gases, under conditions sufficient to deposit a pre-treated film network reaction. The film can be deposited in a process chamber capable of forming chemical vapor deposition (CVD) with the help of plasma. The plasma can be generated by a constant radio wave (RF) power, pulsed radio wave, high frequency RF, dual frequency RF, dual phase RF, or any other known or undiscovered plasma generation technology.
After the film is deposited, the film can be subjected to post-treatments, such as curing, which uses an electron beam to remove suspended organic groups, for example, organic groups incorporated into the film network during deposition. The cyclic group of the compound. The step of applying post-treatment to the film layer can add light energy to the film layer network to volatilize and remove at least part of the organic groups, such as the organic cyclic group in the film layer network, and leave a More porous film network with low dielectric constant value. In most cases, compared to the uncured film prepared according to the embodiment, the film cured by electron beam can exhibit at least two times higher, or even six times higher. hardness. The film hardened by electron beam exhibits unexpected decrease in k value and unexpected increase in hardness. Typically, the dielectric constant of the cured film layer is about 2.5 or less, preferably about 2.2 or less, and its hardness is greater than about 0.6 Gpa.
The term "organosilicon compound" here includes silicon-containing compounds with carbon atoms in its organic group. The organic group may include an alkyl group, an alkene group, and a vinyl group and derivative functional groups thereof. Preferably, the organosilicon compound includes one or more carbon atoms connected to a silicon atom, wherein the carbon atoms cannot be easily removed by the oxidation reaction in the process conditions.
Suitable linear, oxygen-free organosilicon compounds include fatty organosilicon compounds, which have a linear or branched structure composed of one or more silicon atoms and one or more carbon atoms. Some examples of linear, oxygen-free organosilicon compounds include: methyl silane CH<sub>3</sub>-SiH<sub>3</sub>Dimethylsilane (CH<sub>3</sub>)<sub>2</sub>-SiH<sub>2</sub>Trimethylsilane (CH<sub>3</sub>)<sub>3</sub>-SiH Tetramethylsilane (CH<sub>3</sub>)<sub>4</sub>-Si Ethyl Silane CH<sub>3</sub>-CH<sub>2</sub>-SiH<sub>3</sub>Dimethylsilylmethane SiH<sub>3</sub>-CH<sub>2</sub>-SiH<sub>3</sub>Bis(methylsilyl)methane CH<sub>3</sub>-SiH<sub>2</sub>-CH<sub>2</sub>-SiH<sub>3</sub>-CH<sub>3</sub>1,2-Dimethylsilylethane SiH<sub>3</sub>-CH<sub>2</sub>-CH<sub>2</sub>-SiH<sub>3</sub>1,2-bis(methylsilyl)ethane CH<sub>3</sub>-SiH<sub>2</sub>-CH<sub>2</sub>-CH<sub>2</sub>-SiH<sub>2</sub>-CH<sub>3</sub>2,2-Dimethylsilylpropane SiH<sub>3</sub>-C(CH<sub>3</sub>)<sub>2</sub>-SiH<sub>3</sub>Diethylsilane (C<sub>2</sub>H<sub>5</sub>)<sub>2</sub>-SiH<sub>2</sub>Propyl silane C<sub>3</sub>H<sub>7</sub>-SiH<sub>3</sub>Vinyl methyl silane (CH<sub>2</sub>=CH)-SiH<sub>2</sub>-CH<sub>3</sub>1,1,2,2-Tetramethylethane (CH<sub>3</sub>)<sub>2</sub>-SiH-SiH-(CH<sub>3</sub>)<sub>2</sub>Hexamethylethane (CH<sub>3</sub>)<sub>3</sub>-Si-Si-(CH<sub>3</sub>)<sub>3</sub>1,1,2,2,3,3-hexamethylpropane (CH<sub>3</sub>)<sub>2</sub>-SiH-Si(CH<sub>3</sub>)<sub>2</sub>-SiH-(CH<sub>3</sub>)<sub>2</sub>1,1,2,3,3-pentamethylpropane (CH<sub>3</sub>)<sub>2</sub>-SiH-SiH(CH<sub>3</sub>)-SiH-(CH<sub>3</sub>)<sub>2</sub>1,3-bis(methylsilyl)propane CH<sub>3</sub>-SiH<sub>2</sub>-CH<sub>2</sub>)<sub>3</sub>-SiH<sub>2</sub>-CH<sub>3</sub>1,2-bis(dimethylsilyl)ethane (CH<sub>3</sub>)<sub>2</sub>-SiH-(CH<sub>2</sub>)<sub>2</sub>-SiH-(CH<sub>3</sub>)<sub>2</sub>1,3-bis(dimethylsilyl)propane (CH<sub>3</sub>)<sub>2</sub>-SiH-(CH<sub>2</sub>)<sub>3</sub>-SiH-(CH<sub>3</sub>)<sub>2</sub>
The one or more linear, oxygen-free organosilicon compounds react with one or more oxygen-free hydrocarbons, the hydrocarbons containing one or more rings and one or two carbon-carbon double bonds On the ring. The ring may only contain 4 carbon atoms. In addition, the ring is preferably bonded to a linear or branched functional group. The linear or branched functional group preferably contains an alkyl group or a vinyl alkyl group and has about 1 to 20 carbon atoms. In a preferred embodiment, the oxygen-free hydrocarbon has the following general formula:<chemistry general="n"><img file="TW200529250A_D0002.tif" /></chemistry>Wherein R is selected from linear alkyl groups having 1 to 5 carbon atoms. In one embodiment, R is a methyl group and the oxygen-free hydrocarbon is a commercially available alpha-terpinene (ATP).
The one or more linear, oxygen-free organosilicon compounds and the one or more oxygen-free hydrocarbons react with one or more oxidizing gases. Suitable oxidizing gases include oxygen (O<sub>2</sub>), ozone (O<sub>3</sub>), nitrous oxide (N<sub>2</sub>O), carbon monoxide (CO), carbon dioxide (CO<sub>2</sub>), water, 2,3-butanedione or a combination thereof.
Alternatively, the low-k film layer is post-treated. In one aspect, the low-k film is post-processed with an electron beam. When ozone is used as the oxidizing gas, an ozone generator can convert 6% to 20%, typically about 15% (weight %) of oxygen in one of the oxygen sources into ozone, and the rest is still oxygen. However, the ozone concentration can be increased or decreased according to the required amount of ozone and the form of the ozone generator used. The oxygen or oxygen-containing compound can be dissociated in a microwave chamber before the gas enters the deposition chamber, thereby reducing the excessive dissociation of the silicon-containing compound. Preferably, a radio wave power is applied to the reaction zone to increase the degree of dissociation.
Alternatively, in addition to the one or more linear, oxygen-free organosilicon compounds, one or more oxygen-free hydrocarbons and one or more oxidizing gases, one or more carrier gases can be introduced into the deposition chamber . Examples of carrier gases that can be used include helium, argon, hydrogen, ethylene, and combinations thereof.
In addition, one or more linear, oxygen-free organosilicon compounds, one or more oxygen-free hydrocarbons and one or more oxidizing gases can also be introduced into the deposition chamber. Oxygen-containing organosilicon compounds. Some examples of oxygen-containing organosilicon compounds include: 1,3,5,7-tetramethylcyclotetrasiloxane (TMCTS)-(SiHCH<sub>3</sub>-O-)<sub>4</sub>-(Cyclic) Octamethylcyclotetrasiloxane (OMCTS) -(Si(CH<sub>3</sub>)<sub>2</sub>-O-)<sub>4</sub>-(Cyclic) 1,3,5,7,9-Pentamethylcyclopentasiloxane-(SiHCH<sub>3</sub>-O-)<sub>5</sub>-(Cyclic) 1,3,5,7-Tetrasiloxane-2,6-Dioxy-4,8-Dimethylene-(SiH<sub>2</sub>-CH<sub>2</sub>-SiH<sub>2</sub>-O-)<sub>2</sub>-(Cyclic) Hexamethylcyclotrisiloxane-(Si(CH<sub>3</sub>)<sub>2</sub>-O-)<sub>3</sub>-(Cyclic) Diethoxymethylsilane (DEMS) CH<sub>3</sub>-SiH-(O-CH<sub>2</sub>-CH<sub>3</sub>)<sub>2</sub>1,3-Dimethyldisiloxane CH<sub>3</sub>-SiH<sub>2</sub>-O-SiH<sub>2</sub>-CH<sub>3</sub>1,1,3,3-Tetramethyldisiloxane (CH<sub>3</sub>)<sub>2</sub>-SiH-O-SiH-(CH<sub>3</sub>)<sub>2</sub>Hexamethyldisiloxane (HMDS) (CH<sub>3</sub>)<sub>3</sub>-Si-O-Si-(CH<sub>3</sub>)<sub>3</sub>1,3-Bis(silylmethylene)disiloxane (SiH<sub>3</sub>-CH<sub>2</sub>-O-SiH<sub>2</sub>-)<sub>2</sub>-CH<sub>2</sub>Bis(1-methyldisiloxyalkyl)methane (CH<sub>3</sub>-SiH<sub>2</sub>-O-SiH<sub>2</sub>-)<sub>2</sub>-CH<sub>2</sub>2,2-bis(1-methyldisiloxyalkyl)propane (CH<sub>3</sub>-SiH<sub>2</sub>-O-SiH<sub>2</sub>-)<sub>2</sub>-C(CH<sub>3</sub>)<sub>2</sub>Hexamethoxydisiloxane (HMDOS) (CH<sub>3</sub>O)<sub>3</sub>-Si-O-Si-(OCH<sub>3</sub>)<sub>3</sub>Dimethyldimethoxysilane (DMDMOS) (CH<sub>3</sub>O)<sub>2</sub>-Si-(CH<sub>3</sub>)<sub>2</sub>Dimethoxymethylvinylsilane (DMMVS) (CH<sub>3</sub>O)<sub>2</sub>-Si-(CH<sub>3</sub>)-CH<sub>2</sub>=CH<sub>3</sub>
Preferably, the carbon content of the deposited film layer is about 5 to about 30 atomic% without calculating hydrogen atoms; for example, it is about 10 to about 30 atomic% after hardening. The carbon content of the deposited film refers to the element analysis of the film structure. The carbon content is represented by the percentage of carbon atoms in the deposited film, which is not included in the number of hydrogen atoms, because the number of hydrogen atoms is very difficult to quantify. For example, a film with an average of one silicon atom, one oxygen atom, one carbon atom, and two hydrogen atoms has a carbon content of 20 at% (one carbon atom in every 5 atoms) or does not count A hydrogen atom has a carbon content of 330 at% (one out of every 3 atoms is a carbon atom).
During deposition, the substrate is typically maintained at a temperature of about 25°C to about 350°C. For a substrate of about 300 mm, a typical power density of about 0.07 watts/cm² to about 2.8 watts/cm² is used, which is an RF power between about 50 watts and about 2000 watts. Preferably, the RF power is between about 100 watts and about 1500 watts. The RF power is provided at a frequency of about 0.01 MHz to about 300 MHz. The RF power can be cyclic or pulsed to reduce heating of the substrate and promote the porosity of the deposited film. The RF power can be continuous or discontinuous.
In one aspect of the present invention, the one or more linear, oxygen-free organosilicon compounds have a flow rate of about 100 sccm to about 2,000 sccm, for example, a flow rate of about 300 sccm to about 2,000 sccm, preferably about A flow rate of 1,000 sccm was introduced into a chemical vapor deposition chamber. The one or more oxygen-free hydrocarbons are introduced into a chemical gas phase at a flow rate of about 100 sccm to about 5,000 sccm, for example, a flow rate of about 500 sccm to about 5,000 sccm, preferably a flow rate of about 3,000 sccm In the deposition chamber. Preferably, the flow rate ratio of the oxygen-free organosilicon compound to the oxygen-free hydrocarbon is about 1:3. The flow rate of the one or more oxidizing gases is between about 50 sccm to about 5,000 sccm, for example, a flow rate of about 100 sccm to about 1,000 sccm, preferably a flow rate of about 200 sccm. The flow rate of the one or more optionally added carrier gases is between about 500 sccm and about 5,000 sccm. Preferably, the linear, oxygen-free organosilicon compound is trimethylsilane, the oxygen-free hydrocarbon is α-terpinene, and the oxidizing gas is oxygen and mixed therein carbon dioxide.
Preferably, after depositing the low-k film layer, post-treatment is applied to the film layer. The post-treatment can be performed by thermal or plasma enhanced hardening process or electron beam. In one embodiment, the film layer is cured at a temperature of about 2000° C. to about 400° C. for about 2 hours to about 1 hour, preferably about 30 minutes. A gas such as helium, hydrogen hydrogen, nitrogen or a mixture thereof is introduced at a rate of about 100 sccm to about 10,000 sccm. The pressure of the process chamber is maintained between about 2 torr and about 10 torr. During curing, the RF power is about 200 watts to about 1,000 watts, the frequency is about 13.56 MHz, and the preferred substrate spacing is about 300 mils to about 800 mils. After depositing the low-k film layer, the film layer is hardened at a temperature of about 200° C. to about 400° C. to volatilize at least part of the organic groups on the film layer to form pores in the film layer. The organic group that can be volatilized is derived from the organic composition in the gas mixture, such as the one or more oxygen-free hydrocarbons, which include a ring and one or two carbons located on the ring- Carbon double bond.
In another embodiment, the low-k film is post-processed with electron beam. The typical dose of the electron beam in the electron beam processing is about 50 microcoulombs/cm² (μc/cm<sup>2</sup>) To about 2000 microcoulombs/cm². The electron beam treatment is typically performed at a temperature of about room temperature to about 450° C. for about 1 minute to about 15 minutes, for example, about 2 minutes. Preferably, the electron beam treatment is performed at a temperature of about 400°C for about 2 minutes. In one aspect, the conditions of the electron beam treatment include 4.5KV, 1.5mA and 150 μc/cm at 400°C<sup>2</sup>. Although any electron beam device can be used, the exemplified device is an EBK chamber sold by American Applied Materials.
The electron beam hardening process can improve the mechanical strength of the deposited film network while reducing the k value. The excited electron beam can change the chemical bonds in the molecular network of the deposited film and remove at least part of the molecular groups. The organic composition on the ring of oxygen hydrocarbons. The action of removing molecular groups creates pores in the film and lowers the k value. The electron beam treatment can also strengthen the network structure of the film layer by cross-linking between Si-O-Si and Si-C-Si, which can be confirmed by FTIR spectroscopy analysis.
An example of a process chamber for depositing a low-k film is disclosed below.
<b>Illustrated CVD reactor</b>
FIG. 1 shows a vertical, cross-sectional view of a parallel plate-shaped chemical vapor deposition chamber 10 with a high vacuum zone 15. The process chamber 10 includes a gas distribution manifold 11 with holes for dispersing the process gas so as to pass therethrough and reach a substrate. The substrate is placed on a substrate support plate or receiving plate 12. The supporting plate 12 is erected on a supporting column 13 for connecting the supporting plate 12 to a lifting motor 14. The lifting motor 14 can raise or lower the receiving plate 12 between a processing position and a lower substrate bearing position, so that the receiving plate 12 (and the substrate is supported on the upper surface of the receiving plate 12) Move in a controllable manner between a lower loading/unloading position and a higher processing position near the manifold 11. When the receiving plate 12 and the substrate are at a higher processing position, they are surrounded by an insulator 17.
During the treatment, the gas system introduced into the manifold 11 is uniformly distributed radially across the surface of the substrate. The vacuum pump 32 with a throttle valve can control the exhaust rate of the gas from the manifold 24 in the self-control chamber. The deposition gas and the carrier gas flow through the gas line 18 into a mixing system 19 and then into the manifold 11. Roughly speaking, each process gas supply line 18 includes (i) a safety shut-off valve (not shown), which is used to automatically or manually close the process gas so as not to flow into the process chamber, and (ii) a flow controller (not shown) (Shown), which is used to measure the flow of gas through the gas supply line. When toxic gas is used in the process, several safety shut-off valves are set on each process gas supply line 18.
The deposition process is performed in the process chamber 10, and it can be a thermal process or a plasma enhancement process. In the plasma process, an RF power supply 25 is typically applied to the gas distribution manifold 11 to form a controlled plasma near the substrate. Alternatively, the RF power can be provided on the receiving board 12 or the RF power can be provided to different components at different frequencies. The RF power supply 25 can provide single-frequency or mixed-frequency RF power to enhance the deposition of reactive species introduced into the high vacuum zone 15. A mixed RF power supply can typically supply power to the distribution manifold 11 at a high RF frequency (RF1) of 13.56 MHz, and provide power to the receiving board 12 at a low RF frequency (RF2) of 360 KHz .
When the oxidizing gas needs to be further dissociated, a microwave chamber 28 can be used to input about 0 watts to about 6000 watts of electricity to the oxidizing gas before the gas enters the process chamber. Using the additional microwave power on the oxidizing gas can prevent the organosilicon compound from being excessively dissociated before reacting with the oxidizing gas.
Typically, any or all of the process chamber liner, the manifold 11, the receiving plate 12, and various other reactor hardware are made of materials such as aluminum or anodized aluminum. An example of this type of CVD reactor is disclosed in U.S. Patent No. 5,000,113 by Wang et al., entitled "A Thermal CVD/PECVD Reactor and Use for Thermal Chemical Vapor Deposition of Silicon Dioxide and<i>In-situ</i>Multi-step Planarized Process", the full text of which is incorporated here as a reference. The processing system 10 can be integrated into an integrated process platform, such as the Producer produced by American Applied Materials.<img file="TW200529250A_D0003.tif" />platform. The Producer<img file="TW200529250A_D0004.tif" />The detailed content of the platform is disclosed in US Patent No. 5,855,681 of Maydan et al., which is owned by the co-assignee of this application, entitled "Ultra High Throughput Wafer Vaccum Processing System", the full text of which is incorporated herein by reference.
A system controller 34 can control the lift motor 14, the gas mixing system 19, and the RF power supply, which is connected to each of the above by a control line 36. The system controller 34 can control the activities of the CVD reactor and typically includes a hard disk, a floppy disk and a card rack. The card holder contains a single board computer (SBC), analog and digital input/output boards, interface boards and stepper motor controller boards. The system controller 34 conforms to the Versa Modular Eupoeans (VME) standard that is specifically used to define the size and type of boards, card holders, and connectors. The VME standard also defines a bus structure with a 16-bit data bus and a 24-bit address bus.
Figure 2 shows a flow chart of the hierarchical control structure of a computer program product used in the CVD reactor illustrated in Figure 1. The system controller 34 is operated under the control of a computer program 410, and the computer program 410 is stored on the hard disk 38. The computer program can indicate a specific production time, gas mixture, RF power, receiving board position, and other process parameters. The computer program code can be written in any conventional computer-readable programming language, such as 68000 assembly language, C, C++, or Pascal. Appropriate computer code is input into a single file or multiple files with a conventional text editor, and stored or embedded in a computer usable medium, such as a memory system of the computer. If the input code text is a high-level language, the code is compiled, and then the obtained compiled code is linked with the object code of a pre-compiled window database routine. In order to execute the linked compiled object code, the system user will activate the object code and activate the computer system to load the code stored in the memory. After the CPU reads the code, it will execute all the codes in the program. Defined work.
Referring again to Figure 2, a user will input a process group number and a process room number into a process selector subroutine 420 in response to the menu activated by the light pen interface displayed on the CRT monitor. The process selector subroutine 420(i) is from a tool cluster (for example, Centura<img file="TW200529250A_D0005.tif" />Platform) select a desired process room; and (ii) select a set of process parameters that can operate the process room to execute the desired process. The process parameters used to perform a specific process are provided to the user in the form of a recipe, and they are related to reaction conditions such as process gas composition, flow rate, temperature, pressure, etc., such as the level of RF bias power and magnetic field power. The plasma conditions, cooling gas pressure and process chamber wall temperature. The parameters specified by the recipe are input through the light pen/CRT monitor interface. The signal used to monitor the process is provided by the analog and digital input board of the system controller 34, and the signal used to control the process is output to the analog and digital input board of the system controller 34.
A process sequence routine 430 includes a program code used to receive a process room and a process parameter group specified by the process selector subroutine 420, and a program code used to control the operation of each process room. Multiple users can input multiple process group numbers and multiple process room numbers, or according to the user can input multiple process room numbers, so that the sorting routine 430 can arrange the order of the selected processes in a desired manner. Preferably, the sequence routine 430 includes computer-readable program codes for performing the following steps: (i) monitoring the operation of the process room to determine whether the process room is used; (ii) determining the process that is being used Which process should be executed by the room; and (iii) According to the currently available situation of the process room and the type of process to be executed, execute the desired process. It is possible to use conventional methods for monitoring process rooms, such as sampling surveys. When sorting processes, the sorting subroutine 430 can be specified to take into consideration the conditions of the currently used process room and compare it with the desired process conditions of a selected custom process, or the time required by the user for each input History, or related factors that any system programmer wants to include to determine the sort order.
Once the sequencing subroutine 430 determines the combination of the process room and the process group to be executed next, the sequencing subroutine 430 will pass the specific process group parameters to a process room management subroutine 440. To activate the execution of the process, the process room management routine 440 can control multiple tasks in a process room according to the process determined by the sequence routine 430. For example, the process room management routine 440 includes program codes for controlling the operation of the CVD process in the process room 10. The process room management subroutine 440 can also control the execution of various process room component subroutines, and the process room component subroutines can control the operation of the process room components necessary to execute the customized process. Examples of the process chamber component sub-routines include the receiving board control sub-routine 450, the process gas control sub-routine 460, the pressure control sub-routine 470, the heater control sub-routine 480, and the plasma control sub-routine 490 . Those skilled in the art should be able to easily understand and can also incorporate it into other process room control routines as needed (for example, which process should be executed in a process room, etc.).
During operation, the process room management routine 440 will specifically sort or call the process component routines according to the specific process group to be executed. The process room management subroutine 440 arranges the process component subroutines in a manner similar to the ordering subroutine 430 for the process rooms and process groups to be executed next. Typically, the process room management routine 440 includes the following steps: monitor various process room components, determine which component will be operated according to the process parameters of the process group to be executed, and activate the process room component routines The implementation of the response to the monitoring and decision steps.
The sub-routine operations of specific process chamber components will be described in detail with reference to Fig. 2 as follows. The supporting board control position sub-routine 450 includes controlling the loading of the substrate onto the supporting board 12 and selectively lifting the substrate to a desired height in the process chamber 10 to control the substrate and the gas dispersion manifold. The code of the process room assembly of the distance between the tubes 11. When a substrate is loaded into the process chamber 10, the receiving plate 12 is lowered to receive the substrate, and then the receiving plate 12 is raised to the desired height in the process chamber to maintain the substrate during the CVD process There is a first distance or distance from the gas distribution manifold 11. During operation, the receiving board control subroutine 450 can control the movement of the receiving board 12 in response to the process group parameters sent by the process room management subroutine 440.
The process gas control subroutine 460 includes code for controlling the composition and flow rate of the process gas. The process gas control subroutine 460 can control the on/off position of the safety shut-off valve, and can also adjust the flow controller up/down to obtain a desired gas flow rate. The process gas control subroutine 460 is activated by the process room management subroutine 440, and all other process room component subroutines are the same. And can receive the process parameters about the desired process gas flow rate from the process room management routine. Typically, the process gas control routine 460 operates by opening the gas supply line and repeating the following steps: (i) reading the necessary mass flow controller, (ii) connecting the renewal value and management from the process room Compare the desired flow rate received by the subroutine 440, and (iii) adjust the flow rate of the gas supply line if necessary. In addition, the process gas control routine 460 also includes the following steps: monitoring the unsafe gas flow rate, and activating the safety valve when an unsafe condition is detected.
In some processes, an inert gas such as helium or argon is introduced into the process chamber 10 before the reactive process gas is introduced to stabilize the pressure in the process chamber. For these processes, the process gas control routine 460 is programmed to perform the steps of flowing inert gas into the process chamber 10 for a period of time to stabilize the pressure of the process chamber, after which the aforementioned steps can be performed. In addition, when the process gas system is volatilized from a precursor liquid, the process gas control routine 460 can be written to include passing a carrier gas such as helium from a venting component to the precursor. Stylization of liquid steps. For such steps, the process gas control routine 460 can adjust the flow rate, ventilation pressure, and ventilation temperature of the carrier gas so as to maintain the process gas flow rate within a desired range. As mentioned above, the desired process gas flow rate is sent to the process gas control subroutine 460 for use as a process parameter. In addition, the process gas control routine 460 also includes the steps of obtaining the necessary carrier gas flow rate, ventilation pressure, and ventilation temperature for the desired process gas flow rate by accessing a storage table containing a gas flow rate value necessary for the customized process. . Once the necessary values are obtained, the flow rate, ventilation pressure and ventilation temperature of the carrier gas can be monitored and adjusted according to the obtained values.
The pressure control subroutine 470 includes a program code that can control the pressure of the process chamber 10, which controls the pressure by adjusting the opening of the throttle valve of the exhaust pump 32. The opening size of the throttle valve can be relative to the total process gas flow, the volume of the process chamber, and the set point pressure of the exhaust pump 32 to control the process chamber pressure to a desired range. When the pressure control routine 470 is activated, the desired target pressure value will be received from the process room management routine 440 as a parameter. The pressure control subroutine 470 can be operated to measure the pressure in the process chamber 10 by reading the value on a conventional pressure gauge connected to the process chamber, and then comparing it with the target value, from the value corresponding to the target pressure value. Obtain a PID value (proportional, complete pressure and partial pressure) on the pressure storage table, and adjust the throttle valve according to the PID value. Alternatively, the pressure control routine 470 can be written into a program code that can open or close the throttle valve to a specific opening size to adjust the pressure of the process chamber 10 to a desired range.
The heater control subroutine 480 includes a program code for controlling the temperature of the heating module or radiant heat that can heat the receiving board 12. The heater control subroutine 480 may also be activated by the process room management subroutine 440 and receive a target value or a set value of the temperature parameter. The heater control sub-normal 480 can measure the temperature by measuring the output potential of a thermocouple on the receiving board 12 and comparing it with a temperature setting value, and then increasing or decreasing the temperature applied to the thermal module. Current to obtain the set temperature value. The temperature can be calculated from the measured potential by looking at the corresponding temperature on a storage conversion table, or the temperature can be calculated by a multivariate quartic equation. The heater control subroutine 480 can gradually control the current applied to the heating module by adjusting up/down. The upward/downward adjustment step by step can increase the life of the heating module and its reliability. In addition, a built-in fail-safe mode can be introduced to detect whether the process meets the safety setting, and the heating module can be turned off when the process chamber 10 is not properly operated.
The plasma control routine 490 includes a code for setting the level of the RF bias potential applied to the process electrode in the process chamber 10, and can optionally set the magnitude of the magnetic field generated by the reactor. Similar to the aforementioned process chamber component subroutine, the plasma control subroutine 490 can also be activated by the process chamber management subroutine 440.
The method for depositing a low-k film layer of the present invention is not limited to be implemented on any specific equipment, nor is it limited to be implemented by any specific plasma excitation method. The above description of the CVD system is for illustrative purposes only, and other CVD equipment can also be used, such as electron cyclotron resonance (ECR) plasma CVD equipment, induced-coupled RF high-density plasma CVD equipment, and so on. In addition, various changes can also be made to the above system, such as changing the design of the receiving plate, the design of the heater, and the location of the RF power connection. For example, a resistively heated receiving plate can be used to support and heat a substrate.
<b>Invention description of low dielectric constant film (low-k film)</b>
Figure 3 shows an embedding structure with a low-k film of the present invention deposited thereon. The low-k film layer is deposited on a dielectric liner layer or barrier layer 312 with a dielectric layer 314. A cap layer 316 is deposited on the dielectric layer 314. The cap layer 316 is used as an etch stop layer or as a liner layer during subsequent substrate processing. The cap layer 316, the dielectric layer 314, and the dielectric pad layer or barrier layer 312 are patterned and etched to define the opening of the interconnection 317, for example, to expose the etched line of the conductive feature 310 thereunder. A conductive liner layer/barrier layer 318 is deposited in the interconnection 317, and a conductive material 320 is deposited thereon to fill the interconnection 317. The substrate is typically flattened as shown after deposition.
4A-4C are schematic cross-sectional views of a substrate 300 having a low-k film layer of the present invention deposited thereon. As shown in FIG. 4A, a low-k dielectric layer 314 is approximately 5,000<img file="TW200529250A_D0006.tif" />To about 10,000<img file="TW200529250A_D0007.tif" />The thickness of (depending on the size of the structure to be manufactured) is deposited on the liner layer or barrier layer 312. The liner layer or barrier layer 312 may be a silicon carbide layer, for example, a plasma obtained from an alkyl silane by PECVD using an inert gas. The silicon carbide layer can be doped with oxygen or nitrogen. The liner layer or barrier layer 312 may also include other materials, such as silicon nitride, which can oxidize and or otherwise include conductive materials (such as copper, which may also include conductive features 300 previously formed on the substrate 300). Diffusion is minimized.
After that, the cap layer 316 (which may be a silicon carbide layer with a low-k value) is deposited on the dielectric layer 314 by a reaction between trimethylsilane, with a thickness of about 200<img file="TW200529250A_D0008.tif" />Up to about 1000<img file="TW200529250A_D0009.tif" />, For a 200mm wafer, the RF power used is between 10 watts and 1000 watts. The silicon carbide material can also be doped with oxygen or nitrogen.
As shown in 4B, the cap layer 316, the dielectric layer 314, and the liner layer or barrier layer 312 are patterned to define interconnects 317 and expose the conductive features 310 on the substrate 300. Preferably, the cap layer 316, the dielectric layer 314, and the liner layer or barrier layer 312 are patterned by conventional photolithographic etching methods and silicon carbide layer etching methods. Any photoresist or other materials used to pattern the cap layer 316 are removed by oxygen stripping or other appropriate methods.
After the deposited material is etched and the photoresist material is removed, a reactive pre-clean process can be used to process the exposed portions of the cap layer 316, the dielectric layer 314, and the liner layer or barrier layer 312 to remove Any contaminants, material particles, residues and oxides that may be formed on the surface of the upper substrate on the exposed surface of the interconnection 317 are removed. The reactive pre-cleaning process involves exposing the substrate to a plasma. The plasma preferably contains hydrogen, argon, helium, nitrogen, or a mixture thereof. For a 200 mm wafer, the The current density is between 0.03 watts/cm² to 3.2 watts/cm², or at least about 10 watts to 100 watts. During the reactive pre-cleaning process, the process chamber is maintained at a pressure of about 20 ears or lower, and the substrate temperature is about 450° C. or lower.
4C, after etching the cap layer 316, the dielectric layer 314, and the liner layer or barrier layer 312 to define the interconnection 317 and the photoresist is removed, a conductive material 320 is used to fill the Inner line 317. The structure is preferably filled with a conductive material such as aluminum, copper, tungsten or a combination thereof. The current trend is to use copper to form smaller features, due to the lower resistance of copper (1.7Ω-cm vs. 3.1Ω-cm for aluminum).
Preferably, the conductive resistance barrier layer 318 is first conformally deposited on the interconnection 317 to prevent copper from migrating into the surrounding silicon and/or dielectric materials. The barrier layer includes titanium, titanium nitride, tantalum, tantalum nitride, and combinations thereof, and other conventional barrier layer materials. After that, copper 320 is deposited by chemical vapor deposition, physical vapor deposition, electroplating, or a combination thereof to form the conductive structure. Once the structure has been filled with copper or other conductive materials, the surface can be planarized by chemical mechanical polishing to produce the final embedded structure as shown in Figure 3.
FIG. 5 shows a double-insertion structure including two low-k film layers and two silicon carbide cap layers or doped silicon carbide cap layers deposited thereon. A conductive feature 502 is formed on the substrate 500. The first low-k film layer is deposited on a pad or barrier layer 512 in the form of a first dielectric layer 510, for example, a silicon carbide layer. A first silicon carbide cap layer 514 is deposited on the first dielectric layer 510. The silicon carbide cap layer 514 can reduce the dielectric constant of the low-k film layer, and it is patterned and etched to define openings for vertical interconnects (such as contact holes/vias). For dual embedded engraving applications, a second dielectric layer 518 including the second low-k film layer is deposited on the patterned silicon carbide cap layer 514. The second silicon carbide cap layer 519 is deposited on the second dielectric layer 518 and it is patterned and etched to define horizontal internal lines (for example, contact lines). And before filling the interconnection with a conductive material, an etching process is performed to define the horizontal interconnection down to the first silicon carbide cap layer 514 that can be used as an etching stop layer, and define the vertical The interconnection and the conductive features 502 on the substrate 500 are exposed.
The preferred method for preparing a double embedding structure shown in Figure 5 is shown in Figures 6A-6G, which is a cross-section of the substrate on which the low-k film of the present invention is depositedFace map. Face map. Face map. As shown in FIG. 6A, an initial first dielectric layer 510 of the low-k film layer is deposited on the liner or barrier layer 512 to a value between about 5,000<img file="TW200529250A_D0010.tif" />To about 10,000<img file="TW200529250A_D0011.tif" />The thickness depends on the size of the structure to be manufactured. The liner layer 512 may be a silicon carbide film, and may be doped with oxygen or nitrogen. The liner/barrier layer 512 may also include other materials, such as silicon nitride, to minimize oxidation and/or diffusion of conductive materials such as copper. The conductive material may include previously formed on the substrate 500.Onconductive feature 502.
As shown in Figure 6B, for a 200 mm substrate, the RF power that can range from about 10 watts to about 1000 watts will include the first cap of a silicon carbide layer or a silicon carbide layer containing dopants. The layer 514 is deposited on the first dielectric layer with a thickness of about 200<img file="TW200529250A_D0012.tif" />Up to about 1000<img file="TW200529250A_D0013.tif" />. Afterwards, pattern etching is applied to the first cap layer 514 to define the contact/via opening 516, and to expose the first dielectric layer 510 located in the desired contact/via region, such as As shown in Figure 6C. Preferably, the first cap layer 514 is patterned and etched by a conventional photolithographic etching process and silicon carbide film etching method.
After the first cap layer 514 is etched to pattern the contact/via 516 and the photoresist is removed, as with the aforementioned first dielectric layer 510, a thickness of about 5,000 is deposited on the first cap layer 514<img file="TW200529250A_D0014.tif" />To about 10,000<img file="TW200529250A_D0015.tif" />The second dielectric layer 518 is as shown in FIG. 6D.
The second cap layer 519 including a silicon carbide layer or a silicon carbide layer containing dopants is deposited on the second dielectric layer 518 with a thickness of about 200<img file="TW200529250A_D0016.tif" />Up to about 1000<img file="TW200529250A_D0017.tif" />. The silicon carbide material can be doped with oxygen or nitrogen. Then, a patterned etching is applied to the second cap layer 519 to define a line 520 as shown in FIG. 6E. Afterwards, the line 520 and the contact/via 521 are etched by reactive ion etching or other anisotropic etching techniques to define the metallization structure (that is, the opening of the line and the contact/via), and The conductive feature 520 is exposed, as shown in Figure 6F. Oxygen stripping or other suitable processes can be used to remove the photoresist 522 and other materials used to pattern and etch the second cap layer 519.
After etching the deposition material and removing the photoresist material, the second cap layer 519, the second dielectric layer 518, the first cap layer 514, and the first dielectric layer can be processed by one of the above-mentioned reactive pre-cleaning processes. The exposed portion of the electrical layer 510 and the pad or barrier layer 512 to remove the contamination that may be formed on the exposed portion of the contact/via opening 516, the pad opening 520, and the conductive feature 502 Substances, particulate matter and oxides.
Then, a conductive material such as aluminum, copper, tungsten or a combination thereof is used to form the metalized structure. The current trend is to use copper to form small features because of the low resistance of copper (1.7Ω-cm vs. 3.1Ω-cm for aluminum). Preferably, as shown in FIG. 6G, a resistive barrier layer 524 is first conformally deposited in the metal scribe pattern to prevent copper from migrating into the surrounding silicon and/or dielectric materials. The barrier layer includes titanium, titanium nitride, tantalum, tantalum nitride, and combinations thereof, and other conventional barrier layer materials. Thereafter, copper 526 is deposited by chemical vapor deposition, physical vapor deposition, electroplating, or a combination thereof to form the conductive structure. Once the structure has been filled with copper or other conductive materials, the surface can be planarized by chemical mechanical polishing to produce the final embedded structure as shown in Figure 5.
These processing steps are preferably integrated on a processing platform to avoid contamination of the substrate. An example of the processing tool of accumulation is ENDURA sold by American Applied Materials.<img file="TW200529250A_D0018.tif" />platform. Figure 7 is an example of a system 700 with multiple process chambers (for example, ENDURA<img file="TW200529250A_D0019.tif" />The floor plan of the platform. A similar multiple process chamber processing system is disclosed in US Patent No. 5,186,718, issued on February 16, 1993, under the title "Stage Vaccum Wafer Processing System and Method", the full text of which is incorporated herein by reference.
The system 700 generally includes load lock chambers 702 and 704 for transporting substrates in and out of the system 700. Since the system 700 is generally in a vacuum state, the load lock chambers 702 and 704 can adjust the pressure of the substrate introduced into the system 700 downward. A first robot 710 can transfer substrates between the load lock chambers 702, 704 and a first set of one or more substrate processing chambers 712, 714, 716, 718 (four shown). Each substrate processing chamber 712, 714, 716, 718 can be set to perform several substrate processing operations, such as cyclic deposition of different or the same deposition layer, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, Degassing, positioning and other substrate processing. The first robot 710 can also transfer substrates between one or more transfer chambers 722 and 724. A second robot 730 can transfer substrates between the transfer chambers 722, 724 and a second set of one or more substrate processing chambers 732, 734, 736, 738. Similar to the substrate processing chambers 712, 714, 716, 718, the processing chambers 732, 734, 736, 738 can also be set to perform several substrate processing operations, such as cyclic deposition of different or the same deposition layer, chemical vapor Deposition, physical vapor deposition, etching, pre-cleaning, degassing, positioning and other substrate processing. If a certain substrate processing chamber is not required for a specific process to be executed on the system 700, any of the processing chambers 712, 714, 716, 718, 732, 734, 736, 738 can also be moved from the system 700. remove.
In one aspect, each processing chamber 732 and 738 may be a cyclic deposition chamber for depositing a crystal nucleus layer; each processing chamber 734 and 736 may be a cyclic deposition chamber suitable for forming a bulk filled deposition layer , Chemical vapor deposition chamber, physical vapor deposition chamber; each processing chamber 712 and 714 can be a cyclic deposition chamber suitable for depositing a dielectric layer as described above or a chemical vapor deposition chamber; and each processing chamber 716 and 718 may be an etching chamber suitable for etching interconnection holes or openings. The specific configuration of the system 700 is only for reference and used to illustrate the present invention, and is not used to limit the scope of the present invention.
The following examples illustrate the low dielectric constant film of the present invention. These layers are made of a Producer<img file="TW200529250A_D0020.tif" />A chemical vapor deposition chamber such as the DxZ system is deposited on a 300 mm substrate. The Producer<img file="TW200529250A_D0021.tif" />Each chemical vapor deposition chamber of the DxZ system has two processing areas, and the system is a product of American Applied Materials.
<u style="single">Example 1</u>
A low dielectric constant film was deposited on a 300 mm substrate under a pressure of about 8 ears and a substrate temperature of about 225°C. The process gas used and its flow rate are as follows: Trimethylsilane (TMS) 1,000 sccm α-terpinene (ATP) 3,000 mgm Oxygen 200 sccm Helium 1,500 sccm
The substrate and the gas distribution showerhead are separated by about 300 mils (mils). 13.56MHz, 600 watts of power was applied to the nozzle to perform the plasma enhanced deposition process of the film. The film is about 1,000<img file="TW200529250A_D0022.tif" />/Min rate of deposition. At 400°C, use 4.5KeV, 1.5 mA, and the dose is about 150μc/cm<sup>2</sup>The high temperature electron beam treatment (e-treatment) is used to process the deposited film. This e-treatment lasts about 4 minutes. After e-treatment, measured with SSM 5100 Hg CV measuring tool at 0.1MHz, the dielectric constant of the film is about 2.5. The refractive index of the film is about 1.35.
<u style="single">Example 2</u>
A low dielectric constant film is deposited on a substrate at a pressure of about 8 ears and a substrate temperature of about 225°C. The process gases used and their flow rates are as follows: α-terpinene (ATP) 3,000 mgm Trimethylsilane (TMS) 500 sccm Diethoxymethylsilane 600 mgm (DEMS) Oxygen 100 sccm Carbon dioxide 1,500 sccm
The substrate and the gas distribution showerhead are separated by about 300 mils (mils). 13.56 MHz, 600 watts of power was applied to the nozzle to perform the plasma enhanced deposition process of the film. The film layer is about 2,000<img file="TW200529250A_D0023.tif" />Deposition rate per minute, measured with SSM5100 Hg CV measuring tool at 0.1MHz, the dielectric constant of the film is about 4.3. The hardness of the film is about 0.1 GPa.
<u style="single">E-BEAM of 400°C, 200μc/cm2</u>
At 400°C, use 4.5KeV, 1.5 mA, and the dose is about 200μc/cm<sup>2</sup>The high temperature electron beam treatment (e-treatment) is used to process the deposited film. This e-treatment lasts about 30 seconds. After e-treatment, measured with SSM 5100 Hg CV measuring tool at 0.1MHz, the dielectric constant of the film is about 2.2, which is about 50% lower than that of the uncured film. The hardness of the film is about 0.7 Gpa, which is about 600% more than the uncured film.
<u style="single">Example 3</u>
A low dielectric constant film is deposited on a substrate under a pressure of about 8 ears and a substrate temperature of about 225°C. The process gases used and their flow rates are as follows: α-terpinene (ATP) 4,000 mgm trimethylsilane (TMS) 1,000 sccm octamethylcyclotetrasiloxane 200 mgm (OMCTS) oxygen 100 sccm carbon dioxide 1,500 sccm
The substrate and the gas distribution showerhead are separated by about 300 mils (mils). 13.56MHz, 500 watts of power is applied to the nozzle to perform the plasma enhanced deposition process of the film. The film is about 1,600<img file="TW200529250A_D0024.tif" />It is deposited at a rate of 1/min, measured with SSM5100 Hg CV measuring tool at 0.1 MHz, and the dielectric constant of the film is about 4.5. The hardness of the film is about 0.1 GPa.
<u style="single">E-BEAM of 400°C, 200μc/cm2</u>
At 400°C, use 4.5KeV, 1.5mA, and the dose is about 200μc/cm<sup>2</sup>The high temperature electron beam treatment (e-treatment) is used to process the deposited film. This e-treatment lasts about 30 seconds. After e-treatment, measured with SSM 5100 Hg CV measuring tool at 0.1MHz, the dielectric constant of the film is about 2.3, which is about 50% lower than that of the uncured film. The hardness of the film is about 0.7 Gpa, which is about 600% more than the uncured film.
Although the present invention has been described in detail with the preferred embodiments, those skilled in the art should be able to understand that the present invention has many changes, which still belong to the scope of the accompanying patent application.
<p>10. . . Chemical vapor deposition chamber</p><p>11. . . Gas distribution manifold</p><p>12. . . Undertake board</p><p>13. . . Support column</p><p>14. . . Lifting motor</p><p>15. . . High vacuum zone</p><p>17. . . Insulator</p><p>18. . . Gas pipeline</p><p>19. . . Hybrid system</p><p>twenty four. . . Manifold</p><p>25. . . RF power supply</p><p>28. . . Microwave room</p><p>32. . . Vacuum pump</p><p>34. . . System controller</p><p>36. . . Control line</p><p>38. . . Hard drive</p><p>300. . . Substrate</p><p>310. . . Conductive characteristics</p><p>312. . . Barrier layer</p><p>314. . . Dielectric layer</p><p>316. . . Cap layer</p><p>317. . . Inline</p><p>318. . . Conductive liner layer/barrier layer</p><p>320. . . Conductive material (copper)</p><p>410. . . Computer program</p><p>420. . . Process selector subroutine</p><p>430. . . Process sequencing subroutine</p><p>440. . . Process room management subroutine</p><p>450. . . Undertake board control sub-routine</p><p>460. . . Process gas control sub-routine</p><p>470. . . Pressure control subnormal</p><p>480. . . Heater control sub-normal</p><p>490. . . Plasma control subroutine</p><p>500. . . Substrate</p><p>502. . . Conductive characteristics</p><p>510. . . First dielectric layer</p><p>512. . . Cushion layer/barrier layer</p><p>514. . . First cap</p><p>518. . . Second dielectric layer</p><p>519. . . Second cap</p><p>522. . . Photoresist</p><p>524. . . Conductive resistance barrier</p><p>526. . . Conductive material (copper)</p><p>700. . . System with multiple process chambers</p><p>702, 704. . . Load lock room</p><p>710. . . First robot</p><p>712, 714, 716, 718, 732, 734, 736, 738. . . Substrate processing room</p><p>722, 724. . . Transfer room</p><p>730. . . Second robot</p>
Figure 1 shows a cross-sectional view of a CVD reactor set up in accordance with an embodiment of the present invention.
Figure 2 shows a flow chart of the hierarchical control structure of a computer program product used in the CVD reactor illustrated in Figure 1.
Figure 3 shows an embedding structure with a low-k film of the present invention deposited thereon.
Figures 4A-4C show a cross-sectional view of an embedding deposition embodiment.
FIG. 5 shows a double-insertion structure including two low-k film layers and two silicon carbide cap layers or doped silicon carbide cap layers deposited thereon.
Figures 6A-6G show a cross-sectional view of a dual embedding deposition embodiment.
Figure 7 shows an example of an integrated processing platform.
31 members in 7 offices
Priority claims2
| Document | Office | Kind | Date |
|---|---|---|---|
| 10773060 | United States of America | – | |
| 77306004 | United States of America | A |
Members31
| Document | Office | Kind | |
|---|---|---|---|
| US2003194495A1 | United States of America | A1 | |
| US2003211244A1 | United States of America | A1 | |
| WO03095702A2 | World Intellectual Property Organization (WIPO) | A2 | |
| US2003232495A1 | United States of America | A1 | |
| TW200403766A | Taiwan Province of China | A | |
| US2004069410A1 | United States of America | A1 | |
| WO03095702A3 | World Intellectual Property Organization (WIPO) | A3 | |
| US2004101632A1 | United States of America | A1 | |
| US2004101633A1 | United States of America | A1 | |
| US2004156987A1 | United States of America | A1 | |
| US2004159638A1 | United States of America | A1 | |
| US2004266123A1 | United States of America | A1 | |
| KR20050004844A | Republic of Korea | A | |
| EP1504138A2 | European Patent Office (EPO) | A2 | |
| US2005130404A1 | United States of America | A1 | |
| US2005153073A1 | United States of America | A1 | |
| JP2005524983A | Japan | A | |
| WO2005078155A1 | World Intellectual Property Organization (WIPO) | A1 | |
| US6936551B2 | United States of America | B2 | |
| CN1662676A | China | A | |
| TW200529250AThis record | Taiwan Province of China | A | |
| US7056560B2 | United States of America | B2 | |
| US7060330B2 | United States of America | B2 | |
| TWI282125B | Taiwan Province of China | B | |
| US7256139B2 | United States of America | B2 | |
| US2007275569A1 | United States of America | A1 | |
| US7323399B2 | United States of America | B2 | |
| US2008041415A1 | United States of America | A1 | |
| CN100400707C | China | C | |
| US7422774B2 | United States of America | B2 | |
| US7790583B2 | United States of America | B2 |
Numbers
- Publication
- 200529250
- Application
- 94103756
Titles4
- Chinese
- 利用PECVD之直鏈型矽先趨物及有機致孔劑之混合系統的超低K值介電材料
- English
- ULTRA LOW DIELECTRIC MATERIALS BASED ON HYBRID SYSTEM OF LINEAR SILICON PRECURSOR AND ORGANIC POROGEN BY PLASMA-ENHANCED CHEMICAL VAPOR DEPOSITION(PECVD)
- Unlabeled
- 利用PECVD之直鏈型矽先趨物及有機致孔劑之混合系統的超低K值介電材料
- Unlabeled
- Ultra-low-K dielectric material using PECVD linear silicon precursor and organic porogen hybrid system
Classification
- CPC, 14
- C23C16/401
- B05D1/60
- B05D3/068
- C23C16/30
- C23C16/56
- H10P14/6922
- H10P14/6682
- H10P14/6686
- H10P14/6336
- H10P14/6539
- H10P95/08
- H10W20/086
- H10W20/081
- H10W20/095
- IPC, 10
- H01B3 00
- B05D3 06
- B05D7 24
- C23C16 30
- C23C16 40
- C23C16 56
- H01L21 3105
- H01L21 312
- H01L21 314
- H01L21 768