AC sensing for a resistive memory

Used for alternating current (AC) sensing of a resistive memory

The present invention relates to resistive memory devices, and more specifically, to read/sensing circuits for programmable contact random access memory (PCRAM) devices.

Integrated circuit designers have been looking for the ideal semiconductor memory-a device that can be accessed randomly, can be read and written extremely quickly, is non-volatile but can be changed infinitely and consumes very little power. Programmable contact random access memory (PCRAM) technology has increasingly been recognized as providing all of these advantages.

Digital memory is widely used in computers, computer system components, and computer processing systems. Resistive memory stores digital information in the form of binary bits or bits such as "0" and "1" based on the resistance of the memory element or unit. The resistive memory device is configured as an array, in which a resistive element or unit is located at the intersection of a column line (word line) and a row line (digit line or bit line). In order to read or sense the state of the memory cell, it is necessary to first select the desired memory cell by selecting the row line and the column line that cross the desired memory element. Once the desired memory element is isolated, then read the selected memory cell by applying a read voltage to the cell to detect the resistance of the memory cell and thereby determine the logic of the memory cell state.

For the sensing of binary logic states, it is not necessary to know the absolute value of the resistance of the memory cell, only to know whether the resistance of the memory cell is higher or lower than the threshold value between logic one and logic zero resistance. Even so, sensing the logic state of PCRAM memory devices is difficult because the technology of PCRAM devices imposes multiple constraints.

The present invention provides an embodiment that uses alternating current (AC) to read the state of a resistive memory device. Reading the state of the resistive memory device with AC avoids proceduralizing or erasing the memory device.

The memory bits based on the resistance change of the material in response to a programmed (write or erase) voltage or current have a lot of expectations for non-volatile memory. Some of these resistive memory bits (mbits) exhibit changes in their viability if they are repeatedly read due to repeated application of a small current to the sensing/reading device. Because of its inability to survive, the memory bits are not so easily programmed or erased and can even remain in a logical state.

The resistive memory bit can be used as a model of a resistor. In a conventional direct current (DC) reading/sensing circuit, a current is applied to a memory bit and the voltage is measured, or a voltage is applied to the memory bit and the current is measured.

Figure 1 shows a part of a PCRAM device, which includes a resistive memory cell (memory bit line) arranged at the intersection of row lines (bit lines/digital lines) 20a-20d and column lines (word lines) 15a-15d Element) array 9. In addition, the array 9 includes cell plate lines 22a, 22b, 22c, and 22d paired with bit lines 20a, 20b, 20c, and 20d, respectively.

The figure shows two exemplary memory cells 10a and 10b. The memory cell 10a is addressed by the column line 15b and the digit line 20b and the cell plate line 22b. The memory cell 10b is addressed by the row line 15c and the line 20b. The memory cells 10a and 10b each include an access transistor 25 and a programmable resistance element 30 connected in series between the digit line 20b and the cell plate line 22b. The digit line 20b is connected to all the cells in the same row in the array 9 like the cell plate line 22b. In the following discussion, an exemplary embodiment of the present invention is described with reference to an exemplary memory cell 10a.

According to an exemplary embodiment of the present invention, the bit lines 20a, 20b, 20c, and 20d are each connected to an individual AC sensing circuit 35, and can be implemented as shown in FIGS. 2A and 2B or by other suitable components. If necessary, the array 9 and peripheral circuits can be integrated into a single integrated circuit.

FIG. 2A shows an exemplary embodiment of the AC sensing circuit 35 together with other components of the memory device 8 in a simplified block diagram form. The AC sensing circuit 35 includes a switching circuit 110 and a comparison circuit 115. The memory device 8 also includes a clock/control circuit 105 coupled to the memory element 10a through the word line 15b and further coupled to the switching circuit 110. The memory cell 10a is also coupled to the switching circuit 110 through the bit line 20b and the cell plate line 22b.

The clock/control circuit 105 receives a source clock signal 120 and provides a cell board count signal 135 and a bit count signal 130 to the switching circuit 110. The clock/control circuit 105 also provides a signal to the word line 15b.

The memory cell 10a and other cells in the same row receive the signal on the word line 15b. The signal on the ZigZag of each row operates as a control signal to control when to perform the sensing operation of all the units in the row. A high pulse on a ZigZag line turns on the transistor 25 of each unit, providing a conductive path through the resistive element 30.

In response to the signals 130 and 135, the switching circuit 110 provides two signals to the comparison circuit 115 through the two signal lines 122. At any point in time, where the signals are compared on the line 125, a signal line 122 is at the supply voltage V_cc, And the other signal line is at a voltage that depends on the resistance element 30. The signal passing through the resistive element 30 alternates polarity during the read operation.

Fig. 2B shows a more detailed exemplary embodiment of the assembly shown in Fig. 2A. The illustrated switching circuit 110 includes PMOS transistors 45 and 50 controlled by signals 135 and 130, respectively. The cell plate line 22b and the bit line 20b are each coupled to the supply voltage V through individual transistors 45 and 50_cc。

The clock/control circuit 105 includes a cell board counter 60, a bit counter 65, an exclusive OR (XOR) gate 80, and two inverters 70, 75 . A source clock signal is supplied to the cell board counter 60 and the bit line counter 65. The cell plate counter 60 provides its output to the inverter 70 and the XOR gate 80. The bit line counter 65 similarly supplies its output to the inverter 75 and the XOR gate 80. The XOR gate 80 then modulates the signal on the word line 15b to control when the transistor 25 is turned on. Inverters 70 and 75 provide signals 135 and 130, respectively.

The comparison circuit 115 includes an inverter 85, CMOS multiplexers 90 and 95 and a switched capacitor sense amplifier 100. The signal 135 from the inverter 70 is applied to the gate of the transistor 45 and the inverter 85. The signal 135 from the inverter 70 is also applied to each CMOS multiplexer 90, 95 as a control signal, like the output of the inverter 85. The output from the inverter 75 is applied to the gate of the transistor 50. When the signal 135 becomes low and turned on, the transistor 45 pulls the cell board line 22b to V_cc; When the signal 130 turns low and turns on, the transistor 50 pulls the bit line 20b to V_cc。

The line 122 connects the bit line 20b and the cell plate line 22b to both the CMOS multiplexers 90, 95. The CMOS multiplexers 90 and 95 can be conventional four transistor multiplexers, and each multiplexer has five terminals (two input terminals, two control terminals, and one output terminal). The CMOS multiplexers 90 and 95 are based on the output of the signal 135 and the inverter 75 each selects one input from the line 122 as its output. When the signal 135 is low, the CMOS multiplexer (MUX) 95 provides the signal from the bit line 20b, and the MUX 90 provides the V from the transistor 45_cc; When the signal 135 is high, MUX 90 provides 50 V from the transistor_cc, And MUX 95 provides the signal from the unit board 22b. As a result, MUX 95 always provides the sensing signal from the memory cell 10a, and MUX 90 always provides V as the reference voltage_cc。

The outputs of the CMOS multiplexers 90, 95 are applied to the switched capacitor sense amplifier 100. The switched capacitor sense amplifier 100 is a current input amplifier that should measure a small amount of positive or negative current at its terminals and compare the current with a threshold value. The threshold is set so that the output of the switched capacitor sense amplifier 100 corresponds to the logic state of a specific memory cell (such as the memory cell 10a) connected to the bit line 20b and the cell board line 22b. There is a switched capacitor sense amplifier 100 for each row or bit line, but only one cell column is read at a time under the control of the word line.

Figures 2A and 2B only depict a single unit. The memory device has a plurality of memory elements arranged in columns and rows. The circuit of the present invention is intended to be adjusted for use in a memory device. When adjusted for use with a memory device, a single control circuit is used for each row with additional selection logic and access devices (not shown). That is, the XOR gate is an "enabled" XOR gate activated by the word line decoding circuit. Multiple counters are advantageously stacked in the column direction, with one set of counters per row or one set of counters per wafer. Likewise, one comparison circuit per row would be advantageous. The switching circuit will advantageously have an additional multiplexer for the memory device.

FIG. 3 is a timing diagram of signals from the circuit 105 in FIG. 2B. Transistor 25 turns on when the signal on word line 15b goes high. In the first case where the word line 15b goes high, the cell plate count signal 135 is high and the bit count signal 130 is low. When the word line 15b becomes high, the cell plate count signal 135 is low and the bit count signal 130 is high. The reading cycle therefore alternates in the direction of current passing through the resistor 30. However, the comparison circuit 115 effectively adjusts the AC before the switched capacitor sense amplifier 100 provides output bits. It should be understood that the relationship between the bit count signal and the cell board count signal is 6:2 or 3:1, and each pair of transitions (rising and falling edges) of the cell board count signal 135 has four of the bit count signals 130 Clock transition (rising and falling edges). That is, the cell board count signal 135 is the (input) clock signal divided by 6, and the bit count signal 130 is the clock signal divided by 2.

The XOR gate 80 (Figure 2B) ensures that the signal on the word line signal 15b is high when the cell board count signal 135 is high and the bit count signal 130 is low, or when the cell board count signal 135 is low and the bit count signal 130 is high. . When the signal 135 is low and the word line 15b is high, current flows from the transistor 45 to the switched capacitor sense amplifier 100 through the resistive element 30 and the CMOS multiplexer 95. When the signal 130 is low and the word line 15b is high, current flows from the transistor 50 to the switched capacitor sense amplifier 100 through the resistive element 30 and the CMOS multiplexer 90.

One of the advantages of using AC sensing for resistive memory cells is to extend the survivability of the memory cells of the memory device. Using AC to read the state of the memory device/cell avoids proceduralization or partial erasure of the memory device.

The present invention has been described using PMOS transistors, but it can also be implemented using NMOS transistors. The control signal is described as a clock signal, and the cell board line and bit line have a certain relationship with these clock signals. The control signals can have any other form or relationship, as long as they operate as described herein to control the memory cells and gate the transistors in the switching circuit. As long as the required functionality is implemented, the control circuit, switching circuit, and comparison circuit of the present invention can be implemented by moving individual components to another circuit. For example, the inverter of the control circuit can be regarded as a part of the switching circuit. The inverter and multiplexer of the comparison circuit can also be regarded as part of the switching circuit.

4 illustrates an exemplary digital processing system 500 whose component 508 utilizes a memory device 8 using the sensing circuit 35 of the present invention disclosed above in conjunction with FIGS. 1-3. The processing system 500 includes one or more processors 501 coupled to a local bus 504. The memory controller 502 and the main bus bridge 503 are also coupled to the local bus 504. The processing system 500 may include multiple memory controllers 502 and/or multiple main bus bridges 503. The memory controller 502 and the main bus bridge 503 can be integrated into a single device 506.

The memory controller 502 is also coupled to one or more memory buses 507. Each memory bus accepts a memory component 508 that includes at least one memory device 8, and the memory device includes a sensing circuit 35. Each memory component 508 can be a memory card or a memory module. Examples of memory modules include single-row embedded memory modules (SIMM) and dual-row embedded memory modules (DIMM). The memory component 508 may include one or more additional devices. The memory controller 502 can also be coupled to a cache memory 505. The cache memory 505 may be the only cache memory in the processing system. Alternatively, other devices (such as the processor 501) may also include a cache memory, which may form a cache hierarchy with the cache memory 505. If the processing system 500 includes a bus master or a peripheral device or controller that supports direct memory access (DMA), the memory controller 502 can implement a cache consistent protocol. If the memory controller 502 is coupled to a plurality of memory buses 507, each of the memory buses 507 can be operated in parallel, or different address ranges can be mapped to different memory buses 507.

The main busbar bridge 503 is coupled to at least one peripheral busbar 510. Various devices such as peripheral devices or additional busbar bridges may be coupled to the peripheral busbar 510. These devices may include a storage controller 511, a hybrid I/O device 514, a secondary bus bridge 515, a multimedia processor 518, and a legacy device interface 520. The main bus bridge 503 can also be coupled to one or more high-speed ports 522 for specific purposes. For example, in a personal computer, the dedicated port may be an accelerated graphics port (AGP), which is used to couple a high-performance video card to the processing system 500.

The storage controller 511 couples one or more storage devices 513 to the peripheral bus 510 via a storage bus 512. For example, the storage controller 511 may be a SCSI controller, and the storage device 513 may be a SCSI disk. The I/O device 514 can be any type of peripheral device. For example, the I/O device 514 may be a local area network interface, such as an Ethernet card. The secondary bus bridge can be used to interface additional devices to the processing system via another bus. For example, the secondary bus bridge may be a universal serial port (USB) controller, which is used to couple the USB device 517 to the processing system 500. The multimedia processor 518 can be a sound card, a video capture card, or any other type of media interface, and it can also be coupled to an additional device such as a speaker 519. The traditional device interface 520 is used to couple the traditional device 521 (for example, an old keyboard and mouse) to the processing system 500.

The processing system 500 illustrated in FIG. 4 is only an exemplary processing system that can be used in the present invention. Although FIG. 4 illustrates a processing architecture that is particularly suitable for general-purpose computers (such as personal computers or workstations), it should be recognized that well-known modifications can be made to configure the processing system 500 to become more suitable for various applications. For example, a simpler architecture that relies on the CPU 501 coupled to the memory component 508 can be used to implement many electronic devices that require processing. Such electronic devices may include (but are not limited to) audio/video processors and recorders, game consoles, digital televisions, wired or wireless telephones, navigation devices (including GPS-based and/or inertial navigation System), and digital cameras and/or recorders. Modifications may include, for example, eliminating unnecessary components, adding specialized devices or circuits, and/or integrating multiple devices.

Although the embodiments of the present invention have been described in the above description, it should be understood that these embodiments are exemplary embodiments of the present invention and are not to be regarded as restrictive. Although the present invention has been described in terms of PCRAM, it is not limited to this, and is applicable to, for example, magnetoresistive random access memory (MRAM) PCRAM and other circuits in which signals are sensed at different levels. Additions, deletions, substitutions and other modifications can be made without departing from the spirit and scope of the present invention. Therefore, the present invention is not considered to be limited by the foregoing description but only limited by the scope of the appended patent application.

<p>8Memory device</p><p>9Array</p><p>10a,10bMemory unit</p><p>15a-15dColumn Line (Word Line)</p><p>20a-20drow line (bit line/digital line)</p><p>22a-22dunit board line</p><p>25Access Transistor</p><p>30Programmable resistance element/resistive element</p><p>35AC sensing circuit</p><p>45,50PMOS Transistor</p><p>60unit board counter</p><p>65Bit Counter/Bit Line Counter</p><p>70,75,85Inverter</p><p>80Exclusive OR (XOR) gate</p><p>90,95CMOS multiplexer</p><p>100Switching Capacitor Sensing Amplifier</p><p>105Clock/control circuit</p><p>110Switching circuit</p><p>115Comparison circuit</p><p>120Source clock signal</p><p>122 signal line</p><p>130Bit count signal</p><p>135unit board counting signal</p><p>500Digital Processing System</p><p>501Processor</p><p>502Memory Controller</p><p>503Main bus bridge</p><p>504Local Bus</p><p>506Single device</p><p>507Memory bus</p><p>508Memory Components</p><p>510 Peripheral Bus</p><p>511Storage Controller</p><p>512Storage bus</p><p>513Storage Device</p><p>514Miscellaneous I/O device</p><p>515Secondary Bus Bridge</p><p>517USB device</p><p>518Multimedia Processor</p><p>519Speaker</p><p>520Traditional device interface</p><p>521Traditional installation</p>

Fig. 1 shows a part of a programmable contact random access memory (PCRAM) device; Fig. 2A shows the AC sensing circuit and other components of the PCRAM device of Fig. 1 in simplified block diagram; Fig. 2B shows Fig. 2A in more detail Fig. 3 is a timing diagram of signals provided by the clock/control circuit of Fig. 2B; and Fig. 4 shows a digital processing system incorporated into a memory device according to an exemplary embodiment of the present invention.