Semiconductor device

Semiconductor device

The present invention relates to a semiconductor device equipped with a Mask Programmable ROM (Mask Programmable ROM) that can use masks for program planning

Among the conventional semiconductor devices, for example, there is one disclosed in Patent Document 1. In paragraphs 0002~0006 on page 2 of this document and FIG. 2, the structure of the mask ROM with the contact method is disclosed.

Fig. 9 is a circuit diagram showing the structure of the mask ROM of the above-mentioned contact method. The mask ROM of the contact method means that the drain of the memory cell transistor is connected or not connected to the bit line corresponding to the "0" and "1" of the memory data respectively. The mask ROM can use masks for program planning.

The conventional semiconductor device is shown in FIG. 9, and its structure includes a memory cell array 1, a row decoder 2, a sense amplifier 3, a charging transistor 4, an output buffer circuit 6, and a latch circuit 15.

The memory cell array 1 is configured by arranging a plurality of memory cells Mij (i=1~m, j=1~n) composed of N-type MOS transistors into a matrix. The memory cells Mij with the same i value, that is, the gates of the memory cells arranged in the column direction, are commonly connected to the word line selection signal WLi (i=1~m). In addition, the source of the memory cell Mij is connected to the wiring of the ground potential. The drain is connected to the bit line BLj (j=1~n) when the memory data of the memory cell is "0", and becomes a floating state when the memory data of the memory cell is "1".

The row decoder 2 includes an N-type MOS transistor Cj (j=1~n). The drains of the N-type MOS transistors Cj (j=1~n) are connected in common, the source is connected to the bit line BLj (j=1~n), and the gates are respectively connected to the row selection signal CLj(j= 1~n).

The sense amplifier 3 includes a buffer circuit. Its input is connected to the drain of the N-type MOS transistor Cj (j=1~n) constituting the row decoder 2, and its output is connected to the input terminal D of the latch circuit 15.

The transistor 4 for precharging includes a P-type MOS transistor. The gate of the pre-charging transistor 4 is connected to the charge control signal PCLK, its source is connected to the power supply terminal with a power supply potential, and its drain is connected to the N-type MOS transistor Cj (j = 1~) constituting the row decoder 2 The drain of n).

In the output buffer circuit 6, its input is connected to the output terminal Q of the latch circuit 15, and its output is connected to the output terminal OUT.

In the latch circuit 15, its input terminal is connected to the output terminal of the sense amplifier 3. When the latch control signal LCLK is "L" and the latch control signal NLCLK is "H", the signal with the input terminal D is The signal of the same logic is output to the output terminal Q. In addition, when the latch control signal LCLK is "H" and the latch control signal NLCLK is "L", the output state of the output terminal Q is maintained.

For the semiconductor device constructed in the above manner, for example, the operation of reading the data of the memory cell M11 will be described using the timing chart of FIG. 10. In the row selection signal CLj (j=1~n), the row selection signal CL1 is set to the "H" level, and the row selection signals CL2 to CLn are set to the "L" level. Thereby, among the N-type MOS transistors Cj (j=1~n) constituting the row decoder 2, the N-type MOS transistor C1 is set to be in an ON state, and the other N-type MOS transistors C2 to Cn are set to be in an OFF state.

Next, the precharge control signal PCLK is set to the "L" level during the period Tp, and the precharge transistor 4 is set to the ON state only for a certain period of time Tp. Thereby, the bit line BL1 is charged to become the "H" level.

After the bit line BL1 becomes the "H" level, in the word line selection signal WLi (i=1~m), the word line selection signal WL1 is changed from the "L" level to the "H" level, otherwise The word line selection signals WL2~WLm remain at the "L" level.

Thereby, when the drain of the memory cell M11 is connected to the bit line BL1, the charge charged to the bit line BL1 is discharged by the memory cell M11, so that the bit line BL1 becomes the "L" level, and the sense amplifier The input of 3 also becomes the "L" level. In addition, for the latch control signals LCLK and NLCLK of the latch circuit 15, when one of the word line selection signals WLi (i=1~m) is selected, the latch control signal LCLK becomes the "L" bit Therefore, the latch control signal NLCLK becomes the "H" level. Therefore, the output of the sense amplifier 3 becomes the "L" level, the output Q of the latch circuit 15 becomes the "L" level, and "L" is read from the output terminal OUT of the output buffer circuit 6 (shown by a dotted line in FIG. 10) ).

In addition, when the drain of the memory cell M11 is not connected to the bit line BL1, the charge charged to the bit line BL1 will not be discharged by the memory cell M11, and the bit line BL1 maintains the "H" level. The input of the test amplifier 3 also becomes the "H" level. In addition, for the latch control signals LCLK and NLCLK of the latch circuit 15, when one of the word line selection signals WLi (i=1~m) is selected, the latch control signal LCLK is at the "L" level , The latch control signal NLCLK is at the "H" level. Therefore, the output of the sense amplifier 3 becomes the "H" level, the output Q of the latch circuit 15 becomes the "H" level, and "H" is read from the output terminal OUT of the output buffer circuit 6 (the solid line in FIG. 10 Express).

Patent Document 1: Japanese Patent Laid-Open No. 6-176592 (page 2, figure 2) Patent Document 2: Japanese Patent Laid-Open No. 61-255035 (pages 1 to 2, figure 2) Patent Document 3 : Japanese Patent Laid-Open No. 4-34799 (pages 1 to 2, Fig. 3) The conventional semiconductor device has the following problems. The relationship between "0" or "1" of the memory data and whether the drain of the memory cell transistor is connected to the bit line is fixed. Therefore, when there are more "0"s in the memory data, the connection between the drain of the memory cell transistor and the bit line increases.

In recent years, the structure of the memory cell has become a short TAT (turn around time) due to the multi-layer wiring of the processing, so the wiring steps between the drain of the memory cell transistor and the bit line and Via ( Via) steps. In addition, due to the miniaturization of the processing, the wiring step and the Via step of connecting the drain of the memory cell transistor and the bit line are prone to poor connection problems. Therefore, when the drain of the memory cell transistor is connected to the bit line more, the yield will decrease.

Therefore, a method is proposed. After masking the sense amplifier of the ROM, a circuit to invert the data is added. By changing the logic of the connection between the memory data and the bit line of the memory cell transistor, the memory cell transistor can be The connection between the drain and the bit line becomes less.

However, there is a problem of adding a control circuit. In addition, because the logic is different depending on the mask ROM and each output loaded in the semiconductor device, when analyzing, the data "0" means that the drain of the memory cell transistor is connected or not connected to the bit line information management becomes Difficult question. In addition, when the IP (Intellectual Property) of the mask ROM that can change the logic is not available, there will be a problem that the connection between the drain of the memory cell transistor and the bit line cannot be reduced.

The present invention is used to solve the above-mentioned conventional problems, and its purpose is to provide a semiconductor device that can suppress the increase in circuits and can also change the logic so that the lesser of the "0" or "1" of the memory data becomes the memory The drain of the cell transistor is connected to the bit line. By reducing the connection between the drain of the memory cell transistor and the bit line, the yield can be prevented from decreasing.

Furthermore, an object of the present invention is to provide a semiconductor device that can easily confirm whether the data of a plurality of memory cell transistors are memorized in positive logic or negative logic.

The semiconductor device of the present invention includes: a plurality of bit lines; a plurality of word lines arranged to intersect with the bit lines; and a plurality of memory cell transistors arranged on the plurality of bit lines and the plural word lines At each interleaved point, each gate is connected to the word line, and the data that is different due to the connection or non-connection of the drain and the bit line is memorized; the word line selection circuit selects a word line from a plurality of word lines; The bit line selection circuit is used to select one bit line from a plurality of bit lines; the sense amplifier is used to read out the word line selected by the word line selection circuit and the bit line selection circuit selected The data of the memory cell transistor corresponding to the bit line is determined to determine the level of the bit line selected by the bit line selection circuit; the data holding circuit inputs the output of the sense amplifier and has positive logic and negative The two output terminals of logic; and the output circuit, the input terminal of which is connected to the output terminal of any one of the two output terminals of the data holding circuit.

According to this structure, only the output terminal of the data holding circuit connected to the input terminal of the output circuit is changed, and no additional circuit is required. The logic can be changed, and the number of "0" or "1" in the memory data can be reduced. One side is to connect the drain of the memory cell transistor to the bit line. Therefore, the connection (contact portion) between the drain of the memory cell transistor and the bit line can be reduced, which can prevent a decrease in yield.

In the present invention, it is preferable that the connection/non-connection between the drain of the memory cell transistor and the bit line is formed/non-formed by electrically connecting the drain and the first contact between the bit line The connection between the output terminal of one side of the data holding circuit and the input terminal of the output circuit is formed by the formation of the second contact portion electrically connecting the output terminal of one side and the input terminal of the output circuit. The first contact portion and the second contact portion are formed in the same step.

Thereby, even if the memory data is determined or changed in the step of connecting the drain of the memory cell array and the bit line, the logic change and the drain of the memory cell transistor and the bit line can be changed in the same step. connect. As a result, the contact portion connecting the drain of the memory cell transistor and the bit line can be reduced.

In addition, in the present invention, it is preferable to provide a test terminal, and when a test signal is input to the test terminal, the input of the sense amplifier is fixed at the ground potential or the power supply potential.

In this way, if the test signal is input to the test terminal and the memory data of the memory cell transistor is read during the test mode, regardless of whether the memory data is "0" or "1", the sensor amplifier The input is fixed at ground potential/power supply potential. As a result, the output logic of the sense amplifier input to the data holding circuit is fixed at "0"/"1", the output terminal of the positive logic of the data holding circuit is fixed at "0"/"1", and the negative of the data holding circuit The logic output terminal is fixed at "1"/"0". Therefore, when the input of the sense amplifier is fixed at the ground potential and the output terminal of the positive logic of the data holding circuit is connected to the output circuit, the output of the output circuit will become "0". In this case, the plurality of memory cell transistors use positive logic to store data. On the other hand, when the output circuit is connected to the output terminal of negative logic, the output of the output circuit will become "1". In this case, the plurality of memory cell transistors memorize data with negative logic.

In addition, when the input of the sense amplifier is fixed at the power supply potential and an output circuit is connected to the output terminal of the positive logic of the data holding circuit, the output of the output circuit will become "1". In this case, the plurality of memory cell transistors memorize data in positive logic. On the other hand, when the output circuit is connected to the output terminal of negative logic, the output of the output circuit will become "0". In this case, the plurality of memory cell transistors memorize data with negative logic.

Accordingly, it can be easily confirmed whether the data of the plurality of memory cell transistors are memorized in positive logic or negative logic.

In addition, it is preferable to provide a charging circuit in the present invention. The first node connected to the input of the sense amplifier is charged to the power supply potential, and the bit line is selected from the first node through the bit line selection circuit. The bit line selected by the circuit is charged to become the power supply potential; in addition, there is a test terminal; and a control circuit. When a test signal is input to the test terminal, the first node is prohibited from being charged by the charging circuit. The first node connected to the input of the sense amplifier is fixed at ground potential.

According to this method, if the test signal is input to the test terminal in the test mode, and the memory data of the memory cell transistor is read, regardless of whether the memory data is "0" or "1", the sensor amplifier The input becomes the ground potential. As described above, it is easy to confirm whether the data of the plural memory cell transistors are memorized in positive logic or negative logic.

In addition, it is preferable to provide a charging circuit in the present invention. The first node connected to the input of the sense amplifier is charged to the power supply potential, and the bit line is selected from the first node via the bit line selection circuit. The bit line selected by the circuit is charged to become the power supply potential; in addition, there is a test terminal; and a control circuit. When a test signal is input to the test terminal, the bit line selection circuit is forbidden to select the bit line .

In this way, if the test signal is input to the test terminal in the test mode, and the memory data of the memory cell transistor is read, regardless of whether the memory data is "0" or "1", the sensor amplifier The input becomes the power supply potential. As described above, it is easy to confirm whether the data of the plurality of memory cell transistors are memorized in positive logic or negative logic.

In addition, it is preferable to provide a charging circuit in the present invention. The first node connected to the input of the sense amplifier is charged to the power supply potential, and the bit line is selected from the first node through the bit line selection circuit. The bit line selected by the circuit is charged to become the power supply potential; in addition, it is equipped with a test terminal; and a control circuit. When a test signal is input to the test terminal, the word line selection circuit is prohibited from being selected by the word line selection circuit.

In this way, if the test signal is input to the test terminal in the test mode, and the memory data of the memory cell transistor is read, regardless of whether the memory data is "0" or "1", the sense amplifier The input becomes the power supply potential. As described above, it is easy to confirm whether the data of the plural memory cell transistors are memorized in positive logic or negative logic.

In addition, the semiconductor device of the present invention is provided with: a memory portion having: a plurality of bit lines and a plurality of word lines, which are arranged to intersect with the bit lines, respectively; and a plurality of memory cell transistors are arranged in the plurality of bits At each intersection point of the line and the plural word lines, each gate is connected to the word line, and memory is different due to the connection or disconnection of the drain and the bit line; the word line selection circuit is from the plural word lines Select a word line; bit line selection circuit, select a bit line from a plurality of bit lines; sense amplifier, used to read out the word line and bit selected by the word line selection circuit The data of the memory cell transistor corresponding to the bit line selected by the cell line selection circuit is used to determine the level of the bit line selected by the bit line selection circuit; the data holding circuit inputs the output of the sense amplifier; output Circuit, the output of the input data holding circuit; and the buffer circuit, which is the output of the output circuit of the input memory unit, and has 2 output terminals of positive logic and negative logic; and the data processing circuit, which connects the input terminal to the buffer circuit The output terminal of either one of the 2 output terminals.

According to this structure, even if the IP of the mask ROM that can be logically changed according to the memory data cannot be used, there is no need to add a large circuit. By changing the logic of the buffer circuit that inputs the data from the memory unit, the memory can be changed. The connection between the drain of the unit transistor and the bit line is reduced to prevent the decrease in yield.

In the present invention, it is preferable that the connection/non-connection between the drain of the memory cell transistor and the bit line is formed by electrically connecting the first contact between the drain and the bit line. As a result, the connection between the output terminal of one side of the buffer circuit and the input terminal of the data processing circuit is formed by the formation of the second contact portion electrically connecting the output terminal of one side and the input terminal of the data processing circuit, The first contact portion and the second contact portion are formed in the same step.

In this way, even if the memory data is determined or changed in the step of connecting the drain and bit line of the memory cell array, the logic change and the drain and bit of the memory cell transistor can be performed in the same step. Wire connection. As a result, the contact portion connecting the drain of the memory cell transistor and the bit line can be reduced.

In addition, the semiconductor device of the present invention is provided with: a memory portion having: a plurality of bit lines; a plurality of word lines arranged to be interleaved with the bit lines; and a plurality of memory cell transistors arranged in the plurality of bit lines At each intersection point between the line and the plural word lines, each gate is connected to the word line, and memory is different due to the connection or disconnection of the drain and the bit line; the word line selection circuit is from the plural word lines Select a word line; bit line selection circuit, select a bit line from a plurality of bit lines; sense amplifier, used to read out the word line and bit selected by the word line selection circuit The data of the memory cell transistor corresponding to the bit line selected by the bit line selection circuit is used to determine the level of the bit line selected by the bit line selection circuit; the data holding circuit is input to the output of the sense amplifier; The output circuit, the output of the input data holding circuit; and the data processing unit, which is composed of: an input circuit, which inputs the output of the output circuit of the memory unit, and has 2 output terminals of positive logic and negative logic; data processing circuit , Its input terminal is connected to any one of the two output terminals of the input circuit.

According to this structure, even if the IP of the mask ROM that can be logically changed according to the memory data cannot be used, there is no need to add a large circuit, and the logic can be performed by the input circuit of the data processing unit that inputs the data from the memory unit. The change. As a result, it is possible to reduce the connection between the drain of the memory cell transistor and the bit line, and to prevent the decrease in yield.

In the present invention, it is preferable that the connection/non-connection between the drain of the memory cell transistor and the bit line is formed by electrically connecting the first contact between the drain and the bit line. The connection between the output terminal of the input circuit of the data processing unit and the input terminal of the data processing circuit is formed by electrically connecting the second contact portion between the output terminal of one of the input circuits of the data processing circuit and the input terminal of the data processing circuit. The first contact portion and the second contact portion are formed in the same step.

In this way, even if the memory data is determined or changed in the step of connecting the drain and bit line of the memory cell array, the logic change and the drain and bit of the memory cell transistor can be performed in the same step. Wire connection can reduce the number of contacts between the drain of the memory cell transistor and the bit line.

As explained above, according to the semiconductor device of the present invention, only the output terminal of the data holding circuit connected to the input terminal of the output circuit needs to be changed, and no additional circuit is required, that is, logic changes can be made to store "0" of the data. Or the lesser of "1" is to connect the drain of the memory cell transistor to the bit line. As a result, the connection (contact portion) between the drain of the memory cell transistor and the bit line can be reduced. This can prevent the decrease in yield due to the multilayering and miniaturization of wiring.

Even if the memory data is determined or changed in the step of connecting the drain of the memory cell transistor and the bit line, the logic change and the connection of the drain of the memory cell transistor and the bit line can be performed in the same step. As a result, it is possible to reduce the contact portion connecting the drain of the memory cell transistor and the bit line.

In addition, by setting the test terminal and fixing the input of the sense amplifier at the ground potential or power supply potential when the test signal is input to the test terminal, it is easy to confirm that the data of the plural memory cell transistors are in positive logic To be memorized or to be memorized with negative logic, that is, it is easy to confirm that the data "0"/"1" from the output circuit is the relationship between the drain of the memory cell transistor or not connected to the bit line, respectively. In this way, it can be easily analyzed.

In addition, according to the semiconductor device of the present invention, even when the IP of the mask ROM that can be logically changed according to the memory data cannot be used, there is no need to add a large circuit, and the logic is performed by a buffer circuit that inputs data from the memory unit. The change can reduce the connection (contact portion) between the drain of the memory cell transistor and the bit line. Thereby, it is possible to prevent the decrease in yield due to the multilayering and miniaturization of wiring.

In this case, even if the memory data is determined or changed in the step of connecting the drain and bit line of the memory cell array, the logic change and the drain and bit of the memory cell transistor can be performed in the same step. Line connection. As a result, it is possible to reduce the contact portion connecting the drain of the memory cell transistor and the bit line.

In addition, according to the semiconductor device of the present invention, even if the IP of the mask ROM that can be logically changed according to the memory data cannot be used, there is no need to add a large amount of circuitry. The input circuit of the data processing unit that inputs the data from the memory unit The logic change can reduce the connection (contact portion) between the drain of the memory cell transistor and the bit line. In this way, it is possible to prevent the decrease in yield due to the multilayering and miniaturization of wiring.

In this case, even if the memory data is determined or changed in the step of connecting the drain and bit line of the memory cell array, the logic change and the drain and bit of the memory cell transistor can be performed in the same step. Line connection. As a result, it is possible to reduce the contact portion connecting the drain of the memory cell transistor and the bit line.

(First embodiment)

FIG. 1 is a circuit diagram showing the structure of a semiconductor device, that is, a ROM according to a first embodiment of the present invention.

The semiconductor device of this embodiment is shown in FIG. 1, and its structure includes a memory cell array 1, a row decoder 2, a sense amplifier 3, a charging transistor 4, a latch circuit 5, an output buffer circuit 6, and a charging signal Control circuit 7 and discharging transistor 8. The memory cell array 1, the row decoder 2, the sense amplifier 3, the charging transistor 4, and the output buffer circuit 6 are the same as the prior art, so the same components are assigned the same symbols, and their descriptions are omitted.

In the latch circuit 5, the input terminal is connected to the output of the sense amplifier 3. When the latch control signal LCLK is "L" and the latch control signal NLCLK is "H", a signal with the same logic as the input D is output to The output terminal Q, and the negative logic signal is output to the output terminal NQ. In addition, when the latch control signal LCLK is "H" and the latch control signal NLCLK is "L", the output states of the output terminal Q and the output terminal NQ are maintained.

The charging signal control circuit 7 inputs the charging control signal PCLK and the test control signal TEST, and outputs the signal PCLKA input to the gate of the charging transistor 4 and the signal RESET input to the gate of the discharging transistor 8. When the test control signal TEST is "L", the charge control signal PCLKA becomes the same signal as the latch control signal PCLK, and the signal RESET becomes "L". When the test control signal TEST is "H", the charge control signal PCLKA becomes "L", and the signal RESET becomes "H". In addition, the semiconductor device of this embodiment is provided with a test terminal (not shown in the figure) for inputting a test control signal TEST from the outside.

The discharge transistor 8 is composed of an N-type MOS transistor. The gate of the discharge transistor 8 is connected to the signal RESET, its source is connected to the power supply terminal with ground potential, and its drain is connected to the N-type MOS transistor Cj (j=1~n) constituting the row decoder 2 Drain and sense amplifier 3 input.

Regarding the semiconductor device constructed in the above manner, for example, the operation of reading the data of the memory cell M11 will be described using the timing chart of FIG. 2.

First, the description will be given when the test control signal TEST is at the "L" level (in the normal operation mode).

In the row selection signal CLj (j=1~n), the row selection signal CL1 is set to the "H" level, and the row selection signals CL2 to CLn are set to the "L" level. In this way, among the N-type MOS transistors Cj (j=1~n) constituting the row decoder 2, the N-type MOS transistor C1 becomes the ON state, and the other N-type MOS transistors C2~Cn become the OFF state. .

Secondly, the precharge control signal PCLK is set to the "L" level during the Tp period. In this way, the signal PCLKA connected to the gate of the precharge transistor 4 also becomes the ON state for a certain period of time Tp. Thereby, the bit line BL1 is charged to the "H" level.

After the bit line BL1 becomes the "H" level, in the word line selection signal WLi (i=1~m), the word line selection signal WL1 changes from the "L" level to the "H" level, and other words The line selection signals WL2-WLm remain at the "L" level.

In this way, when the drain of the memory cell M11 is connected to the bit line BL1, the charge charged in the bit line BL1 is discharged by the memory cell M11, so that the bit line BL1 becomes the "L" level , The input of the sense amplifier 3 also becomes the "L" level. In addition, regarding the latch control signals LCLK and NLCLK of the latch circuit 5, when one of the word line selection signals WLi (i=1~m) is selected, the latch control signal LCLK becomes the "L" bit Therefore, the latch control signal NLCLK becomes the "H" level. Therefore, the output of the sense amplifier 3 becomes the "L" level, the output Q of the latch circuit 5 becomes the "L" level, and the output NQ becomes the "H" level. With the positive logic setting, when the output terminal Q of the latch circuit 5 is connected to the output buffer circuit 6, "L" will be read from the output terminal OUT. In addition, with the setting of negative logic, when the output terminal NQ of the latch circuit 5 is connected to the output buffer circuit 6, "H" will be read from the output terminal OUT (indicated by a broken line in FIG. 2).

In addition, when the drain of the memory cell M11 is not connected to the bit line BL1, the charge charged on the bit line BL1 is not discharged by the memory cell M11, and the bit line BL1 maintains the "H" level, and the sense amplifier The input of 3 also becomes the "H" level. In addition, regarding the latch control signals LCLK and NLCLK of the latch circuit 5, when one of the word line selection signals WLi (i=1~m) is selected, the latch control signal LCLK becomes the "L" level , The latch control signal NLCLK becomes the "H" level, the output of the sense amplifier 3 becomes the "H" level, the output Q of the latch circuit 5 becomes the "H" level, and the output NQ becomes the "L" level. With the positive logic setting, when the output Q of the latch circuit 5 is connected to the output buffer circuit 6, "H" will be read from the output terminal OUT. In addition, by setting the negative logic, when the output terminal NQ of the latch circuit 5 is connected to the output buffer circuit 6, "L" is read from the output terminal OUT (shown as a solid line in FIG. 2).

Secondly, when the test control signal TEST becomes the "H" level (in the test mode), the signal PCLKA connected to the gate of the precharge transistor 4 becomes "H", which is connected to the signal of the gate of the discharge transistor 8 RESET becomes "H". Therefore, the input of the bit line BL1 and the sense amplifier 3 becomes the "L" level. Therefore, the output of the sense amplifier 3 becomes the "L" level, the output Q of the latch circuit 5 becomes the "L" level, and the output NQ becomes the "H" level. With the positive logic setting, when the output terminal Q of the latch circuit 5 is connected to the output buffer circuit 6, "L" will be read from the output terminal OUT. In addition, by setting the negative logic, when the output terminal NQ of the latch circuit 5 is connected to the output buffer circuit 6, "H" will be read from the output terminal OUT.

According to this embodiment, no additional circuit is required, only the output terminals Q and NQ of the latch circuit 5 connected to the output buffer circuit 6 need to be switched, that is, the data "0" or "1" and the data can be changed (change in logic) Whether the drain of the memory cell Mij (i=1~m, j=1~n) is connected to the bit line BLj (j=1~n). As a result, the number of drains of the memory cell Mij (i=1~m, j=1~n) connected to the bit line BLj (j=1~n) can be reduced. Thereby, it is possible to prevent the decrease in yield caused by the multilayering and miniaturization of wiring.

In this embodiment, it is preferable to connect/non-connect the drain of the memory cell Mij to the bit line BLj by using the first contact portion (Via portion) that electrically connects the drain to the bit line. The formation/non-formation is obtained. The connection between the output terminal Q or NQ of the latch circuit 5 and the output buffer circuit 6 uses the first electrical connection between the output terminal Q or NQ and the input terminal of the output buffer circuit 6 2 The formation of the contact end (Via part) is obtained, and the first contact part and the second contact part are formed by the same steps. Thereby, even if the memory data is determined or changed in the step of connecting the drain of the memory cell Mij to the bit line BLj, the logic change can be made in the same way as the drain of the memory cell Mij and the connection of the bit line BLj. The steps are carried out. As a result, the contact portion connecting the drain of the memory cell Mij and the bit line BLj can be reduced.

In addition, by controlling the charging operation with the test control signal TEST, it can be easily confirmed that the output of the output buffer circuit 6 is positive logic at "L" and negative logic at "H". In this way, it can be easily analyzed.

(Second embodiment)

3 is a circuit diagram showing the structure of a semiconductor device, that is, a mask ROM according to a second embodiment of the present invention.

The semiconductor device of this embodiment is shown in FIG. 3, and its structure includes a memory cell array 1, a row decoder 2, a sense amplifier 3, a charging transistor 4, a latch circuit 5, an output buffer circuit 6, and a row signal control Circuit 9. The memory cell array 1, the row decoder 2, the sense amplifier 3, the charging transistor 4, the latch circuit 5, and the output buffer circuit 6 are the same as the prior art or the first embodiment, so the same components are added to the same components. Symbol and its description is omitted. In addition, the semiconductor device of this embodiment is provided with a test terminal (not shown in the figure) for inputting a test control signal TEST from the outside.

The row signal control circuit 9 inputs the row selection signal CLj (j=1~n) and the test control signal TEST, and outputs the signal CLAj (j=1~n) input to the gate of the row decoder 2.

Regarding the semiconductor device constructed in the above manner, for example, the operation of reading the data of the memory cell M11 will be described using the timing chart of FIG. 4.

When the test control signal TEST is at the "L" level, it is the same as the moving element of the first embodiment.

When the test control signal TEST is at the "H" level, the signals CLAj (j=1~n) input to the gate of the N-type MOS transistor Cj (j=1~n) constituting the row decoder 2 all become "H". L".

When the precharge control signal PCLK becomes the "L" level during the Tp period, the precharge transistor 4 is used to charge the input node of the sense amplifier 3 to become the "H" level. Because the N-type MOS transistor C1 constituting the row decoder 2 is in the OFF state, the bit line BL1 is not charged.

Secondly, in the word line selection signal WLi (i=1~m), the word line selection signal WL1 changes from the "L" level to the "H" level, and the other word line selection signals WL2~WLm remain at "L" Level. However, because Cj (j=1~n) constituting the row decoder 2 is in the OFF state, the input part of the sense amplifier 3 is irrelevant to the connection/non-connection relationship between the drain of the memory cell M11 and the bit line BL1 Keep it at the "H" level. Therefore, the output of the sense amplifier 3 becomes "H", the output Q of the latch circuit 5 becomes "H" level, and the output NQ becomes "L" level. With the setting of positive logic, when the output terminal Q of the latch circuit 5 is connected to the output buffer circuit 6, "H" will be read from the output terminal OUT. In addition, with the setting of negative logic, when the output terminal NQ of the latch circuit 5 is connected to the output buffer circuit 6, "L" will be read from the output terminal OUT.

According to the present embodiment, by switching the output terminals Q and NQ of the latch circuit 5 connected to the output buffer circuit 6, as in the first embodiment, the memory cells Mij (i=1~m, j=1) can be reduced. ~n) the number of drains connected to bit lines BLj (j=1~n). In this way, it is possible to prevent the decrease in yield caused by the multilayer and miniaturization of wiring.

In this embodiment, it is preferable that the connection/non-connection between the drain of the memory cell Mij and the bit line BLj is made by using the first contact portion (Via portion) that electrically connects the drain and the bit line. Obtained by formation/non-formation, the connection between the output terminal Q or NQ of the latch circuit 5 and the output buffer circuit 6 uses the second electrical connection between the output terminal Q or NQ and the input terminal of the output buffer circuit 6 The formation of the contact part (Via part) is obtained, and the first contact part and the second contact part are formed in the same step. Thereby, even if the memory data is determined or changed in the step of connecting the drain of the memory cell Mij to the bit line BLj, the logic can be changed in the same step as the drain of the memory cell Mij and the bit line BLj Connection. As a result, the contact portion connecting the drain of the memory cell Mij and the bit line BLj can be reduced.

In addition, by controlling the row decoder 2 with the test control signal TEST, it can be easily confirmed that the output of the output buffer circuit 6 is positive logic at "H" and negative logic at "L". In this way, it can be easily analyzed.

(The third embodiment)

FIG. 5 is a circuit diagram showing the structure of a semiconductor device, that is, a mask ROM according to a third embodiment of the present invention.

The semiconductor device of this embodiment is shown in FIG. 5, and its structure includes a memory cell array 1, a row decoder 2, a sense amplifier 3, a charging transistor 4, a latch circuit 5, an output buffer circuit 6, and a word line control Circuit 10. The memory cell array 1, the row decoder 2, the sense amplifier 3, the charging transistor 4, the latch circuit 5, and the output buffer circuit 6 are the same as the prior art or the first embodiment, so the same components are added to the same components. Symbol, and its description is omitted. In addition, the semiconductor device of this embodiment also has a test terminal (not shown in the figure) for inputting a test control signal TEST from the outside.

The word line control circuit 10 inputs the word line selection signal WLi (i=1~m) and the test control signal TEST, and outputs the input to the gate of the memory unit Mij (i=1~m, j=1~n) Word line selection signal WLAi (i=1~m).

Regarding the semiconductor device constructed in the above manner, for example, the operation of reading the data of the memory cell M11 will be described using the timing chart of FIG. 6.

When the test control signal TEST is at the "L" level, the action is the same as that of the first embodiment.

When the test control signal TEST is at the "H" level, the word line selection signals WLAi (i=1~m) input to the gate of the memory cell Mij (i=1~m, j=1~n) all become " L" level.

In the row selection signal CLj (j=1~n), the row selection signal CL1 is set to the "H" level, and the row selection signals CL2 to CLn are set to the "L" level, thereby forming the N of the row decoder 2. In the type MOS transistor Cj (j=1~n), the N-type MOS transistor C1 is turned on, and the other N-type MOS transistors C2 to Cn are turned off.

Next, if the precharge control signal PCLK connected to the gate of the precharge transistor 4 is set to the "L" level during the Tp period, the bit line BL1 is charged to the "H" level.

After the bit line BL1 becomes the "H" level, in the word line selection signal WLi (i=1~m), the word line selection signal WL1 is changed from the "L" level to the "H" level. The word line selection signals WL2~WLm remain at the "L" level. However, because the word line selection signal WLA1 is at the "L" level, regardless of the connection/non-connection between the drain of the memory cell M11 and the bit line BL1, the input part of the sense amplifier 3 remains at the "H" level. Therefore, the output of the sense amplifier 3 becomes the "H" level, the output Q of the latch circuit 5 becomes the "H" level, and the output NQ becomes the "L" level. With the setting of positive logic, when the output terminal Q of the latch circuit 5 is connected to the output buffer circuit 6, "H" will be read from the output terminal OUT. In addition, by setting the negative logic, when the output terminal NQ of the latch circuit 5 is connected to the output buffer circuit 6, "L" will be read from the output terminal OUT.

According to the present embodiment, by switching the output terminals Q and NQ of the latch circuit 5 connected to the output buffer circuit 6, as in the first embodiment, the memory cells Mij (i=1~m, j=1) can be reduced. ~n) The number of drains connected to bit lines BLj (j=1~n). In this way, it is possible to prevent the decrease in yield caused by the multilayer and miniaturization of wiring.

In this embodiment, it is preferable to connect/non-connect the drain of the memory cell Mij to the bit line BLj by using the first contact portion (Via portion) that electrically connects the drain to the bit line. The formation/non-formation is obtained. The connection between the output terminal Q or NQ of the latch circuit 5 and the output buffer circuit 6 uses the first electrical connection between the output terminal Q or NQ and the input terminal of the output buffer circuit 6 2 The formation of the contact part (Via part) is obtained, and the first contact part and the second contact part are formed in the same step. Thereby, even if the memory data is determined or changed in the step of connecting the drain of the memory cell Mij to the bit line BLj, the logic can be changed in the same step as the drain of the memory cell Mij and the bit line BLj Connection. As a result, the contact portion connecting the drain of the memory cell Mij and the bit line BLj can be reduced.

In addition, by controlling the word line selection signal WLAi (i=1~m) with the test control signal TEST, it can be easily confirmed that the output of the output buffer circuit 6 is positive logic when it is at "H", and it is negative logic when it is at "L". . In this way, it can be easily analyzed.

(Fourth embodiment)

Fig. 7 is a circuit diagram showing the structure of a semiconductor device according to a fourth embodiment of the present invention.

The semiconductor device of this embodiment is shown in FIG. 7, and its structure includes a conventional mask ROM 11, a buffer circuit 12 and a data processing circuit 13.

The mask ROM 11 is a semiconductor device with the structure of FIG. 9 described in the prior art, and the relationship between "0" or "1" of the memory data and whether the drain of the memory cell transistor is connected to the bit line is fixed.

The buffer circuit 12 is a buffer circuit having an input terminal D, a positive logic output terminal Q, and a negative logic output terminal NQ.

The data processing circuit 13 is a circuit that inputs memory data, performs data processing, and then outputs the processing result. A specific example of the data processing circuit 13 may include a processor (CPU core or DSP core).

The semiconductor device constructed in the above-mentioned manner will be described below.

When the output terminal Q of the buffer circuit 12 is connected to the input of the data processing circuit 13, when the output of the mask ROM11 is "L", enter "L" in the input of the data processing circuit 13, and when the output of the ROM11 is For "H", enter "H" in the input of the data processing circuit 13.

In addition, when the output terminal NQ of the buffer circuit 12 is connected to the input of the data processing circuit 13, when the output of the mask ROM 11 is "L", input "H" in the input of the data processing circuit 13. When the output of the ROM 11 is "H", input "L" in the input of the data processing circuit 13.

According to this embodiment, by switching the connection between the output terminal Q or NQ of the buffer circuit 12 and the input of the data processing circuit 13, the data "0" or "1" of the mask ROM in FIG. 9 and the memory unit can be changed Whether the drain of Mij (i=1~m, j=1~n) is connected to the bit line BLj (j=1~n). Therefore, the number of drains of the memory cell Mij (i=1~m, j=1~n) connected to the bit line BLj (j=1~n) can be reduced. In this way, it is possible to prevent the decrease in yield caused by the multilayer and miniaturization of wiring. Therefore, when the semiconductor device (mask ROM) of the first to third embodiments of the present invention cannot be used, the same effect can be obtained by the above-mentioned method.

In this embodiment, it is preferable to connect/non-connect the drain of the memory cell Mij to the bit line BLj by using the first contact portion (Via portion) that electrically connects the drain to the bit line. The formation/non-formation is obtained. The connection between the output terminal Q or NQ of the buffer circuit 12 and the data processing circuit 13 uses the second electrical connection between the output terminal Q or NQ and the input terminal of the data processing circuit 13 The formation of the contact part (Via part) is obtained, and the first contact part and the second contact part are formed in the same step. Thereby, even if the memory data is determined or changed in the step of connecting the drain of the memory cell Mij to the bit line BLj, the logic change and the drain of the memory cell Mij and the bit line BLj can be changed in the same steps. connect. As a result, the contact portion connecting the drain of the memory cell Mij and the bit line BLj can be reduced.

(Fifth embodiment)

Fig. 8 is a circuit diagram showing the structure of a semiconductor device according to a fifth embodiment of the present invention.

The semiconductor device of this embodiment is shown in FIG. 8, and its structure includes a mask ROM 11 of the prior art, and a data processing circuit 14 provided with a circuit capable of logic switching in the input section. Since the mask ROM 11 is the same as the fourth embodiment, the same reference numerals are attached to the same constituent elements, and the description thereof is omitted.

The data processing circuit 14 has a positive logic node Q and a negative logic node NQ in the input portion 14a as output nodes, and the connection to the internal circuit 14b can be changed. The input part 14a of the data processing circuit 14 has the same function as the buffer circuit 12 of FIG. 7, and the internal circuit 14b has the same function as the data processing circuit 13 of FIG.

The semiconductor device constructed in the above-mentioned manner will be described below.

In the data processing circuit 14, when the node Q of the input section 14a is connected to the internal circuit 14b, when the output of the mask ROM 11 is "L", "L" is input to the internal circuit 14b of the data processing circuit 14, When the output of the mask ROM 11 is "H", "H" is input to the internal circuit 14b of the data processing circuit 13.

In addition, when the node NQ of the input unit 14a is connected to the internal circuit 14b, when the output of the mask ROM11 is "L", "H" is input to the internal circuit 14b of the data processing circuit 14, and when the output of the mask ROM11 is When the output is "H", "L" is input to the internal circuit 14b of the data processing circuit 14.

According to this embodiment, by switching the connection of the node Q or the node NQ of the input portion 14a of the data processing circuit 14 with the input of the internal circuit 14b, the data "0" or "1" of the mask ROM in FIG. 9 can be changed. Whether the drain of the memory cell Mij (i=1~m, j=1~n) is connected to the bit line BLj (j=1~n). As a result, the memory unit Mij can be reduced (i=1~m, j=1^~The number of drains of n) connected to the bit line BLj (j=1~n). In this way, it is possible to prevent the decrease in yield caused by the multilayer and miniaturization of wiring. Therefore, in the case where the semiconductor device (mask ROM) of the first to third embodiments of the present invention cannot be used, the above method can also be used to obtain the same effect.

In this embodiment, it is preferable to connect/non-connect the drain of the memory cell Mij to the bit line BLj by using the first contact portion (Via portion) that electrically connects the drain to the bit line. The formation/non-formation is obtained. The connection between the output terminal Q or NQ of the input part 14a of the data processing circuit 14 and the internal circuit 14b is achieved by electrically connecting the output terminal Q or NQ with the input terminal of the internal circuit 14b The formation of the second contact portion (Via portion) is obtained, and the first contact portion and the second contact portion are formed in the same step. Thereby, even if the memory data is determined or changed in the step of connecting the drain of the memory cell Mij to the bit line BLj, the logic change and the drain of the memory cell Mij and the bit line BLj can be changed in the same step. connect. As a result, the contact portion connecting the drain of the memory cell Mij and the bit line BLj can be reduced.

(Industrial availability)

The semiconductor device of the present invention has a method for reducing the connection between the memory cell of the mask ROM and the bit line, and is effective as a method for preventing the decrease in yield caused by the multilayering and miniaturization of wiring in the manufacturing process. In addition, the method of fixing the input of the sense amplifier during testing is also very useful for confirming the memory data of the mask ROM and the connection relationship between the memory cell and the bit line.

<p>1. . . Memory cell array</p><p>2. . . Row decoder</p><p>3. . . Sense amplifier</p><p>4. . . Charging transistor</p><p>5. . . Latch circuit</p><p>6. . . Output buffer circuit</p><p>7. . . Charging signal control circuit</p><p>8. . . Transistor for discharge</p><p>9. . . Row signal control circuit</p><p>10. . . Word line control circuit</p><p>11. . . Mask ROM</p><p>12. . . Buffer circuit</p><p>13. . . Data processing circuit</p><p>14. . . Data processing circuit</p><p>14a. . . Input section</p><p>14b. . . Internal circuit</p><p>BLj. . . Bit line</p><p>Cj. . . N-type MOS transistor</p><p>CLj. . . Line selection signal</p><p>D. . . Input</p><p>LCLK. . . Latch control signal</p><p>Mij. . . Memory unit</p><p>NLCLK. . . Latch control signal</p><p>OUT. . . Output terminal</p><p>PCLK. . . Charge control signal</p><p>PCLKA. . . Charge control signal</p><p>Q, NQ. . . Output</p><p>RESET. . . Gate input signal</p><p>TEST. . . Test control signal</p><p>WLi. . . Word line selection signal</p>

Fig. 1 shows the structure of a semiconductor device according to the first embodiment of the present invention.

Fig. 2 is a timing chart showing the operation of the semiconductor device according to the first embodiment of the present invention.

Fig. 3 shows the structure of a semiconductor device according to a second embodiment of the present invention.

4 is a timing chart showing the operation of the semiconductor device according to the second embodiment of the present invention.

Fig. 5 shows the structure of a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a timing chart showing the operation of the semiconductor device according to the third embodiment of the present invention.

Fig. 7 shows the structure of a semiconductor device according to a fourth embodiment of the present invention.

Fig. 8 shows the structure of a semiconductor device according to a fifth embodiment of the present invention.

Fig. 9 shows the structure of a conventional semiconductor device.

FIG. 10 is a timing chart showing the operation of the conventional semiconductor device.