A semiconductor device

Semiconductor device

The present invention relates to a semiconductor device having a semiconductor memory chip, for example, to an MCP (Multi Chip Package: multi-chip package) that is effectively applied to a semiconductor memory chip stacked with a TSOP (Thin Small Outline Package). Packaging) The technology of semiconductor device structure.

In the case of stacking two semiconductor memory chips of the same type to realize MCP, in both semiconductor memory chips, the bonding pads with the same interface function such as address input or data input and output are generally soldered to the same wire terminal . At this time, in the case of stacking two semiconductor memory chips of the same type with the back side facing each other, if the arrangement of the pads of the two semiconductor memory chips is exactly the same, all the pads with the same interface function The position becomes separate. As a result, it is necessary to wire the bonding pads in separate positions to the common wire terminal, or short-circuit and cross with other bonding wires, which becomes substantially difficult.

In order to solve this problem, a new mask pattern can be used to mirror the entire layer of the mask pattern to form a mirror-symmetrical chip, or to make only the pads mirror-symmetrical and form a chip with a modified wiring layer. correspond.

Patent Document 1 describes that when two identical semiconductor memory chips are stacked with the backside facing each other, the bonding pads with the same interface function are not restricted to each other, such as address input and data input and output. Connect each interface function of the same type, and select individual chips to realize a memory device with 2 times the memory capacity without the risk of signal conflict.

[Patent Document 1] Japanese Patent Laid-Open No. 7-86526

<p>However, in the case of forming a new mirror-symmetrical wafer that makes the entire layer of the mask pattern mirror inverted and changes the wiring layer, the cost of the semiconductor device will increase. In addition, the turnaround time of the semiconductor device will become longer and the wafer management It has also become complicated and new problems.</p><p>In the technology described in Patent Document 1, the access body of the access control memory device must change the address and the upper and lower positions of the data between the two semiconductor memory chips to access, and it needs to correspond to this new hardware. Body or software development.</p><p>The present inventors focused on the MCP structure of not only the same type of semiconductor memory chip, the change in the number of input and output data bits in parallel, the stacking with other types of memory chips, and the mounting of semiconductor memory chips on the card substrate. When accessing and controlling its controller chip, sometimes changing the interface function of the bonding pad of the semiconductor memory chip becomes the best policy. At this time, similar to the foregoing, in the formation of a new wafer that reverses the entire layer of the mask pattern and changes the wiring layer, the cost increases, the delivery time becomes longer, and the wafer management becomes complicated.</p><p>The purpose of the present invention is to provide: do not use the entire layer of mirror inversion mask pattern or metal wiring to select the mask mirror symmetry chip consistent, and does not add address or data upper/lower inversion to the access body The processing burden is a semiconductor device with a multi-chip package structure using a plurality of semiconductor memory chips.</p><p>Another object of the present invention is to provide: when the change of the number of input and output data bits is paralleled, the stacking with other forms of memory chips, and then the semiconductor memory chip and the controller chip for access control are mounted on the card substrate. In terms of changing the interface function of the bonding pads of the semiconductor memory chip, it is not necessary to form a new chip semiconductor device that reverses the mask pattern of the entire layer and changes the wiring layer.</p><p>The foregoing and other objectives and new features of the present invention should be apparent from the description of this specification and the drawings.</p>

<p>A brief description of the representative ones among the inventions disclosed in this application is as follows:</p><p>[1] The semiconductor device has a switching circuit (4A, 18A, 50, 51, 60, 70) on a semiconductor memory chip (1) on which a plurality of semiconductor elements and a plurality of external connection electrodes are formed. The aforementioned switching circuit selects the specific second external connection electrode (I/O1~I/O16, / CE, /WE,..., INA, INB, OUTA', OUTB') interface functions. Here, it is assumed that a semiconductor device of either a packaged form or an unpackaged chip form is a target.</p><p>By selecting the bonding pad for the first external connection electrode, the interface function for the second external connection electrode is switched. Therefore, when realizing a semiconductor device with a multi-chip package structure using a plurality of semiconductor memory chips, it is not necessary to use a whole The mirror-reversal mask pattern of the layer or the metal wiring are the same as the mirror-symmetric chip of the mask. In addition, it does not impose processing burdens such as address or data upper/lower inversion on the access body.</p><p>The specific form of the present invention is that the second external connection electrode set as the switching target of the interface function is the electrode for multiple-bit parallel input and output (I/O1~I/O16,...), and the electrode for control signal (/ CE, /WE,...). The external connection electrodes (VCC, VSS, VCCQ) supplying power are excluded from the switching object of the interface function. Switching of the interface function becomes the use of switches or logic gates. The switching of the power supply electrode requires a great current supply capacity for the aforementioned switches. Therefore, the external connection electrode for power supply is regarded as the switching object of the interface function. not realistic.</p><p>Another specific aspect of the present invention is that the aforementioned switching circuit (50, 54) switches the validity and invalidity of the interface function of the specific second external connection electrode. For example, when the maximum number of parallel data input and output bits is 16 bits, it is selectively set to 8 bits.</p><p>Another specific aspect of the present invention is that the aforementioned switching circuit (60, 70) switches the interface function between specific second external connection electrodes. For example, when the number of parallel data input and output bits is 8 bits, the first and eighth bits, the second and seventh bits, the third and sixth bits, and the The 4th and 5th digits. Using this replacement function, if the same semiconductor memory chip is overlapped to realize a multi-chip package structure in consideration of backside butting, the second external connection electrode set as the replacement object of the interface function has a pair of semiconductor memory chips on the back side What is necessary is just to arrange them in a state of overlapping with each other so that the front and back directions are almost the same. In other words, the second external connection electrode to be replaced by the interface function may have a symmetrical arrangement centered on the specific external connection electrode among the external connection electrodes arranged on one side of the chip . As a result, when the same semiconductor memory chip is overlapped with the backside butt, the specific second external connection electrode with the same function is used at almost the same position on the front and back, which can avoid the common connection of the second external connection electrode with the same function to The welding wires of the same wire terminal are in contact with other welding wires.</p><p>In yet another aspect of the present invention, the aforementioned semiconductor memory chip may further include: through pad selection, according to the potential state applied to the third external connection electrode, to switch the control of the input from the specific external connection electrode Function control circuit (10A).</p><p>For example, in the control circuit, when the third external connection electrode (BOAdU) is in the first potential state, the address of the semiconductor memory chip inputted in the address input period is one bit above the uppermost bit ( When I/O7) is the first logic value, it is judged that the command input of the aforementioned address input cycle is invalid. When the bit of the previous bit is the second logic value, it is judged that the command input of the position input cycle is valid. 3 When the external connection electrode is in the second potential state, the bit above the uppermost bit of the address of the semiconductor memory chip input in the address input period is ignored. When the address, data, and external connection electrodes of the chip selection are commonly connected between the same type of semiconductor memory chips to make the MCP structure, the same type of semiconductor memory chips can be selected for access, The address space visible from the outside of the semiconductor device can be expanded. In the utilization form where the same type of semiconductor memory chip is used as individual chip selection, the aforementioned third external connection electrode is assumed to be in the second potential state. In the above-mentioned MCP structure, in the utilization mode of making the chip selection and address input of the same type of semiconductor memory chips common, regarding one semiconductor memory chip, the third external connection electrode is set to the first potential state, Regarding another semiconductor memory chip, when the third external connection electrode is set to the second potential state, and the bit above the uppermost bit of the address is the first logic, the access of the other semiconductor memory chip is The action is set to be possible, and when the previous bit is the second logic, the action of the aforementioned semiconductor memory chip is set to be possible.</p><p>In the foregoing, when there is an instruction for a read operation without address input, when the third external connection electrode is in the first potential state, the start of the read operation is suppressed. In short, when it is instructed that the power of the semiconductor memory chip is turned on, the initial setting data stored in the non-volatile memory element is output to the outside, and the power is turned on for initial loading and reading, etc. , The aforementioned one semiconductor memory chip and the other semiconductor memory chip both act, read data conflicts caused by improper actions can be prevented in advance, and it can be made that only one side can perform power-on reading and so on.</p><p>[2] Regarding the other semiconductor devices of the present invention, especially the packaged form as the object, a semiconductor memory chip in which a pair of a plurality of bonding pads is arranged is laminated on the edge part, and the terminal of the package and the corresponding The structure where the bonding pads are connected by bonding wires. The aforementioned semiconductor memory chip includes a switching circuit for changing the interface function between specific second bonding pads in response to the first potential state or the second potential state of the first bonding pad selected based on the bonding pads. The second pad that is set as the replacement target of the aforementioned interface function is the pad for multiple-bit parallel input and output, and the specific pad selected by the control signal input pad is set as the replacement of the aforementioned interface function The solder pads of the object have a state where the back sides overlap each other, so that a pair of semiconductor memory chips are arranged in the same front and back directions. One of the pair of semiconductor memory chips is soldered so that the first pad becomes the first potential state, and the other semiconductor memory chip is soldered so that the first pad becomes the second potential state.</p><p>For example, when the number of parallel data input and output bits is 8 bits, the aforementioned switching circuit of the interface function is replaced between the specific second pads, and the first bit, the 8th bit, and the second bit are selectively changed. Yuan and 7th bit, 3rd and 6th bit, 4th and 5th bit. Using this replacement function, for example, when a multi-chip package structure is realized by overlapping the aforementioned pair of semiconductor memory chips with the back side butt, the second pads set as the replacement target of the interface function are those with the same function, and the back side overlaps each other. In this state, a pair of semiconductor memory chips are arranged almost in the same front and back directions. Therefore, the second bonding pads of the same function can be prevented from being connected to the bonding wires of the same wire terminal in common with other bonding wires.</p><p>In a specific aspect of the present invention, a TSOP (Slim Small Outline Package) package structure is adopted as the aforementioned package structure, and in this case, the terminals of the aforementioned package are set as lead terminals (31). In the TSOP (Slim Small Outline Package) package structure, the contact avoidance between the bonding wires (32) needs to be matched by the configuration of the bonding pads.</p><p>Another specific aspect of the present invention is that the aforementioned package structure has a CSP (Chip Size Package) structure, and the terminals of the aforementioned package are formed as bonding pads (42) formed on the surface of the package substrate (41). The case where the signal wiring layer is mounted on both sides of the single-layer package substrate with the same type of semiconductor memory chip is the same as described above. When using a multilayer wiring board to mount the same type of semiconductor memory chips on both sides, if the structure of the wiring layer of the multilayer wiring board becomes complicated, it is possible to use two memory chips with exactly the same configuration and structure of the pads. Correspondingly, however, the cost of this type of multilayer wiring board is extremely higher than that of a single-layer wiring board.</p><p>[3] Regarding another semiconductor device of the present invention, a semiconductor memory chip having a plurality of solder pads arranged on the edge portion, and the terminals of the mounting substrate and the corresponding solder pads are connected by bonding wires. The aforementioned semiconductor memory chip includes the first potential state of the first bonding pad, which enables the signal interface function of the bonding pads arranged on the edge portion of the specific side of the semiconductor memory chip to become effective, so that the signal interface function of the bonding pads arranged on the semiconductor memory chip is enabled. The signal interface function of the pad on the edge portion of the chip on the other side becomes an invalid switching circuit, and the first pad is soldered to a terminal on the mounting substrate for making it into the first potential state. This is suitable for the use of bonding pads on one side of the semiconductor memory chip to the terminals of the mounting substrate.</p><p>The specific form of the present invention is a controller chip (20) having access control to the semiconductor chip. In the semiconductor memory chip, the second bonding pad whose interface function is set to be effective is connected to the controller chip. Memory interface terminal. The external interface terminal of the controller chip is connected to the external interface terminal (24) of the mounting substrate (22). The aforementioned controller chip has, for example, a card main interface function that complies with a specific memory card specification, and the semiconductor device is set in a form suitable for the memory card.</p><p>[4] The semiconductor device of the present invention based on the viewpoint of the switching circuit focusing on the selection of the output path has an output switching circuit on a semiconductor memory chip formed with a plurality of circuit elements and a plurality of external connection electrodes (70) The aforementioned output switching circuit responds to the state where the first voltage is applied to the first external connection electrode (BOP), and selects the first signal (OUTA) to be formed by the first circuit (71) formed by the specific circuit element. ) Output to the output path of the second external connection electrode (OUTA'), and output the second signal (OUTB) formed by the second circuit (72) formed by the specific circuit element to the third external connection electrode ( The output path of OUTB') responds to the state where the second voltage is applied to the first external connection electrode, and selects to output the first signal to the third external connection electrode output path, and to output the second signal to the first 2External connection electrode output path.</p><p>The semiconductor device of the present invention, based on the viewpoint of the switching circuit focusing on the selection of the input path, has an input switching circuit (60) on a semiconductor memory chip formed with a plurality of circuit elements and a plurality of external connection electrodes. The switching circuit responds to the state where the first voltage is applied to the first external connection electrode, and selects the first signal input from the second external connection electrode (INA) to the first circuit (65) formed by the specific circuit element The input path, and the input path of the second circuit (66) formed by the specific circuit element to the second signal input by the third external connection electrode (INB), in response to the first external connection electrode being applied to the first external connection electrode 2 Voltage state, and select the input path of the first signal input from the second external connection electrode to the second circuit, and the input path of the second signal input from the third external connection electrode to the first circuit .</p><p>[5] In the semiconductor device based on the switching circuit and other viewpoints, a semiconductor chip formed with a plurality of circuit elements and a plurality of external connection electrodes has a switching circuit. Programming state, and switch the function of the external connection electrode interface. The aforementioned fuse is set to be a laser fuse that responds to information memory based on laser switching, an electrical fuse that responds to information memory based on Joule heat cutting, or it can be erased and written electrically. The flash fuse.</p><p>The aforementioned flash fuse is excluded from the interface function switching function of the reset external connection electrode for inputting the instruction of the reset action. Usually the memory information of the flash fuse is read out by responding to the instruction of the reset action, and is initially set in the internal register, etc., so when the instruction of the reset action is input, the external reset is used The use of flash fuse is not appropriate for the switching purpose of the interface function of connecting the electrode.</p>

<p>To briefly explain the outline of the representative ones of the inventions disclosed in this application, it is as follows: That is, it is not necessary to use the entire layer of mirror-reversed mask patterns or metal wiring to select the mirror-symmetric chip of the mask to be consistent, and it is not correct The access body adds the processing burden of address or data upper/lower inversion, etc., and a semiconductor device with a multi-chip package structure using a plurality of semiconductor memory chips can be realized.</p><p>In addition, when the change of the number of input and output data bits is paralleled, the stacking with other forms of memory chips, and the semiconductor memory chip is mounted on the card substrate and the controller chip for access control is changed when the semiconductor memory chip is changed. In terms of the interface function of the pad, it is not necessary to form a new chip that reverses the mask pattern of the entire layer and changes the wiring layer.</p>

&lt;&lt;Flash memory chip&gt;&gt;

FIG. 1 is a semiconductor memory chip related to the semiconductor device of the present invention, showing an example of a flash memory chip. The semiconductor memory chip 1 is formed on a semiconductor substrate such as single crystal silicon.

The one shown in 3 is a memory array (MRY), which has a memory pad and a sensing latch circuit. The memory pad 3 has a large number of non-volatile memory cell transistors that can be erased and written electrically. Although the memory cell transistors are not specifically shown, they can use a stacked gate structure in which a control gate is overlapped with a floating gate by an insulating film, or a tandem arrangement selection transistor and a memory transistor with a silicon nitride film can be divided Appropriate memory cell structure such as gate structure. For example, in the case of a non-volatile memory cell transistor with a stacked gate structure, the control gate is connected to the word line, the drain is connected to the bit line, and the source is connected to the source line. Although there are no special restrictions on the erasing action of the non-volatile memory cell transistors of the stacked gate structure, it can be set to apply a high voltage to the control gate to make the electrons of the floating gate move in the direction of release, so that the threshold voltage is changed. Low action. Although the writing operation of the non-volatile memory cell transistor of the stacked gate structure is nothing special, it is set to apply a high voltage to the drain and inject electrons into the floating gate to increase the threshold voltage. The read operation is set to take the specific voltage between the low threshold voltage based on the erase operation and the high threshold voltage based on the write operation as the word line selection level. When the memory cell transistor is selected, check The action of changing the current flowing out of the bit line or the level of the bit line to read the memory information.

The external input and output terminals I/O1~I/O16 are also used as address input terminals, data input terminals, data output terminals, and command input terminals, which are connected to multiplexer 4. The sector address input to the external input and output terminals I/O1~I/O16 is input to the sector address buffer (SABUF) 5 by the multiplexer (MPX) 4, and the Y address (column address) is multiplexed The device 4 is preset in the Y address counter (YACUNT) 6. The write data input to the external input and output terminals I/O1~I/O16 are supplied to the data input buffer 7 (DIBUF) by the multiplexer 4, and the read data output from the data output buffer (DOBUF) 8 It is output from the external input and output terminals I/O1~I/O16 through the multiplexer 4.

A part of the command codes and address signals supplied to the external input and output terminals I/O1~I/O16 is supplied to the internal control circuit (IPCNT) 10 by the multiplexer 4.

The sector address supplied to the sector address buffer 5 is decoded by the X decoder (XDEC) 9. According to the decoding result, the memory array 3 selects the word line. Although the Y address counter 6 whose Y address is preset is not limited, it is set to an 11-bit counter, and the address is counted with the preset value as the starting point, and the Y decoder (YDEC) 11 outputs sequentially Y gate (YGAT) 12 selection signal. The Y gate 12 makes the 2048-byte data register (DREG) 13 turn on the byte output of the input data controller (IDCNT) 15 in byte units, or turn on the bit of the data output buffer 8 Tuple input. For example, if the address in the middle of the sector is preset in the Y address counter 6, during the data output operation, the sector data read from the data register 13 starts from its previous address , Are sequentially supplied to the data output buffer 8 from the Y gate 12 in byte units. In addition, in the data input operation, the data supplied to the input data controller 15 from the input data buffer 7 is The front-end address is the starting point, and the Y gate 12 is latched in the data register 13 in byte units.

As external access control signals, there are chip enable signal/CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal/WE, read enable signal/RE, write protection signal/ WP, power-on/read start signal PRE, and reset signal/RES are supplied to the control signal buffer (CSBUF) 18. The mark "/" placed before the signal means that the signal is activated at a low level.

The chip activation signal/CE is a signal for selecting the flash memory chip 1. The flash memory chip (device) 1 is active at a low level, and the flash memory chip 1 is in a standby state at a high level. The read start signal REb controls the data output timing from the external input and output terminals I/O1~I/O16, and the data is read out in synchronization with the clock pulse change of the signal. The write enable signal /WE is an instruction to fetch the command, address and data into the flash memory chip 1 with its rising edge. The command latch start signal CLE is a signal that takes the data supplied from the outside to the external input and output terminals I/O1~I/O16 as the command data and specifies it. The data of the output terminals I/O1~I/O16 are in CLE="H" In the state of (high level), it is taken in synchronously with the rising edge of /WE and recognized as a command. The address latch activation signal ALE is a signal that takes the data supplied from the outside to the external input and output terminals I/O1~I/O16 as the address and specifies the signal. The data of the output terminal I/O1~I/O16 is in ALE="H "(High level) state, it is taken in synchronously with the rising edge of /WE, and recognized as an address. The write protection signal /WP sets the flash memory chip 1 to be erased and write prohibited by the low level. The power-on/read start signal PRE is set to start when the power-on read function that reads the data of a specific sector is used after the power is turned on without input of commands and addresses. The reset signal /RES is converted from a low level to a high level after the power is turned on to instruct the flash memory chip 1 to initialize.

If the operation modes of address input, command input, and data input/output of the flash memory chip 1 indicated by the aforementioned access control signal are sorted and displayed, it is as shown in Figure 2.

The internal control circuit 10 performs interface control based on the operation mode shown in FIG. 2 and at the same time controls internal operations such as erasing, writing, and reading based on the command mode. Figure 3 shows an example of the definition of commands supported by the flash memory chip 1. The internal control circuit 10 outputs the standby/busy signal R/B and the master reset signal/MRES. The standby/busy signal R/B is based on the low level of the flash memory chip 1 to notify the outside of the busy state during the operation of the flash memory chip 1. The main reset signal/MRES is a signal that can be used as a reset signal to an external CPU (central processing unit) or flash memory controller when the power is turned on/read function. The change to the higher level informs that the read data can be outputted externally by turning on the power/reading. It is used as a convenience for the CPU, etc. to use the data read by power-on/read as the initial data.

FIG. 4 shows an example of the read operation cycle controlled by the internal control circuit 10. In the command input mode, the read mode command "00H" is input. Then, in the address input mode, the column addresses CA1 and CA2 are input, and the sector addresses SA1 and SA2 are input. According to the input sector addresses SA1 and SA2, the data of the sector is internally transferred from the memory array 3 to the data register 13, and the transferred data is selected by the Y gate 12 starting from the row address ,Sequentially synchronized with the clock pulse change of the read start signal REb, the read data is output from the output terminals I/O1~I/O16.

&lt;&lt;Switching the interface function by pad selection&gt;&gt;

The switching of the interface function by the pad selection of the flash memory chip 1 is described. This switching function is realized by, for example, the switching circuit held by the multiplexer 4 or the control signal buffer 18. The switching circuit is based on the potential state applied to the first pad by the pad selection to switch the specific first pad. 2 Interface function of the pad. First, explain several switching modes.

&lt;&lt;Switch form of interface function&gt;&gt;

5 and 6 are examples of the switching modes of the interface functions of the pads of the flash memory chip 1. The same figure shows an example of 11 forms. Due to the relationship with the size of the drawing, each form is displayed across Figures 5 and 6. The pad number PAD# is 1~63. PAD#1~PAD#30 are arranged in a row along the left long side of the flash memory chip 1, and PAD#31~PAD#63 are arranged in a row along the right long side of the flash memory chip 1. . The pads used for pad selection (pad selection pads) are set to BONAND of PAD#11, BO1.8 of PAD#13, BOSTD of PAD#15, PROBE of PAD#17, BOMIR of PAD#34, BOX8 of PAD#45, BO1.8 of PAD#47, BOAdU of PAD#59, BOCE1 of PAD#61. Figure 7 shows the function and setting method of the pad selection pad in a list. The pad selection BO1.8 determines the operating power of the external interface circuit to be 3.3V or 1.8V. BOCE decides to set /CE1 as valid or /CE2 as valid. BOX8 decides whether to use I/O in 16-bit parallel or 8-bit parallel. BONAND decides to use the flash memory chip to support (super_AND) or not (NADN) ECC function or storage adjustment function. The details of the other function settings of the pad selection by pad are described in the following.

In Figures 5 and 6, the second pad, which is set as the switching target of the interface function, is the electrode for the parallel input and output of the plural bits shown in I/O1~I/O16, and is used by /RE or / Welding pad for control signal input represented by CE, etc. The pads that supply power represented by VCC, VSS, etc. are excluded from the switching object of the interface function. In the interface function switching, it becomes the use of switches or logic gates. This is the switching of the power supply pads. The aforementioned switches and the like require a large current supply capacity. Therefore, the power supply pads should be used as the interface function switch The object is not feasible in reality. In Figures 5 and 6, the function of the pads for the power supply voltage VCC, the power supply voltage VCCQ (power supply voltage for the external input and output interface), and the ground voltage VSS of the circuit has not changed in any form. In the marks in Figures 5 and 6, the pads of the signal enclosed by the double frame refer to the pads that can be used for the interface function at that time. Other solder pads refer to unusable solder pads.

The shapes shown in Figures 5 and 6 are set to MMC, NAND16, NAND8, CORE16 (MCP-A), CORE16 (MCP-B), CORE8 (MCP-A), CORE8 (MCP-B), MIRROR16 ( MCP-A), MIRROR16 (MCP-B), MIRROR8 (MCP-A), MIRROR8 (MCP-B).

The MMC form is most suitable for the mounting form of MultiMediaCard (MultiMediaCard is a registered trademark of InfineonTechnologies AG. Hereinafter, it is abbreviated as "Multimedia Card".). The PROBE of PAD#17 is connected to the pad of ground potential VSS. The pad on the side becomes available. Although the power supply pad on the right is as mentioned above, it can be used often, but in fact, it does not need to be used at this time. This is because there are a necessary number of power pads on the left and right sides of the chip. Fig. 8 shows an example of the MMC form where the flash memory chip 1 is mounted on the multimedia card. 20 is the controller chip that accesses the flash memory chip 1. Among the pads 19 of the flash memory chip 1, the pad 19 on the left side of the one side where the interface function is enabled is wired The solder pad 21 on the substrate 22 of the memory card. The bonding pad 21 is connected to the memory interface terminal of the controller chip 20 by the wiring (not shown) on the memory card substrate 22. The external interface bonding pad 23 of the controller chip 20 is wired to the external interface terminal 24 of the memory card substrate 22. The controller chip 20 has a card main interface function that complies with the memory card specifications of the multimedia card.

The NAND16 form and the NAND8 form have the interface function (STANDARD) when the standard interface of the flash memory is selected by connecting the pad selection pad BBSTD of PAD#15 to VSS. Especially the pad BOX8 is set to open (floating) by the pad selection, and the 16-bit parallel interface function of I/O1~I/O16 is selected. It is NAND16. The pad is selected by the pad. BOX8 is connected to VCC, and the 8-bit parallel interface function of I/O1~I/O8 is selected, it is NAND8.

The MCP core form and MCP mirror form in Fig. 5 and Fig. 6 are the forms in which the flash memory chip 1 is applied to the MCP structure. The function of the pad is relative to the MCP core form on one side and the MCP on the other side. In the mirrored form, when the back is mated, the same functional terminals are almost at the same position on the front and back, and are arranged symmetrically. For example, the form of CORE16 (MCP-A) and the form of MIRROR16 (MCP-A) correspond to each other. In the pad arrangement on the right side of the chip in Figure 6, the arrangement of I/O1~I/O16 is for PAD#46 and PAD The boundary of #47 is arranged in line symmetry. In the pad arrangement on the left side of the chip in Figure 5, the arrangement of CLE, /WE, /WP, /CE2, and ALE is almost line-symmetrical to the boundary between PAD#14 and PAD#15. The difference between CORE16 and CORE8 is the 16-bit parallel interface function of I/O1~I/O16, or the 8-bit parallel interface function of I/O1~I/O8. The difference between the form of MCP-A and MCP-B is based on chip activation, using /CE1 or /CE2. In addition, in each figure, Vmoni1~Vmoni4 are dedicated solder pads for testing and are not considered as solder pad selection objects.

Figures 9 to 19 show the interface functions of the pads of the flash memory chip 1 selected by the switching modes shown in Figures 5 and 6, and the settings of the pad selection pads state. The terminals of the double frame are solder pads that can be used in this switching mode. Figure 9 corresponds to the MMC form. Figures 10 and 11 correspond to the standard forms of NAND8 and NAND16. Figures 12 and 13 show the mirroring of the 8-bit MCP core and 8-bit MCP of MCP-A. Figures 14 and 15 show the mirrored form of the 8-bit MCP core and 8-bit MCP of MCP-B. Figures 16 and 17 show the mirroring of the 16-bit MCP core and 16-bit MCP of MCP-A. Figures 18 and 19 show the mirroring of the 16-bit MCP core and the 16-bit MCP of MCP-B.

&lt;&lt;MCP structure semiconductor device&gt;&gt;

Fig. 20 is a schematic longitudinal cross-sectional view showing a semiconductor device having an MCP structure. This is assembled using a lead frame for TSOP (Slim Small Outline Package), and the two sides of the solder joints 30 are arranged so that the back faces are opposed to each other, and the flash memory chip 1 is mounted on a pair. 31 is the representative wire shown. For the terminal, 32 is a representative welding wire, and 33 is a sealing resin. Figure 21 shows a reference example of the planar structure when assembled with a lead frame for TSOP (Slim Small Outline Package). In order to simplify the drawing, the reference example in Figure 21 shows that the number of solder pads and wire terminals is less than the actual number.

As mentioned above, the bonding pads used as the replacement target of the interface function have a configuration in which a pair of semiconductor memory chips overlap each other on the back side, and the front and back directions are almost identical to each other. In other words, the solder pads set as the replacement target of the interface function have a symmetrical arrangement centered on the specific solder pads arranged in the solder pads on one side of the chip. As a result, when the backsides of the flash memory chips 1 of the same type are butted and overlapped, the solder pads with the same function, such as I/O1~I/O16, are almost at the same position on the front and back, and the same function is soldered. The bonding wires whose pads are commonly connected to the same wire terminal can avoid contact with other bonding wires. In the case of a package structure with a TSOP (Slim Small Outline Package) as the main body, it is impossible to use a package substrate with multiple signal wiring layers like a CSP (chip size package). Therefore, the path of the bonding wires must not be crossed in multiple ways. Thereby, when realizing a semiconductor device with a multi-chip package structure using a plurality of flash memory chips 1, it is not necessary to make the mirror-symmetrical wafers of the mirror-reversal mask pattern using the full wiring layer or the selective mask of the metal wiring consistent. In addition, there is no need to add processing burdens such as address or data upper/lower reversal to the access subject.

Fig. 22 is a schematic longitudinal cross-sectional view showing another semiconductor device having an MCP structure. The difference from FIG. 20 is that the flash memory chip on one side and the other memory chip 40 are stacked. For example, when the flash memory chip 1 is of the AND type, the memory chip 40 is assumed to be a NOR (or) type flash memory chip. It can be used separately according to the type of memorized information. The AND type increases the capacity and the NOR type random access performance is improved.

&lt;&lt;Semiconductor device with CSP (chip size package) structure&gt;&gt;

Figure 23 shows an example of the planar structure of the semiconductor device when the package structure adopts the CSP (chip size package) structure. 41 is a CSP (Chip Size Package) substrate. On the mounting surface of the flash memory chip 1, there are formed most of the bonding pads 42 wired to the bonding pads 19 of the chip 1. In the case of mounting one flash memory chip 1, a solder bump electrode (not shown) connected to the pad 42 is formed on the back of the CSP (chip size package) substrate 41. The solder bump electrode It is mounted on the mounting board. The CSP (chip size package) substrate can adopt any structure in which the signal wiring layer is a single layer or multiple layers. If there are many signal wiring layers, the wiring can be routed freely in the CSP (chip size package) substrate. Therefore, although the positions of the solder bump electrodes and the pads 42 can be freely arranged, the cost of the CSP (chip size package) substrate Significant increase. When the same type of memory chips are mounted on both sides of the CSP (chip size package) substrate, such as CORE8 (MCP-A) and MIRROR8 (MCP-A), a pair of flash memory chips with switching interface functions are used 1 This is the best policy. This is the relationship that a single-layer signal wiring substrate can be used for a CSP (chip size package) substrate.

FIG. 33 shows an example of the longitudinal cross-sectional structure of another semiconductor device using a CSP (chip size package) structure. Figure 34 shows its plan structure. 80 is a CSP (chip size package) substrate, on which two flash memory chips 1a, 1b, and a different type of semiconductor chip 83 are mounted. Solder ball electrodes 85 are formed on the back of the CSP (chip size package) substrate 80, and on the surface are solder joints 87 carrying bump electrodes 86 of one flash memory chip 1a, and connected to other chips 1b The soldering pad 88 of 83, the aforementioned soldering joint 87, the soldering pad 88 and the solder ball electrode 85 are achieved by the wiring layer in the CSP (chip size package) substrate 80, which is not shown in the figure, to achieve the required connection state.

Even if both of the flash memory chips 1a and 1b are flash memory chips (core chips) 1 of the aforementioned MCP core form, or one of them 1a is the core chip 1, and the other 1b is the aforementioned MCP mirrored form of flash Memory chips (mirror chips) can also be used. If the core chip and the mirror chip are used, the wiring of the CSP (chip size package) substrate 80 can be simplified. In terms of the shape of the CSP (chip size package) substrate 80, if the wiring becomes complicated, it will not be hindered if both chips 1a and 1b are core chips. The other semiconductor chips 83 are, for example, other circuit types, such as NOR flash memory chips. The bonding pads 90 and 91 formed on the chips 1b and 83 are wired to the aforementioned bonding pad 88. For example, when the bonding pad 88a that is commonly connected to the bonding pads 90 and 91 of the chips 1b and 83 is an address bonding pad, the chip selection is performed individually for each chip 1b and 83. Although not shown in particular, the chip 1a also shares the address input with the other chips 1b and 83, and the chip selection is individualized.

&lt;&lt;Specific Examples of Switching Circuit&gt;&gt;

Here, a specific example of the switching circuit will be described. The aforementioned switching circuit switches the interface function of the specific signal pad according to the potential state applied to the pad selection pad. From the description of the function of the pad selection electrode in Fig. 7, it can be understood that the first switching form of the switching circuit is to switch between valid and ineffective the interface function of the pad for a specific signal. For example, in the case of selectively making I/O1~I/O16 unusable. The second switching mode is to replace the interface function between multiple signal pads. For example, when the number of parallel data input and output bits is 8 bits, selectively replace I/O1 and I/O8, I/O2 and I/O7, I/O3 and I/O6, I/O4 and I/ O5 situation.

Fig. 24 shows an example of the switching circuit of the first switching mode. The example in the same figure is a circuit that selects the solder pads for signal input. INA and INB are the signal input pads, and the BOP is the pad selection. The input from the signal input pads INA and INB is set to be communicated to the later stage in the chip selection state by /CE. The input from the pad selection pad BOP is used as complementary signals SEL1 and /SEL1 to be supplied to the input switching circuit 50. The input switching circuit 50 has an input gate circuit 51 that takes in the input signal from the signal input pad INA when the signal SEL1 is high, and takes in the input from the signal input pad INB when the signal /SEL1 is high. The input gate circuit 52 of the signal, the output of the input gate circuit 51 and the output of the input gate circuit 52 are connected to the internal circuit 53 by bonding wires/or (wired OR). In the pull-up state of the pad selection pad BOP, the input function of the signal input pad INA is set to be valid, and the input function of the signal input pad INB is set to be invalid. In the pull-down state of the pad selection pad BOP, the signal input function becomes the opposite.

Fig. 25 shows another example of the switching circuit of the first switching mode. The example in the same figure is a circuit for selecting solder pads for signal output. The input from the pad selection pad BOP is used as complementary signals SEL2 and /SEL2 and is supplied to the output switching circuit 54. The output switching circuit 54 has the output gate circuit 55 that transmits the read start signal RE to the subsequent output gate when the signal SEL2 is high level, and transmits the read start signal RE to the subsequent output gate when the signal /SEL2 is high level Circuit 56. OUTA' and OUTB' are the signal output pads, and the BOP series pads are selected as pads. The signal output pads OUTA' and OUTB' are combined with the output terminals of the output buffer circuits 57 and 58. The output buffer circuit 57 outputs the output data OUT supplied by the internal circuit 59 to the signal output pad OUTAwhen the output of the output gate circuit 55 is at a high level. The output buffer circuit 58 outputs the output data OUT supplied by the internal circuit 59 to the signal output pad OUTBwhen the output of the output gate circuit 56 is at a high level. In the pull-up state of the pad selection pad BOP, the output function of the signal output pad OUTA' is set to be valid, and the output function of the signal output pad OUTB' is set to be invalid. In the pull-down state of the pad selection pad BOP, the signal output function becomes the opposite.

Fig. 26 shows an example of the switching circuit of the second switching mode. The example in the same figure is a circuit that replaces the function of the signal input pad. INA and INB are the signal input pads, and the BOP is the pad selection. The input from the signal input pads INA, INB is in the chip selection state by /CE, and is set to be communicated in the later stage. The input from the pad selection pad BOP is used as complementary signals SEL1 and /SEL1 and is supplied to the input switching circuit 60. The input switching circuit 60 has an input gate circuit 61 that takes in the input signal from the signal input pad INA when the signal SEL1 is high, and takes in the input signal from the signal input pad INA when the signal /SEL1 is high. When the input gate circuit 62 of the signal /SEL1 is high level, the input gate circuit 63 that takes in the input signal from the signal input pad INB, and when the signal SEL1 is high level, the input signal from the signal input pad INB is taken in Input gate circuit 64. The output of the input gate circuit 61 and the output of the input gate circuit 63 are connected to the internal circuit 65 by wire bonding or bonding. The output of the input gate circuit 62 and the output of the input gate circuit 64 are connected to the internal circuit 66 by wire bonding or bonding. In the pull-up state of the pad selection pad BOP, the input from the signal input pad INA can be input to the internal circuit 65 through the input gate circuit 61, and the input from the signal input pad INB can be input through the input gate The circuit 64 is input to the internal circuit 66. In the pull-down state of the pad selection pad BOP, the signal input function is switched, and the input from the signal input pad INA can be input to the internal circuit 66 through the input gate circuit 62, and the input from the signal input pad INB The input can be input to the internal circuit 65 through the input gate circuit 63.

Fig. 27 shows another example of the switching circuit of the second switching mode. The example in the same figure is a circuit that replaces the output function of the solder pad for signal output. The input from the pad selection pad BOP is used as complementary signals SEL2 and /SEL2 and is supplied to the output switching circuit 70. The output switching circuit 70 has, when the signal SEL2 is at a high level, the output OUTA of the internal circuit 71 is selected, and when the signal SEL2 is at a low level, the output OUTB of the internal circuit 72 is selected and transmitted to the output gate circuit (output selection circuit) 73 in the subsequent stage , And when the signal /SEL2 is at a high level, the output OUTA of the internal circuit 71 is selected, and when the signal /SEL2 is at a low level, the output OUTB of the internal circuit 72 is selected and transmitted to the output gate circuit (output selection circuit) 74 of the subsequent stage. The output gate circuits 73 and 74 are composed of p-channel MOS transistors MP1~MP4 and n-channel MOS transistors MN1~MN4. MP3 and NM4 selectively block the transmission path of the signal OUTB, and MP2 and MN2 are selected It is constituted by sexually blocking the transmission path of the signal OUTA. OUTA', OUTB' are signal output pads. The signal output pads OUTA' and OUTB' are combined with the output terminals of the output buffer circuits 75 and 76. The output buffer circuit 75 outputs the output of the output gate circuit 73 to the signal output pad OUTAwhen the read start signal RE is in the active state (high level). The output buffer circuit 76 outputs the output of the output gate circuit 74 to the signal output pad OUTBwhen the read start signal RE is in the active state (high level). In the pull-up state of the pad selection pad BOP, SEL2 is set to a high level and /SEL2 is set to a low level. Therefore, the output pad OUTA' is assigned as the output of the output signal OUTA of the internal circuit 71. The pad OUTB' is allocated as the output of the output signal OUTB of the internal circuit 72. In the pull-down state of the pad selection pad BOP, contrary to the foregoing, SEL2 is set to a low level, and /SEL2 is set to a high level. Therefore, the output pad OUTA' is assigned as the output of the output signal OUTB of the internal circuit 72 , The output pad OUTB' is allocated as the output of the output signal OUTA of the internal circuit 71.

&lt;&lt;Switching the control function by pad selection&gt;&gt;

Next, the switching of the control function by pad selection is explained. Here, the switch function of selecting the bonding pad BOAdU by the bonding pad shown in Fig. 7 is explained. This function is realized by the control unit (CNT) 10A (refer to FIG. 1) held by the aforementioned internal control circuit 10.

When the pair of flash memory chips 1 described in FIG. 20 is mounted, the pads for address, data, and chip selection are commonly connected between the flash memory chips 1 to form an MCP structure. At this time, select the flash memory chip 1 individually and make the access action as shown in Figure 28. The address space of 0000~3FFF is allocated to the flash memory chip on one side and the flash memory chip on the other side. The memory chip is allocated with an address space of 4000~7FFF, and individual address spaces need to be allocated in this way. In the same condition, the flash memory chips 1 of both sides are arranged in the same space, but they are simply parallel operations.

Therefore, when the bonding pad selection pad BOAdU is opened, the lower address space is allocated to the flash memory chip, and when the bonding pad selection pad BOAdU is set to the ground potential VSS, the flash memory chip is allocated Upper side address space. For the allocation of the aforementioned address space of the chip, the value of I/O7 in the address input cycle of SA2 described in Figure 4 is used. That is, when the pad selection pad BOAdU is set to the ground potential VSS, the I/O7 value of the address input cycle of SA2 is taken as the high level as its condition, and the command input for the address input cycle is set to be valid. If the value of I/O7 is low, the instruction input of the address input cycle becomes invalid and no access action is performed. When the pad selection pad BOAdU is set to open, the value of I/O7 in the address input cycle of SA2 is ignored.

Here, the input of I/O7 of the address input cycle of SA2 is positioned as a bit above the uppermost bit of the address of the flash memory chip 1. In the case of using the flash memory chip where the action of the x8 device of I/O1~I/O8 is selected, the address input form of the address input cycle is as shown in the example in Figure 29, set to column position The address is 11 bits, and the sector address is 14 bits. The high-level input from I/O7 above it is regarded as the access request for the upper space. In the case of using the flash memory chip where the action of the x16 device of I/O1~I/O16 is selected, the address input form of the address input cycle is shown as an example in Figure 30, and the column address is set It is 10 bits, and the sector address is 14 bits. The uppermost bit A23 of the sector addresses SA1 and SA2 is input to I/O6, and the higher-level input from I/O7 of the upper bit is regarded as an access request for the upper space. In addition, in Figures 29 and 30, the symbol L^＊It means to be used at a low level. In addition, the symbol L/H means that it can be set to a low level or a high level.

In the aforementioned MCP structure illustrated in FIG. 20, when the chip selection and address input of the flash memory chip 1 are used in common, for one flash memory chip 1, a pad selection pad is set BOAdU is open. Regarding the other flash memory chip 1, set the pad selection pad BOAdU to pull down to the ground potential VSS. When the input from I/O7 of the address input cycle SA2 is high, the other flash memory mentioned above The access action of the chip 1 becomes possible. When the input from the I/O7 is low level, the action of the aforementioned flash memory chip becomes possible. Thereby, when the external connection electrodes for address, data, and chip selection are commonly connected between the flash memory chip 1 to form an MCP structure, the flash memory chip 1 can be selected for access, Expand the address space seen by the outside of the semiconductor device.

In the aforementioned MCP structure described in Fig. 20, when the chip selection and the address input of the flash memory chip 1 are used in common, the pad selection is for the power-on/read instructions. The bonding pad BOAdU is pulled down to the ground potential of the flash memory chip 1, inhibiting the read operation when the power is turned on. Thereby, when the power is turned on/reading is instructed, it is possible to prevent the two actions of a pair of flash memory chips mounted in the MCP form, so that the improper situation of reading data conflicts is prevented. Figure 31 shows an example of a timing chart for reading when the power is turned on.

Explains the form of the invention based on the switching circuit of the interface function from another point of view. The aforementioned switching circuit having a semiconductor chip formed with a plurality of circuit elements and a plurality of external connection electrodes can also be set as an interface function for switching the external connection electrodes by programming the fuse. The aforementioned fuses can be set as: a laser fuse for information memory in response to switching by laser, an electrical fuse for information memory in response to switching by Joule heat, or an electrically erasable /Write the flash fuse. The flash fuse must read the memory information in response to the reset instruction. Therefore, the flash fuse must be switched from the interface function of the reset external connection electrode that inputs the instruction of the reset action to be excluded. This is usually the memory information of the flash fuse is read out in response to the instruction of the reset operation, and is initially set in the internal register, etc., and is used for resetting the instruction of the reset operation. The use of flash fuses is not appropriate for the switching of the interface function of the external connection electrode. In short, before reading the flash fuse, the assignment of reset terminals and power terminals must be determined. Taking this into consideration, the internal operation sequence when the power supply rises in the case of using the flash fuse becomes as shown in Fig. 32, for example.

As mentioned above, although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to this, and it is needless to say that various changes are possible without departing from the gist of the present invention.

For example, the semiconductor memory chip is not limited to a flash memory chip, but may also be a memory chip of other memory forms such as SRAM, synchronous DRAM, EEPROM, and so on. In the case of the MCP structure, the number of chips to be mounted is not limited to two, and may be two or more. The function or arrangement of the pads is not limited to the foregoing description, and can be appropriately changed. In addition, the signal interface function is set to replace the arrangement of the pads, which is not limited to a structure that is almost symmetrical to the line crossing the length side of the chip. The line along the length side may be almost symmetrical. However, the structure of wiring routing inside the chip required for interface switching is simpler than the latter. Furthermore, the memory card is not limited to MMC, and can also be applied to memory cards of other memory card specifications. The present invention can be understood as the semiconductor memory chip itself.

<p>1.Flash memory chip</p><p>3Memory Array</p><p>4Multiplexer</p><p>10Internal control circuit</p><p>18Control signal buffer</p><p>19Solder pad</p><p>20controller chip</p><p>31Wire terminal</p><p>32Wire</p><p>50Input switching circuit</p><p>54Output switching circuit</p><p>60Input switching circuit</p><p>70Output switching circuit</p>

FIG. 1 is a block diagram showing an example of a flash memory chip as a semiconductor memory chip related to the semiconductor device of the present invention.

Figure 2 is an explanatory diagram showing various operation modes of address input, command input, and data input/output of the flash memory chip indicated by the access control signal.

Figure 3 is an explanatory diagram showing an example of the definition of commands supported by the flash memory chip.

Figure 4 is an example of a timing diagram of the read operation cycle controlled by the internal control circuit.

Fig. 5 is an explanatory diagram showing the switching mode of the interface function of the pad of the flash memory chip together with Fig. 6.

Fig. 6 is an explanatory diagram showing the switching mode of the interface function of the pad of the flash memory chip together with Fig. 5.

Figure 7 is an explanatory diagram showing the function and setting method of the pad selection pad in a list.

Fig. 8 is a plan view showing an example of a state in which a flash memory chip is mounted on a multimedia card in the MMC form.

Figure 9 is an explanatory diagram showing the interface function of the MMC form of the solder pad and the setting state of the solder pad selection pad.

Figure 10 is an explanatory diagram showing the interface function of the pad corresponding to the standard NAND8 form and the setting state of the pad selection pad.

Figure 11 is an explanatory diagram showing the interface function of the pad corresponding to the standard NAND16 form and the setting state of the pad selection pad.

Figure 12 is an explanatory diagram showing the interface function of the pad corresponding to the 8-bit MCP core form of MCP-A and the setting state of the pad selection pad.

Figure 13 is an explanatory diagram showing the interface function of the pad corresponding to the 8-bit MCP mirrored form of MCP-A and the setting state of the pad selection pad.

Figure 14 is an explanatory diagram showing the interface function of the pad corresponding to the 8-bit MCP core form of MCP-B and the setting state of the pad selection pad.

Figure 15 is an explanatory diagram showing the interface function of the pad corresponding to the 8-bit MCP mirrored form of MCP-B and the setting state of the pad selection pad.

Figure 16 is an explanatory diagram showing the interface function of the pad corresponding to the 16-bit MCP core form of MCP-A and the setting state of the pad selection pad.

Figure 17 is an explanatory diagram showing the interface function of the pad corresponding to the 16-bit MCP mirrored form of MCP-A and the setting state of the pad selection pad.

Figure 18 is an explanatory diagram showing the interface function of the pad corresponding to the 16-bit MCP core form of MCP-B and the setting state of the pad selection pad.

Figure 19 is an explanatory diagram showing the interface function of the pad corresponding to the 16-bit MCP mirrored form of MCP-B and the setting state of the pad selection pad.

Fig. 20 is a schematic longitudinal sectional view of a semiconductor device having an MCP structure.

Figure 21 is an explanatory diagram showing a reference example of the planar structure when assembled with a lead frame for TSOP (Slim Small Outline Package).

Fig. 22 is a schematic longitudinal sectional view of another semiconductor device having an MCP structure.

FIG. 23 is an explanatory diagram showing an example of the planar structure of a semiconductor device when the package structure adopts a CSP (chip size package) structure.

Fig. 24 is a circuit diagram showing an example of the switching circuit of the first switching mode.

Fig. 25 is a circuit diagram showing another example of the switching circuit of the first switching mode.

Fig. 26 is a circuit diagram showing an example of the switching circuit of the second switching mode.

Fig. 27 is a circuit diagram showing another example of the switching circuit of the second switching mode.

Figure 28 is an address map showing the state of assigning individual address spaces in order to individually select flash memory chips for access operations.

Figure 29 is an explanatory diagram showing the address input state of the address input cycle of the flash memory chip selected by using the action of the x8 device of I/O1~I/O8.

Figure 30 is an explanatory diagram showing the address input state of the address input cycle of the flash memory chip selected by using the action of the x16 device of I/O1~I/O16.

Figure 31 is a timing chart of the power-on read operation.

Figure 32 is a flow chart showing an example of the internal operation sequence when the power supply is rising in the case of using a flash fuse.

Figure 33 is a longitudinal cross-sectional view of another semiconductor device using a CSP (chip size package) structure.

Fig. 34 is a plan view of the semiconductor device of Fig. 33.