MultiprotocolRFID reader

Multi-protocol RFID reader

The present invention is related to the interrogation of radio frequency identification (RFID) transceivers, especially related to high-end RFID readers compatible with PC card standards, with improved sensitivity, reduced distortion, and multi-protocol function.

RFID technology is widely used in automated identification. The basic RFID system includes an RFID tag or transceiver that carries identification data and an RFID interrogator or reader that reads and/or writes identification data. RFID tags typically include microchips for data storage and processing, and coupling elements such as antenna coils for communication. Tags can be classified as active or passive. Active tags have a built-in power supply, while passive tags are powered by radio waves received from the reader, so they cannot implement any communication.

The RFID reader is operated by using interrogation tags that write data to tags or their data via a radio frequency (RF) interface. During the interrogation, the reader forms and transmits an RF wave, which is used by the tag to generate response data based on the information stored in it. At the same frequency, the reader detects the reflected or backscattered signal from the tag, or asks the waveform with chirps at a slightly different frequency. The reader typically detects the reflected or backscattered signal by mixing this signal with the local oscillator signal. This detection mechanism is a homodyne structure.

In conventional homodyne readers such as the one described in US Patent No. 2,114,971, two separate decoupling antennas dedicated to transmission (TX) and reception (RX) are used, which leads to an increase in the weight and physical size of the reader. not ideal. In order to solve this problem, by using a microwave circulator or a unidirectional coupler to separate the reflected signal from the transmission signal, a reader with a dedicated single antenna for TX and RX dual functions has been developed, such as the one described in US Patent No. 2,107,910. In another US patent number 1,850,187, the tapped transmission line acts as a phase shifter and a one-way coupler.

The development of RFID systems in recent years has challenged conventional RFID readers. First, the identification data stored on the tag must be sent to the reader in a reliable manner. Encoding this data and transmitting it through a modulated signal are two important communication components between the tag and the reader. Although the data coding determines the data representation, the signal modulation determines the communication protocol between the tag and the reader. There are three main categories of digital modulation: according to Amplitude Shift Keying (ASK) (Amplitude Shift Modulation) or EPCglobal Standard Class 1 protocol, Frequency Shift Keying (FSK) (Frequency Shift Keying) or EPC Cglobal Class 0 protocol, and Phase Shift Keying (PSK) (Phase Shift Keying). Each of these categories has its own power consumption, reliability, and bandwidth requirements. For RFID readers, it is ideal to be able to process the signal from the tag using different protocols.

Because the same signal used to communicate with the tag must be used to power the tag, other challenging questions come from asking about passive RFID tags. Passive tags receive power from the reader via inductive coupling or remote energy results. Because of the modulation in the signal, the received power will be greatly reduced. In addition, the modulation information to another pure sine wave propagates the signal in the frequency domain. This spread is often referred to as "sideband" and is regulated by the government. In this way, the amount of information sent from the reader to the tag is limited by these modulation restrictions.

Moreover, the FRID reader has not been made in the PC card format, so that it can be combined with a hand-held, portable, or laptop computer to read or write RFID tags from RFID tags. The flexibility of the RFID reader on the PC card also enables intelligent long-range (ILR) systems to be easily integrated into enterprise systems and can be combined with other technologies such as barcodes and wireless local area networks (LAN). However, PC card RFID readers have other problems, because the RF components of conventional readers cannot be installed in the small PC card housing and the operation of the PC interface will produce distortion in the reader's transmission channel, resulting in read The spurious launch of the device cannot comply with the government's control requirements. The PC card RFID reader must be low-cost, but still highly sensitive to incoming signals.

The present invention includes a dedicated RFID reader for interrogating passive RFID tags, which preferably has a small size, high sensitivity, and low cost. In an embodiment of the present invention, the reader is in a standard PC card format and includes a crystal oscillator, a frequency synthesizer that refers to the clock signal from the crystal oscillator, and is based on the same clock signal from the crystal oscillator. PC card interface and controller for operation. In this way, the signal crystal oscillator is used to provide clock signals to the frequency synthesizer, PC card interface, and controller. Therefore, the digital conversion in the PC card interface and the controller is synchronized with the frequency synthesizer without disturbing the accuracy of the synthesis. Using the same crystal oscillator can greatly reduce the disturbance of the reader's transmission function and the spurious transmission caused by the operation of the PC card interface and the controller.

In another aspect of the present invention, the RFID reader additionally includes a power detector, which is configured to detect the reflected power in the reader and generate two signals. One signal is used to indicate an antenna error, and the other signal is Used as feedback to adjust the power level in the transmission signal.

In another aspect of the present invention, the RFID reader includes a linear power amplifier modulator for adding modulation to the transmission signal. The linear power amplifier modulator includes a pulse shaping filter coupled to the bias input of the linear power amplifier. The pulse shaping filter includes an operational amplifier and a low-pass filter and is configured to convert the square modulation pulse into a ramp pulse. The linear power amplifier includes a bias control module, a signal input module, and a conventional power amplifier. The bias control module is configured to generate a reference current signal from the ramp pulse. The power amplifier uses the reference current signal to amplify and modulate the continuous wave signal sent to the signal input module. The linear power amplifier modulator greatly reduces spurious radiated power, and because it reduces the RF gain required by the power amplifier and reduces the power consumption of the power amplifier at low bias currents, it consumes less DC power.

In another embodiment of the present invention, the reader 100 is configured to be able to operate in the LISTEN-only mode according to the recommended ETSI standard EN302 208, and includes a unidirectional coupler with a shunt switch, which when activated The reader can be operated in LISTEN mode. In the LISTEN mode, in one view, the one-way coupler becomes a quarter-wavelength variable device, while in another view, the one-way coupler becomes a direct path from the antenna to the receiving chain of the reader. Therefore, the transmitted signal will not reach the antenna and the received signal will only have the most appropriate loss (typically <1 dB) when traversing the unidirectional coupler. As a result, the sensitivity of the reader is greatly improved in the LISTEN mode.

In another aspect of the present invention, the RFID reader can use more than one antenna and an antenna selection module including a switching element with a parasitic component combined with a low-pass filter prototype structure. In an embodiment of the present invention, the antenna selection module includes a first filter network (network A), a second filter network (network B), and a third filter network (network C), And the switching element coupled between the network A and the network B and C. The switch element may be a conventional switch device configured to select the connection between the network B or the network C and the network A. In an embodiment of the present invention, the characteristic of the parasitic components of the switching element is to determine their values and these values indicate that when the values of the components in the network A, B, and C are selected, the network A, B, and The parasitic components of C and switching elements are combined into a low-pass filter prototype structure. Therefore, the signal strength loss through the antenna selection module is minimized and the signal quality is maximized.

In another embodiment of the present invention, the RFID reader includes a device configured to receive an RF signal from the tag and generate at least an in-phase signal, at least one quadrature signal, and at least one FSK signal to be supplied to the controller. The controller selects in-phase, quadrature, or FSK signals for further processing based on their relative strength and/or other reliability indications. Therefore, the reader is a multi-protocol reader capable of interrogating class_0 and class_1 RFIS tags.

In an embodiment of the present invention, the receiving chain includes an in-phase branch configured to generate at least an in-phase signal, a quadrature branch configured to generate a quadrature signal, and a quadrature branch configured to reject RF signals from the tag. The image of the image signal rejects the mixer (IRM). The image rejection mixer shares a pair of mixers with the in-phase and quadrature branches and includes an IRM channel with a pair of all-pass filters. The pair of all-pass filters are all configured from any one of the pair of mixers. The mixer produces different phase shifts in the signal. Each of the all-pass filters includes an operational amplifier. By using an operational amplifier for the phase shift, it is possible to achieve the desired phase shift while still maintaining the small size of the reader in the PC card format. The IRM path additionally includes blocking capacitors inserted in various positions of the IRM path, adder, and low-pass filter. The adder and the low-pass filter are combined into the low-pass filter prototype structure, and the blocking capacitor is also combined with the remaining components in the IRM path, so that the IRM path has high-pass and low-pass functions, in its frequency response in the narrow intermediate frequency band Provides fast phase shift frequency.

In another aspect of the present invention, arbitrary phase shifters are placed in the transmission or reception chain to increase the sensitivity of the reader. Another option is to place the dual phase shifters on the in-phase and quadrature branches to receive the same result. The phase shifter is adjusted to minimize the conversion of phase modulation (phase noise) in the local oscillator signal into amplitude noise in the baseband.

In another aspect of the present invention, when the reader is processing the data received from the tag, the frequency synthesizer and other RF components of the reader are turned off during the elapsed time to reduce the total power consumed by the reader.

Although the components in the RFID reader are used to illustrate various viewpoints of the present invention, these components can be used in other applications than the RFID reader.

The present invention also includes a method for interrogating an RFID tag through a computer system using the RFID reader according to an embodiment of the present invention. The method includes the following steps: generating a clock signal, generating a continuous wave signal with reference to the clock, generating a complex control signal, controlling the generation of the control signal through a PC card interface that operates according to the clock signal, and adjusting according to one of the complex control signals Change continuous wave signal.

In an embodiment of the present invention, the control signal used to modulate the continuous wave signal includes step transition. The step of modulating the continuous wave signal additionally includes the following steps: generating a ramp signal according to the control signal, the ramp signal includes each linear ramp corresponding to the step transition in the control signal, using a current mirror to generate a reference current signal according to the ramp signal, and supply The reference current signal is sent to the power amplifier that receives the continuous wave signal, and the power amplifier is used to modulate the continuous wave signal according to the reference current signal.

In an embodiment of the present invention, the method for interrogating the RFID tag further includes the following steps: transmitting the first continuous wave signal to the RFID tag for a first time period, and transmitting the modulated signal to the RFID tag after the first time period For the second time period, maintain the continuous wave output power for the third time period to receive data from the RFID tag, the third time period is after the second time period, and the fourth time period after the third time period While processing the data from the RFID tag, turn off the RF component in the reader.

In an embodiment of the present invention, the method for interrogating an RFID tag further includes the following steps: receiving an RF signal from the RFID tag, demodulating the RF signal to generate at least an in-phase signal, at least one quadrature signal, and at least one FSK signal , And select at least one phase signal, at least one quadrature signal, or at least one FSK signal to guide the information contained in the RF signal from the RFID tag.

In an embodiment of the present invention, the local oscillator signal generated in the RFID reader is used to demodulate the RF signal from the RFID tag, and the method additionally includes an arbitrary step as follows: generating an adjustable signal in the local oscillator signal The phase shift minimizes the conversion of the phase shift noise in the local oscillator signal into the amplitude noise in the at least in-phase signal, at least one quadrature signal, or at least one FSK signal.

In an embodiment of the present invention, the step of demodulating the RF signal additionally includes the following steps: dividing the RF signal into a first RF signal and a second RF signal, and dividing the local oscillator signal into a first local oscillator signal and a second local oscillator signal. The oscillator signal, the second local oscillator signal and the first local oscillator signal are 90° phase-shifted, the first RF signal and the first local oscillator signal are mixed to generate the first IF signal, and the second RF signal and the second The local oscillator signal is used to generate the second IF signal, the first all-pass filter is used to generate a first phase shift in the first IF signal, and the second all-pass filter is used to generate a second phase shift in the second IF signal in order to A total phase shift of 90° is generated between the first and second IF signals, and the first and second IF signals are totaled.

FIG. 1A is a block diagram of an RFID reader 100 according to an embodiment of the invention. As shown in FIG. 1A, the reader 100 includes a crystal oscillator 102 configured to generate a clock signal, and a frequency synthesizer 104 configured to generate a continuous wave (CW) signal with reference to the clock signal. The reader 100 additionally includes a local oscillator (LO) buffer amplifier 106 coupled to the synthesizer 104 and configured to amplify the CW signal. The LO buffer amplifier 106 in turn protects the synthesizer from interference from other parts of the reader 100. The LO buffer amplifier 106 can be implemented using known mechanisms.

The reader 100 additionally includes a transmission (TX) chain 110 configured to form and transmit the transmission (TX) signal of the interrogating tag, and a receiving (RX) chain 130 configured to receive the RF signal from the tag, and used to transmit the RF signal from the tag. The signal generates a complex output signal. The TX chain 110 includes an output power control module 112, a modulator 114, a power detector 116, and an attenuation driver 118. RX chain 130 includes splitter 132, 90° hybrid 134, I branch 140, Q branch 150, IRM channel 136, FSK receiver 138, filter 172, digital-to-analog (A/O) converters 174 and 176, and optional Phase shifter 170.

The reader 100 additionally includes a splitter 108, which is coupled between the LO buffer amplifier 106 and the TX/RX chains 110 and 130 and is configured to split the CW signal from the LO buffer amplifier 106 into a TX CW signal dedicated to the TX chain and RX LO signal dedicated to the RX chain. When the reader 100 can use more than one antenna, the reader 100 further includes an antenna selection module 122 configured to select one of the plurality of antennas 124 to broadcast TX signals or receive RF signals. The reader 100 additionally includes a unidirectional coupler 120 coupled between the antenna selection module 122 and the TX/RX chains 110 and 130. The unidirectional coupler 120 is configured to pass the TX signal from the TX chain 110 through at least one antenna via the antenna selection module 122 and is configured to couple the RF signal to the RX chain 130 by the antenna.

The reader 100 additionally includes a controller 164 configured to control the operation of the various components of the reader 100 by processing a plurality of input signals from various components and generating a plurality of output signals used by each component. Input signals may include signals I, Q, FSK_CD, FSK_data, Q_SIG, I_SIG, Ant_Fault, and DET, and output signals may include signals Ant_Select, 12C_Data, 12C_Clock, MOD, Rcv_Select, VCO_Enable, Xcvr_Enable, and SYNTH. The use of these signals will be explained in more detail below. In an embodiment of the present invention, a conventional commercially available controller can be used, and after programming according to the RFID standard, it can be used as the controller 164.

In an embodiment of the present invention, a host computer system can be used to operate the reader 100. In order to interface with the computer system, the reader 100 additionally includes a PC card interface 162 configured to provide an interface between the reader 100 and the host computer system. FIG. 1B is a block diagram of a computer system 180 that can be used to operate the reader 100. As shown in FIG. 1B, the computer system 180 is a conventional computer system, and includes a central processing unit (CPU) 182, a memory unit 184, a PC card expansion slot 186, a user interface 188, and a display device 190. The CPU 182, the memory unit 184, the user interface 188, and the display device 190 are interconnected through the bus 192. The PC card expansion slot 186 may be a PCMCIA expansion slot connected to the CPU 182 through the bus 192 and the PCMCIA bus 194 is compatible with the PCMCIA standard. The computer system 180 may be a desktop, laptop, or hand-held personal computer system that is commercially available. In an embodiment of the present invention, the reader 100 is a PC card format such as the Type II PC card format defined by the PCMCIA standard, and can be inserted into the Type II PC card format specified by the PCMCIA standard. PCMCIA expansion slot of computer system such as II expansion slot. In order to install all the RF components of the reader 100 into the PCMCIA housing, insert them into the PCMCIA expansion slot specified by the PCMCIA standard. The reader 100 includes many inventive features which will be described in detail below.

Referring back to FIG. 1A, the PC card interface 162 and the controller 164 both operate according to the clock signal from the crystal oscillator 102. If the controller 164 operates at a different frequency than the PC card interface 162, the frequency divider 166 is configured to divide the frequency of the clock signal. For example, in one embodiment of the present invention, the PC card interface 162 operates at 14.75 MHz and the controller operates at approximately 3-8 MHz. In this example, the frequency of the oscillator 102 can be set to the frequency of the PC card (ie 14.75 MHz). When the frequency of the oscillator 102 is set at 14.75 MHz, the 1/2 frequency divider 166 can be set between the crystal oscillator 102 and the controller 164 to divide the 14.75 MHz oscillator frequency by 1/2, so that the controller 164 and The PC card interface 162 can use a single crystal oscillator 102 to operate. It should be noted that the frequency of the crystal oscillator 102 can also be set to an integer multiple of the frequency of the PC card interface 162 by using the frequency divider inserted between the crystal oscillator 102 and the PC card interface 162 and between the crystal oscillator 102 and the controller 164 .

FIG. 2 includes a block diagram of the frequency synthesizer 104 according to an embodiment of the invention. As shown in FIG. 2, the frequency synthesizer includes a clock signal referenced at a lower frequency such as 14.75 MHz, for example, a conventional phase locked loop (PLL) operating at a carrier frequency such as 900 MHz. The carrier frequency is preferably close to one of the narrow frequency bands designated by regulatory agencies such as the Federal Communications Commission (FCC) for RFID operations. As shown in FIG. 2, the frequency synthesizer 104 includes a voltage controlled oscillator (VCO) 202 configured to generate a CW signal having a frequency close to 900 MHz, for example, a loop filter 204 coupled to the voltage controlled oscillator 202, and The phase detector 206 of the loop filter 204, the frequency divider 212 coupled between the voltage control oscillator 202 and the phase detector 206, and the frequency division coupled between the phase detector 206 and the crystal oscillator 102Device214. The resistors Ra, Rb, and Rc are used to split the CW signal from the VCO 202 into a first part to be sent to the LO buffer amplifier 106 and a second part to be sent to the frequency divider 212.

In an embodiment of the present invention, the frequency synthesis shown in FIG. 2 uses an "integer N" architecture. The second part of the output signal of the VCO 202 is sent to the frequency divider 212, which is divided by an integer N, and its value can be adjusted to obtain different output frequencies. The reference signal from the crystal oscillator 102 is sent to the frequency divider 214 where its frequency is divided by a generally fixed integer M. The outputs of the frequency dividers 212 and 214 are sent to two separate inputs of a phase detector 206, which is configured to compare the phase of the two signals and produce an output proportional to the phase difference between the two signals. The loop filter 204 is a low-pass filter configured to remove unwanted signal components from the output of the phase detector 206. The output of the loop filter 204 is a DC voltage used to control the phase and frequency of the CW signal from the VCO 202. In an embodiment of the present invention, the frequency synthesizer 104 receives the SYNTH signal from the controller 164, and the signal is used to adjust the integer N and/or the integer M and therefore the output frequency.

In this way, a single crystal oscillator is used to provide the clock signal used by the frequency synthesizer 104, the PC card interface 162, and the controller 164, so that the digital conversion in the PC card interface 162 and the controller 164 is synchronized with the frequency synthesizer 104, This will not interfere with the accuracy of frequency synthesis. Using the same crystal oscillator can greatly reduce the interference to the TX chain 110 and the spurious transmission generated by operating the PC card interface 162 and the controller 164.

1A again, in an embodiment of the present invention, in the TX chain 110, the output power control module 112 is configured to adjust the power level of the TX CW signal, and the modulator 114 is configured to adjust And zoom in TX The CW signal forms the TX signal. During normal operation, the TX signal should travel through the unidirectional coupler 120 and the antenna selection module 122 and reach at least one antenna 124. However, when the reader 100 is properly installed or when the selected antenna is actually separated from the reader 100, errors may occur. During such errors, the TX signal cannot reach the antenna and is reflected back towards the TX/RX chain 110/130. The amount of power in the reflected TX signal may cause damage to the components in the TX chain 110. The power detector 116 is configured to prevent this from happening. In an embodiment of the present invention, the power detector 116 is configured to detect the reflected power coupled to the RX chain 130 and generate two signals: a feedback signal back to the output power control module 112 and a feedback signal sent to the controller 164 Ant-Fault (anti-fault) signal to indicate whether the antenna has an error. The output power control module 112 uses the feedback signal to adjust the output power, and the Ant_Fault signal is provided to the host computer system through the controller 164 and the PC card interface 162 as a flag of possible antenna error. In an embodiment of the present invention, a conventional power attenuator driven by the attenuation driver 118 is used to implement the output power control module, and the attenuation driver 118 receives commands from the controller 164 in the form of signals 12C_Data and 12D_Clock.

In an embodiment of the present invention, the modulator 114 in the TX chain 110 receives the power adjustment TX CW signal from the output power control module 112, and amplifies and modulates the TX CW signal according to the MOD output from the controller 164. A combination of a conventional modulator and amplifier can be used as the modulator 114. However, the conventional technology modulator will encounter the following disadvantages.

The current and foreseeable future standards are expected to use simple amplitude modulation of the TX signal, because the demodulation of this signal in the tag only requires a diode detector and filter, and the low cost and low power of passive RFID tags The needs are consistent. 3 illustrates a conventional transmitter 300, which includes a modulator made of a switching attenuator 310 inserted in a transmission signal path 301 and a power amplifier 320, and the power amplifier 320 amplifies the output from the switching attenuator. In this way, the power amplifier 320 remains completely turned on during the signal modulation period. This configuration has at least two disadvantages. First, the switching attenuator 310 imposes an insertion loss, which must be compensated by increasing the gain (and power consumption) of the power amplifier 320. Second, when the transmitter 300 is turned on, the amplifier 320 operates under full power conditions all the time, wasting DC power. Because the DC power consumption of the amplifier plays an important role in the overall power performance of the RFID reader, it is important to limit the power consumption of the amplifier to power the battery and the portable RFID reader to achieve a long battery life.

In addition to power consumption, modulation methods also play an important role in complying with regulatory requirements on sideband transmission. RFID systems must operate in one of the narrow frequency bands designated by regulatory agencies such as the Federal Communications Commission (FCC). Regulatory agencies have strict requirements on the "spurious" radiated power outside the designated frequency band. It is well known that a completely steep switch between the high and low modulation states will produce a frequency spectrum of (sin[ω-ω_c]/[ω-ω_c]) signal of the form, where ω_cCorresponds to the center of the frequency band and is usually the nominal frequency used for communication between the reader and the tag. When the frequency is shifted from the nominal carrier frequency, the signal intensity of this frequency spectrum decreases very slowly, so that obvious spectral energy will be found outside the specified frequency band. In this way, in order to comply with regulatory requirements, readers that use switching to transmit waveforms must reduce their output RF power, so as to shorten the range of tags that can be read, or reduce the modulation rate, so as to limit the tags that can be read within a specific time period. number. In either case, the utility and functionality of the reader is reduced.

In order to solve the problems caused by the steep switching between the modulation states, a time-domain filter between successive amplitude states can be used to provide a smooth transition with reduced spectral width. 4 is another conventional transmitter 400, which includes a modulator made of a linear response attenuator 410, a filter 420 coupled between the attenuator 410 and the control output of the controller 430, and a filter 420 coupled to the attenuator 410 output power amplifier 440. In this way, the attenuator 410 is controlled by the filtered control voltage and can provide a smooth transition between the modulation states. However, the transmitter 400 using the controllable attenuator 410 dedicated for modulation is more expensive and has a higher insertion loss than the transmitter 300 of FIG. 3 using simple modulation switching.

FIG. 5 is a block diagram of the modulator 114 in the reader 100 according to an embodiment of the invention. As shown in FIG. 5, the modulator 114 includes a linear power amplifier (LPA) 510 located in the transmission signal path between the splitter 108 and the unidirectional coupler 120, and a bias control port 512 and a bias control port 512 coupled to the LPA 510. A pulse shaping filter (PSF) 520 between the MOD outputs of the controller 164. The modulator 114 additionally includes an optional preamplifier 530 coupled between the splitter 108 and the signal input 514 of the LPA 510. The preamplifier 530 can be implemented using a conventional preamplifier.

During signal transmission, the frequency synthesizer 104, the LO buffer amplifier 106, and the optional preamplifier 530 generate an input signal of sufficient amplitude to drive the LPA 510 of approximately 1 dB into compression in a normal high gain state to obtain the maximum output performance . As shown in Figure 5, there is no RF switch or attenuator placed in the transmission signal path, so there will be no adverse results of insertion loss. Instead, after being filtered by the pulse shaping filter 520, the MOD signal is directed to the bias control port 512 of the LPA 510. Therefore, the self-power amplifier requires less gain, which reduces the preset power consumption of the LPA 510.

FIG. 6 is a block diagram of LPA 510 according to an embodiment of the invention. As shown in FIG. 10, the LPA 510 includes a bias control module 610, a signal input module 620, and a power amplifier 630. The bias control module is coupled between the bias control port 512 of the LPA 510 and the reference input 631 of the power amplifier 630, and is configured to generate a reference signal in response to the filtered MOD signal from the PSF 520. The signal input module 517 is coupled between the signal input port 514 of the LPA 510 and the signal input 632 of the power amplifier 630, and is configured to use the TX CW signal from the output power control module 112 or the optional preamplifier 530 to generate power The input signal of the amplifier 630. The power amplifier 630 is configured to receive the reference signal and the input signal to amplify and modulate the input signal and output the TX signal according to the reference signal. In an embodiment of the present invention, the power amplifier 630 may be a conventional power amplifier.

Appropriate implementation of the bias control module 516 is important to achieve satisfactory TX signal shaping. FIG. 7 is a schematic diagram of a power amplifying circuit 700 built together with a conventional power amplifier 710. As shown in Figure 7, the power amplifier 710 includes a reference transistor Q_ref, Reference resistor R_e,ref, And buffer transistor Q at will_buffAnd optional buffer resistor R_buf, Bias resistor R_bia, And complex power transistor unit Q_rf1...Q_rfn. Reference resistor Q_refWith reference resistor R_e,refThe emitter connected to the ground, through the control resistor R of a large precision resistor_ctrlConnect to control voltage source V_ctrlThe collector, and through the bias resistor R_biasConnect to power transistor unit Q_rf1...Q_rfnThe base of the base. When the buffer transistor Q is set_buff, The buffer transistor Q_bufWith through-collector buffer transistor R_c,bufConnect to supply voltage V_ccThe collector and connected to the power transistor Q_rf1...Q_rfnThe emitter of the base and through the snubber resistor R_bufAnd control resistor R_ctrlConnect to V_ctrlThe base. Power transistor unit Q_rf1...Q_rfnWith thru-bias resistor R_biasFix and connect to reference transistor Q_refThe base of the base, and through the resistor R_c,ampFixed and connected to V_ccAnd via resistor R_c,ampAnd capacitor C_c,ampThe collector connected to the ground. Each power transistor Q_rf1...Q_rfnAll emitters are connected to ground through resistors (not shown). The RF input is supplied to the power transistor unit Q_rf1...Q_rfnThe base of the power transistor unit Q_rf1...Q_rfnThe collector leads out the RF output. Although FIG. 7 illustrates the power amplifying circuit 700 implemented using a bipolar transistor, a similar configuration can also be used when a field effect transistor (FET) is used.

During the operation of the power amplifier circuit 700, the reference transistor Q_refThe base of the bias voltage adjusts itself to provide flow through the control resistor R_cntrlAnd reference transistor Q_refThe reference current. It is necessary to amplify and modulate the RF input signal with reference to the current, and provide the same bias voltage to the power transistor unit Q that is manufactured on the same integrated circuit and therefore has the same characteristics and environmental conditions_rf1...Q_rfnThe base. Without considering the characteristics of the transistor or the operating temperature or other environmental conditions, each power transistor unit Q_rf1...Q_rfnThe modulated bias current of is thus generated and is equal to the reference current multiplied by the ratio of the width of the power transistor unit to the width of the reference transistor Qref. Because of the bias current, each power transistor unit Q_rf1...Q_rfnThe modulated and amplified signals are generated in the collector. Buffer transistor Q_bufAnd buffer resistor R_bufIt has the function of improving the performance of the power amplifier circuit 700.

In this way, the configuration type shown in Figure 7 can be used by first using the resistor R_cntrlConvert the control voltage into a reference current, and then mirror the reference current to the complex power transistor Q_rf1...Q_rfnTo convert the control voltage into a modulated bias current. However, the output power of the power amplifier circuit 700 is a high flying linear function of the control voltage, even when viewed in logarithmic form. As shown in FIG. 8, when the control voltage is reduced, when the control voltage is greater than 2.5V and quickly decreases to a small residual value of the control voltage<1.8V, the output power from the power amplifier circuit 700 is substantially unchanged. Moreover, as shown in FIG. 9, even when the filtered control voltage is used, the output spectrum of the power amplifier circuit 700 still has a large energy when replacing the nominal carrier frequency. The output spectrum shown in Figure 9 is obtained using an input signal that complies with the recommended standard of Electronic Product Code (EPC) for Class 1 RFID readers. The input signal is supplied to the power transistor unit Q_rf1...Q_rfnThe base.

When the high-power transistor is operated in a large-signal driving condition, the undesirable spectral components of FIG. 8 from the power amplifier circuit 700 are derived from the power transistor Q in the power amplifier 710_rf1...Q_rfnThe nature of the relationship between the reference current and the collector current. Figure 10 shows the power transistor Q_rf1...Q_rfnThe collector current in vs. the reference transistor Q through the power amplifier 710_refThe graph of the reference current, and FIG. 11 is a graph of the reference convection of the collector current vs. logarithmic scale based on the exemplary measurement of the power transistor. Should understand the power transistor Q_rf1...Q_rfnThe collector current in is substantially linear in the logarithm of the reference current rather than in the reference current value. The strong bending at x=1 (log x) produces strict nonlinearity in the total transfer function of the power amplifier circuit 700, and therefore generates spurious components in the output spectrum of the power amplifier circuit 700. A logarithmic ramp over time or even a linear reference current over time can help remedy this problem, because this reference current will generate an RF collector current, so the output power from the power amplifier is linear or approximately linear over time Slope.

In contrast to the conventional modulator, FIG. 12 schematically illustrates the LPA 510 and the PSF 520 in the modulator 114 according to an embodiment of the present invention. As shown in FIG. 12, the PSF 520 includes a ramp generator 522 and a low-pass filter 524. The ramp generator 522 includes an operational amplifier (op-amp) U coupled between the supply voltage Vcc and the ground.₁, Coupled to op-amp U₁The first input ν₊And V_ccThe first resistor between R_v1, Coupled to op-amp U₁The first input ν₊And the second resistor R between ground_v2, Coupled to the MOD output of the controller 164 and op-amp U₁The second input ν_-The third resistor between R_r1, And coupled in op-amp U₁The second input ν_-And output ν_outCapacitor C between_r1. The low-pass filter 524 is a coupling in the op-amp U₁The output ν_outRC low-pass filter between the bias input 512 and the LPA 510, which includes two series-connected resistors R_f1And R_r2And capacitor C_f1。

In an embodiment of the present invention, compared with the ideal ramp time (for example, 1.5 millionths of a second) for modulating the TX signal, op-amp U₁It has a large voltage gain and a much faster conversion rate. As a result, U₁Output voltage during adjustment period ν₀To ensure that ν_-=ν₊. Because by R_r1,R_r2And supply voltage V_ccSet ν₊, So it can effectively maintain ν_-It is a fixed value. In this way, the control voltage V of the MOD output from the controller 164_cntrlFor any specified value of, the current i flowing through resistor Rr1_r1It is fixed. Fixed ratio<maths><img file="TW200529084A_D0001.tif" /></maths>Charging capacitor C_r1Until the output voltage or ramp voltage ν₀Reach orbit value and op-amp U₁The effective voltage gain decreases. So, the step function input V_cntrl(t) Generate linear ramp output ν₀, The slope of which depends on the step function input V_cntrl(t) the step value and R_r1And C_r1Depends on the value. Ramp time (i.e. ramp output ν₀The time required to reach the orbital value) can be approximately calculated as follows:<maths><img file="TW200529084A_D0002.tif" /></maths>

Then a low-pass filter 524 filters the linear slope to smooth out the V_cntrlThe ramp output ν produced by any change in the value of₀In the possible shape change. Two resistors R in low pass filter 522_r1And R_r2It is best to have the same or similar value to ensure that the capacitor C_f1Therefore, the shape of the output voltage characteristic is symmetrical with the positive and negative slopes. Select a fixed value for the total time<i>t</i>_<i>sm</i><img file="TW200529084A_D0003.tif" />R_f1C_f1, So that the sum of the ramp time and the filter time is equal to the minimum pulse time in the MOD signal:<maths><img file="TW200529084A_D0004.tif" /></maths>

The smooth ramp output is delivered to the bias input 512 of the LPA 510. Still referring to FIG. 12, the LPA 510 includes a bias control module 516, a signal input module 517, and a power amplifier 630. In this embodiment, the power amplifier 630 is a conventional power amplifier configured similarly to the power amplifier 710. The bias control module 516 includes a bias control module 516 configured as a diode and coupled to the bias input 512 and V_ccBetween the first transistor Q_m1, And with transistor Q_m1Identical or similar characteristics and in the current mirror configuration with the transistor Q_m1Coupled second transistor Q_m2. The bias control module 516 additionally includes a transistor Q_m2The collector and V_ccBetween and between the reference input 631 and V of the power amplifier 630_ccBetween the resistor R_m1. The signal input module 517 includes a capacitor C coupled between the signal input 514 of the LPA 510 and the signal input 632 of the power amplifier 630_in. The power amplifier 630 additionally includes a ground terminal coupled to the ground and a through resistor R_ampCoupled to V_ccAnd through resistor R_ampAnd capacitor C_ampA bias terminal coupled to the ground.

Although FIG. 12 illustrates an LPA 510 implemented using a bipolar transistor, a similar configuration can also be used when using a field effect transistor (FET) or in combination with a bipolar transistor. For example, the transistor Q can be replaced by two FETs with the same or similar configuration_m1And Q_m2, Making the gates of FETs correspond to transistor Q_m1And Q_m2The emitter of FETs and the sink of FETs respectively correspond to transistor Q_m1And Q_m2The collector.

During operation of LPA 510, the filtered ramp output voltage from PSF 520 in bias output 512 and V_ccThe difference between allows current to flow through transistor Q_m1, And this current is controlled by transistor Q_m2Mirroring to generate a reference current I(ref) that flows into the power amplifier 630 via the reference input 631. The reference current input makes the power amplifier 630 adjustable and amplified via the capacitor C_inThe TX CW signal sent to the power amplifier 630 and the modulated and amplified TX CW signal is used as the TX signal. Resistor R_m1 Set the nominal modulation depth so that when the transistor Q is actually turned off_m2Time, after R_m1The current of is the lower limit of the reference current setting.

Table 1 illustrates the values of some components in the LPA 510 and PSF 520 according to an embodiment of the present invention. All the components in Table 1 are commercially available components at an appropriate cost.

<maths><img file="TW200529084A_D0005.tif" /></maths>

Figure 13 is the control voltage V from the MOD output of the controller 164_cntrl, The output voltage ν from the ramp generator 522₀, And flowing through the bias crystal Q_refThe analog plot of the reference current I(ref). Figure 13 illustrates V with a pulse width of 2 μs_cntrlThe ramp voltage ν of the step function input₀And the behavior of the reference current I(ref). As shown in FIG. 13, the ramp generator 522 uses a small delay and has a ramp time of approximately 1.5 μs per step transition of the ramp. The reference current I(ref) is also delayed and has roughly corresponding to V_cntrlThe linear slope of each step change in.

FIG. 14 illustrates the measured output spectrum from the LPA 510 according to an embodiment of the present invention. Compared with Figure 9, the spectral density of energy far away from the nominal frequency in Figure 14 is reduced by at least 6 dB, and shows a lower dependence on frequency. This reduction in sideband power is quite consistent with regulatory requirements for mutual interference between radio frequencies operating in adjacent bands. As such, embodiments of the present invention provide reduced spurious radiated power, and because the required RF gain of the power amplifier 630 is reduced and the power consumed by the power amplifier 630 in a low bias current is reduced, lower DC power is consumed. For the supply voltage and temperature changes required by the general operation of commercial radio frequency transmission devices, these advantages are sturdy and durable, and can be obtained with only a slight increase in manufacturing cost.

Referring again to FIG. 1A, the output of the modulator 114 is directed to one or more of the multiple antennas 124 transmitted to the tag by the unidirectional coupler 120 and the antenna selection module 122. The RF signal from the tag is also received by the antenna 124 and directed to the RX chain 130 by the unidirectional coupler 120. A conventional unidirectional coupler can be used as the unidirectional coupler 120.

In some cases, such as according to the recommended ETSI standard EN302 208, etc., the RFID reader needs to operate in the LISTEN mode before transmitting the transmission signal. In the LISTEN mode, the RFID reader should not radiate significant RF power and should have good sensitivity to detect other similar devices operating on the channel before interrogation. As such, in another embodiment of the present invention, the unidirectional coupler 120 includes a shunt switch to prevent the reader 100 from transmitting signals in the LISTEN mode. As shown in FIGS. 15A and 15B, the unidirectional coupler 120 includes a main line 1510 extending between ports A and B of the unidirectional coupler 120, and a port C and a terminating resistor R extending between the ports A and B of the unidirectional coupler 120._dThe secondary line between one terminal, the terminal resistor R_dThere is another terminal connected to the ground. Port A is connected to the modulator 124, port B is connected to the antenna selection module 122, and port C is connected to the RX chain 130. The main line 1510 and the secondary line 1520 may be part of a conventional quarter-wavelength, coaxial directional coupler. In an embodiment of the present invention, the main line 1510 and the secondary line 1520 each extend over a length corresponding to a quarter wavelength of the center frequency.

Still referring to FIGS. 15A and 15B, the unidirectional coupler 120 additionally includes shunt switching elements (switches) 1530, 1540, and 1550, which are implemented using PIN diodes, FET switches, or other conventional mechanisms. The switch 1530 is coupled between port A and ground, and the switch 1540 is coupled to the resistor R_dBetween the two terminals of the switch 1550, the switch 1550 is coupled between the port B and the port C of the unidirectional coupler 120.

In the LISTEN mode of operation, the switches 1530, 1540, and 1550 are generally activated as shown in FIG. 15B, and in one view, the unidirectional coupler 120 becomes a quarter-wavelength converter, and in another view , Becomes a direct path from the antenna 124 to the RX chain 130. When used as a quarter-wavelength converter, under the main line 1510 in port B, the short circuit generated by the switch 1530 is converted into an open-circuit quarter-wavelength by the unidirectional coupler 120 activated by the switch, and in port C Under the secondary line 1520, another short circuit generated by the switch 1540 is transformed into an open-circuit quarter-wavelength, so that the TX signal will not reach the antenna and the unidirectional coupler 120 will not lead to energy from the self-received signal. The start switch 1550 provides a direct path to the RX chain 130, so that in the LISTEN mode, when traversing the unidirectional coupler 120, the received signal has only some loss (typically &lt;1 dB), which is different from the use of conventional unidirectional couplers. The typical loss of 10 dB or more is much less.

When the reader 100 is transmitting a signal to the tag or is receiving a signal from the tag, the switches 1530, 1540, and 1550 are generally not activated as shown in FIG. 15A, making the one-way coupler 120 function as a conventional one-way coupler, according to The directions of signal propagation are separated. In contrast to the conventional LISTEN mode architecture in which the switch is inserted in the signal path and the received signal has a serious insertion loss (as much as 0.5 dB), the switches 1530, 1540, and 1550 in the unidirectional coupler 120 are not in the signal path. Therefore, they cause almost no loss to the transmitted or received signal.

The unidirectional coupler 120 connects the through hole B to the antenna 124 to transmit and receive signals. The antenna 124 may be contained in the reader 100 and built in a single housing together with other components of the reader 100. Another option is that the antenna 124 is external to the reader 100 and can be manually connected to the reader 100. 1A again, by including an antenna selection module 122 configured to select an antenna for transmitting TX signals or receiving RF signals from the tag, the reader 100 can use more than one antenna 124. In an embodiment of the present invention, the antenna selection module 122 is configured to select one of the two antennas Ant_0 and Ant_1, and includes switching elements in which parasitic components are incorporated in the low-pass filter prototype structure. As shown in FIG. 16A, in an embodiment of the present invention, the antenna selection module 122 includes a first filter network (network A), a second filter network (network B), and a third filter network. Circuit (network C), and a switching element 1610 coupled between the network A and the networks B and C.

Network A includes at least one sensor L_A1And L_A2And other inductors and at least one such as capacitor C_A1And C_A2Wait for the LC series of capacitors,

Network B includes at least one sensor such as L_B1And L_B2And other inductors and at least one such as capacitor C_B1,C_B2, And C_B3The LC series of capacitors, and the network C includes at least one such as inductor L_C1And L_C2And other inductors and at least one such as capacitor C_C1,C_C2, And C_C3Wait for the LC series of capacitors. Networks A, B, and C can also include resistors located at various positions in the network. Networks B and C are actually matched so that each component in network B matches the corresponding component in network C. In the embodiment where the network B and the network C include LC series, as shown in FIG. 16A, the values of the inductors and capacitors in the network B are selected to be actually equal to the corresponding inductors and capacitors in the network C The value of L_B1=L_C1,L_B2=L_C2,C_B1=C_C1,C_B2=C_C2, And C_B3=C_C3。

The switch element 1610 may be a conventional switch device configured to connect the network B or the network C to the network A according to the Ant_Select signal from the controller 164. FIG. 16C illustrates the components of the switching element 1610 according to an embodiment of the present invention. As shown in FIG. 16C, the switching element 1610 includes a pair of diodes 1611 and 1612 connected in series between the inputs of the network B and C, and connected in series between the Vcc and the Ant_Select output of the controller. The resistors 1621 and 1622 are connected in series with each other between the Ant_Select output of the controller 164 and a pair of inverters 1631 and 1632 between the low-pass filter structure containing capacitors 1641 and 1642 and inductors 1651 and 1652, low The pass filter structure is coupled between the inverters 1631 and 1632 and the circuit nodes between the diodes 1611 and 1612, and each is coupled to the circuit nodes between the inverters 1631 and 1632 and their respective networks A pair of LRC filter networks 1661 and 1662 between the circuit nodes in B and C. In operation, the Ant_Select signal is converted into a voltage signal by the resistors 1621 and 1622. The voltage signal is first inverted by the inverter 1631 and then inverted by the inverter 1632. The output of the inverter 1632 is supplied to the circuit node between the diodes 1611 and 1612 via a low-pass filter structure made of capacitors 1641 and 1642 and inductors 1651 and 1652. The output of the inverter 1631 is each passed through the LRC network 1661. And 1662 is supplied to the other terminals of the diodes 1611 and 1612. In this way, the diode 1671 or the diode 1672 connects the network B or the network C to the network A according to the Ant_signal transmission.

FIG. 16E illustrates another implementation of the switching element 1610 according to another embodiment of the present invention. As shown in FIG. 16E, field effect transistors (FETs) 1671 and 1672 are used instead of diodes 1611 and 1612 to switch between network B and network C. The source/sink of the FET 1671 is diffusely connected to the respective net A output and net B input. The source/sink of the FET 1672 are diffusely connected to the respective net C input and net A output. The gates of FETs 1671 and 1672 pass through their respective capacitors C_F1And C_F2Connect to the ground and to the output of the respective inverters 1632 and 1631, so that the FET 1671 or FET 1672 conducts according to the Ant_ signal.

Although FIGS. 16C and 16E only illustrate two examples of implementing the switching element 1610, other implementations of the switching element 1610 known in the art can also be used. Regardless of how it is implemented, switching elements contribute to parasitic components that need to be accounted for in order to obtain the best signal quality. As an example, when the switching element 1610 is switched to connect the network B and the network A, that is, Ant_0 is selected as shown in Figures 16A and 16B, such as diodes 1611 and 1612 or FETs 1671 and 1672 and other components in the switching element 1610 Contribute to parasitic components, so that the switching element 1610 can be compared to a resistor R_S, Capacitor C_SAnd sensor L_S1,L_S2, And L_S3The combination of parasitic components. Sensor L_S1, Resistor R_S, And sensor L_S2They are serially connected between network A and network B. Capacitor C_SAnd sensor L_S1Connected in series with each other, and sensor L_S1With resistor R_SAnd sensor L_S2Parallel and serially connected to each other between network A and network C. The switching element further includes other parasitic components not shown in FIG. 16B.

In order to optimize the transfer function of the low-pass filter related to the antenna selection module 122 between the unidirectional coupler 120 and the selection antenna, the parasitic components of the switching element 1610 are characterized by determining their values and when these values indicate when Select the values of inductors, capacitors and/or resistors in networks A, B, and C so that the parasitic components of networks A, B, and C and switching element 1610 are incorporated into a prototype low-pass filter structure . Examples of low-pass filter prototype structures include the well-known Chebyshev or Bessel low-pass filter prototype structures. When determining the values of components in networks A, B, and C, conventional circuit simulation programs or rules of thumb can be used. For example, when network B is connected to network A by switching element 1610, sensor L_A1The value of can be adjusted to illustrate the parasitic inductance L_S1And L_S2And parasitic resistance R_S, And the values of capacitors CB1 and CC1 can be adjusted to illustrate the parasitic capacitance C_S, Parasitic inductance L_S3, And the effect of network C. FIG. 16D illustrates a schematic circuit diagram of the antenna selection module 122 illustrating exemplary values of various components according to an embodiment of the present invention.

Although FIGS. 16A to 16D illustrate that networks A, B, and C include LC or LRC serial, other filter network types known in the art can also be used as networks A, B, and C. No matter what type of filter network is used, by selecting the appropriate component values in the network, the parasitic components in the networks A, B, and C and the switching element 1610 are integrated into a filter prototype structure, so that the network A, B, C and the switching element 1610 together form a single filter structure, replacing the two-series connection filter structure between the unidirectional coupler 120 and the selection antenna 124. Therefore, the loss of signal strength is minimized and signal quality is maximized.

1A again, in an embodiment of the present invention, the RX chain 130 includes an I branch 140 configured to generate at least in-phase signals I-SIG and/or I according to the RF signal received from the tag; and a Q branch 150, It is configured to generate at least one quadrature signal Q-SIG and/or Q according to the RF signal received from the tag. The RX chain 130 additionally includes a splitter 132 configured to receive the RF signal from the unidirectional coupler 130 and split the received RF signal into two RF_receive signals of the I branch 140 and the Q branch 150. The RX chain 130 additionally includes a 90° (quarter-wavelength) hybrid 134, which is configured to receive the RX LO signal from the splitter 108 and split the RX LO signal to be in phase with the RX LO signal and enter the first branch of the I branch 140. The LO signal, and the second LO signal that is 90° phase-shifted from the RX LO signal and enters the Q branch 150.

The function of the I branch 140 and the Q branch 150 is to demodulate the ASK or EPCglobal class-I signal from the tag and may include the conventional heterodyne or superheterodyne technology dedicated to the I/Q demodulator. As shown in FIG. 1A, the I branch 140 includes a mixer 141 excited by a first LO signal and is configured to transform the RF_receive signal into a first intermediate frequency (IF) signal. The RF_receive signal can be filtered by a preselection filter (not shown), amplified by a low noise amplifier (not shown), and then further filtered by a second preselection filter (not shown) before being applied to the mixer 141. The I branch 140 additionally includes a first low-pass filter 142 coupled to the mixer 141 and configured to filter out LO signal components in the first IF signal, at least one baseband gain amplifier 144 coupled to the low-pass filter 142, And a second low-pass filter 146 coupled to the baseband gain amplifier 144 and configured to filter out the noise generated by the baseband gain amplifier 144. The output of the filter is the in-phase signal I_SIG. The I branch 140 may additionally include a comparator, which functions as an analog-to-digital (A/D) converter 148 configured to generate a digital in-phase signal I from the I_SIG signal. The I_SIG and I signals are provided to the controller 164.

Likewise, the Q branch 150 includes a mixer 151 that is excited by the second LO signal and is configured to convert the RF_receive signal into a second IF signal. As in the I branch, the RF_receive signal can be filtered by a preselection filter, amplified by a low noise amplifier, and then further filtered by a second preselection filter before being applied to the mixer 151. The Q branch 150 additionally includes a first drip-pass filter 152 coupled to the mixer and configured to filter out the LO signal component in the second IF signal, at least one baseband gain amplifier 154 coupled to the low-pass wave filter, and A second low-pass filter 156 coupled to the baseband gain amplifier 154 and configured to filter out noise generated by the baseband gain amplifier 154. The output of the filter 156 is the quadrature signal Q_SIG. The Q branch 150 may additionally include a comparator, which functions as an A/D converter 158 configured to convert the Q_SIG signal into a digital quadrature signal Q. The Q_SIG and Q signals are provided to the controller 164.

In terms of a typical mixer and a specified IF frequency, there are two types of signals that can produce the same IF output from the mixer 141 or 151. If one of these outputs is considered to be an ideal signal, the other signal is collectively called an image, because the two signals are mirror images of each other with respect to the LO frequency. The image signal affects the sensitivity of the RX chain 130 and should be rejected. When the IF frequency is quite high so that the ideal signal and the image are far apart in frequency, the preselection filter can be placed in the signal path before the mixer to suppress not only the out-of-band signal but also the image signal. However, as far as the extremely low IF frequency is concerned, the ideal signal and the image signal are quite close to each other in frequency, and the preselection filter usually cannot properly filter out the image signal. Very low IF frequencies are generally preferred because they can use a monolithic combinable filter to perform channel filtering in an FSK receiver configured to demodulate class 0 signals received from a specific RFID tag type.

In order to solve the image problem related to low IF frequency and demodulate FSK or EPCglobal class 0, the RX chain 130 additionally includes an image rejection mixer (IRM) path 136 and an FSK receiver 138 coupled to the output of the IRM path 136. The IRM path 136 is configured to receive the filtered first and second IF signals from the filters 142 and 152, respectively, and generate an output with suppressed image signals. In this way, the IRM channel 136 together with the mixers 141 and 151 and the filters 142 and 152 form an image rejection mixer for rejecting image signals. The image rejection mixer shares the mixers 141 and 151 and the filters 142 and 152 with the I and Q demodulators in the I and Q branches 140 and 150.

Figure 17 is a block diagram of an IRM channel 136 according to an embodiment of the present invention. As shown in FIG. 17, the IRM path 136 has two input ports P1 and P2 connected to the filters 152 and 142, and an output port P3 connected to the FSK receiver 138. The IRM path 136 additionally includes first and second buffer amplifiers 1710 and 1720 that receive signals from the filters 152 and 142 via input ports P1 and P2, respectively, coupled to the first and second buffer amplifiers 1710 and 1720, respectively Two all-pass filters 1730 and 1740, an adder 1750 having a first input S1 coupled to the first all-pass filter 1730 and a second input S2 coupled to the second all-pass filter 1740, and an adder 1750 coupled to the adder 1750 The output of the low-pass filter 1760. The IRM path 136 additionally includes blocking capacitors C inserted between the input ports P1 and P2 and the buffer amplifiers 1710 and 1720._b1And C_b2, Respectively inserted between the all-pass filter 1730 and the first input S1 of the adder 1750, and C_b3And C_b4, C inserted between the adder 1750 and the low-pass filter 1760_b5, And C inserted between the low-pass filter 1760 and the output port P3_b6. The function of the blocking capacitor is to produce a low frequency roll-off in the output spectrum of the IRM path 136, which will be described in more detail below.

The buffer amplifiers 1710 and 1720 may include conventional buffer amplifier circuits configured to amplify the signals from the filters 152 and 142, respectively, and provide low source impedance to the all-pass filters 1730 and 1740, respectively. The all-pass filters 1730 and 1740 are configured to change the phase response of the signals from the buffer amplifiers 1710 and 1720, respectively, without changing the amplitude of the signals. In an embodiment of the present invention, the all-pass filter 1730 is configured to produce a first phase shift in the signal from the filter 1730, and the all-pass filter 1740 is configured to produce a first phase shift in the signal from the filter 1730 Two phase shifts, resulting in a total relative phase shift of 90° between the two signals.

<tables><img file="TW200529084A_D0006.tif" /></tables>

<tables><img file="TW200529084A_D0007.tif" /></tables>

FIG. 18 illustrates a schematic circuit diagram of an IRM path 136 according to an embodiment of the present invention. As shown in FIG. 18, the buffer amplifier 1710 includes a transistor 1711, which has a blocking capacitor C_b1Connect to input port P1 and through resistor R₁₂The base connected to the ground, via the resistor R₁₃The emitter connected to the ground, and via the resistor R₁₁Connected to its base and via resistor R₁₄And capacitor C₁₁The collector connected to the ground. Similarly, the buffer amplifier 1720 includes a transistor 1721 with a blocking capacitor C_b2Connect to input port P2 and through resistor R₂₂The base connected to the ground, via the resistor R₂₃The emitter connected to the ground, and via the resistor R₂₁Connected to its base and via resistor R₂₄And capacitor C₂₁The collector connected to the ground. Tables 2 and 3 list exemplary component selections in buffer amplifiers 1710 and 1720, respectively.

The all-pass filter 1730 includes an op-amp 1731, which has a resistor R₃₁The first input connected to the collector of transistor 1711, via resistor R₃₂Connected to the collector of transistor 1711 and via capacitor C₃The second input connected to the ground, through the blocking capacitor C_b3Coupled to the first input S1 of the adder 1750 and through the resistor R₃₃The output connected to the first input of the op-amp 1731 and the ground terminal connected to the ground. Similarly, the all-pass filter 1740 includes an op-amp 1741, which has a resistor R₄₁The first input connected to the collector of the transistor 1721, through the resistor R₄₂Connected to the collector of transistor 1721 and via capacitor C₄The second input connected to the ground, through the blocking capacitor C_b4Coupled to the second input S2 of the adder 1750 and through the resistor R₄₃The output connected to the first input of the op-amp 1741, and the ground terminal connected to the ground. Resistor R in the all-pass filter 1730 or 1740₃₂Or R₄₂The value of R_phAnd capacitor C₃Or C₄The value of C_phEach is selected to achieve the ideal phase response of the all-pass filter 1730 or 1740 for the IF frequency, because the phase shift Φ through the all-pass filter 1730 or 1740 is determined by R according to the following equation_phAnd C_phDecided:<maths><img file="TW200529084A_D0008.tif" /></maths>

Tables 4 and 5 each list exemplary component selections in all.

Although the components in Tables 2 to 5 are selected to have an IF frequency of approximately 2-4 MHz, the all-pass filter 1730 produces a first phase shift and the all-pass filter 1740 produces a second phase shift, as long as it does not violate the spirit of the present invention The sum category can change the values of these components and the structure of the all-pass filters 1730 and 1740. For example, as long as there is a 90° relative phase shift between the signals output from the all-pass filters 1730 and 1740, the first and second phase shifts may be 45° and -45°, 30° and -60°, respectively, 10 ° and 80°, or 90° and 0°.

<tables><img file="TW200529084A_D0009.tif" /></tables>

<tables><img file="TW200529084A_D0010.tif" /></tables>

The adder 1750 is configured to total the outputs from the all-pass filters 1730 and 1740 and output a signal with greatly suppressed image signals. The following example is the ideal signal S(t) and image M(t) in the RF_receive signal:<maths><img file="TW200529084A_D0011.tif" /></maths>

Where A_SAnd A_MEach is the amplitude of S(t) and M(t), ω_LOAnd ω_IFEach is the LO and IF frequency within the radius, and <img file="TW200529084A_D0012.tif" />Is the phase difference between S(t) and M(t). The output signal I of the mixer 141 in the I branch 140_OUTYes:<maths><img file="TW200529084A_D0013.tif" /></maths>

And the output signal Q of the mixer 151 in the Q branch 150_OUTYes:<maths><img file="TW200529084A_D0014.tif" /></maths>

So, by using all-pass filters 1730 and 1740 in I_OUTAnd Q_OUTA relative phase shift of 90° is generated between them, and the adder 1750 is used to total the final signal. In the most ideal state, I_OUTAnd Q_OUTThe image signal in should be completely eliminated.

The output of the adder 1750 is then filtered by the low-pass filter network 1760 and then supplied to the FSK receiver 138. As shown in FIG. 18, the adder 1750 includes an op-amp 1751, which has a resistor R connected in series.₅₁And R₅₃Connect to blocking capacitor C_b3, Through the series connection resistor R₅₂And R₅₃Connect to blocking capacitor C_b4, Through resistor R₅₄And capacitor C₅₁The first input connected to the ground. Op-amp 1751 also has a through capacitor C₅₂The second input connected to the ground, the ground terminal connected to the ground, and through the capacitor C₅₃Connect to blocking capacitor C_b5, To the first input, and through the resistor R₅₄And capacitor C₅₁The output connected to the ground.

The low-pass filter 1760 includes an op-amp 1761, which has a series connection resistor R₆₁And R₆₃Connect to blocking capacitor C_b5And through resistor R₆₃And capacitor C₆₁The first input connected to the ground. Op-amp 1761 has a through capacitor C₆₂The second input connected to the ground, the ground terminal connected to the ground, and the capacitor C₆₃Connect to blocking capacitor C_b6, And via resistor R₆₄And capacitor C₆₁The output connected to the ground.

In an embodiment of the present invention, the component values in the adder 1750 and the low-pass filter 1760 are integrated into a low-pass filter prototype structure, so that the low-pass filter prototype structure and the adder 1750 share the op-amp 1751 and its Related components, such as resistor R₅₃And R₅₄, And capacitor C₅₁,C₅₂, And C₅₃Wait. In the example shown in FIG. 18, the prototype structure of the low-pass filter including the adder 1750 and the filter network 1760 has a first op-amp, op-amp 1751, and a second op-amp, op-amp 1752. The two-component low-pass filter network. Table 6 lists exemplary component selections in the adder 1750 and the low-pass filter 1760 according to an embodiment of the present invention.

Blocking capacitor C_b1,C_b2,C_b3,C_b4,C_b5, And C_b6The value of is selected so that the IRM channel 136 also has a high-pass function with a fast low-frequency roll-off in its frequency response. Table 7 lists exemplary values of blocking capacitors in an implementation of IRM 136.

<tables><img file="TW200529084A_D0015.tif" /></tables>

<tables><img file="TW200529084A_D0016.tif" /></tables>

The component values in IRM 136 are again selected to maintain the symmetry of the signal from port P1 to port P3 and the signal from port P2 to port P3. However, because of the different phase shifts produced by the all-pass filters 1730 and 1740, the resistor R₃₂And capacitor C₃The value of is different from the resistor R₄₂And capacitor C₄The corresponding value. As a result, the resistor R₅₁And R₅₂The value is adjusted and the blocking capacitor Cb₃And Cb₄The value of is also adjusted to compensate for the difference between the output impedance of the all-pass filter 1730 and the output impedance of the all-pass filter 1740. So, with capacitor Cb₁, Buffer amplifier 1710, all-pass filter 1730, and capacitor Cb₃The first source impedance provided by the first branch of the IRM path 136 to the first input S1 of the adder 1750 and the capacitor Cb2, the buffer amplifier 1720, the all-pass filter 1740, and the capacitor Cb₄The second source impedance provided by the second branch of the IRM path 136 to the second input S2 of the adder 1750 will be equal or almost equal. Therefore, the signal from the port P1 to the port P3 and the signal from the port P2 to the port P3 will be equally or almost equally weighted in the addition performed by the adder 1750.

Figures 19A and 19B illustrate the simulated and measured phase response of the IRM channel 162, respectively. As shown in Figures 19A and 19B, the curves 1910S and 1910M are the analog and measured frequency responses of the IRM path 136 of the input signal supplied to the input port P1 when the input port P2 maintains a fixed voltage, and the curves 1920S and 1920M are respectively equivalent The analog and measurement frequency response of the IRM channel 136 of the input signal supplied to the input port P2 when the input port P1 maintains a fixed voltage. As shown in FIGS. 19A and 19B, the IRM path 136 acts as a band-pass filter with a fast roll-off in the frequency response at frequencies below 2 MHz and about 4 MHz.

19C illustrates the difference curve 1905S of the difference plot between the curves 1901S and 1902S, and the difference curve 1915S of the difference plot between the curves 1910S and 1920S. 19D illustrates the difference curve 1905M of the difference plot between the curves 1901M and 1902M, and the difference curve 1915M of the difference plot between the curves 1910M and 1920M. As shown in Figures 19A and 19B, the difference curves 1905S, 1905M, 1915S, and 1915M all have small values between the ideal frequency bands between 2-4 MHz, indicating that the IRM mixer with IRM channel 136 is included in the rejected image signal efficient.

Referring again to FIG. 1A, the FSK receiver 138 may be a conventional FSK receiver configured to demodulate the FSK signal and generate two outputs (ie, FSK_CD output and FSK_Data output). The A/D converter 174 receives the FSK_CD output and converts it into the FSK_CD signal supplied to the controller 164. The FSK_Data output passes through the low-pass filter 172 and the A/D converter 176 and becomes the FSK_Data signal that is also supplied to the controller 164. In an embodiment of the present invention, comparators are used to implement the A/D converters 174 and 176.

The controller 164 selects the in-phase, quadrature, or FSK signals for further processing according to their relative strength and/or other reliability indicators.

Optionally, as shown in FIG. 1, a single adjustable phase shifter 170 can be located in the TX chain 110 or the RX chain 130 to improve sensitivity. Alternatively, dual phase shifters (not shown) can be located in the I and Q branches 140 and 150 respectively, but they are usually not required. The phase shifter 170 is adjusted to minimize the conversion of phase modulation (or phase noise) in the LO signal into amplitude noise in the baseband. This action can be understood by doubling the first and second signals of equal frequency. The first signal (LO signal) is characterized by a zero-average fixed phase offset Φ related to the second signal (eg, RF_receive signal)₀And variable phase noise δ Φ:<maths><img file="TW200529084A_D0017.tif" /></maths>

The product can be re-expressed as a sum:<maths><img file="TW200529084A_D0018.tif" /></maths>

After low-pass filtering, only the first component remains in the total:<maths><img file="TW200529084A_D0019.tif" /></maths>

The sensitivity of the filtered output voltage to small phase noise is obtained by using the derivative of this formula:<maths><img file="TW200529084A_D0020.tif" /></maths>

In this way, if the phase offset is equal to 0 or a multiple of π radians, the filtered output is completely insensitive to phase noise in the local oscillator. A phase shift of π/2 will result in zero in the ideal signal voltage, so phase noise dominates the output. However, when a weaker signal (I or Q) is rejected and discarded by the signal processing logic in the controller 164, this situation is not important. In fact, it is important that the best conditions for the I and Q local oscillator signals are comparative examples of π/4 radians, such that:<maths><img file="TW200529084A_D0021.tif" /></maths>

In other words, the phase noise in the LO is used to directly modulate the filtered output signal strength, which has the same effect on I and Q. The signal processing logic in the controller 164 will select I or Q as the input signal. As a result, sensitivity is lost because the frequency synthesizer phase noise is integrated into the baseband bandwidth. Because the phase noise is usually very close to the carrier frequency (&lt;100 KHz far), and the typical RFID tag uses a signal with a very low modulation rate, so that all power is contained within the typical upload carrier frequency of 6 to 200 KHz, the phase cannot be rejected Noise can cause significant degradation in sensitivity. The use of the adjustable phase shifter 170 makes the selected I or Q branch most suitable for phase noise rejection. When an appropriate phase shifter is used according to an embodiment of the present invention, it can be found that the IF phase noise is improved by as much as 15-20 dB.

FIG. 20 is an operation timing diagram of the reader 100 according to an embodiment of the present invention. As shown in FIG. 20, the operation timing of the reader 100 is controlled by a plurality of control signals including the VCO enabling control voltage, the PLL lock indicator, and the XCVR_Enable voltage. When the time t=0, the reader 100 starts the interrogation cycle by sending a command to the frequency synthesizer 104 to lock to the desired multiple reference frequencies. Typically, the frequency synthesizer 104 will encounter a short delay of the order of 100 μsec before reaching the desired transmission frequency. During this period, the VCO_Enable control voltage remains low, so that the VCO 202, the LO buffer amplifier 106, and the receiver baseband gain amplifiers 144 and 154 are turned on, but the power amplifier in the TX chain 110 is not turned on. When the frequency synthesizer 104 is trying to lock to the ideal frequency in order to isolate the synthesizer transient distribution from output load changes, the buffer amplifier 106 must be turned on. When the synthesizer 104 is in the time period T_sAfter that, when a stable phase unlocked output is reached, the PLL_lock indicator voltage becomes high and the XVCR_ENABLE voltage is pulled down, turning on the power amplifier in the TX chain 110. Then, the reader 100 transmits a continuous wave (CW) output signal for a period of t_p, Set the period t as required_pTo provide sufficient transmission power to enable passive tags to store power and actuate themselves, and can be issued at a fixed period of time. At t_pAfter that, turn on the modulator to control the MOD to send data, as the output power changes as shown in Figure 20. Modulation period t_txThe duration can also be fixed with reference to the standard. At time t_txAfter that, the CW output is restored for some response time t_dAfter that, the tag that has been addressed by the interrogator reacts by modulating the load connected to its antenna, as shown in Figure 20, which generally induces the modulation in the received power. CW output power is maintained for a period of time t_rx, This period of time is typically specified by applicable operating standards, and is selected so that the time for all data can be transmitted from the farthest imaginable tag. Then, the reader 100 generates the elapsed time required to process all the data received during this interrogation cycle, including possible communication with the network or local control device in order to receive instructions for the next activity. During this elapsed time, the VCO enabling voltage and the SCVR_Enable voltage (not shown) are both pulled up, turning off the VCO 202 and the voltage to the RF component, thus greatly reducing the total power consumed by the reader 100.

Although some embodiments have been used to illustrate the present invention, this description is not intended to limit the scope of the present invention. As long as it does not violate the spirit and scope of the present invention disclosed herein, those skilled in the art will understand that many changes are possible. Moreover, although the components in the RFID reader are used to illustrate specific points of the present invention, these components can be separated from the RFID reader and used in other applications.

In summary, the present invention includes an RFID reader accessible via a computer system for interrogating at least one RFID tag. The RFID reader includes: a frequency synthesizer configured to generate a continuous wave signal; a controller, coupled to the computer system via a PC card interface and configured to generate a plurality of control signals; a transmission chain configured to generate a plurality of control signals according to at least one of the control signals A control signal forms a transmission signal from the first part of the continuous wave signal; and the receiving chain is configured to form a complex signal for extracting information related to the RFID tag according to the received signal from the RFID tag and the second part of the continuous wave signal ; Wherein the frequency synthesizer, the controller, the transmission chain, and the receiving chain are mutually coupled in a housing suitable for insertion into a PCMCIA slot of a computer system.

In an embodiment of the present invention, both the controller and the PC card interface operate according to the clock signal generated by the crystal oscillator referred to by the frequency synthesizer that generates the continuous wave signal. The frequency of the clock signal is approximately 14.75 MHz or an integer multiple of 14.75 MHz, and the reader additionally includes a frequency divider coupled between the crystal oscillator and the controller.

In an embodiment of the present invention, the transmission chain in the RFID reader includes a linear power amplifier modulator, which includes: a ramp generator configured to receive the modulation control signal from the controller and generate the modulation control signal according to the modulation control signal. A ramp signal; a current mirror, coupled to the ramp generator and configured to generate a reference current according to the ramp signal; and a power amplifier, which receives the reference current at the bias input and at least a part of the continuous wave signal at the signal input and is configured to output transmission Signal. The control signal includes a step transition, and the ramp signal includes a linear ramp that corresponds to each step transition that is obliquely standing in the ramp time period. The ramp signal can be a voltage signal and the reference current is linearly proportional to the ramp signal. The linear power amplifier modulator may additionally include a low-pass filter coupled to the output of the ramp generator and configured to smooth the ramp signal.

In an embodiment of the present invention, the RFID reader additionally includes a switch device coupled to the transmission chain and configured to connect at least one of the plurality of antennas to the transmission chain according to an antenna selection control signal from the controller. The switch device includes: first, second, and third filter networks, and coupled to the controller and between the first filter network and the second and third filter networks and is configured to connect to the second Or the switching element from the third filter network to the first filter network; wherein the parasitic components related to the switching element and the first, second, and third filter networks are integrated into a low-pass filter circular structure . The second and third filter networks actually match, so that each component in the second filter network matches a corresponding component in the third filter network. When the first, second, and third filter networks include inductors and capacitors, the values of the inductors and capacitors in the first, second, and third networks are selected to account for the parasitic components in the switching element The value of the switch device constitutes a prototype low-pass filter structure.

In an embodiment of the present invention, the receiving chain in the RFID reader generates at least an in-phase signal, at least one quadrature signal, and at least one frequency shift keying (FSK) signal. The receiving chain includes: an in-phase demodulator, configured to generate at least in-phase signals; a quadrature demodulator, configured to generate at least one quadrature signal; an image rejection mixer (IRM), coupled to the in-phase and quadrature solutions The modulator is configured to suppress image signals related to the RF signal; and a frequency shift keying (FSK) receiver, coupled to the IRM and configured to generate at least one FSK signal.

In an embodiment of the present invention, the IRM and the in-phase demodulator share the first mixer, and the IRM and the quadrature demodulator share the second mixer. The IRM additionally includes: a first all-pass filter coupled to the in-phase demodulator and configured to generate a first phase shift in the first intermediate frequency (IF) signal from the in-phase demodulator; and a second all-pass filter, Coupled to the quadrature demodulator and configured to produce a second phase shift in the second IF signal from the quadrature demodulator; and an adder, coupled to the first and second all-pass filter networks and configured To generate an output that is the sum of the first IF signal from the first all-pass filter and the second IF signal from the second all-pass filter, wherein each of the first and second all-pass filters includes an associated component op-amp, and the component values in the first all-pass filter and the second all-pass filter are selected as the first IF signal from the first all-pass filter and the second from the second all-pass filter The total relative phase shift between IF signals is 90°.

In an embodiment of the present invention, the IRM additionally includes a low-pass filter structure, wherein the adder is integrated in the low-pass filter structure and shares at least one operational amplifier with the low-pass filter structure. The IRM also includes a blocking capacitor inserted in a specific position of the IRM, where the capacitance of the blocking capacitor is selected so that the IRM has a high-pass function of filtering frequencies below the preset IF frequency band.

In an embodiment of the present invention, the RFID reader additionally includes a power detector and an output power control module. The power detector is coupled to the transmission and reception chain and is configured to detect the signal power level in the reception chain And to provide feedback to the transmission chain, the output power control module is configured to adjust the power level in the transmission signal according to the feedback. The power detector generates additional signals to indicate possible antenna errors.

The present invention additionally includes a multi-protocol RFID reader capable of interrogating EPCglobal class_0 and class_1 RFID tags. The multi-protocol RFID reader includes: a frequency synthesizer configured to generate a local oscillator signal; and an RF receiver configured to receive the local oscillator signal from the frequency synthesizer and the RF signal from the RFID tag, and according to the RF signal and The local oscillator signal generates at least an in-phase signal, at least one quadrature signal, and at least one frequency shift keying (FSK) signal.

In an embodiment of the present invention, the RF receiver includes: an in-phase demodulator configured to generate at least an in-phase signal; a quadrature demodulator configured to generate at least one quadrature signal; an image rejection mixer ( IRM), coupled to in-phase and quadrature demodulators and configured to suppress image signals related to RF signals; and a frequency shift keying (FSK) receiver, coupled to IRM and configured to generate at least one FSK signal.

In an embodiment of the present invention, the IRM and the in-phase demodulator share a first mixer, and the first mixer is configured to generate a first intermediate by mixing the first part of the RF signal and the first part of the local oscillator signal. Frequency (IF) signal, and IRM and quadrature demodulator share a second mixer, the second mixer is configured to be generated by mixing the second part of the RF signal and the second part of the local oscillator signal phase shift The second IF signal. The IRM additionally includes: a first all-pass filter coupled to the in-phase demodulator and configured to produce a first phase shift in the first IF signal from the in-phase demodulator; and a second all-pass filter coupled to the quadrature A demodulator and configured to generate a second phase shift in the second IF signal from the quadrature demodulator; and an adder, coupled to the first and second all-pass filter networks and configured to generate a second phase shift from the first The output of the sum of the first IF signal of an all-pass filter and the second IF signal from the second all-pass filter, wherein each of the first and second all-pass filters includes an op-amp with related components, And the component values in the first and second all-pass filters are selected so that the total relative phase shift between the first IF signal and the second IF signal is 90° or close to 90°.

The IRM additionally includes a first buffer amplifier, coupled between the first mixer and the first all-pass filter; and a second buffer amplifier, coupled between the second mixer and the second all-pass amplifier, the first and The second buffer amplifier is actually identical in configuration. The IRM also includes a blocking capacitor located at a specific position of the IRM, where the capacitance of the blocking capacitor is selected so that the IRM has a high-pass function for filtering frequencies below the preset frequency band.

In an embodiment of the present invention, the adder includes a first resistor coupled to the first all-pass filter through the first blocking capacitor; and a second resistor coupled to the second all-pass filter through the second blocking capacitor ; The values of the first and second resistors and the first and second blocking capacitors are selected to compensate for the impedance difference between the first all-pass filter and the second all-pass filter, so that the first IF signal and the second The IF signal is weighted equal or almost equal in the sum generated by the adder. The IRM additionally includes a low-pass filter structure, where the low-pass filter structure and the adder are integrated to share at least one operational amplifier.

In an embodiment of the present invention, the multi-protocol RFID reader additionally includes an adjustable phase shifter, which is coupled between the frequency synthesizer and the in-phase and quadrature demodulators and is configured to generate variable signals in the local oscillator signal. Adjust the phase shift to minimize the conversion of phase noise in the local oscillator signal into amplitude noise in the in-phase and quadrature signals.

The present invention also includes an image rejection mixer (IRM) for use with an RF receiver. The RF receiver is configured to receive a local oscillator signal from a local frequency synthesizer and an RF signal from a remote object. The IRM includes: a first mixer configured to generate a first intermediate frequency (IF) signal by mixing the first part of the RF signal and the first part of the local oscillator signal; the second mixer configured to generate a first intermediate frequency (IF) signal by mixing The second part of the RF signal and the second part of the local oscillator signal are phase-shifted to produce a second IF signal; a first all-pass filter, coupled to the first mixer and configured to connect to the first from the in-phase demodulator A first phase shift is generated in the IF signal; a second all-pass filter coupled to the quadrature demodulator and configured to generate a second phase shift in the second IF signal from the quadrature demodulator; and an adder, Coupled to the first and second all-pass filter networks and configured to generate an output of the sum of the first IF signal from the first all-pass filter and the second IF signal from the second all-pass filter, wherein each A first and second all-pass filter both contain op-amps with related components, and the component values in the first and second all-pass filters are selected to be between the first IF signal and the second IF signal The total relative phase shift is 90° or close to 90°.

The IRM additionally includes a first buffer amplifier, coupled between the first mixer and the first all-pass filter; and a second buffer amplifier, coupled between the second mixer and the second all-pass amplifier, the first and The second buffer amplifier is actually identical in configuration. The IRM also includes a blocking capacitor located at a specific position of the IRM, where the capacitance of the blocking capacitor is selected so that the IRM has a high-pass function for filtering frequencies below the preset frequency band.

In an embodiment of the present invention, the adder includes a first resistor coupled to the first all-pass filter through the first blocking capacitor; and a second resistor coupled to the second all-pass filter through the second blocking capacitor ; The values of the first and second resistors and the first and second blocking capacitors are selected to compensate for the impedance difference between the first all-pass filter and the second all-pass filter, so that the first IF signal and the second The IF signal is weighted equal or almost equal in the sum generated by the adder. The IRM additionally includes a low-pass filter structure, where the low-pass filter structure and the adder are integrated to share at least one operational amplifier.

The present invention further includes a method for interrogating RFID tags, including: generating a clock signal; generating a continuous wave signal with reference to the clock signal; generating a complex control signal; controlling the generation of the control signal through a PC card interface operating according to the clock signal; and The continuous wave signal is modulated according to one of the control signals of the complex control signal.

The method for interrogating the RFID tag additionally includes: generating a ramp signal according to one of the control signals including step transfer, the ramp signal includes each linear ramp corresponding to the step transfer in the control signal; using a current mirror according to the ramp signal Generate a reference current signal; supply the reference current signal to a power amplifier that receives a part of the continuous wave signal; and use the power amplifier to modulate the continuous wave signal according to the reference current signal. In an embodiment of the present invention, the reference current signal is linearly proportional to the ramp signal.

The method for interrogating the RFID tag additionally includes: receiving an RF signal from the RFID tag; demodulating the RF signal to generate at least an in-phase signal, at least one quadrature signal, and at least one FSK signal; and selecting at least an in-phase signal, at least one positive The cross signal, or at least one FSK signal, leads the information contained in the RF signal from the RFID tag. In an embodiment of the present invention, the RF signal is demodulated by mixing the RF signal and a part of the continuous wave signal, and the method further includes generating an adjustable phase shift in the part of the continuous wave signal to minimize the phase noise conversion of the continuous wave signal A conversion of amplitude noise in at least in-phase signal, at least one quadrature signal, and at least one FSK signal.

The present invention also includes a linear power amplifier modulator for modulating the input signal according to the control signal, including: a pulse shaping filter configured to receive the control signal and generate a ramp output according to the control signal; a current mirror configured to Receiving the ramp output and generating a reference current according to the ramp output; and a power amplifier configured to receive the reference current and the input signal and configured to modulate the input signal according to the reference current. The ramp output can be a ramp voltage output and the reference current is linearly proportional to the ramp output. The control signal includes a step transition and the ramp output includes a linear ramp corresponding to each step transition in the control signal during the ramp time.

In an embodiment of the present invention, the pulse shaping filter includes an operational amplifier having a first input connected to the ground potential through a first resistor and a supply voltage through a second resistor; connected through a third resistor A second input to the control voltage related to the control signal, and an output coupled to the second input through a capacitor. The operational amplifier has a relatively fast slew rate compared to the ramp time period.

The modulator may additionally include an output coupled to the pulse shaping filter and a low-pass filter configured to smooth the slope output.

In an embodiment of the present invention, the current mirror in the modulator includes a first transistor configured as a diode between the supply voltage and the output of the pulse shaping filter; and a second transistor, It is coupled with the first transistor in the current reflection configuration, and the reference current is generated in the second transistor. The power amplifier includes a reference transistor, which is coupled between the supply voltage and the ground potential and is configured to receive a reference current from the current mirror; and a plurality of power amplifier units, each of which generates a bias current based on the reference current and the input signal.

In an embodiment of the present invention, the linear power amplifier modulator is located in the transmission signal path of the RFID reader. The input signal is a continuous wave signal generated by a frequency synthesizer in an RFID reader.

The present invention further includes a method for modulating an input signal, including: receiving a control signal, the control signal including step transition; generating a ramp signal according to the control signal, and the ramp signal ramps each step transition in the control signal during the ramp time period; A current mirror is used to generate a reference current signal according to the ramp signal; the reference current signal is supplied to the power amplifier that receives the input signal; and the power amplifier is used to modulate the input signal according to the reference current signal.

In a specific embodiment of the invention, the reference current signal is linearly proportional to the ramp signal. Receiving the control signal includes receiving the control signal in the first input of the operational amplifier, the second input of the operational amplifier is coupled to the ground via the first resistor and the supply voltage via the second resistor, and the output of the operational amplifier is transmitted through The capacitor is coupled to the first input. Generating the ramp signal includes filtering the output signal from the operational amplifier through a low-pass filter. Supplying the reference current signal to the power amplifier includes supplying the reference current to the reference transistor in the power amplifier. Modulating the input signal according to the reference current signal includes generating a bias current according to the reference current in each of the plurality of power transistors.

The present invention further includes a switch device for routing the RF signal according to the control signal from the controller. The switching device includes: first, second, and third filter networks, and the switching element is coupled to the controller and coupled between the first filter network and the second and third filter networks and is configured to Connect the second or third filter network to the first filter network according to the control signal; wherein the parasitic components related to the switching element and the first, second, and third filter networks are integrated into a low-pass filter Prototype structure. The low-pass filter prototype structure is a Chebyshev low-pass filter prototype structure, a Bessel low-pass filter prototype structure, etc. The second and third filter networks are matched with corresponding components in the third filter network.

In an embodiment of the present invention, the first, second, and third filter networks all include LC series, and the inductors or capacitors in the first, second, and third filter networks The value is selected to account for the parasitic component in the switching element, so that the switching device acts as a prototype low-pass filter for the RF signal.

In an embodiment of the present invention, at least one inductance value in the first filter network and at least one capacitance value in each of the second and third filter networks are selected according to the value of the parasitic component in the switching element.

In an embodiment of the present invention, the parasitic components of the switching element include: a first parasitic inductor, coupled to the first filter network; a parasitic resistor and a second parasitic inductor, connected in series with each other and when the switching element is connected The first filter network and the second filter network are located between the first inductor and the second filter network; and the parasitic capacitor and the third parasitic inductor are connected in series with each other and when the switching element is connected to the first A filter network and a second filter network are located between the first sensor and the third filter network.

In an embodiment of the present invention, the first, second, and third filter networks all include at least two series-connected inductors coupled between the input and output of the filter network; the first capacitor, coupled Between the input and the ground terminal; and the second capacitor, coupled between the circuit node in the filter network and the ground terminal, and each of the first, second, and third capacitors is selected according to the parasitic components in the switching element At least one capacitance value in the filter network.

In an embodiment of the present invention, the component of the switching element that contributes to the parasitic component includes: a first diode coupled between the output of the first filter network and the input of the second filter network; And the second diode, coupled between the output of the first filter network and the input of the third filter network. The switching element may additionally include a pair of series-connected inverters, coupled between the output of the first filter network and the controller; a circuit node between the pair of series-connected inverters, coupled to each The circuit nodes in the second and third filter networks make the first diode or the second diode conduct in response to the control signal from the controller. The switching element additionally includes a low-pass filter structure coupled between the output of the first filter network and a pair of serially connected inverters.

In another embodiment of the present invention, the component in the switching element that contributes to the parasitic component includes: a first FET having a source coupled to the output of the first filter network and the input of the second filter network, respectively Pole/sink diffusion and coupled to the gate of the controller via an inverter; and a second FET having a source/sink coupled to the input of the third filter network and the output of the first filter network, respectively Diffusion and coupling to the gate of the controller via a pair of inverters.

In an embodiment of the present invention, the second and third filter networks are respectively coupled to a pair of antennas, and the switch device is configured to select the antenna formed in the RFID reader for transmitting RF signals.

The present invention further includes a method for routing RF signals, including: generating a control signal; using a switching element that receives the control signal to connect the second filter network or the third filter network to the first filter network; The filter network filters the RF signal; and filters the RF signal through a second filter network or a third filter network connected to the first filter network using switching elements; wherein the parasitic elements related to the switching elements and the first , Second, and third filter networks are integrated into a low-pass filter prototype structure, so that a low-pass filter is used to filter the second filter network that passes through the first filter network and is connected to the first filter network by switching elements Or the RF signal of the third filter network.

The present invention further includes a method for forming a switching element for routing RF signals, including: arranging first, second, and third filter networks; arranging coupled to the first filter network and the second and third filters The switching element between the networks, the switching element is configured to select the second or third filter network to be connected to the first filter network; determine the value of the parasitic component related to the switching element; and adjust according to the value of the parasitic component The component values in the first, second, and third filter networks make the switching device act as a prototype low-pass filter for the RF signal.

In an embodiment of the present invention, adjusting the component value includes: performing circuit simulation or using experience to adjust the determined component value so that the first filter network, the switching element, and the second filter network connected to the first filter network by the switching element The second or third filter network and the third or second filter network not connected to the first filter network are integrated to form a low-pass filter prototype structure.

In an embodiment of the present invention, the first, second, and third filter networks all include capacitors and inductors, and adjusting component values therein includes selecting at least one of the first filter networks according to the values of parasitic components An inductance value and at least one capacitance value in each of the second and third filter networks.

In an embodiment of the present invention, the component of the switching element that contributes to the parasitic component includes a pair of diodes or a pair of FETs.

In an embodiment of the present invention, determining the value of the parasitic component includes: determining the value of the first parasitic inductor coupled to the first filter network; determining the serial connection with each other and when the switching element is connected to the first filter network And the second filter network when the parasitic resistor and the second parasitic inductor are located between the first inductor and the second filter network; and determine the serial connection with each other and when the switching element is connected to the first filter The filter network and the second filter network are the values of the parasitic capacitor and the third parasitic inductor between the first inductor and the third filter network.

The present invention additionally includes a one-way coupler having a first input port, a second input port, and a coupling port. The unidirectional coupler includes: a first conductive line extending between the first and second input ports; a second conductive line extending between the coupling port and the first terminal of the resistor; a first shunt switch coupled to the first terminal Between an input port and the coupling port; a second shunt switch, coupled between the first terminal and the second terminal of the resistor; and a third shunt switch, coupled between the third input port and the ground potential.

In an embodiment of the present invention, the unidirectional coupler is coupled to the transmission and reception chain of the RFID reader, and when activated, the shunt switch enables the unidirectional coupler to be converted into a quarter wavelength conversion from the transmission chain And provide a direct path for the signal received by the antenna associated with the RFID reader to reach the receiving chain.

<p>100Reader</p><p>102Crystal Oscillator</p><p>104Frequency Synthesizer</p><p>106Local Oscillator Buffer Amplifier</p><p>108 Splitter</p><p>110Transmission chain</p><p>112Output power control module</p><p>114Modulator</p><p>116Power Detector</p><p>118Attenuation driver</p><p>120One-way coupler</p><p>122Antenna Selection Module</p><p>124antenna</p><p>130Receiving Chain</p><p>132 Splitter</p><p>13490°Blend</p><p>136Image rejection mixer channel</p><p>138Frequency shift keying receiver</p><p>140I branch</p><p>141Mixer</p><p>142First low-pass filter</p><p>144Baseband gain amplifier</p><p>146Second low-pass filter</p><p>148Analog to Digital Converter</p><p>150Q branch</p><p>151Mixer</p><p>152The first low-pass filter</p><p>154Baseband gain amplifier</p><p>156Second low-pass filter</p><p>158Analog to Digital Converter</p><p>162PC card interface</p><p>164controller</p><p>166Crossover</p><p>170Phase Shifter</p><p>172Filter</p><p>174Digital to Analog Converter</p><p>176Digital to Analog Converter</p><p>180Computer System</p><p>182Central Processing Unit</p><p>184Memory Unit</p><p>186PC card expansion slot</p><p>188User Interface</p><p>190Display device</p><p>192Bus</p><p>194PCMCIA bus</p><p>202Voltage Controlled Oscillator</p><p>204loop filter</p><p>206Phase Detector</p><p>212Crossover</p><p>214Crossover</p><p>300Transmitter</p><p>301Transmission signal path</p><p>310Switching Attenuator</p><p>320Power Amplifier</p><p>400Transmitter</p><p>410Attenuator</p><p>420Filter</p><p>430controller</p><p>440Power Amplifier</p><p>510Linear Power Amplifier</p><p>512Bias control port</p><p>514Signal input</p><p>516Bias Control Module</p><p>520Pulse Integer Filter</p><p>522Ramp Generator</p><p>524Low Pass Filter</p><p>530Preamplifier</p><p>610Bias Control Module</p><p>620Signal input module</p><p>630Power Amplifier</p><p>631Reference input</p><p>632Signal input</p><p>700Power amplifier circuit</p><p>710Power Amplifier</p><p>1510Main Line</p><p>1520secondary line</p><p>1530Shunt switch element</p><p>1540Shunt switch element</p><p>1550Shunt switch element</p><p>1610Switching element</p><p>1611Diode</p><p>1612Diode</p><p>1621Resistor</p><p>1622Resistor</p><p>1631Inverter</p><p>1632Inverter</p><p>1641Capacitor</p><p>1642Capacitor</p><p>1651Sensor</p><p>1652Sensor</p><p>1661LRC filter network</p><p>1662LRC filter network</p><p>1671Diode</p><p>1672Diode</p><p>1710First buffer amplifier</p><p>1711Transistor</p><p>1720Second buffer amplifier</p><p>1721Transistor</p><p>1730First all-pass filter</p><p>1731Operational amplifier</p><p>1740Second all-pass filter</p><p>1741Operational amplifier</p><p>1750Adder</p><p>1751Operational amplifier</p><p>1760Low Pass Filter</p><p>1761Operational amplifier</p><p>RaResistor</p><p>RbResistor</p><p>RcResistor</p>

Fig. 1A is a block diagram of an RFID reader according to an embodiment of the present invention.

Figure 1B is a block diagram of a computer system that can be used to operate an RFID reader.

2 is a schematic block diagram of a frequency synthesizer used in an RFID reader according to an embodiment of the present invention.

Figure 3 is a block diagram of a conventional RF transmitter using a controllable attenuator and filtered control voltage.

Fig. 5 is a block diagram of a modulator used in an RFID reader according to an embodiment of the present invention.

FIG. 6 is a block diagram of a linear power amplifier in a modulator according to an embodiment of the invention.

Fig. 7 is a schematic circuit diagram of a power amplifier circuit built together with a conventional power amplifier.

Figure 8 is the output power vs. reference input voltage diagram of the power amplifier circuit.

Figure 9 shows the output spectrum of the power amplifier circuit.

Figure 10 is the measured collector current of the power transistor vs. the reference current in the power amplifier.

Fig. 11 is a graph of the collector current of the power transistor vs. the reference current in the power amplifier measured on a logarithmic reference scale.

FIG. 12 is a schematic circuit diagram of a linear power amplifier modulator according to an embodiment of the present invention.

FIG. 13 is a diagram of control voltage and current of a linear power amplifier modulator according to an embodiment of the present invention.

FIG. 14 is an exemplary output spectrum diagram of a linear power amplifier modulator according to an embodiment of the present invention.

15A and 15B are schematic diagrams of the circuit of the unidirectional coupler in the RFID reader according to an embodiment of the present invention.

16A and 16B are circuit schematic diagrams of the antenna selection module in the RFID reader according to an embodiment of the present invention.

16C is a schematic circuit diagram of the switching element in the antenna selection module according to an embodiment of the present invention.

FIG. 16D is a schematic circuit diagram of an antenna selection module with component values according to an embodiment of the present invention.

16E is a schematic circuit diagram of a switching element in an antenna selection module according to another embodiment of the present invention.

Fig. 17 is a block diagram of an IRM channel in an RFID reader according to an embodiment of the present invention.

Fig. 18 is a schematic circuit diagram of an all-pass filter in an IRM path according to an embodiment of the present invention.

19A and 19B are plots of the phase and frequency response of the simulation and measurement of the IRM channel according to an embodiment of the present invention.

19C and 19D are different plots of the phase and frequency response of the simulation and measurement of the IRM channel according to an embodiment of the present invention.

20 is a timing diagram of various signals in an RFID reader according to an embodiment of the present invention.