Thin film transistor device and method of manufacturing the same and liquid crystal display device

Thin film transistor device and its manufacturing method, and liquid crystal display device

[Technical Field to which the Invention belongs]

Field of invention

The present invention relates to a thin film transistor device, a manufacturing method thereof, and a liquid crystal display device, and in particular to a thin film transistor device formed on an insulating substrate of a liquid crystal display device or the like, a manufacturing method thereof, and a liquid crystal display device.

[Prior Art]

Background of the invention

The liquid crystal display device has the characteristics of light weight, thin thickness, low power consumption, etc., and its application fields are quite wide, such as mobile terminals, camera viewfinders, notebook computers, etc. In particular, active matrix liquid crystal display devices using thin film transistors (hereinafter abbreviated as "TFT") as switching elements are often used for applications requiring high-quality and high-resolution displays, such as computer monitors or similar devices.

In the active matrix liquid crystal display device, a TFT with a polysilicon film as a working layer (hereinafter referred to as "pSi-TFT") is used because of its high driving capability. In recent years, with the advancement of polysilicon thin film forming technology, in order to reduce costs and improve functions, the thin film transistors in the display area (hereinafter referred to as pixel TFT) and the surrounding circuits outside the display area have been formed on the same substrate. Research on the structure of TFT.

Since pixel TFTs are used to drive liquid crystals, high voltages must be applied to their gates and drains. Therefore, such pixel TFTs must provide a relatively high breakdown voltage for the gate voltage and drain voltage. On the contrary, the TFTs in the surrounding circuit parts require low power consumption and high-speed operation.

In order to meet this demand, in the patent publication (KOKAI) Hei10-170953, etc., it has been proposed that on the same substrate, the gate insulating film formed in the pixel TFT is thicker, and the gate insulating film formed in the TFT of the surrounding circuit part is relatively thick. Example of thinness.

Figure 1 shows a cross-sectional structure diagram of the liquid crystal display device, in which the thickness of the insulating film formed on the same substrate is different from that of the pixel TFT and the TFT of the surrounding circuit part. In this example, a high voltage is also applied to some TFTs in the surrounding circuit part, so the TFT in the surrounding circuit part uses the same structure as the pixel TFT.

According to the above-mentioned method for manufacturing a liquid crystal display device, a gate insulating film made of a silicon oxide film is formed on the island-shaped semiconductor films 4a, 4b made of a polysilicon film. At the same time, the thickness of the film can be adjusted by changing the number of insulating film stacks in the thicker part and the thinner part. In particular, as described below, multiple insulating films are continuously formed and unnecessary insulating films are etched.

That is, a first insulating film is formed on the entire surface of the substrate, and then the first insulating film 5 in the thicker portion of the TFT forming area is etched and left, while the first insulating film 5 in other areas is removed remove.

After that, a second insulating film and a metal thin film are formed in this order on the entire surface, and then the metal thin film is subjected to a patterning process. Therefore, in the thinner portion of the TFT forming area, the first gate electrode 7a is formed on the second insulating film 6a; at the same time, in the thicker portion of the TFT forming area, the second gate electrode 7b is formed by the first insulating film 5 And the second insulating film 6a is formed on the layered structure. Thus, in the thinner portion of the TFT forming area, the first gate insulating film having a single-layer structure composed of the second insulating film 6a is formed under the first gate electrode 7a; at the same time, in the thicker portion of the TFT forming area , A second gate insulating film having a double-layer structure composed of the first and second insulating films 5, 6b is formed under the second gate electrode 7b.

Moreover, in the thicker part of the TFT, the deterioration of the'ON' characteristics caused by hot electrons should generally be suppressed, and the'OFF' current should be reduced. In view of this, as shown in Figure 5, the structure has an LDD ( Lightly doped drain) structure. When viewed from the upper side, the boundary between the channel region 4be and the low-concentration impurity regions 4bc, 4bd is substantially located directly below the edge of the gate electrode 75. In some cases, the regions corresponding to the low-concentration impurity regions 4bc and 4bd may form offset regions that are not doped with impurities.

The standard TFT is formed in the thinner part, and the TFT with the LDD structure is formed in the thicker part. Therefore, as shown in FIG. 6A, the first gate electrode 72 is first formed on the first insulating film 71 in the thinner portion of the TFT forming area. After that, in the thicker part of the TFT forming area, an anti-corrosion mask 73a with a width wider than the gate electrode forming area in the LDD area is formed, and then the first gate electrode 72 and the anti-corrosion mask 73a are used as the mask to implant ions . Therefore, high-concentration impurity regions 4as, 4ab are formed in the island-shaped semiconductor film 4a on both sides of the first gate electrode 72, and high-concentration impurity regions 4ba, 4bb are formed in the island-shaped semiconductor film 4a on both sides of the etching resist 73a.

After that, the etching resist 73a is removed. Then, as shown in Figure 6B, in the thicker TFT forming area, a new etching resist 73b is formed in an area narrower than the forming area of the etching resist 73a, and then used The etching resist 73b implants ions. Therefore, low-concentration impurity regions 4bc, 4bd are formed in the region between the edge of the etching resist 73b and the edge of the high-concentration impurity regions 4aa, 4ab. In this example, the region sandwiched between the low-concentration impurity regions 4bc, 4bd is used as Channel area 4be.

After that, the first insulating film 71 is etched using the first gate electrode 72 and the etching resist 73b as a mask. Therefore, as shown in FIG. 5, the first insulating film 71a is formed under the first gate electrode 72, and the first insulating film 71b remains under the etching resist 73b. Then, the etching resist 73b is removed, and then a second insulating film and a metal film are formed on the entire surface.

Then, the metal film is subjected to a patterning process, and then, as shown in FIG. 5, in the thinner portion of the TFT forming area, the second gate electrode 75 is formed above the channel area 4be. Next, using the second gate electrode 75 as a mask, the second insulating film is etched, leaving the second insulating film 74a. Therefore, a second gate insulating film having a two-layer structure composed of the first and second insulating films 71 b and 74 a is formed under the second gate electrode 75.

Thereafter, the thin film transistor device as shown in Figure 5 can be formed by standard steps. In this example, reference numeral 76 in FIG. 5 denotes a first interlayer insulating film, 76a to 76d denote contact holes, 77a to 77d denote source/drain electrodes, and 78 denotes a second interlayer insulating film.

However, as shown in FIG. 2, in the conventional manufacturing method shown in FIG. 1, the first insulating film 5 is etched by dry etching. In this example, the surface of the island-shaped semiconductor film 4a in the thinner portion of the TFT forming area, especially the surface of the channel area, is exposed to the plasma of the etching gas. Therefore, since the damage layer 13 is generated on the surface of the island-shaped semiconductor film 4a, the resulting problem is that the TFT characteristics in the thinner portion are degraded compared to the TFT characteristics in the thick portion.

On the contrary, as shown in FIG. 3A, the first insulating film 5 is etched with hydrofluoric acid or the like by a wet etching method. In this example, since it is not easy to obtain the selective etching ratio of the island-shaped semiconductor films 4a, 4b to the underlying silicon oxide film 3, the underlying silicon oxide film 3 is also etched during over-etching, so that the silicon oxide film 3 is A "scraped portion" 14 is generated under the edge portions of the island-shaped semiconductor films 4a, 4b.

In order to avoid this situation, as shown in Figure 3B, a second insulating film 6 and a metal film 7 are formed as gate electrodes. Then, as shown in Figures 4A and 4B, the metal film 7 is patterned with an anti-corrosion mask. The process is made to form the gate electrode 7a. If this is done, the gate insulating film of the TFT in the thinner part is formed only by the second insulating film 6a, and its thickness is thinner, so the second insulating film at the scraped part of the edge part of the island-shaped semiconductor film 4a Cracks are likely to occur in 6a, so the problem is that the gate breakdown voltage of the TFT in the thinner portion is greatly reduced.

In addition, the edge portion of the island-shaped semiconductor film 4a is reduced by etching so that the top end thereof forms an acute angle. In view of this, unless a scraped portion is generated at the edge portion of the island-shaped semiconductor film 4a, when a gate voltage is applied, an electric field concentration phenomenon will occur, especially in a thinner portion of the TFT. Therefore, the problem arises that the so-called parasitic TFT will operate faster than the standard TFT.

Furthermore, in order to prevent these situations, a structure is used to cover only the edge portion of the island-shaped semiconductor film 4a of the TFT in the thinner portion. This structure is usually formed by exposing the upper surface of the substrate 1 with a photomask. In this example, from the viewpoint of ensuring the edge accuracy and alignment accuracy of the mask, the width of the island-shaped semiconductor films 4a, 4b must be set to be quite large, so the miniaturization of the TFT is restricted.

In addition, in the conventional manufacturing method illustrated in Figures 6A and 6B, miniaturization is improved, so it is not easy to balance the high-concentration impurity regions 4ba, 4bb, the low-concentration impurity regions 4bc, 4bd, and the gate electrode 75. The LDD structure is formed under the configuration, which hinders miniaturization.

Furthermore, as shown in FIG. 5, the gate insulating film is etched into multilayer insulating films 71b and 74a by using various steps. Therefore, these steps are time-consuming and laborious, so these steps must be simplified.

[Summary of the invention]

Summary of the invention

First of all, the object of the present invention is to provide a thin film transistor device with TFT, the insulating film of the TFT has different thicknesses on the same substrate, and the thicker part has an LDD structure; this thin film transistor device can prevent its characteristics And breakdown voltage degradation, and suppress the parasitic TFT operation at the edge of the working layer.

Secondly, the object of the present invention is to provide a manufacturing method capable of forming such a thin film transistor device while achieving simplification of steps and miniaturization of the device.

Third, the object of the present invention is to provide a liquid crystal display device using a thin film transistor device.

The method for manufacturing a thin film transistor device published in the first item of the scope of patent application of the present invention includes the steps of forming a first island-shaped semiconductor film and a second island-shaped semiconductor film on a surface of a transparent substrate; forming a layer A first insulating film used to cover the first island-shaped semiconductor film and the second island-shaped semiconductor film; a negative photoresist film is formed on the first insulating film; the light of the entire area of the first island-shaped semiconductor film is shielded by one Cover, the negative photoresist film is exposed from a light source; the negative photoresist film is exposed from the back of the transparent substrate; the negative photoresist film is developed to form an anti-corrosion pattern, which faces the inner area around the first island-shaped semiconductor film The first insulating film in the opening of the etching resist pattern is etched; the resist pattern is removed; a second insulating film is formed on the entire surface of the transparent substrate, and then a conductive film is formed thereon; in the first A first photomask pattern is formed on the conductive film above the island-shaped semiconductor film, and a second photomask pattern is formed on the conductive film above the second island-shaped semiconductor film; and the first photomask pattern is used as a photomask to etch the conductive film The first gate electrode is formed, the second mask pattern is used as the mask, and the conductive film is etched to form the second gate electrode.

According to the present invention, in the thin-film transistor forming region of the first gate insulating film with a relatively thin thickness, the surrounding portion of the first island-shaped semiconductor film is covered by the first insulating film before the first gate insulating film is formed. Therefore, if the second insulating film as the first gate insulating film and the conductive film as the first gate electrode are laminated on the first insulating film, the surrounding portion of the first island-shaped semiconductor film under the first gate electrode is separated from the first gate electrode. An insulating film and a second insulating film cover. Therefore, when the gate voltage is applied, the electric field density around the first island-shaped semiconductor thin film can be reduced to prevent the operation of the parasitic thin film transistor.

At the same time, in the thin film transistor forming area of the first gate insulating film with a thicker portion, the first island-shaped semiconductor film is used as a mask, so that the exposure source is irradiated from the back of the glass substrate on the first island-shaped semiconductor film. Above the unexposed area of the negative photoresist film, so the unexposed area can be exposed in a self-adjusting manner within the range where light can be emitted from the periphery of the first island-shaped semiconductor film, and the surrounding part of the first island-shaped semiconductor film can be very precise The ground is covered by the first insulating film. Therefore, the edge of the first island-shaped semiconductor film can be minimized in the channel width direction, and the thin film transistor can be minimized.

The method for manufacturing a thin film transistor device published in the third item of the scope of patent application of the present invention includes the steps of forming a first island-shaped semiconductor film and a second island-shaped semiconductor film on a substrate; forming a layer for covering the first island-shaped semiconductor film; A semiconductor film of an island-shaped semiconductor film and a second island-shaped semiconductor film, and then an insulating film is formed on the semiconductor film; the insulating film above the second island-shaped semiconductor film is selectively etched to form an insulating film pattern; The semiconductor film under the film pattern and in other areas is oxidized to form a first gate insulating film composed of an insulating film formed by oxidizing the semiconductor film on the first island-shaped semiconductor film, and on the second island-shaped semiconductor film A second gate insulating film composed of an insulating film and an insulating film pattern formed by oxidizing the semiconductor film is formed on the film; and a first gate electrode is formed on the first gate insulating film, and the second gate is insulated A second gate electrode is formed on the film.

According to the present invention, when the insulating film as part of the second gate insulating film is formed by etching the insulating film on the semiconductor film, the first island-shaped semiconductor film is protected by the underlying semiconductor film. Therefore, the first island-shaped semiconductor film is protected by the underlying semiconductor film. The channel region of an island-shaped semiconductor thin film is not exposed to the plasma of the etching gas of the insulating film, so the characteristics of the thin film transistor with the thinner first gate insulating film can be prevented from deteriorating, thus ensuring a thicker second gate Both the thin film transistor of the insulating film and the thin film transistor with the thinner first gate insulating film have excellent characteristics.

Moreover, the underlying substrates of the first and second island-shaped semiconductor films are also protected by the semiconductor film. Therefore, even if the insulating film is formed on the surface of the substrate, there will be no "scratch" at the edge of the first and second island-shaped semiconductor films. Except part". If it is not protected, the "scratch part" will be generated on the edge when etching the silicon oxide film on the surface of the substrate.

In addition, when the insulating film as part of the second gate insulating film is formed by etching the insulating film on the semiconductor film, since the semiconductor film is resistant to the etchant of the insulating film, the film thickness will not decrease . In this embodiment, since the first gate insulating film is formed by oxidizing the semiconductor film, the film thickness of the first gate insulating film can be controlled quite accurately.

The manufacturing method of a thin film transistor device published in the 7th item of the scope of patent application of the present invention includes the steps of forming a first semiconductor film on a substrate; continuously forming a first insulating film and a first semiconductor film on the first semiconductor film. Two semiconductor films and a second insulating film; the second insulating film is selectively etched to form a second insulating film pattern; the second semiconductor film is selectively etched to form an island without the second insulating film pattern The second semiconductor film and an island-shaped second semiconductor film containing a second insulating film pattern; the second insulating film pattern and the island-shaped second semiconductor film under other regions are oxidized by the first insulating film, and the first The area of the semiconductor film that is not covered by the island-shaped second semiconductor film is oxidized to form a first island-shaped layer consisting of an area of the first semiconductor film covered by the island-shaped second semiconductor film without the second insulating film pattern Semiconductor thin film, and also forming a second island-shaped semiconductor thin film consisting of a region of the first semiconductor thin film covered by an island-shaped second semiconductor thin film containing a second insulating film pattern, and then on the first island-shaped semiconductor thin film A first gate insulating film composed of an insulating film formed by oxidizing the second semiconductor film and a first insulating film is formed, and then a layer of the second insulating film pattern and a layer of the second insulating film are formed on the second island-shaped semiconductor film. A second gate insulating film composed of an insulating film formed by oxidizing the second semiconductor thin film and the first insulating film; and forming a first gate electrode on the first gate insulating film, and forming a second gate on the second gate insulating film electrode.

According to the present invention, when the insulating film as a part of the second gate insulating film is formed by etching the insulating film on the semiconductor film, the first island-shaped semiconductor film is protected by the second semiconductor film on the bottom layer, so , The channel region of the first island-shaped semiconductor thin film is not exposed to the plasma of the etching gas of the second insulating film, so it can prevent the thin film transistor with the thinner first gate insulating film from degrading, thus ensuring the Both the thin film transistor with the thick second gate insulating film and the thin film transistor with the thinner first gate insulating film have excellent characteristics.

At the same time, the second insulating film, which is the thicker part of the second gate insulating film on the second semiconductor film, is etched, and then the second semiconductor film is oxidized, and the first semiconductor film under the second semiconductor film is selectively oxidized, The first and second island-shaped semiconductor films are formed. In this way, since the surface of the underlying substrate is not exposed to etching gas or the like, so-called "scratch portions" are not generated at the edge portions of the first and second island-shaped semiconductor films.

In addition, when the insulating film as a part of the second gate insulating film is formed by etching the second insulating film, the second semiconductor film is resistant to the etchant of the second insulating film, so the film thickness will not reduce. In this embodiment, since the first gate insulating film is composed of both the insulating film formed by oxidizing the second semiconductor film and the first insulating film, the film thickness of the first gate insulating film can be controlled quite accurately .

A thin film transistor device published in the 11th item of the scope of patent application of the present invention includes a first thin film transistor, which includes a first island with a pair of source/drain regions and a channel region therebetween. A first gate insulating film made of a first insulating film formed on the channel region of the first island-shaped semiconductor film; and a first gate insulating film made of a first conductive film formed on the first gate insulating film A gate electrode; and a second thin film transistor, which includes a layer of a second island-shaped semiconductor film with a pair of source/drain regions to insert a channel region therebetween; a layer consisting of a second island-shaped semiconductor film A second gate insulating film made of a first insulating film and a second insulating film formed on the channel region; and a second gate electrode made of a second conductive film formed on the second gate insulating film, the first thin film electric Both the crystal and the second thin film transistor are formed on the same substrate; the first thin film transistor is provided by the second insulating film over the edge of the side part of the first island-shaped semiconductor film and on the first gate electrode The electric field relaxation electrode is formed by the second conductive film, and the second thin film transistor is provided with the first conductive film under the second gate electrode and above the edge of the side part of the second island-shaped semiconductor film through the first insulating film. The formed electric field relaxes the electrode.

According to the present invention, in the first thin film transistor device, an electric field relaxation electrode is provided on the first gate electrode by the second silicon oxide film above the edge of both sides of the first island-shaped semiconductor film. Therefore, compared to the capacitance formed by the first island-shaped semiconductor film, the first insulating film and the first gate electrode, the parasitic capacitance at this portion is larger than the electrostatic capacitance formed by the first gate electrode and the electric field relaxation electrode. Therefore, if the gate of the TFT is driven by alternating current, the change of the gate potential acting on the edge portions of both sides of the first island-shaped semiconductor film will be slowed down, so the parasitic electricity formed at the edge portions of both sides of the first island-shaped semiconductor film can be suppressed. The crystal works.

And in the second thin film transistor device, the electric field relaxation electrode is provided under the second gate electrode by the first silicon oxide film above the two side edges of the second island-shaped semiconductor film. Therefore, if the potential of the electric field relaxation electrode is set to the potential when the channels on both sides of the second island-shaped semiconductor film cannot conduct electricity, the conductivity of the channels on both sides of the second island-shaped semiconductor film can be suppressed, and Since the electric field induction of the second gate electrode can be isolated, the turning on of the parasitic transistor can be suppressed.

The method for manufacturing a thin film transistor device published in the 12th item of the scope of patent application of the present invention includes the steps of forming a first island-shaped semiconductor film and a second island-shaped semiconductor film on a substrate; forming a layer for covering the first island-shaped semiconductor film A first insulating film of an island-shaped semiconductor film and a second island-shaped semiconductor film; a first conductive film is formed on the entire surface, and then the first conductive film is selectively etched so that the first insulating film above the first island-shaped semiconductor film A gate electrode is formed on an insulating film; a second insulating film and a second conductive film are continuously formed on the entire surface; a photomask pattern is formed on the second conductive film, and then the photomask pattern is used as the photomask, and the first The two conductive films are side-etched to form a second gate electrode with a narrower width than the mask pattern. The mask pattern is used as the mask, and the second insulating film is anisotropically etched with the first gate electrode and the mask pattern. As a photomask, the first insulating film is etched anisotropically, so that a first gate insulating film made of the first insulating film is formed under the first gate electrode, and a first gate insulating film made of the first insulating film is formed under the second gate electrode. A second gate insulating film composed of a first insulating film and a second insulating film; removing the mask pattern; using the first gate electrode as the mask, and implanting an impurity into the first island-shaped semiconductor film by ion implantation, A high-concentration impurity region is formed on both sides of the first gate electrode, and the second gate electrode and the second gate insulating film are used as masks to implant impurities into the second island-shaped semiconductor film by ion implantation. A pair of high-concentration impurity regions are formed on both sides of the gate electrode; and the second gate electrode is used as a mask. Under a condition that ions can pass through the second gate insulating film around the second gate electrode, ion implantation is used to implant Impurities are implanted into the second island-shaped semiconductor film, and a pair of low-concentration impurity regions are formed under the second gate insulating film on both sides of the second gate electrode.

According to the present invention, the second conductive film is side-etched using the mask pattern to form a second gate electrode with a narrower width than the mask pattern. In addition, the first and second insulating films are anisotropically etched using the same mask pattern to form a second gate insulating film wider than the second gate electrode. Then, under the condition that the ions cannot pass through the second gate electrode and the second gate insulating film, an ion implantation process is performed to form a high-concentration impurity region. In addition, under the condition that ions cannot pass through the second gate electrode but can pass through the second gate insulating film, an ion implantation process is performed to form a low-concentration impurity region in the second island-shaped semiconductor film. Therefore, the low-concentration impurity region and the high-concentration impurity region are sequentially formed in the second island-shaped semiconductor film from the end of the channel, so that the channel region under the second gate electrode can be inserted in between

Therefore, if the width of the side etching is adjusted to the required width of the LDD region, the gate electrode and the gate insulating film can be used without increasing the number of exposure masks to form the LDD structure in a self-adjusting manner.

Moreover, since the first and second gate insulating films each having different thicknesses can be formed by one etching step, the forming step can be simplified. In this example, since the channel regions in the first and second island-shaped semiconductor films are not exposed to the plasma of the etching gas together, it is possible to prevent the surface of the channel regions in the first and second island-shaped semiconductor films from being damaged. .

A liquid crystal display device published in the 16th item of the scope of patent application of the present invention includes a first thin film transistor; a second thin film transistor; the first thin film transistor and the second thin film transistor system are formed on a substrate ; A pixel electrode connected to the source/drain region of the second thin film transistor; and a storage capacitor bus line intersecting the pixel electrode; wherein the first thin film transistor includes a layer with a pair of source/drain regions, in order to A first island-shaped semiconductor film interposed in a channel region; a first gate insulating film made of a first insulating film formed on the channel region of the first island-shaped semiconductor film; and a first gate insulating film on top The first gate electrode made of the first conductive film formed, the second thin film transistor includes a second island-shaped semiconductor film having a pair of source/drain regions with a channel region interposed therebetween, and the pair of source / Any one of the drain regions is connected to the pixel electrode; a second gate insulating film made of the first insulating film and the second insulating film formed on the channel region of the second island-shaped semiconductor film; and a second gate insulating film made of the second insulating film The second gate electrode is made of the second conductive film formed on the gate insulating film, and the storage capacitor bus line is formed by the first conductive film, and the second insulating film and the second conductive film connected to the pixel electrode are based on this They are sequentially stacked in a partial area above the storage capacitor bus line.

According to the present invention, the storage capacitor bus line in the display part and the first gate electrode of the first thin film transistor are formed of the same material. Moreover, the second insulating film and the second conductive film connected to the pixel electrode are laminated on the storage capacitor bus line in this order. In other words, in the formed capacitor element, one of the electrodes is formed by the storage capacitor bus line The capacitor insulating film is formed of the same material as the second insulating film of the second gate insulating film, and the other electrodes are formed of a second conductive film made of the same material as the second gate electrode.

Therefore, since the gate insulating film formed is usually thinner, the capacitor element has a higher per unit area than the capacitor element having other electrodes made of an ITO film and a capacitor insulating film made of an interlayer insulating film. capacitance. Furthermore, this will reduce the area of the storage capacitor bus line required to form the storage capacitor, that is, the light shielding area, and therefore can increase the aperture ratio.

A liquid crystal display device published in the 17th item of the scope of patent application of the present invention includes a first thin film transistor; a second thin film transistor; the first thin film transistor and the second thin film transistor system are formed on a substrate ; A pixel electrode connected to the source/drain region of the second thin film transistor; and a storage capacitor bus line intersecting the pixel electrode; wherein the first thin film transistor includes a layer with a pair of source/drain regions, in order to A first island-shaped semiconductor film interposed in a channel region; a first gate insulating film made of a first insulating film formed on the channel region of the first island-shaped semiconductor film; and a first gate insulating film on top The first gate electrode made of the first conductive film formed, the second thin film transistor includes a second island-shaped semiconductor film having a pair of source/drain regions with a channel region interposed therebetween, and the pair of source / Any one of the drain regions is connected to the pixel electrode; a second gate insulating film made of the first insulating film and the second insulating film formed on the channel region of the second island-shaped semiconductor film; and a second gate insulating film made of the second insulating film The second gate electrode is made of the second conductive film formed on the gate insulating film, and the storage capacitor bus line is formed by the first conductive film, and the storage capacitor bus line provides a third film in a part of its area Transistor, the third thin film transistor includes a gate electrode formed by a storage capacitor bus line, a third island-shaped semiconductor film with source/drain regions connected to the pixel electrode, and a layer made of a first insulating film Chengzhi gate insulating film.

According to the present invention, there is provided a storage capacitor bus line constructed with a first conductive film made of the same material as the first gate electrode, and a third film containing the storage capacitor bus line gate electrode in a partial area of itself Transistor. And in the third thin film transistor, the source/drain region of the third island-shaped semiconductor thin film is connected to the pixel electrode in it, and the gate insulating film is made of the same material as the first insulating film of the second gate insulating film become.

If a gate voltage that can always open the channel area is applied to the gate electrode, the third island-shaped semiconductor film can be used as an electrode with a low impedance value, and a storage capacitor element with a storage capacitor bus line can be formed as a The electrodes, the first insulating film serve as capacitor insulating films, and the third island-shaped semiconductor thin film serves as other electrodes.

Therefore, since the gate insulating film formed is generally thinner, the capacitor element has a higher capacitance per unit area than the storage capacitor element having ITO as the other electrode and the interlayer insulating film as the capacitor insulating film. Furthermore, this will reduce the area of the storage capacitor bus line required to form the storage capacitor, that is, the light shielding area, and therefore can increase the aperture ratio.

Schematic description

Figure 1 shows a cross-sectional view of a thin film transistor device in the prior art;

Figure 2 shows a cross-sectional view of the problem of the thin film transistor device manufacturing method in the prior art;

Figures 3A and 3B show cross-sectional views of another problem in the manufacturing method of thin film transistor devices in the prior art;

Figure 4A shows a plan view of an intermediate step of the thin film transistor device manufacturing method in the prior art, and Figure 4B shows a plan view of another intermediate step of the same thin film transistor device manufacturing method, and Figure 4B The bottom side view is a cross-sectional view taken along the line XIV-XIV of the top side view;

Figure 5 shows a cross-sectional view of another thin film transistor device in the prior art;

Figures 6A and 6B show cross-sectional views of another problem in the manufacturing method of thin film transistor devices in the prior art;

Figure 7 shows a block diagram of a configuration of the thin film transistor device (emissive liquid crystal display device) of the first embodiment of the present invention;

Figure 8 shows a plan view of the thin film transistor device of the first embodiment of the present invention;

Figures 9A to 9P show several cross-sectional views of the method of manufacturing a thin film transistor device according to the first embodiment of the present invention;

Figure 10A shows a plan view of an intermediate step of the thin film transistor device manufacturing method of the first embodiment of the present invention, and Figure 10B shows a plan view of another intermediate step of the same thin film transistor device manufacturing method from the top side view , The bottom side view of Figure 4B is a cross-sectional view taken along the line II-II of the top side view.

Figure 11A shows a plan view of another intermediate step of the thin film transistor device manufacturing method of the first embodiment of the present invention, and Figure 11B shows the top side view of another intermediate step of the same thin film transistor device manufacturing method The plan view, the bottom side view of Figure 4B is a cross-sectional view taken along the line III-III of the top side view;

Figures 12A to 12H show several cross-sectional views of a method of manufacturing a thin film transistor device according to a second embodiment of the present invention;

Figures 13A to 13D show cross-sectional views of another method of manufacturing a thin film transistor device according to the second embodiment of the present invention;

Figures 14A to 14F show cross-sectional views of a method of manufacturing a thin film transistor device according to a third embodiment of the present invention;

Figure 15 shows a cross-sectional view of another method of manufacturing a thin film transistor device according to the third embodiment of the present invention;

FIG. 16A shows a plan view of the thin film transistor device according to the third embodiment of the present invention, and FIG. 16B is a cross-sectional view taken along the line VV of FIG. 16A;

Figure 17A shows a plan view of another thin film transistor device according to the third embodiment of the present invention, and Figure 17B is a cross-sectional view taken along the line VII-VII of Figure 17A;

Figure 18 shows a cross-sectional view of a liquid crystal display device having the thin film transistor device of the fourth embodiment of the present invention;

Figure 19A is also a cross-sectional view taken along the line IX-IX of Figure 18, and Figure 19B is a cross-sectional view also taken along the line XX of Figure 18;

FIG. 20 is a plan view of a liquid crystal display device having the thin film transistor device of the fifth embodiment of the present invention;

Figure 21A is also a cross-sectional view taken along the line XII-XII in Figure 20, and Figure 21B is a cross-sectional view also taken along the line XIII-XIII in Figure 20.

[Implementation mode]

Detailed description of the preferred embodiment

Hereinafter, various embodiments of the present invention will be described with reference to the drawings.

(First embodiment)

(Structure of thin film transistor device)

Fig. 7 shows a configuration block diagram of the thin film transistor device (emissive liquid crystal display device) of the first embodiment of the present invention, and Fig. 8 shows the configuration plan view of one of the pixels of the display part. The following example will illustrate the XGA (1024x768 pixel) mode liquid crystal display device in this example. A pixel is composed of three pixels, R (red), G (green), and B (blue).

The liquid crystal display device in this first embodiment includes a control circuit 101, a vertical driver 102, a gate driver 103, and a display section 104. The display signal RGB, horizontal synchronization signal Hsync, vertical synchronization signal Vsync and other signals are transmitted from an external device such as a computer (not shown) to this LCD device, and the high voltage V_H(18V), low voltage V_L(3.3V or 5V) and ground potential V_GNDIt is provided by a power supply (not shown).

In this article, the display portion 104 is configured with 3072 (1024xGRB)x768 pixels in the horizontal and vertical directions, and each pixel is composed of n-channel type TFT 105 (hereinafter referred to as "n-type TFT", unless otherwise mentioned, Then TFT means n-type TFT), a display unit (liquid crystal unit) 106 connected to the source electrode of the TFT 105, and a storage capacitor 107.

The display unit 106 is composed of a pair of electrodes, one of which is connected to the pixel electrode 110 of the source electrode of the TFT 105, and the other electrode is an electrode (not shown) arranged on the CF substrate, liquid crystal (not shown) ) Is sealed between these electrodes.

At the same time, the display portion 104 is configured with 3072 data bus lines 108 extending in the vertical direction, 768 gate bus lines 109 extending in the horizontal direction, and several storage capacitor bus lines 111 also extending in the horizontal direction. Each TFT105 gate electrode of the pixels arranged in the horizontal direction is connected to the same gate bus line 109, and each TFT105 drain electrode of the pixels arranged in the vertical direction is connected to the same data bus line 108, and the storage capacitor bus line 111 It crosses the pixel electrode 110 and constitutes one electrode of the pair of electrodes of the storage capacitor 107. The pixel electrode 110 of the storage capacitor 107 forms a pair of electrodes with the storage capacitor bus line 111, and the interlayer insulating film disposed between the pair of electrodes serves as the capacitor insulating film.

After the control circuit 101 receives the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync, it then outputs a data enable signal DSI that is activated at the beginning of the horizontal synchronization period, a data clock DCLK that divides the horizontal synchronization period into predetermined intervals, and one for the vertical synchronization A gate start signal GSI activated at the beginning of the cycle and a gate clock GCLK that divides the vertical cycle into predetermined intervals. This control circuit 101 is composed of n-type TFT and p-channel type TFT (p-type TFT), both of which pass the low voltage V_LOperation.

The vertical driver 102 is composed of a shift register 102a, a horizontal shifter 102b and an analog switch 102c.

The shift register 102a has 3072 output electrodes. The shift register 102a is activated by the data enable signal DSI. Then, while the data clock DCLK is output, each output electrode continuously outputs a low voltage (3.3V). Or 5V) effective signal. The shift register 102a is composed of n-type TFT and p-type TFT, both of which pass the low voltage V_LOperation.

The horizontal shifter 102b has 3072 input electrodes and 3072 output electrodes. The horizontal shifter 102b converts the low-voltage effective signal output by the shift register 102a into a high-voltage (18V) signal, and then outputs the high-voltage signal . The horizontal shifter 102b is driven by the low voltage V_LOperating n-type TFT and p-type TFT with high voltage V_HIt is composed of working n-type TFT and p-type TFT.

The analog switch 102c also has 3072 input electrodes and 3072 output electrodes. The output electrodes of the analog switch 102c are respectively connected to the corresponding data bus lines 108. When the analog switch 102c receives a valid signal from the horizontal shifter 102b, it will output the display signal RGB (any one of the R signal, G signal, and B signal) to the input electrode corresponding to the valid signal Output electrode. The analog switch 102c is composed of n-type TFT and p-type TFT, both of which pass the high voltage V_HOperation.

In other words, the vertical driver 102 continuously outputs the R signal, G signal, and B signal to 3072 data bus lines 108 of the display part 104 during the horizontal synchronization period while outputting the data clock DCLK.

The gate driver 103 is composed of a shift register 103a, a horizontal shifter 103b and an output buffer 103c.

The shift register 103a has 768 output electrodes. The shift register 103a is activated by the gate activation signal, and then continuously outputs a low voltage (3.3V or 5V) horizontal signal from each output electrode while the gate clock GCLK is output. The shift register 103a is composed of n-type TFT and p-type TFT, both of which pass the low voltage V_LOperation.

The horizontal shifter 103b has 768 input electrodes and 3072 output electrodes, and each output electrode of the output buffer 103c is respectively connected to the corresponding gate bus line 109. The output buffer 103c sends the horizontal signal output by the horizontal shifter 103b to the gate bus line 109 through the output terminal corresponding to the input terminal. The output buffer 103c is composed of n-type TFT and p-type TFT, both of which pass the low voltage V_HOperation.

In other words, the gate driver 103 continuously outputs horizontal signals to 3072 gate bus lines 109 of the display part 104 during the vertical synchronization period while outputting the gate clock GCLK.

When the horizontal signal reaches the gate bus line 109, the TFT 105 of the display part 104 is turned on. At this time, when the display signal RGB (any one of the R signal, G signal, and B signal) is sent to the data bus line 108, the display signal RGB is loaded into the display unit (liquid crystal unit) 106 and the storage capacitor 107. Then, the tilt angle of the liquid crystal molecules in the display unit (liquid crystal unit) 106 will change in response to the display signal RGB, thus changing the light transmittance of the display unit 106, so the display can be displayed by controlling the light transmittance of the display unit 106 of each pixel The desired image.

In the following embodiments, the TFT provided in the display part 104 is called a pixel TFT, and among the TFTs provided by the vertical driver 102 and the gate driver 103, the TFT driven by a high voltage (18V) is called a high voltage driving TFT. In addition, among the TFTs provided by the control circuit 101, the vertical driver 102, and the gate driver 103, a TFT driven by a low voltage (3.3V or 5V) is called a low-voltage driving TFT.

(Thin film transistor structure used in liquid crystal display devices)

The structure of the above three types of TFTs will be described below. In this text, since the high-voltage driving TFT and the pixel TFT have almost the same structure, the pixel TFT is used as a substitute for description, and the description of the high-voltage driving TFT will be omitted here. At the same time, since the p-type TFT and the n-type TF-T have almost the same structure, the description of the p-type TFT will be omitted here.

The left side view of FIG. 9P shows a cross-sectional view of the low-voltage driving TFT structure, and the right side view of the figure shows a cross-sectional view of the pixel TFT structure. These views show a cross-sectional view taken along the line II in Figure 8.

As shown in the left side view of Fig. 9P, in the low-voltage driving TFT, a layered underlying insulating film 22 composed of a silicon nitride film 22a and a silicon oxide film 22b is first formed on a glass substrate 21, and then On the bottom insulating film 22 is formed a first island-shaped semiconductor film 24a made of a polysilicon film and used as a TFT working layer. A pair of high-concentration TFT source/drain electrodes are formed in the first island-shaped semiconductor film 24a. Impurity regions (ohmic contact regions) 24aa, 24ab, to insert a channel region 24ac therebetween.

There is a layer of silicon oxide (SiO₂) A gate insulating film made of the thin film 28a is formed on the underlying insulating film 22 and the first island-shaped semiconductor film 24a, and a gate electrode 29a is formed on the silicon oxide film 28a. In the low-voltage driving TFT, the two sides of the high-concentration impurity regions 24aa and 24ab on the side of the channel region are almost directly below the edge of the gate electrode 29a. A silicon oxide film 31 with a thickness of 90 nm and a silicon fluoride (SiN) film 32 with a thickness of 350 nm are laminated on the silicon oxide film 28a and the gate electrode 29a. On the silicon nitride film 32, several electrodes (a source Pole and a drain) 34a34b. These electrodes 34a, 34b are energized with the high-concentration impurity regions 24aa, 24ab through the metal buried in the contact holes 33a, 33b, and the contact holes 33a, 33b are respectively connected from an upper surface of the silicon nitride film 32 to the high-concentration impurities Area 24aa, 24ab.

As described above, in the low-voltage driving TFT, the gate insulating film is only formed by the silicon oxide film 28a with a thickness of 30 nm, and the LDD region is not provided, so that it can perform high-speed operation at low voltage. Since the high-concentration impurity regions 24aa, 24ab can be formed with the gate electrode 29a in a self-adjusting manner, it can be easily made into a miniaturized device. In this example, the low-voltage driving TFT does not provide an LDD region. However, because this type of TFT is driven by a low voltage, the number of hot electrons is quite small, so the reduction of ON characteristics and the increase of OFF current caused by hot electrons can be avoided. .

Next, as shown in the right side view of Figure 9F, in the pixel TFT, an underlying insulating film 22 with the same layered structure as described above is formed on the glass substrate 21, and a layer made of polysilicon film is formed on the underlying insulating film 22 And the second island-shaped semiconductor film 24a as the working layer of the TFT. A pair of n-type high-concentration impurity regions (ohmic contact regions) 24ba, 24bb are formed in the second island-shaped semiconductor film 24b as the source/drain of the TFT. , To insert a channel area 24be between them. Furthermore, LDD regions 24bc, 24bd as n-type low-concentration impurity regions are formed at the end portions of these n-type high-concentration impurity regions 24ba, 24bb on the side of the channel region 24be.

A gate oxide film formed by laminating a silicon oxide film 25a with a thickness of 90nm and a silicon oxide film 28b with a thickness of 30nm is formed on the underlying insulating film 22 and the second island-shaped semiconductor film 24b, and then on the silicon oxide film A gate electrode 29b is formed on 28b. The gate electrode 29b is integrally formed with the gate bus line 109, and the storage capacitor bus line 111 and the gate electrode 29b are made of the same material.

In this pixel TFT, when viewed from the upper side, the edges of the LDD regions 24bc and 24bd on the channel region 24be side are located almost directly below the two sides of the gate electrode 29b, respectively. In the pixel TFT, since positive and negative signals are used as the display signal, unless the LDD regions 24bc and 24bd are provided on both the source side and the drain side, the characteristics of the transistor will be degraded due to hot electrons.

The exposed surface of the gate electrode 29b is covered with a silicon oxide film 31 and a silicon nitride film 32 with a thickness of 350 nm. A number of electrodes (source/drain) 34c and 34d are formed on the silicon nitride film 32. These electrodes 34a, 34b are energized with the high-concentration impurity regions 24ba, 24bb through the metal buried in the contact holes 33c, 33d, and the contact holes 33c, 33d are respectively connected from the upper surface of the silicon nitride film 32 to the high-concentration impurity region 24ba, 24bb. The source/drain 34c of the source/drain 34c and 34d is integrally formed with the data bus line on the drain side.

As described above, according to these pixel TFTs, since the gate insulating film is formed of a thick silicon oxide film (silicon oxide film 25a + silicon oxide film 28b) with a thickness of 120 nm, the breakdown voltage of the pixel TFT is quite high, so this type of pixel TFT can be Driven by high voltage.

In this example, the description of the high-voltage driving TFT is omitted in this article. One difference from the pixel TFT is that this high-voltage driving TFT only has an LDD region on the drain side where the high voltage is applied, and the high-voltage driving p-type in the surrounding circuit TFT does not provide an LDD area, and its description will be omitted here. The reason is that in the p-type TFT paradigm, since the hole is used as the carrier, the heat carrier is rarely generated, and unless the LDD area is provided, the heat carrier will never interfere with the characteristics of the transistor.

(Method of manufacturing thin film transistor device)

Next, referring to FIGS. 9A to 9P and FIGS. 11A to 11B, the method of manufacturing the thin film transistor device of the first embodiment will be described. In this example, the left side views of FIGS. 9A to 9P are cross-sectional views of the low-voltage driving TFT forming area, and the right side views thereof are the cross-sectional views of the pixel TFT forming area. Meanwhile, FIG. 10A is a plan view of FIG. 9K, which is the middle part of the entire low-voltage driving TFT manufacturing process. The top side view of Figure 10B is a plan view of Figure 9L, which is also the middle part of the entire low-voltage driver TFT manufacturing process, and the bottom side view of Figure 10B is taken along the line II-II of the top side view. A cross-sectional view of. FIG. 11A is a plan view of FIG. 9K, which is the middle part of the entire pixel TFT manufacturing process. The top side view of Figure 11B is a plan view of Figure 9L, which is also the middle part of the entire pixel TFT manufacturing process, and the bottom side view of Figure 11B is a cross-sectional view taken along the line III-III of the top side view. .

As shown in Figure 9A, first a silicon nitride film 22a with a thickness of about 50 nm and a silicon oxide film 22b with a thickness of 200 nm are formed by plasma CVD as the underlying insulating film on the glass substrate 21, and then on the silicon oxide film 22b A layer of amorphous silicon film 24 with a thickness of about 50 nm is formed.

After that, in order to reduce the hydrogen content in the amorphous silicon film 24, annealing is performed at a temperature of 450°C. Next, an excimer laser is irradiated on the amorphous silicon film 24 to convert the amorphous silicon film 24 into a polysilicon film.

Afterwards, a photoresist is coated on the polysilicon film, and then a predetermined anti-corrosion mask (not shown) is formed through selective exposure and development steps. Afterwards, as shown in Figure 9B, the polysilicon film is dry-etched using this anti-corrosion mask, leaving only the first and second island-shaped semiconductor films 24a, 24b made of the polysilicon film on the predetermined area, and then move In addition to the anti-corrosion mask.

Then, as shown in Figure 9C, a first silicon oxide thin film (first insulating film) 25 with a thickness of 90 nm is formed on the entire upper surface of the glass substrate 21 by the plasma CVD method, and then the first silicon oxide film (first insulating film) 25 is formed by a coating method. A negative photoresist film 26 is formed on the thin film 25. After that, the negative photoresist film 26 is exposed by a mask that can shield the entire area of the first island-shaped semiconductor film 24a in the low-voltage driving TFT forming area. Therefore, the unexposed area of the negative photoresist film 26 will remain in the low-voltage driving TFT. The area above the first island-shaped semiconductor film 24a in the forming area is wider than the forming area of the first island-shaped semiconductor film 24a.

Then, as shown in Figure 9D, the negative photoresist film 26 is exposed from the back of the glass substrate 21. At this time, the exposure light source is shielded by the first island-shaped semiconductor film 24a. The upper portion of the predetermined internal area of the photoresist film 26 is exposed from the periphery of the first island-shaped semiconductor film 24a.

Then, as shown in FIG. 9E, the negative photoresist film 26 is developed, so the negative photoresist film 26 will form an opening 26a in the inner region instead of the circumference of the first island-shaped semiconductor film 24a.

Then, as shown in Figure 9F, the first silicon oxide film 25 is dry-etched through the opening 26a formed in the negative photoresist film 26 by development, so that the first silicon oxide film 25 will be formed in the inner area. The opening portion 25a is not on the circumference of the first island-shaped semiconductor film 24a, that is, the first silicon oxide film 25 still covers the surrounding portion of the first island-shaped semiconductor film 24a. Next, the negative photoresist film 26 is removed.

Then, as shown in FIG. 9G, a second silicon oxide thin film (second insulating film) 28 with a thickness of 30 nm is formed on the entire upper surface of the glass substrate 21 by the plasma CVD method.

Then, as shown in Figure 9H, an Al-Nd (aluminum-neodymium: neodymium content of 2%) film (conductor film) 29 with a thickness of about 300 nm is formed on the second silicon oxide film 28, and then on the Al-Nd film 29 A photoresist film 30 is formed thereon.

Then, as shown in Fig. 9I, by selectively exposing and developing the photoresist film 30, a resist mask 30a, 30b is formed in the region where the gate of each TFT is to be formed, and then as shown in Fig. 9J, The Al-Nd film 29 is etched using the anti-corrosion masks 30a and 30b to form the gate electrode 29a of the low-voltage driving TFT and the gate electrode 29b of the pixel TFT.

Afterwards, as shown in Figure 9K, the second silicon oxide film 28 is anisotropically etched using the anti-corrosion masks 30a and 30b. At this time, if viewed from the upper side, the low-voltage driving TFT forming area is as shown in Figure 10A. If viewed from the upper side, the pixel TFT forming area is as shown in Figure 11A.

Then, as shown in FIG. 9L, the first silicon oxide film 25 remaining on the glass substrate 21 and not covered by the anti-corrosion masks 30a, 30b is removed by etching. At this time, in the low-voltage driving TFT forming area, as shown in Figure 10B, the silicon oxide films 25b, 28a to cover the first island-shaped semiconductor film 24a are still located under the gate electrode 29a, where the gate electrode 29a crosses the first The area around the island-shaped semiconductor thin film 24a. At the same time, as shown in FIG. 11B, in the pixel TFT forming area, the silicon oxide films 25a, 28b to cover the second island-shaped semiconductor film 24b are still located under the gate electrode 29b, where the gate electrode 29b crosses the second island-shaped semiconductor The area around the film 24b. In the high-voltage driving TFT forming area of this example, both the thick silicon oxide film and the thin silicon oxide film to be covered with the island-shaped semiconductor film 24b are also maintained under the gate electrode.

Then remove the anti-corrosion masks 30a, 30b.

Then, as shown in Figure 9M, at 25keV acceleration voltage and 7×10¹⁴cm^-2The first and second island-shaped semiconductor films 24a, 24b are implanted with phosphorus (P) by ion implantation. This voltage allows P ions to pass through the gate electrodes 29a, 29b and the gate insulating films 28b, 25b, but Ions are not allowed to pass through the gate insulating film 28a. Therefore, regions of the first island-shaped semiconductor film 24a that are not covered by the gate electrode 29a in the low-voltage driving TFT forming area will form high-concentration impurity regions (source/drain regions) 24aa, 24ab, and at the same time, the second island-shaped semiconductor film The regions of the thin film 24b that are not covered by the gate electrode 29b and the gate insulating films 28b, 25b in the pixel TFT forming area will form high-concentration impurity regions (source/drain regions) 24ba, 24bb. At this time, the high-voltage driving TFT forming area High-concentration impurity regions (source/drain regions) are also formed in the island-shaped semiconductor film inside.

Then at 70kev acceleration voltage and 2×10¹³cm^-2Phosphorus is implanted by ion implantation at a low dose. This voltage does not allow P ions to pass through the gate electrodes 29a, 29b, but allows P ions to pass through the gate insulating films 28b, 25b. Therefore, low-concentration impurity regions (low-concentration source/drain regions) 24bc and 24bd are formed between the edges of the gate electrode 29b and the edges of the gate insulating films 28b and 25b in the pixel TFT forming area, which are used as one of the low-concentration impurity regions at this time. The LDD area is also formed on the drain side of the island-shaped semiconductor film in the high-voltage driving TFT forming area. In this example, the ion implantation acceleration voltage in the low-voltage driving TFT forming area is quite high, so ions can penetrate the first island-shaped semiconductor film 24a, so impurities will not enter the first island-shaped semiconductor film 24a.

Then, as shown in FIG. 9N, a silicon oxide film 31 with a thickness of 90 nm is formed on the entire upper surface of the glass substrate 21 by the plasma CVD method. In addition, a silicon nitride film 32 with a thickness of 350 nm is formed thereon.

Then, as shown in Fig. 90, a number of contact holes 33a, 33b passing through the silicon nitride film 32 and the silicon oxide film 31 on the high-concentration impurity regions 24aa, 24ab are formed in the low-voltage driving TFT forming area, and A number of contact holes 33c, 33d passing through the silicon fluoride film 32 and the silicon oxide film 31 on the high-concentration impurity regions 24ba, 24bb are formed in the pixel TFT forming area.

Then, as shown in Figure 9P, a Ti film with a thickness of 100 nm, an Al film with a thickness of 200 nm, and a Ti film with a thickness of 50 nm are successively deposited on the entire upper surface of the glass substrate 21, so that the contact holes 33a, 33b, 33c, and 33d are embedded in these metal films, and a layer of metal layered film is formed on the silicon nitride film 32. Afterwards, a photolithography technology is used to form an anti-corrosion mask (not shown), and then the metal film is dry-etched using this anti-corrosion mask, thereby forming a source in contact with the high-concentration impurity regions 24aa, 24ab of the low-voltage driving TFT. The drain/drain electrodes 34a, 34b, and the source/drain electrodes 34c, 34d in contact with the high-concentration impurity regions 24ba, 24bb of the pixel TFT are formed at the same time.

In this example, the data bus line 108 in the display portion 104 of the liquid crystal display device is formed at the same time as the source/drain electrodes 34a to 34d, and in the forming area of the control circuit 101, the vertical driver 102 and the gate driver 103, The predetermined wiring pattern is formed simultaneously with the source/drain electrodes 34a and 34d. After coating with photosensitive resin, a resin film with a thickness of 3.0μm is formed in sequence.

As described above, the thin film transistor device is completed. In order to manufacture the liquid crystal display device, the following steps are continuously performed.

After that, in a predetermined area of the resin film 35, a through hole leading to the source/drain electrode 34d is formed by the wiring pattern. Then, an ITO (Indium Tin Oxide) thin film with a thickness of 70 nm is formed on the entire upper surface of the glass substrate 21 by a sputtering method. Then, using standard photolithography steps, the ITO film is patterned to form a pixel electrode 36 that is energized with the source-side impurity region of the pixel TFT. Next, an alignment film (not shown) is formed on the entire upper surface of the glass substrate 21 to determine the initial state of the liquid crystal molecules (when no voltage is applied).

In this way, the TFT substrate of the liquid crystal display device is completed.

The counter substrate of the liquid crystal display device is formed by a well-known method. In more detail, the black matrix used to cover the area between the pixels from light is formed of Cr (chromium) on the glass substrate, and is formed on the glass substrate. Red, green, and blue color filters are formed on the substrate, and color filters having any of red, green, or blue are arranged for each pixel. Then, a transparent electrode made of ITO film is formed on the entire upper surface of the glass substrate, and an alignment film is formed on the transparent electrode.

The liquid crystal display panel is constructed by pasting the TFT substrate made in this way and the opposite substrate together, and then injecting liquid crystal between them, and sealing the injection port. After that, polarizing plates are arranged on both sides of the liquid crystal display panel, and a backlight source is arranged on the back to complete the liquid crystal display device.

As described above, according to the first embodiment of the present invention, in the low-voltage driving TFT forming area depicted in Fig. 9F, the surrounding portion of the first island-shaped semiconductor film 24a is covered by the thick silicon oxide film 25, which is The gate insulating film 28 is used as a part of the thick gate insulating film of the high-voltage driving TFT before being formed. In this state, the second silicon oxide film 28 as the gate insulating film and the metal film 29 as the gate electrode are laminated on the thick silicon oxide film 25 immediately. Then, as shown in Fig. 9L, the gate electrode 29a and the gate insulating film 28a are formed by etching using a stripe-shaped resist mask 30a intersecting the first island-shaped semiconductor film 24a. Therefore, as shown in FIG. 10B, the surrounding portion of the first island-shaped semiconductor film 24a under the gate electrode 29a is covered by the thick silicon oxide film 25b in addition to the silicon oxide film 28a. Therefore, when the gate voltage is applied, the operation of the parasitic TFT can be prevented by reducing the electric field density at the surrounding portion of the first island-shaped semiconductor film 24a.

As shown in Figures 9C and 9D, in the low-voltage driving TFT forming area, when the first island-shaped semiconductor film 24a is used as a mask, the exposure source is irradiated on the first island-shaped semiconductor film 24a from the back of the glass substrate 21 The upper negative photoresist film 26 has an unexposed area, so the unexposed area can be exposed in a self-adjusting manner within the range where light is emitted from the periphery of the first island-shaped semiconductor film 24a, so the area around the first island-shaped semiconductor film 24a Part can be covered by the silicon oxide film 25 very accurately. Therefore, the size edge of the first island-shaped semiconductor film 24a can be minimized in the channel width direction, and the TFT can be minimized.

(Second embodiment)

Next, the second embodiment of the present invention will be described below with reference to the drawings.

(Thin film transistor device structure used in liquid crystal display device)

Hereinafter, the structure of the thin film transistor device used in the liquid crystal display device of the second embodiment will be described with reference to FIG. 12H. In this article, since the high-voltage driving TFT and the pixel TFT have almost the same structure, the pixel TFT is used as a substitute for description in the following, and the description of the high-voltage driving TFT will be omitted here. At the same time, since the p-type TFT and the n-type TFT have almost the same structure, the description will be omitted here.

The left side view of FIG. 12H shows a cross-sectional view of the n-channel type low voltage driving TFT structure, and the right side view of FIG. 12H shows a cross-sectional view of the n-channel type pixel TFT structure.

As shown in the left side view of FIG. 12H, firstly, on the glass substrate 21, an underlying insulating film 22 of a layered structure composed of a 50nm thick silicon nitride film 22a and a 200nm thick silicon oxide film 22b is formed, and the underlying insulating film 22 is formed thereon. On the film 22 is formed a first island-shaped semiconductor film 24a made of a 40nm thick polysilicon film and used as the TFT working layer. A pair of high-concentration impurities is formed in the first island-shaped semiconductor film 24a as the source/drain of the TFT. Areas (ohmic contact areas) 24aa, 24ab to place the channel area 24ac in between.

A first gate insulating film 51a made of a silicon oxide film 28a with a thickness of about 30 nm is formed on the underlying insulating film 22 and the first island-shaped semiconductor film 24a. The gate insulating film 51a is formed by oxidizing the amorphous silicon film. become.

At the same time, the first gate electrode 54a is formed on the first gate insulating film 51a, and the two sides of the high-concentration impurity regions 24aa, 24ab on the side of the channel region are almost directly below the edge of the gate electrode 54a.

A silicon nitride film 55 (first interlayer insulating film) with a thickness of 370 nm is formed on the first gate insulating film 51a and the first gate electrode 54a, and a pair of source/drain electrodes are formed on the silicon nitride film 55 57a, 57b. These source/drain electrodes 57a, 57b are energized with the high-concentration impurity regions 24aa, 24ab through the metal buried in the contact holes 56a, 56b. The contact holes 56a, 56b are connected to the high-concentration impurity regions from an upper surface of the silicon nitride film 55. The impurity regions 24aa and 24ab communicate with each other.

As described above, since the first gate insulating film 51a is only formed of a silicon oxide film with a thickness of about 30 nm and no LDD region is provided, the low-voltage driving TFT can perform high-speed operation at low voltage. Moreover, since the high-concentration impurity regions 24aa, 24ab can be formed with the first gate electrode 54a in a self-adjusting manner, a miniaturized device can be easily made. In this example, the low-voltage driving TFT does not provide an LDD region. Since this type of TFT is driven by a low voltage, the number of hot electrons is relatively small, and therefore the reduction of ON characteristics and the increase of OFF current caused by hot electrons can be avoided.

Next, as shown in the right side view of Figure 12H, in the pixel TFT, an underlying insulating film 22 having the same layered structure as described above is formed on the glass substrate 21, and a second island-shaped semiconductor film 24b is formed on the underlying insulating film 22 , As the working layer of TFT. In the second island-shaped semiconductor film 24b, a pair of n-type high-concentration impurity regions 24ba, 24bb serving as ohmic contact regions of the TFT source/drain are formed to interpose the channel region 24be. Moreover, n-type low-concentration impurity regions (LDD regions) 24bc, 24bd are formed at the edge portions of these high-concentration impurity regions 24ba, 24bb on the side surface of the channel region 24be, respectively.

A silicon oxide film 51a with a thickness of about 10 nm and a silicon oxide film 52b with a thickness of 100 nm are laminated on the underlying insulating film 22 and the second island-shaped semiconductor film 24b, and then a second gate electrode 54b is formed on the silicon oxide film 52b. The layered structure composed of the silicon oxide film 51a and the silicon oxide film 52a under the second gate electrode 54b constitutes the second gate insulating film.

In this pixel TFT, when viewed from the upper side, the edges of the LDD regions 24bc and 24bd on the channel region 24be side are almost respectively directly below the two sides of the gate electrode 54b. In the pixel TFT, since positive and negative signals are used as the display signal, unless the LDD regions 24bc and 24bd are provided on both the source side and the drain side, the characteristics of the transistor will be degraded due to hot electrons.

A silicon nitride film 55 with a thickness of 370 nm is formed on the second gate electrode 54b and the silicon insulating film 51a, and a pair of source/drain electrodes 57c, 57d are formed on the silicon nitride film 55. These source/drain electrodes 57c, 57d It is in contact with the high-concentration impurity regions 24ba and 24bb through the contact holes 56c and 56d.

As described above, according to the above-mentioned pixel TFT, since the second gate insulating film is formed of a thick silicon oxide film (silicon oxide film 51a + silicon oxide film 52a) with a thickness of 110 nm, the breakdown voltage of the pixel TFT is quite high. The pixel-like TFT can be driven by high voltage.

In this example, the description of the high-voltage driving TFT is omitted in this article. One difference from the pixel TFT is that this high-voltage driving TFT only has an LDD region on the drain side where the high voltage is applied, and the high-voltage driving p-type in the surrounding circuit TFT does not provide an LDD area, and its description will be omitted here. The reason is that in the p-type TFT paradigm, since the hole is used as the carrier, a heat carrier is rarely generated, and unless an LDD area is provided, the heat carrier will never interfere with the characteristics of the transistor.

(Method for manufacturing thin film transistors used in liquid crystal display devices)

Next, the method of manufacturing the thin film transistor device in the liquid crystal display device of this embodiment will be described below with reference to FIGS. 12A to 12H. The left side view of FIGS. 12A to 12H shows a cross-sectional view of the low-voltage driving TFT forming area, and the right side view thereof shows a cross-sectional view of the pixel TFT forming area.

As shown in Figure 12A, first, a silicon nitride film 22a with a thickness of about 50 nm and a silicon oxide film 22b with a thickness of 200 nm are successively formed by the plasma CVD method as the underlying insulating film on the glass substrate 21, and then the silicon oxide film 22b An amorphous silicon film 24 with a thickness of about 40 nm is formed thereon.

Afterwards, in order to reduce the hydrogen content in the amorphous silicon film, annealing is performed at a temperature of 450°C. Then, an excimer laser is irradiated on the amorphous silicon film to transform the amorphous silicon film into a polycrystalline silicon film.

Afterwards, a photoresist is coated on the polysilicon film, and then a predetermined anti-corrosion mask (not shown) is formed through the exposure and development steps. Afterwards, the polysilicon film is dry-etched using the anti-corrosion mask, leaving only the first island-shaped semiconductor film 24a and the second island-shaped semiconductor film 24b made of the polysilicon film in a predetermined area, and then the anti-corrosion mask is removed.

Then, an amorphous silicon film 51 with a thickness of 10 nm is formed on the entire surface of the upper side of the glass substrate 21 by a plasma CVD method, and then a silicon oxide film (insulating film) 52 with a thickness of 100 nm is formed.

Then, a photoresist film is formed on the silicon oxide film 52 by a coating method, and then as shown in FIG. 12B, an etching resist 53 is formed in the pixel TFT forming area through the exposure and development steps as shown in FIG. 12B.

Next, through the anti-corrosion mask 53, the silicon oxide film 52 is wet-etched with diluted hydrofluoric acid. At this time, the amorphous silicon formed under the silicon oxide film 52 with corrosion resistance to the diluted hydrofluoric acid is used. The film 51 serves as an etching stopper, so a silicon oxide film pattern (insulating film pattern) 52a is formed under the etching resist 53 and then the etching resist 53 is removed.

Then, as shown in FIG. 12C, a high-pressure oxidation method is used to oxidize the entire amorphous silicon film 51 including the silicon oxide film pattern 52a to form a silicon oxide film (an insulating film formed by oxidizing a semiconductor film) 51a. The high-pressure oxidation process is completed by adjusting the steam pressure to 2MPa and oxidizing for one hour at a temperature of 550°C. In this example, the well-known thermal oxidation method, plasma oxidation method, etc. can be used instead of the high-pressure oxidation method.

Therefore, the first gate insulating film made of the silicon oxide film 51a is formed on the first island-shaped semiconductor film 24a, and the second gate insulating film made of the silicon oxide film 51a and the silicon oxide film pattern 52a is formed on the second island A shaped semiconductor film 24b is formed on the upper surface.

Then, as shown in FIG. 12D, a sputtering method is used to form an Al-Nd film with a thickness of 300 nm, and then the Al-Nd film is etched using an etching mask (not shown). Therefore, the first gate electrode 54a is formed on the first gate insulating film 51a in the low-voltage driving TFT forming area, and the second gate electrode 54b is formed on the second gate insulating films 51a and 52a in the pixel TFT forming area. The second gate electrode 54b is formed in a region smaller than the upper surface of the second gate insulating film 52a and located on the inner side than the surrounding portion of the second gate insulating film 52a. Then remove the anti-corrosion mask 53.

Then, as shown in Figure 12E, the first gate electrode 54a is used as a mask to implant high-concentration phosphorus into the first island-shaped semiconductor film 24a by ion implantation, and the second gate electrode 54b is insulated from the second gate at the same time. The films 51a and 52a are used as photomasks to implant high-concentration phosphorus into the second island-shaped semiconductor thin film 24b by means of ion implantation. At this time, the acceleration voltage is set to 25keV and the dose is set to 7×10¹⁴cm^-2, As an ion implantation condition. Therefore, n-type high-concentration impurity regions 24aa, 24ab are formed in the first island-shaped semiconductor film 24a located on both sides of the first gate electrode 54a, and the second island-shaped semiconductor film on both sides of the second gate insulating film 51a, 52a is formed In 24b, n-type high-concentration impurity regions 24ba, 24bb are formed.

Then, under the condition that P ions are not allowed to pass through the first and second gate electrodes, but P ions are allowed to pass through the first and second island-shaped semiconductor films 24a, 24b and the second gate insulating films 51a, 52a, ion implantation The second island-shaped semiconductor film 24b is implanted with a low concentration of phosphorus by the method of injection, in which the acceleration voltage is set to 70keV and the dose is as low as 2×10¹³cm^-2, As an ion implantation condition. Therefore, n-type low-concentration impurity regions (LDD regions) 24bc, 24bd are formed in the second island-shaped semiconductor film 24b between the edges of the second gate electrode 54b and the edges of the high-concentration impurity regions 24ba, 24bb.

Then, as shown in FIG. 12F, a silicon oxide film 55 with a thickness of about 370 nm is formed on the entire surface of the glass substrate 21 by the plasma CVD method.

Then, as shown in Figure 12G, use the anti-corrosion mask (not shown) and use SF at the same time₆The silicon oxide film (first interlayer insulating film) 55 is dry-etched with gas, and contact holes 56a passing through the silicon nitride film 55 are formed on the high-concentration impurity regions 24aa, 24ab in the first island-shaped semiconductor film 24a , 56b. At the same time, contact holes 56c, 56d passing through the silicon nitride film 55 are formed on the high-concentration impurity regions 24ba, 24bb in the second island-shaped semiconductor film 24b. Then remove the anti-corrosion mask.

Then, as shown in Figure 12H, a Ti film with a thickness of 50nm, an Al film with a thickness of 100nm, and a Ti film with a thickness of 50nm are successively deposited on the entire surface of the upper side of the glass substrate 21 by sputtering, thereby depositing these metals The thin film is embedded in the contact holes 56a, 56b, 56c, and 56d, and a layered thin film composed of these metal thin films is formed on the silicon nitride thin film 32. After that, a photolithography technology is used to form an anti-corrosion mask (not shown), and then the metal layered film is dry-etched using this anti-corrosion mask. In this step, a high-concentration impurity region (source/drain) with the low-voltage driving TFT is formed. The source/drain electrodes 57a, 57b contacting the regions 24aa, 24ab, and the source/drain electrodes 57c, 57d contacting the high-concentration impurity regions (source/drain regions) 24ba, 24bb of the pixel TFT are formed at the same time.

In this example, the data bus line 108 in the display portion 104 is formed at the same time as the source/drain regions 57a to 57d, and predetermined wiring is formed in the forming area of the control circuit 101, the vertical driver 102 and the gate driver 103 pattern.

Then, photosensitive resin is applied to form a resin film (second interlayer insulating film) 58 with a thickness of 3.0 μm. As described above, the thin film transistor device is completed. Then, the following steps are performed to manufacture the liquid crystal display device.

After that, a through hole is formed in the resin film 58 above the source/drain electrode 57d. Next, an ITO (Indium Tin Oxide) thin film with a thickness of 70 nm is formed on the entire surface of the upper side of the glass substrate 21 by a sputtering method. After that, using standard photolithography steps, the ITO film is patterned to form a pixel electrode 60 that is in contact with the source-side impurity region of the pixel TFT. Next, an alignment film (not shown) that determines the initial state of the liquid crystal molecules (when no voltage is applied) is formed on the entire surface of the upper side of the glass substrate 21.

In this way, the TFT substrate of the liquid crystal display device is completed.

The counter substrate of the liquid crystal display device is formed by a well-known method. More specifically, the black matrix used to cover the area between the pixels from light is formed of Cr (chromium) on the glass substrate, and is formed on the glass substrate. Red, green, and blue color filters are formed on the substrate, and color filters having any of red, green, or blue are arranged for each pixel. Then, a transparent electrode made of an ITO film is formed on the entire surface of the upper side of the glass substrate, and an alignment film is formed on the transparent electrode.

The liquid crystal display panel is constructed by pasting the TFT substrate made in this way and the opposite substrate together, and then injecting liquid crystal between them, and sealing the injection port. After that, polarizing plates are arranged on both sides of the liquid crystal display panel, and a backlight source is arranged on the back to complete the liquid crystal display device.

As described above, according to the second embodiment, as shown in FIG. 12B, when the silicon oxide film is etched to form an insulating film as a part of the second inter-insulating film, the first island-shaped semiconductor film 24a is It is protected by the underlying amorphous silicon film 51. Therefore, the channel region of the first island-shaped semiconductor film 24a is not exposed to the plasma of the etching gas of the silicon oxide film 52, which prevents the low-voltage driving TFT from being thinner. Part of the TFT characteristics are degraded, so it is possible to ensure that the TFT in the thicker part of the pixel TFT and the TFT in the thinner part have excellent characteristics at the same time.

Moreover, the silicon oxide film 22b located under the first and second island-shaped semiconductor films 24a, 24b is also protected by the amorphous silicon film 51, so even if the silicon oxide film 22b is formed on the surface of the substrate, the first and second island-shaped semiconductor films There is no "scratch part" at the edge of the films 24a, 24b. If it is not protected, etching of the silicon oxide film 22b on the surface of the substrate 21 will produce a "scraped portion" at the edge.

In addition, when the silicon oxide film 52 is etched to form an insulating film that is part of the second gate insulating film, the amorphous silicon film 51 is resistant to the etchant of the silicon oxide film 52, so the film thickness will not reduce. In this embodiment, since the first gate insulating film 51a is formed by oxidizing the amorphous silicon film 51, the film thickness of the first gate insulating film 51a can be accurately controlled.

In the above embodiment, the amorphous silicon film 51 is formed directly on the first and second island-shaped semiconductor films 24a, 24b. A silicon oxide film for covering the first and second island-shaped semiconductor films 24a, 24b can be formed, and then an amorphous silicon film 51 and a silicon oxide film 52 can be formed thereon. Therefore, in addition to the above effects, when the first gate insulating film is formed by oxidizing the amorphous silicon film 51, the film thickness of the first gate insulating film can be further controlled. In this example, the film thickness of the first gate insulating film is composed of a silicon oxide film covering the first island-shaped semiconductor film 24a and a silicon oxide film 51a formed by oxidizing the amorphous silicon film 51, and the second gate The insulating film is formed of a silicon oxide film covering the second island-shaped semiconductor film 24b, and a silicon oxide film 51a and a silicon oxide film 52a formed by oxidizing the amorphous silicon film 51.

(Another method for manufacturing thin film transistor devices)

13A to 13D are cross-sectional views showing another method of manufacturing a thin film transistor device according to the second embodiment of the present invention.

As shown in FIG. 13A, as in the first embodiment, a silicon oxide film 22a with a thickness of 50 nm, a silicon oxide film 22b with a thickness of 200 nm, and an amorphous silicon film with a thickness of 40 nm are first formed on the glass substrate 21. Then, the excimer laser is irradiated on the amorphous silicon film to convert the amorphous silicon film into a polysilicon film (first semiconductor film) 24.

After that, a plasma CVD method is used to form a 10nm thick first silicon oxide film (first insulating film) 62, a 10nm thick amorphous silicon film (second semiconductor film) 63, and a 100nm thick second silicon oxide film (Second insulating film) 64.

Then, as shown in FIG. 13B, an anti-corrosion mask 65 is formed in the pixel TFT forming area. Then, the silicon oxide film 64 is etched to form the second silicon oxide film pattern (second insulating film pattern) 64a by using the etching resist 65 and the diluted hydrofluoric acid at the same time, and then the etching resist 65 is removed.

Then, as shown in Figure 13C, a new anti-corrosion mask (not shown) is formed. Then, using this new resist mask, the amorphous silicon film 63 is dry-etched using an etching gas containing fluorine, thereby forming a first island-shaped amorphous silicon film (a second island-shaped semiconductor film without a second insulating film pattern) ) 63a and a second island-shaped amorphous silicon film (a second island-shaped semiconductor film containing a second insulating film pattern) 63b. Afterwards, the anti-corrosion mask 65 is removed.

Then, the first island-shaped amorphous silicon film 63a and the second island-shaped amorphous silicon film 63b located under the second silicon oxide film pattern 64a and other parts are oxidized by the high pressure oxidation method, while passing through the first silicon oxide film 62 The areas of the polysilicon film 24 that are not covered by the first island-shaped amorphous silicon film 63a and the areas of the polysilicon film 24 that are not covered by the second island-shaped amorphous silicon film 63b are oxidized. Therefore, as shown in Figure 13D, the first island-shaped semiconductor film 24a made of polysilicon film is formed in the area covered by the first island-shaped amorphous silicon film 63a; at the same time, the second island-shaped semiconductor film 24a made of polysilicon film The island-shaped semiconductor film 24b is formed in the area covered by the second island-shaped amorphous silicon film 63b. In other words, the first island-shaped semiconductor film 24a is provided with a first gate insulating film 65 made of the first silicon oxide film 62 and an insulating film formed by oxidizing the first island-shaped amorphous silicon film 63a. At the same time, the second island-shaped semiconductor film 24b is provided with an insulating film 65 and a second silicon oxide film made of the first silicon oxide film 62 and an insulating film formed by oxidizing the second island-shaped amorphous silicon film 63b. The second gate insulating film formed by the thin film pattern 64a.

Thereafter, a thin film transistor device is formed through similar steps shown in Figures 12D to 12F. Then, the liquid crystal display device is manufactured through the standard steps in the liquid crystal display device manufacturing method described in the first and second embodiments.

As described above, according to another thin film transistor device manufacturing method of the second embodiment, as shown in FIG. 13B, when the silicon oxide film 64 is etched, an insulating film that is a part of the second gate insulating film is formed At 64a, the first island-shaped semiconductor film 24a is protected by the underlying amorphous silicon film 63. Therefore, the channel area of the first island-shaped semiconductor film 24a is not exposed to the plasma of the etching gas of the silicon oxide film 64 Therefore, it is possible to prevent the degradation of the TFT characteristics in the thinner part, so that it can ensure that the TFT in the thicker part and the TFT in the thinner part have excellent characteristics at the same time.

Furthermore, as shown in FIG. 13D, the silicon oxide film 64 on the amorphous silicon film 63 is etched as a thicker part of the second gate insulating film. Then, the polysilicon film 24 under the amorphous silicon film 63 is selectively oxidized to form the first and second island-shaped semiconductor films 24a, 24b. In this way, the underlying silicon oxide film 22b is not exposed to the etching gas. Therefore, the edge portions of the first and second island-shaped semiconductor films 24a, 24b will not be "scratched" by etching the underlying silicon oxide film 22b.

In addition, when the silicon oxide film 64 is etched to form an insulating film as a part of the second gate insulating film, the amorphous silicon film 63 is resistant to the etchant of the silicon oxide film 64, so the amorphous silicon film The thickness will not decrease. In this embodiment, since the first gate insulating film is formed by the insulating film 63a formed by oxidizing the amorphous silicon film 63 and the first silicon oxide film 62, the film thickness of the first gate insulating film can be accurately controlled.

(Third embodiment)

Next, the structure of the thin film transistor device manufacturing method according to the third embodiment of the present invention will be described below with reference to the drawings.

In the thin film transistor device of the third embodiment, a TFT composed of at least one of an n-type TFT and a p-type TFT having a thin gate insulating film (referred to as a TFT in the thinner portion) and a TFT having A TFT composed of at least one of the n-type TFT and the p-type TFT of the thick gate insulating film (referred to as the TFT in the thicker portion) is mounted on the same substrate. The n-type TFT in the thinner portion will be described below. The structure of the -type TFT and the n-type TF-T in the thicker part.

Figure 16A shows a plan view of the TFT in the thinner portion when viewed from the upper side, and the left side view of Figure 14F is a cross-sectional view taken along the line IV-IV in Figure 16A, and Figure 16B This is a cross-sectional view taken along the line VV in Figure 16A.

The left side views of Figures 16A and 14F show the components of the TFT (first thin film transistor) in the thinner part. In more detail, the TFT in the thinner part includes a polysilicon film with a thickness of about 50nm. The first island-shaped semiconductor film 24a made, a first gate insulating film 81a made of a first silicon oxide film (first insulating film) with a thickness of 30nm, and a first Al-Nd ( The first conductive film) is made of the first gate electrode 82. A pair of n-type source/drain regions 24aa and 24ab are formed in the first island-shaped semiconductor film 24a to insert a channel region 24ac therebetween. The channel region 24ac in the first island-shaped semiconductor film 24a is continuously formed with a first The gate insulating film 81 a and the first gate electrode 82.

At the same time, the TFT in the thinner portion includes a first interlayer insulating film 87 made of a silicon nitride film with a thickness of 400 nm, contact holes 87a, 87b formed in the first interlayer insulating film 87, and a Ti film. (200nm)/Al film (200nm)/Ti film (200nm) composed of three-layer structure metal film source/drain electrodes 88a, 88b, and a second intermediate layer made of silicon nitride film with a thickness of 400nm Insulation film 89. The first interlayer insulating film 87 covers the first island-shaped semiconductor film 24a and the first gate electrode 82. The source/drain electrodes 24aa, 24ab formed in the first island-shaped semiconductor film 24a are respectively connected to the source through contact holes 87a, 87b. /Drain electrodes 88a, 88b, and the second interlayer insulating film 89 covers the source/drain electrodes 88a, 88b.

In addition, as shown in Figures 16A and 16B, the thinner portion of the TFT is formed by the second silicon oxide film (second insulating film ) 83b provides electric field relaxation electrodes 84c to 84f made of a second Al-Nd thin film (second conductive film) with a thickness of 300 nm.

Next, the TFT in the thicker part will be explained below. Figure 17A shows a plan view of the TFT in the thicker part viewed from the upper side, and the right side view of Figure 14F is a cross-sectional view taken along the VI-VI line of Figure 17A, and Figure 17B is along Sectional view taken on line VII-VII in Figure 17A.

The right side views of Figures 17A and 14F show the components of the TFT (second thin film transistor) in the thicker part. In more detail, the TFT in the thicker part includes a polysilicon film with a thickness of about 50nm. A second island-shaped semiconductor film 24a, a second gate insulating film composed of a first silicon oxide film 81a with a thickness of 30 nm and a second silicon oxide film 83b with a thickness of 70 nm, and a second gate insulating film composed of a thickness of 300 nm. -A second gate electrode 84a made of Nd thin film (second conductive film). A pair of n-type source/drain regions 24ba and 24bb are formed in the second island-shaped semiconductor thin film 24b to insert a channel region 24be therebetween. A second gate insulating film and a second gate electrode 84a are continuously formed on the channel region 24be. .

In addition, the TFT (second thin film transistor) in the thicker part has a silicon nitride film (first interlayer insulating film) 87, source/drain electrodes 88c, 88d, and an oxide layer covering the source/drain electrodes 88c, 88d. Silicon thin film (second interlayer insulating film) 89. The silicon nitride film 87 covers the second island-shaped semiconductor film 24b and the second gate electrode 84a, and the source/drain electrodes 88c and 88d are respectively connected to the second island through the contact holes 87c and 87d formed in the silicon oxide film 87 The source/drain regions 24ba and 24bb formed in the semiconductor thin film 24b.

In addition, as shown in Figures 17A and 17B, the thicker portion of the TFT is provided by the first silicon oxide film 81b above both sides of the second island-shaped semiconductor film 24b under the second gate electrode 84a. The electric field relaxation electrodes 82b, 82c made of the first Al-Nd thin film.

As described above, according to the thin film transistor device of the third embodiment of the present invention, in the thinner portion of the TFT, the second silicon oxide film 83b above the both sides of the first island-shaped semiconductor film 24a is used. Electric field relaxation electrodes 84c to 84f are provided on the first gate electrode 82. Therefore, compared to the capacitance formed by the first island-shaped semiconductor film 24a, the first silicon oxide film 81a, and the first gate electrode 82, the parasitic capacitance at this portion is greater than the capacitance formed by the first gate electrode 82 and the electric field relaxation electrode 84c. The electrostatic capacitance formed by 84f is large. Therefore, if the gate of the TFT is driven by alternating current, the change of the gate potential acting on the edge portions on both sides of the first island-shaped semiconductor film 24a will be slowed, so the parasitic formed at the edge portions on both sides of the first island-shaped semiconductor film can be suppressed. Transistor operation.

In the TFT in the thicker part, the electric field relaxation electrodes 82b and 82c are provided under the second gate electrode 84a by the first silicon oxide film 81b above the edges of both sides of the second island-shaped semiconductor film 24b. According to this structure, the potentials of the electric field relaxation electrodes 82b and 82c are set to the potential when the channels at the edge portions on both sides of the second island-shaped semiconductor film 24b cannot conduct electricity, which suppresses the edge portions on both sides of the second island-shaped semiconductor film 24b. The conductivity of the channel. At the same time, by isolating the electric field induction of the second gate electrode 84a, the turning on of the parasitic transistor can be suppressed.

Next, the method of manufacturing the thin film transistor device of the third embodiment will be described below with reference to FIGS. 14A to 14F.

As shown in FIG. 14A, first, a silicon oxide film 22a with a thickness of 50 nm and a silicon oxide film 22b with a thickness of 250 nm are successively formed on the glass substrate 21 in a laminated manner. In this example, if circumstances permit, the silicon nitride film 22a can be omitted.

After that, an amorphous silicon film with a thickness of 50 nm is formed on the substrate. Then, annealing is performed at a temperature of 400°C to complete the dehydrogenation process. The energy used afterwards is 300mJ/cm²The excimer laser annealed the amorphous silicon film to transform it into a polysilicon film. Then, the polysilicon film is subjected to a patterning process to form the first and second island-shaped semiconductor films 24a, 24b.

After that, a first silicon oxide film (first insulating film) 81 with a thickness of 30 nm covering the first and second island-shaped semiconductor films 24a, 24b is formed by CVD method, and then the thickness is formed on the entire surface by PVD method. The first Al-Nd film (the first conductive film) with a thickness of 300 nm, and then a solution containing phosphoric acid and acetic acid is used to selectively etch the first Al-Nd film through an anti-corrosion mask (not shown). A first gate electrode 82 is formed on the first silicon oxide film above the shaped semiconductor film 24a.

At this time, as shown in Figures 17A and 17B, the electric field relaxation electrodes 82b, 82c made of the first Al-Nd thin film are located above the edges on both sides of the second island-shaped semiconductor thin film 24b and on the first silicon oxide thin film 81 It is formed in the range where it intersects with the TFT second gate electrode 84a in the thicker part.

After that, an anti-corrosion mask (not shown) is used to cover the TFT forming area in the thinner portion. Then, the silicon oxide film is lightly etched with a solution containing hydrofluoric acid, and then the resist mask is removed. Here, if a silicon nitride film is selected as the material of the gate insulating film 81 of the TFT in the thinner part, and chromium (Cr) is selected as the material of the first gate electrode 82, these materials have corrosion resistance to the solution containing hydrofluoric acid . Therefore, the TFT forming area in the thinner part does not need to be covered with an anti-corrosion mask.

Then, as shown in Figure 14B, a second silicon oxide film (second insulating film) 83 with a thickness of 70 nm is formed on the entire surface by the CVD method, and then a second Al-Nd film (with a thickness of 300 nm) is formed by the PVD method ( Second conductive film) 84.

Then, as shown in FIG. 14C, a resist mask (mask pattern) 85 is formed on the second Al-Nd film 84. Then, using the anti-corrosion mask 85 and a solution containing phosphoric acid and acetic acid at the same time, the second Al-Nd film 84 is wet-etched to remove the area on the second Al-Nd film 84 that is not covered by the anti-corrosion mask 85. Afterwards, the second Al-Nd film 84 under the anti-corrosion mask is side-etched to form a second gate electrode 84a whose width is narrower than the width of the LDD region of the anti-corrosion mask.

At this time, as shown in Figures 16A and 16B, the second silicon oxide films 83b, 83c above the edges of both sides of the first island-shaped semiconductor film 24a form a second Al-Nd film on the first gate electrode 24a. The fabricated electric field relaxation electrodes 84c to 84f.

Then, as shown in Figure 14D, use CHF₃The etching gas is used to etch the second silicon oxide film 83 anisotropically through the same resist mask 85, and then the first silicon oxide film 81 is etched anisotropically according to the first gate electrode 82 and the resist mask 85 Therefore, a first insulating film made of the first silicon oxide film 81a is formed under the first gate electrode 82, and a first insulating film made of the first and second silicon oxide films 81b, 83a is formed under the second gate electrode 84a. The second gate insulating film 86.

In this example, as shown in FIG. 15, a first silicon oxide film 81c with a thickness of about 10 nm can be left on the first and second island-shaped semiconductor films 24a, 24b and other regions. Then remove the anti-corrosion mask 85.

Then, as shown in Figure 14E, the first gate electrode 82 is used as a mask, and high-concentration phosphorus (impurity) is implanted into the first island-shaped semiconductor film 24a by ion implantation. Therefore, two of the first gate electrodes 82 High-concentration impurity regions 24aa and 24ab are formed on the upper side. At the same time, using the second gate electrode 84a and the second gate insulating films 83a and 81b as a mask, a high concentration of phosphorus (impurity) is implanted into the second island-shaped semiconductor thin film 24b by means of ion implantation. Therefore, a pair of high-concentration impurity regions 24aa and 24ab are formed on both sides of the second gate electrode 84a. At this time, the acceleration voltage is set to 10keV and the dose is set to 1×10.¹⁵/cm², As an ion implantation condition.

After that, the second gate electrode 84a is used as a mask, and phosphorus (impurity) is implanted by ion implantation under the condition that P ions can pass through the second gate insulating films 83a, 81b around the second gate electrode 84a. The second island-shaped semiconductor film 24b. Therefore, a pair of low-concentration impurity regions 24bc, 24bd as LDD regions are formed under the second gate insulating films 83a, 81b located on both sides of the second gate electrode 84a. At this time, the acceleration voltage is set to 100 keV and the dose is set to 1. ×10¹⁴/cm², As an ion implantation condition.

In this embodiment, if a mixture of p- channel type TFT, the mask not to cover the active layer of the p- channel type TFT, implanted in patients before and after the use of phosphorus ions acceleration voltage of 10keV and 1 × 10¹⁶/cm²The dose of high concentration of boron ions will be implanted. Therefore, since the phosphorus ion concentration is compensated by the boron in the working layer of the p-channel type TFT, the working layer of the p-channel type TFT becomes p-type.

Then, annealing is performed at a temperature of 400° C. to complete the dehydrogenation process of the first and second island-shaped semiconductor films 24a, 24b. Then at 250mJ/cm²Under the conditions, laser irradiation is used to perform annealing to activate the phosphorus in the first and second island-shaped semiconductor films 24a and 24b.

Then, as shown in Fig. 14F, a silicon oxide film (first interlayer insulating film) with a thickness of 300 nm is formed by the CVD method. Then the first silicon oxide film 87 is patterned to form contact holes 87a, 87b on the high-concentration impurity regions 24aa, 24ab in the thinner part of the TFT forming area, and at the same time in the thicker part of the TFT forming area. Contact holes 87c and 87d are formed on the high-concentration impurity regions 24ba and 24bb.

After that, PVD is used to form a three-layer metal film with a thickness of 200 nm and consisting of one film/a layer of Al film/a layer of Ti. Then the three-layer metal film is subjected to a patterning process, and the contact holes 87a and 87b are respectively formed and high. The source/drain electrodes 88a, 88b contacting the impurity-concentration regions 24aa, 24ab, and the source/drain electrodes 88c, 88d contacting the impurity-concentration regions 24ba, 24bb, respectively, are formed through the contact holes 87c, 87d.

After that, a silicon nitride film (second interlayer insulating film) 89 with a thickness of 400 nm and covering the source/drain electrodes 88a to 88d is formed by the CVD method, thus completing the thin film transistor device.

As shown in the right side view of Figure 14F, in the case of manufacturing the TFT substrate of the liquid crystal display device and the liquid crystal display device, a through hole 89a is formed in the silicon nitride film 89 above the source/drain electrode 88d, and then ITO is formed Then, the ITO film is subjected to a patterning process to form a pixel electrode 90 in contact with the source/drain electrode 88d through the through hole 89a. After that, various steps are performed according to the manufacturing method described in the first and second embodiments.

As described above, in the manufacturing method of the thin film transistor device of the third embodiment of the present invention, as shown in Figure 14C, the Al-Nd film is side-etched by the etching resist 85 to form a side with a width that is more resistant to light. The cover 85 is smaller than the second gate electrode 84a of the width of the LDD region. In addition, the silicon oxide films 83 and 81 are anisotropically etched using the anti-corrosion mask 85 to form a second gate insulating film 86 whose width is larger than that of the second gate electrode 84a by the width of the LDD region. Then, as shown in FIG. 14E, during the ion implantation, the ion implantation process is performed at a high dose under the condition that the ions cannot pass through the second gate insulating film 86. In addition, under the condition that the ions can pass through the second gate insulating film 86, the ion implantation procedure is performed at a low dose. Therefore, an LDD structure is formed in the second island-shaped semiconductor film 24b.

In this way, the gate electrode 84a and the gate insulating film 86 can be used without increasing the number of exposure masks to form the LDD structure in a self-adjusting manner.

Moreover, as shown in FIGS. 14C and 14D, since gate insulating films 81a and 86 having different thicknesses can be formed at a time by one etching step, the forming step can be simplified. In this example, since the channel regions in the first and second island-shaped semiconductor films 24a, 24b are not exposed to the plasma of the etching gas together, it is possible to prevent the first and second island-shaped semiconductor films 24a, 24b from being exposed to the plasma A damaged layer is generated on the surface of the channel area.

(Fourth embodiment)

Next, the structure of a liquid crystal display device equipped with a thin film transistor device in the fourth embodiment of the present invention will be described below with reference to the drawings.

In the liquid crystal display device described in the first embodiment, the TFT (first thin film transistor) in the thinner part and the TFT (second thin film transistor) in the thicker part are formed on the same substrate. The TFT in the thin part is used for the surrounding circuit part, and the TFT in the thicker part is used for the display part, and the TFT similar to the TFT in the thicker part is also used to handle the high voltage buffer part in the surrounding circuit part.

Since this fourth embodiment has a feature in the structure of the display part, especially the structure of the storage capacitor element connected to the storage capacitor bus line, this structure will be mainly described below.

Fig. 18 shows the structure of a pixel in the display section when the liquid crystal display device of the fourth embodiment of the present invention is viewed from the upper side, and a cross-sectional view taken along the line VIII-VIII in Fig. 18 is shown The cross-sectional view of the TFT is shown in the right side view of Figure 14F. Figure 19A is a cross-sectional view taken along the line IX-IX of Figure 18, and Figure 19B is a cross-sectional view taken along the line XX of Figure 18.

As shown in Figure 18, first connect a pixel electrode 110 (90) to the source/drain region 24bb through the source/drain electrode 88d of the TFT in the thicker part, and then make the storage capacitor bus line 111 (82c) and The pixel electrodes 90 cross. The storage capacitor bus line 82c and the first gate electrode 82 of the TFT in the thicker part are formed of the same material, and the bus line is connected to the source/drain electrode of the TFT in the thicker part.

The data bus line 108 and the source/drain electrode 88c are formed of the same material, and this line is connected to the other source/drain electrode 24ba of the TFT in the thicker part. At the same time, the gate bus line 109 and the second gate electrode 84a of the TFT in the thicker part are formed of the same material, and this line is even connected to the second gate electrode 84a.

As shown in the right side view of Fig. 14F, the TFT in the thicker portion includes a second island-shaped semiconductor film 24b, a second gate insulating film 86 composed of first and second silicon oxide films 81b, 83a, and A second gate electrode 84a made of a second Al-Nd thin film. The second island-shaped semiconductor film 24b has a pair of source/drain regions 24ba and 24bb to interpose the channel region 24be therebetween, and any one of them is connected to the pixel electrode 90. The second gate insulating film 86 and the second gate electrode 84a are continuously formed on the channel region 24be.

As shown in the right side views of Figures 19A and 19B, respectively, the storage capacitor bus line 82c is formed of a first Al-Nd film, and the second silicon oxide film 83d and the second Al-Nd film 84f are continuously laminated on the storage capacitor Above a partial area of the bus line 82c, and as shown in FIG. 19A, the second Al-Nd film 84f is connected to the source/drain electrode 88d of the TFT in the thicker part. Then, as shown in the left side view of FIG. 19B, the second Al-Nd film 84f is connected to the pixel electrode 90 through the source/drain electrode 88d. In this example, the source/drain electrode 88d has a three-layer structure composed of a layer of Ti film 88da/a layer of Al film 88db/a layer of Ti film 88dc. Since the elements denoted by the same symbols in Figure 14F are the same as the same elements in Figure 14F, their description will be omitted herein.

In this example, since the TFT in the thinner portion has the same structure as the TFT in the left side view of FIG. 14F, its description will be omitted herein.

As described above, according to the liquid crystal display device of the fourth embodiment of the present invention, the storage capacitor bus line 108 in the display portion and the first gate electrode 82 of the TFT in the thinner portion are formed of the same material. And in the capacitor element provided, one of the electrodes is formed by the storage capacitor bus line 108, the capacitor insulating film 83d is formed of the same material as the second insulating film 83a of the second gate insulating film 86, and the other electrode 84f It is formed of the same material as the second gate electrode 84a.

Therefore, since the gate insulating film formed is usually thinner, the capacitor element has a higher per unit area than the capacitor element having other electrodes made of an ITO film and a capacitor insulating film made of an interlayer insulating film. capacitance. Therefore, since the area of the storage capacitor bus line 108 required to form the storage capacitor, that is, the light shielding area, can be reduced, the aperture ratio can be increased.

The thin film transistor device manufacturing method of the third embodiment is used to form the thin film transistor device used in the liquid crystal display device. In this example, the storage capacitor bus line 82c and the like are formed by the following TFT and other gate electrode forming steps Formed by the common steps in.

When the first gate electrode 82 is formed, the storage capacitor bus line 82c is simultaneously formed of the first Al-Nd film, and when the second silicon oxide film 83 is etched to form the second gate insulating film 86 of the TFT in the thicker part At this time, the second silicon oxide film 83d remains on the storage capacitor bus line 82a. The second Al-Nd film 84f on the second silicon oxide film 83d is formed by performing a patterning process while the second gate electrode 84a is formed, and the gate bus line 109 and the gate electrode 84a are formed at the same time. The bus line 108 is formed simultaneously with the source/drain electrodes 88a to 88d.

Then, after the silicon nitride film 89 described in the third embodiment is formed, the silicon nitride film 89 is patterned to form a through hole 89a on the source/drain electrode 88d, and then the thickness is 100 nm by the PVD method. Then, the ITO film is patterned to form the pixel electrode 90.

After that, an alignment film (not shown) that determines the initial state of the liquid crystal molecules (when no voltage is applied) is formed on the entire upper surface of the glass substrate 21.

In this way, the TFT substrate of the liquid crystal display device is completed.

The counter substrate of the liquid crystal display device is formed by a well-known method. In other words, the black matrix used to cover the area between the pixels from light is formed of Cr (chromium) on the glass substrate and on the glass substrate The color filters of red, green and blue are formed, and the color filters of any one of red, green or blue are arranged for each pixel. Then, a transparent electrode made of ITO film is formed on the entire upper surface of the glass substrate, and an alignment film is formed on the transparent electrode.

The liquid crystal display panel is formed by bonding the TFT substrate made in this way and the counter substrate together, and then sealing the liquid crystal in a space between them. After that, polarizing plates are arranged on both sides of the liquid crystal display panel, and a backlight is arranged on the back side to complete the liquid crystal display device.

(Fifth embodiment)

Next, the structure of a liquid crystal display device equipped with a thin film transistor device in the fifth embodiment of the present invention will be described with reference to the drawings.

Like the liquid crystal display device of the fourth embodiment, the liquid crystal display device of the fifth embodiment includes a TFT in a thinner portion formed on the substrate, a TFT in a thicker portion, and a source/sink connected to the TFT in the thicker portion. The pixel electrode 110 (90) and the data bus line 108 (88c) in the region, the gate bus line 109 (84a) connected to the gate electrode of the TFT in the thicker part, and the storage capacitor bus that crosses the pixel electrode 90 Flat line 111 (82c).

One difference from the fourth embodiment is the structure of the display part, especially the storage capacitor element connected to the storage capacitor bus line 111 (82c).

Fig. 20 shows a plan view of the structure of one of the pixels of the display part when the liquid crystal display device of the fifth embodiment of the present invention is viewed from the upper side. A cross-sectional view taken along the line XI-XI in Fig. 20 is a TFT The cross-sectional view is shown in the right side view of Figure 14F. Figure 21A is a cross-sectional view taken along the line XII-XII in Figure 20, and Figure 21B is a cross-sectional view taken along the line XIII-XIII in Figure 20.

Since among the constituent elements of the display device, the TFT in the thinner part and the TFT in the thicker part have the same structure as the fourth embodiment, the detailed description will be omitted here.

As shown in Figures 21A and 21B, the storage capacitor bus line 82c (111) is formed by a first Al-Nd thin film (first conductive film), and its material is the same as the first gate electrode 82 of the TFT in the thinner part. same. A storage capacitor element with a storage capacitor bus line 82c as an electrode is arranged in a part of the cable. The storage capacitor element is composed of an electrode made of a storage capacitor bus line 82c, a combination of the material and the TFT in the thinner part. A capacitor insulating film made of the same first silicon oxide film 81e as the first gate insulating film 81a, and others made of a third island-shaped semiconductor film 24c made of the same material as the first and second island-shaped semiconductor films 24a, 24b The electrodes are constructed. A pair of p-type impurity regions is formed in the third island-shaped semiconductor film 24c on both sides of the storage capacitor bus line 82c, and any one of the pair of p-type impurity regions is connected to the pixel electrode 90, in other words, forms a The p-channel type third thin film transistor has the same structure, which uses the storage capacitor bus line 82c as the third gate electrode, the first silicon oxide film 81e as the third gate insulating film, and the third island-shaped semiconductor film 24c As a working layer, and a pair of p-type impurity regions as source/drain regions.

The reason for using the p-channel type third thin film transistor will be explained below, that is, if an n-channel type TFT is used as the pixel TFT, the ON current will be quite high, and the amount of stored charge of the pixel will easily increase. At the same time, if an n-channel type TFT is used as the pixel TFT, and the structure shown in Figures 17A and 17B is also used to prevent the induction of the parasitic TFT, it is better to apply the electric field relaxation electrodes 82a, 82b of the pixel TFT The voltage on the top is set to a negative value. In addition, if the electric field relaxation electrodes 82a and 82b of the pixel TFT and the gate electrode (storage capacitor bus line) 82c of the storage capacitor element are set to the same potential, the number of power supplies can be reduced. As mentioned above, since the negative potential acts on the gate electrode (storage capacitor bus line) 82c of the storage capacitor element, if the third thin film transistor is composed of a p-channel type TFT, the channel can always be maintained in an ON state. That is, the third island-shaped semiconductor thin film 24c can be used as an electrode.

Next, the method for manufacturing a liquid crystal display device of the fifth embodiment will be described below. At this time, the method of manufacturing a thin film transistor device of the third embodiment is used to form a thin film transistor device. In this example, the storage capacitor bus line 82c and the like are formed by a common step in the gate electrode forming steps such as TFT and the like described below.

When the first and second island-shaped semiconductor films 24a, 24b are formed, the third island-shaped semiconductor film 24c is simultaneously formed by a patterning process; when the first gate insulating film 81a and part of the second gate insulating film 86 are When the silicon monoxide film 81 is formed by the patterning process, the gate insulating film made of the first silicon oxide film 81e is simultaneously formed by the patterning process; when the first gate electrode 82 is patterned by the first Al-Nd film When formed by the production process, the storage capacitor bus line 82c is simultaneously formed by the pattern production process.

Then, after the silicon nitride film 89 described in the third embodiment is formed, the silicon nitride film 89 is patterned to form a through hole 89a on the source/drain electrode 88d, and then the thickness is 100 nm by the PVD method. Then, the ITO film is patterned to form the pixel electrode 90.

After that, an alignment film (not shown) that determines the initial state of the liquid crystal molecules (when no voltage is applied) is formed on the entire upper surface of the glass substrate 21.

In this way, the TFT substrate of the liquid crystal display device is completed.

The counter substrate of the liquid crystal display device is formed by a well-known method. In other words, the black matrix used to cover the area between the pixels from light is formed of Cr (chromium) on the glass substrate and on the glass substrate The color filters of red, green and blue are formed, and the color filters of any one of red, green or blue are arranged for each pixel. Then, a transparent electrode made of ITO film is formed on the entire upper surface of the glass substrate, and an alignment film is formed on the transparent electrode.

The liquid crystal display panel is constructed by bonding the TFT substrate made in this way and the counter substrate together, and then sealing the liquid crystal in a space between them. After that, polarizing plates are arranged on both sides of the liquid crystal display panel, and a backlight is arranged on the back side to complete the liquid crystal display device.

As described above, according to the fifth embodiment of the present invention, there is provided a storage capacitor element composed of the following elements. In other words, the storage capacitor element includes a first gate electrode 82 made of the same material as the thin portion of the TFT. The electrodes of the storage capacitor bus line 108, the capacitor insulating film 81e made of the same material as the first insulating film 81b of the second gate insulating film 86, and the first and second island-shaped semiconductor films 24a, 24b Other electrodes made of the same material.

Therefore, since the gate insulating film formed is generally thinner, a capacitor element having a higher capacitance per unit area can be obtained than a storage capacitor element using ITO as other electrodes and an interlayer insulating film as a capacitor insulating film. Therefore, since the area of the storage capacitor bus line 108 required to form the storage capacitor 4, that is, the light shielding area, can be reduced, the aperture ratio can be increased.

At the same time, if the pixel TFT with the electric field relaxation electrodes 82a and 82b shown in Figures 17A and 17B is formed, a storage capacitor bus line 82c can provide voltage to the gate electrode 82c and the electric field relaxation electrodes 82a and 82b of the storage capacitor element. Therefore, voltage can be supplied to the gate electrode 82c and the electric field relaxation electrodes 82a, 82b of the storage capacitor element without adding additional wiring, so that the aperture ratio can be prevented from decreasing.

The foregoing description of the present invention is based on various embodiments. However, the present invention is not limited to the examples specifically disclosed in the above-mentioned embodiments, and is made to the above-mentioned embodiments within the scope of not deviating from the present invention and the main points. The changes are all included in the scope of the present invention.

For example, thin film transistor devices are suitable for the above-mentioned liquid crystal display devices, but such thin film transistor devices are also suitable for organic EL display devices.

At the same time, a transparent substrate in which a silicon nitride film and a silicon oxide film are laminated on a glass substrate is used as a substrate. However, in addition to a manufacturing method having a step of irradiating an exposure source from the back, an opaque substrate can also be used.

<p>1, 21...substrate 4be, 24ac, 24be... channel area</p><p>3, 22b, 25, 25a, 25b, 5, 6, 6a, 6b, 22, 64a,</p><p>28, 28a, 28b, 31, 55, 71, 71a, 71b, 74a, 81b,</p><p>51a, 52, 52a, 62, 64, 8176, 78...Insulating film</p><p>, 81a, 81b, 81e, 83, 83a7...metal film</p><p>, 83b, 83d... Silicon oxide film 7a, 7b, 29a, 29b, 54a,</p><p>4a, 4b, 24a, 24b, 24c 54b, 72, 75, 82, 82c,</p><p>...Island-shaped semiconductor film 84a...gate electrode</p><p>4ba, 4bb, 24aa, 24ab, 9c, 30a, 30b, 53, 65,</p><p>24ba, 24bb...High-concentration impurity area 73a, 73b, 85...Anti-corrosion mask</p><p>4bc, 4bd, 24bc, 24bd13... damage layer</p><p>...Low-concentration impurity area 14...scrape part</p><p>22a, 32, 55, 87, 8981e... capacitor insulating film</p><p>...Silicon nitride film 82a, 82b, 82c, 84c to 84f</p><p>24, 51, 63, 63a, 63b... Electric field relaxation electrode</p><p>...Amorphous silicon film 84a, 109...gate bus line</p><p>24aa, 24ab, 57a, 57b, 87, 89...Interlayer insulating film</p><p>57c, 57d, 77a, 77b, 77c88c, 108...Data bus line</p><p>, 24ba, 24bb... source/drain 88da, 88dc...Ti film</p><p>24bc, 24bd...LDD area 88db...Al film</p><p>25a, 26a...Open part 89a...Through hole</p><p>25b, 28, 51a, 65, 81a, 101... control circuit</p><p>81b, 83a, 86...Gate insulation film 102...Vertical drive</p><p>30...photoresist film 102a, 103a...shift register</p><p>84, 84f...Al-Nd film 102b, 103b...Horizontal shifter</p><p>33a, 33b, 33c, 33d, 56a102c... analog switch</p><p>, 56b, 56c, 56d, 76a, 103...Gate Driver</p><p>76b, 76c, 76d, 87a, 87b103c... output buffer</p><p>, 87c, 87d...Contact hole 104...Display part</p><p>34a, 34c...source 105..TFT</p><p>34b, 34d...Drain 106...Display unit (liquid crystal unit)</p><p>35, 58... Resin film 107... Storage capacitor</p><p>90, 110... pixel electrode 111, 108, 82c... storage capacitor</p><p>64a...Silicon oxide thin film patterned bus line</p><p>77d, 88a, 88b, 88c,</p><p>88d...source/drain electrode</p>

Figure 1 shows a cross-sectional view of a thin film transistor device in the prior art;

Figure 2 shows a cross-sectional view of the problem of the thin film transistor device manufacturing method in the prior art;

Figures 3A and 3B show cross-sectional views of another problem in the manufacturing method of thin film transistor devices in the prior art;

Figure 4A shows a plan view of an intermediate step of the thin film transistor device manufacturing method in the prior art, and Figure 4B shows a plan view of another intermediate step of the same thin film transistor device manufacturing method, and Figure 4B The bottom side view is a cross-sectional view taken along the line XIV-XIV of the top side view;

Figure 5 shows a cross-sectional view of another thin film transistor device in the prior art;

Figures 6A and 6B show cross-sectional views of another problem in the manufacturing method of thin film transistor devices in the prior art;

Figure 7 shows a block diagram of a configuration of the thin film transistor device (emissive liquid crystal display device) of the first embodiment of the present invention;

Figure 8 shows a plan view of the thin film transistor device of the first embodiment of the present invention;

Figures 9A to 9P show several cross-sectional views of the method of manufacturing a thin film transistor device according to the first embodiment of the present invention;

Figure 10A shows a plan view of an intermediate step of the thin film transistor device manufacturing method of the first embodiment of the present invention, and Figure 10B shows a plan view of another intermediate step of the same thin film transistor device manufacturing method from the top side view , The bottom side view of Figure 4B is a cross-sectional view taken along the line II-II of the top side view.

Figure 11A shows a plan view of another intermediate step of the thin film transistor device manufacturing method of the first embodiment of the present invention, and Figure 11B shows the top side view of another intermediate step of the same thin film transistor device manufacturing method The plan view, the bottom side view of Figure 4B is a cross-sectional view taken along the line III-III of the top side view;

Figures 12A to 12H show several cross-sectional views of a method of manufacturing a thin film transistor device according to a second embodiment of the present invention;

Figures 13A to 13D show cross-sectional views of another method of manufacturing a thin film transistor device according to the second embodiment of the present invention;

Figures 14A to 14F show cross-sectional views of a method of manufacturing a thin film transistor device according to a third embodiment of the present invention;

Figure 15 shows a cross-sectional view of another method of manufacturing a thin film transistor device according to the third embodiment of the present invention;

FIG. 16A shows a plan view of the thin film transistor device according to the third embodiment of the present invention, and FIG. 16B is a cross-sectional view taken along the line VV of FIG. 16A;

Figure 17A shows a plan view of another thin film transistor device according to the third embodiment of the present invention, and Figure 17B is a cross-sectional view taken along the line VII-VII of Figure 17A;

Figure 18 shows a cross-sectional view of a liquid crystal display device having the thin film transistor device of the fourth embodiment of the present invention;

Figure 19A is also a cross-sectional view taken along the line IX-IX of Figure 18, and Figure 19B is a cross-sectional view also taken along the line XX of Figure 18;

FIG. 20 is a plan view of a liquid crystal display device having the thin film transistor device of the fifth embodiment of the present invention;

Figure 21A is also a cross-sectional view taken along the line XII-XII in Figure 20, and Figure 21B is a cross-sectional view also taken along the line XIII-XIII in Figure 20.