Method and arrangement for regulating low output voltages in multiple output flyback dc/dc converters

(54)

INVENTOR'S OFFICE NAME (56) (57)

Bengt Assow, Norsborg SE Ericsson Microelectronics AB Procedure and device for regulating low voltages in flyback type DC converters with multiple outputs

CALLED PUBLICATIONS:

US 6,038,150 (369/89)

SUMMARY·

In addition to generating a main output voltage (U1), at least one additional output voltage (U2) is generated in a flyback type DC converter having a transformer (TR) having a primary winding connected in series with a primary switch (Ti), a secondary winding (NI + N2) connected in series with a first rectifier (D1) to a first output capacitor (C1) to generate said main output voltage (U1) and a second secondary winding (N2) connected in series with a synchronous rectifier (T2) to a second output capacitor (C2) for generating said additional output voltage (U2), an error amplifier (3) is arranged to compare the actual value of said additional output voltage (U2) with a setpoint and is a control circuit (C4, R.4, R3, T5) coupled between the fault amplifier (3) and the synchronous rectifier (T2) to adjust the synchronous rectifier (T2) turn-off time depending on differences between the actual value of said additional output voltage (U2) and the hearing value in and to adjust the actual value to the hearing value.

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519 148

TECHNICAL FIELD

The present invention relates generally to flyback type DC outputs with multiple outputs and more particularly to a method and apparatus for controlling low voltages within tight tolerances in flyback type DC outputs with multiple outputs.

BACKGROUND OF THE ART

There is a demand for converters which, in addition to a main DC voltage, also provide at least one additional DC voltage lower than the main voltage.

If diodes are used to generate the additional direct voltages, the voltage drop across the diodes can be as high as 0.5 V. This means too low voltages, e.g. &lt;3.3 V, low efficiency.

When high efficiency is required, synchronous rectification must be used since the voltage drop across synchronous rectifiers, ie MOSFETs, is much lower than over diodes.

In transducers with multiple outputs, the main output voltage is regulated in a manner known per se by regulating the working switch of the primary switch. However, additional output voltages in converters with multiple outputs cannot be controlled by regulating the primary switch's working ratio but must be controlled separately, e.g. with the help of complicated switched series controllers

519 148

DISCLOSURE OF THE INVENTION

The object of the invention is to provide a method and a device for controlling a synchronous rectifier used MOSFET to control low voltages within tight tolerances.

This is achieved in accordance with the invention by controlling the MOSFET off time to vary its timing.

Hereby, the output voltage can be regulated between the forward voltage case of the MOSFET's body diode and the MOSFET's joint voltage drop. This voltage difference is only approx.

0.3 V to 0.4 V but large enough to control a voltage of 3.3 V within tight tolerances.

DESCRIPTION

The invention will be described in more detail below with reference to the accompanying drawing, in which Fig. 1 shows an embodiment of a flyback type DC output converter with multiple outputs according to the invention and Figs. 2A - 2F are diagrams illustrating various signals in the embodiment of Fig. 1.

DESCRIPTION OF THE INVENTION

Fig. 1 shows an embodiment of a flyback type DC voltage converter with multiple outputs according to the invention.

In the embodiment of Fig. 1, in addition to a main output voltage U1, a single additional output voltage U2 is generated. However, it is to be understood that it is possible to generate more than one additional output voltage. In such a case, for each additional output voltage to be generated, a device must be present corresponding to the device to generate the additional output voltage U2, which device will be described below.

519 148

The converter of Fig. 1 comprises in a known manner a transformer TR with a primary winding connected in series with a primary witch TI to a schematically shown DC voltage source VI and a secondary winding NI + N2 connected in series with a diode D1 to an output capacitor C1 to generate the main output voltage U1.

The switching and switching times of the primary switch TI, that is, its working ratio, are controlled by a switch working rate regulator or switch controller 1 in dependence on outputs from a fault amplifier 2 connected with its input terminals over capacitor C1 to generate outputs in response to differences between the actual value of the output voltage setpoint value in the fault amplifier 2.

In order to generate the additional output voltage U2 according to the invention, in the embodiment of Fig. 1, part N2 of the secondary winding of the transformer TR is connected in series with a synchronous rectifier in the form of a MOSFET T2 to an output capacitor C2.

Instead of a common secondary winding N1 + N2, it is understood that separate secondary winding (not shown) can be used to generate the main output voltage U1 and the additional output voltage U2, respectively.

In a manner known per se, the MOSFET T2 comprises an emitter S, a collector D and a control G as well as a body diode D2 which is connected with its anode to the emitter S and with its cathode to the collector D of the MOSFET T2.

In the embodiment shown in Fig. 1, the collector D of the MOSFET T2 is connected to the emitter S of the MOSFET T2 via a resistor R1 in series with a diode D3 and a capacitor C3.

519 148 ·· ·

The interconnection point between diode D3 and capacitor C3 is connected to the collector of a transistor T3. The emitter of transistor T3 is connected to the controller G of the MOSFET T2 and to the emitter of a transistor T4 whose collector is connected to the emitter of the MOSFET T2.

Transistors T3 and T4 are two emitter followers that can quickly charge / discharge the control G of the MOSFET T2.

The bases of the transistors T3 and T4 are interconnected and connected via a resistor R2 to the collector of transistor T3.

The interconnected bases of transistors T3 and T4 are also connected to the collector of a transistor T5 whose emitter is connected to the emitter S of the MOSFET T2.

The base of transistor T5 is connected via a resistor R3 in series with a capacitor C4 to the collector D of the MOSFET T2.

In accordance with the invention, the connection point between resistor R3 and capacitor C4 is connected via an resistor R4 to an output terminal of a fault amplifier 3. Fault amplifier 3 is connected with its input terminals across capacitor C2 to generate outputs to control the MOSFET T2 the actual value of the additional output voltage U2 and a set value set in the error amplifier 3.

As mentioned above, the switch is the TI flyback converter's primary switch. When the switch T1 is on, magnetic energy is stored in the transformer TR and the voltage across the secondary winding of the transformer TR is assumed to be negative. When the primary switch TI turns off, the voltage across the transformer TR secondary winding becomes positive and

519 148 a current IDI flows through diode D1 to charge capacitor C1 and current IT2 flows through MOSFET T2 to charge capacitor C2.

With reference to the diagrams in Figures 2A - 2F, the function of the transducer shown in Fig. 1 will now be described in more detail during a withdrawal period of the primary switch T1.

It should be mentioned that the diagrams in Figures 2A - 2F are essentially theoretical, ie more or less idealized.

The primary switch T1 is assumed to be from the wave and is assumed to be switched off at time t1 and again switched on at time t4 as shown in Fig. 2A.

When the primary switch T1 is on, the voltage across winding N2 is negative and capacitor C3 is charged via resistor R1 in series with diode D3.

When the primary switch T1 turns off at the time t1, the body diode D2 of the MOSFET T2 leads to charge to charge the output capacitor C2.

Emitter collector voltage U_s.dT2 of the MOSFET T2 is illustrated in Fig. 2B.

Base current is supplied to transistor T3 via resistor R2. The control G of the MOSFET T2 is loaded, which causes the MOSFET T2 to be saturated.

The control emitter voltage Ug_sT2 of the MOSFET T2 is illustrated in Fig. 2C.

In the following description, it is assumed that the output voltage U2 at time t1 is higher than the hearing value set in the fault amplifier 3.

519 148 ’·· ·

The error amplifier 3 senses that the output voltage U2 is higher than the hearing value and waves discharge from capacitor C4 via resistor R4.

This causes transistor T5 to conduct at time t2 as shown in Fig. 2D illustrating the base-emitter voltage U_b_eT5 of transistor T5.

When transistor T5 waves pass at time t2, the control charge of MOSFET's control G wave discharges via transistor T4 as illustrated in Fig. 2C.

The control charge of the control G is assumed to be completely discharged at time t3.

Thus, the MOSFET T2 turns off at time t3.

When the MOSFET T2 turns off at time t3, current IT2 drops through it as shown in Fig. 2E. However, because the transformer TR is not ideal and the presence of the body diode D2 in the MOSFET T2, however, the current IT2 does not decrease to zero.

The decrease in current IT2 causes a corresponding increase in current IDI through diode D1 as shown in Fig. 2F.

This increase in current IDI tends to increase the main voltage U1.

The error amplifier 2 will sense this increase in the main voltage U1 and, as a result, control the working rate controller 1 to adjust the working rate of the primary switch T1 in such a way that the main voltage U1 is reduced to the set value.

Between the time t3 when the MOSFET switches off and the time t4 when the primary switch T1 switches on again, the currents IT2 and IDI decrease because the energy stored in the transformer TR decreases.

519 148

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By controlling the MOSFET T2 in this way, ie by adjusting its switch-off time depending on the actual value of the additional output voltage U2 exceeding the set value, it is possible to control low voltages in the interval between the bias drop of the body diode D2 and the arcing voltage drop of the MOSFET T2 within tight tolerances.

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