Semiconductor ic chip

(54) NAME Semiconductor chip for integrated semiconductor circuits and identification circuit for the same (56) QUOTE PUBLICATIONS: - - - (57) SUMMARY: A semiconductor chip for integrated semiconductor circuits with an identical ifier circuit in it is shown. The semiconductor washer comprises a pair of voltage power clamps and a plurality of clamps and an iden- tified circuit which is connected between any of the voltage power clamps and one of the clamps. The identification circuit means comprises: a voltage limiter stage having a predetermined limiting voltage level for limiting the inpotential difference between the voltage power of the clamp and the clamp; and a selector means which is connected to the voltage limiter step for determining identification in the nformation of the ha 1 v1 ore tag in accordance with whether or not a current path is formed during the manufacturing process of the ha ve conductor bridge. In the dentifier, the test for semiconductor washers of the present semiconductor was performed via the existing input and output terminals and voltage power terminals without any additional test and diagnostic connection pins and without the aid of laser equipment or the like.

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The numbers in brackets indicate international identification code, INlD code. Letters in clamps indicate international document code.

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Field of the Invention

The present invention relates to having a semiconductor chip for integrated semiconductor circuits, and more particularly to a semiconductor chip for integrated semiconductor circuits (ICs) having a semiconductor chip identification circuit for sorting semiconductor chips via a test.

Background of the invention.

Lately, there is a growing tendency for electronic systemization to be achieved throughout the industrial area in line with the development of high conductor technology. Accordingly, the appropriate characterization of the electronics system is required to fulfill the peculiarity of each area. For this reason, semiconductor manufacturers have not neglected the effort to change products to meet different user requirements. For example, in addition to a basic working mode, different working modes have been developed to a corresponding degree when the storage capacity of the DRAM (dynamic direct memory) memory has increased to M-bit. That is, in a eller or 4M DRAM memory, the working modes are divided into 1 bit, 4 bit, 3 bit and so on, in accordance with the number of bits for a data output and divided into a fast page mode, a sub mode, a static column mode etc., in accordance with a control input. Therefore, in order to fulfill the requirements of the users, the suppliers of DRAMs provide different DRAMs which perform the different modes according to different selected modes by voluntarily providing the specific working modes in addition to a basic working mode of the DRAMs during the manufacturing process of the same. For example, the fast side mode, such as the basic work, is assumed to be the method in a single DRAM-1 in operation mode and the DRAM memory for the sub-mode or the static column mode is produced by voluntarily providing the working mode during the respective manufacturing steps.

Such a voluntary action is performed disc by disk of semiconductor material and the manufactured DRAMs are divided into each mode. Then, after the DRAM memory has been manufactured, during a mounting process, the sheet of semiconductor material is separated into an individual matrix or semiconductor chip by a drawing process, the separated matrices being packaged in a specific capsule through the processes of a matrix.

508 000 assembly, a welding wire joint and a molding, and the packaged DRAM memory will be passed on as a final product after marking the data for the product, for example, the serial number, date of manufacture and the line of manufacture under product 11 est.

However, in the case of DRAM memories made with the aforementioned process, the matrices or the 1 v 1 edar bricks that are divided in each mode are often mixed with other types of semiconductor trays when the matrices or the 1-wire bridges are produced in a single line. In this case, the products for the various work methods are checked as faulty semiconductor washers during the next test step and treated as an article of poor quality, resulting in yield reduction.

In order to prevent the same types of matrices from being mixed with other types of matrices, very careful attention is also needed, thereby reducing the working power of one.

Accordingly, a technique has been required which makes it possible to sort or identify the same types of semiconductor washers during the test step, when having the conductor washers with the different modes mixed with each other prior to packaging.

Such identification technology for the semiconductor chips has been disclosed in US Patent No. 4,150,331 and 4,510,673 to U.S. Pat. 4,150,331 discloses a technique that identifies each conductor chip by the use of the programmable circuitry on the surface of the semiconductor chip. The circuitry is provided to program an identification code in accordance with whether or not a diode is formed between a test and diagnostic connection provided and a selected input / output pin.

However, the above-mentioned technology has a defect in that the large size cap, which has an important effect on the price of the semiconductor chip, becomes too large due to the extra test connection test available.

In U.S. Pat. 4,510,673 discloses a technique by which the specific identification mark is indicated on the back surface of the semiconductor tray by the use of a laser apparatus, and a human or machine can distinguish the identification mark by the use of a laser apparatus or optical apparatus. However, the technique of this patent has a deficiency in the fact that expensive laser devices must be present to label the specific identi

508 000 commemorative indication, for example, a production line, a production line.

Summary of the Invention.

It is an object of the present invention to provide a semiconductor chip for integrated conductor circuits with a new identification circuit that does not require an additional test and diagnostic connection and addresses the aforementioned problems present in the prior art.

Another object of the present invention is to provide a semiconductor chip for integrated semiconductor circuits having an identification circuit that is simple in construction and facilitates identification of the semiconductor chip.

In order to achieve the above-mentioned objects of the present invention, a semiconductor chip for integrated semiconductor circuits is provided with a pair of voltage power terminals and a plurality of terminals and an identification circuit means connected between any of the voltage power terminals and any of the terminals, identifying the circuit

a voltage limiter stage having a predetermined limit voltage level for limiting the inpotential difference between one of the voltage power terminals and one of the input terminals; and a selector means connected in series with the voltage limiter step for determining the identification information of the semiconductor chip in accordance with whether or not a current path is formed during the semiconductor chip manufacturing process.

According to the present invention there is also provided a semiconductor chip for integrated semiconductor circuits having a pair of voltage power terminals and at least three input terminals and an identification circuit means which is connected to one of the voltage effect t terminals and which is connected to three of the at least three input terminals, inside f;

a voltage limiter step with a predetermined limit voltage level for limiting the inpotential difference between the voltage power terminal and one of the three input terminals; and

508 000 then generating a predetermined control voltage by dividing the limited voltage range;

a selector means connected between the remaining two of the three input terminals for determining the identification information of the 1 wire conductor may be in accordance with whether a current path is formed or during the manufacturing process of the semiconductor disk; and a switching means connected in series with the selector means, the switching means being switched on by the control voltage supplied from the voltage limiter stage.

With this design, the present invention can adopt an identification circuit for having the conductor bridge without adding an additional connector pin such as the test and diagnostic connector pin.

Brief description of the drawings,

FIG. 1 shows a simplified depiction of an embodiment of a semiconductor chip for integrated semiconductor circuits with an identification circuit according to the present invention;

FIG. 2 shows a simplified depiction of another embodiment of a semiconductor chip for integrated semiconductor circuits having an identification circuit according to the present invention;

FIG. 3 is a circuit diagram showing a modification of a selector shown in FIG. 1 and FIG. 2; and

FIG. 4 illustrates, in simplified form, a yet another embodiment of a semiconductor chip for integrated semiconductor circuits having an identification circuit according to the present invention.

Detailed description of the invention.

Below, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 depicts in schematic form a semiconductor chip for integrated semiconductor circuits having an identification circuit according to the present invention. In FIG. 1, a semiconductor chip for integrated semiconductor circuits includes an internal circuit 10, protection circuits PC1-PCn, buffer circuits B1-Bn, terminals IN1-INn, terminals UT1-OUTn and a pair of voltage power clamps Vdd and Vss. The IC semiconductor chip is not connected to one herein

508 000 shown power source so as to receive power voltage of, for example, 5V via the voltage power terminal Vdd and receives a ground potential via voltage power t the terminal Vss. The internal circuit 10 receives the output voltage from the voltage power terminals Vdd and Vss, performs a given function by receiving input signals transmitted at the input terminals IN1-IN3 and generates predetermined output signals via the output terminals UT1-OUTn. The terminal blocks IN1-INn are also connected to the intercircuit 10 via the respective protective circuits PC1-PC, which prevents the interruption of the internal circuit 10 due to a noise voltage, for example a voltage jump or the like, which is supplied to the terminal blocks.

The output terminals UT1-UTn are connected to the internal circuit 10 via the buffer circuits B1-Bn.

An identification circuit 20, the characterizing part of the present invention, is connected between a terminal IN1 of the input terminals and the voltage power terminal Vss of the IC conductor washer 1. This identification circuit comprises a voltage limiting step 22 and a selector means 24. A voltage limiting step 22 is provided for limiting supply 22. which is transmitted between the input terminal IN1 and the voltage power terminal Vss to a predetermined logic level which is to be supplied to the internal circuit 10. This voltage limiter step 22 consists of a plurality of series connected MOS transistors M_n of which respective control electrodes are connected to respective collectors thereof. The voltage limiter step 22 may also set the predetermined logic level by the sum of the threshold voltage for each MOS transistor.

For example, the predetermined logic level will be set to approximately more than 2.5 V when the TTL level is supplied to the input terminal; and approximately more than +3 V when the CMOS level is fed to the input terminal.

Although the diode design of the MOS transistor is used in this embodiment, it is pointed out that any unilateral current flow device having a predetermined threshold voltage, for example a PN layer diode or Zener diode or the like, can be used as the voltage limiter stage.

Selector means 24 is provided for determining a current flow which passes through the voltage limiter step 22 during the manufacturing process and is connected in series with the voltage limiter step 22. To provide the selector means 24,

508 000 a simple selector wire wiring technique in which connection or from coupling of a fuse or metal wire formed during manufacturing process determines the mode of the semiconductor chip.

In this embodiment, after the sacrificial ring has been formed, identification is written in the infor mation to have the 1v 1 vein washer through the selector process where melting of the fuse via laser firing process is determined.

For example, during the manufacturing process of the semiconductor washer, the fuse FU is held in a semiconductor washer connected to a DRAM memory with fast side mode operation; and melted down for one

DRAM memory with partial mode, which makes it possible to identify the semiconductor chip. During a test step for the semiconductor chip manufacturing process for the aforementioned identification-processed semiconductor chip, the input terminal IN1 is connected to a predetermined high voltage source 2, for example a voltage source of approximately 15 V and the voltage power of the terminal Vss is connected to an amperimeter. the maturity of the DRAM memory. If the current is flowing, the test piece is identified as a DRAM memory for fast side mode operation, while if the current is not flowing, it is identified as a partial mode DRAM memory, by controlling the current flow using the ammeter 3.

In the case of sub-mode, the fuse here is fused so that the input signal is transmitted to the internal circuit 10 independent of the existence of the identification circuit 20 during the normal operation of the semiconductor chip; but in the case of fast side mode, if it were not for the voltage limiter step 22, the input terminal IN1 would always be in the state of a logic 0 ”via the fuse FU. The occurrence of this phenomenon will be prevented by the voltage limiter step 22. In more detail, when a logic "0 is transmitted to the input terminal IN1, a logic" 0 is input to the internal circuit 10 independently of the connection of the identification circuit 20; but when a logic 1 is transmitted to the input terminal IN1, the current flows through the identification circuit 20 thus generating a predetermined voltage difference in the voltage limiter step 22, which causes the internal circuit 10 to be supplied with a logic 1 ".

The identification circuit 20 is preferably connected to the input terminal INI via the protection circuit PC1 which protects the identification circuit from damage due to the external voltage jump or the like.

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FIG. 2 illustrates another embodiment of the semiconductor chip for integrated conductor circuits according to the present invention, wherein the circuit design is similar to that of the first embodiment except that the identification circuit 20 is connected between the voltage power k1 of the Vdd and the input terminal IN1. Since the voltage of +15 V supplied to the input terminal is higher than the voltage of +5 V supplied from the voltage output terminal Vdd during the identification test, the underlying operating principles of the semiconductor disk are the same as those of the first embodiment.

FIG. 3 illustrates the modification of the weather means 24 for identifying two or more than two types of semiconductor washers. As shown in FIG. 3, the selector 24 comprises a plurality of MOS transistors Mal-MAn whose control electrodes are connected to the collectors of the same and a plurality of fuses FU1-FUn are respectively connected to the respective MOS transistor. Each combination of a MOS-1 resistor and a fuse are connected in parallel with each other between the voltage limiter stage 22 and the voltage power terminal Vss (or Vdd).

In order to identify having the conductor washers with the above constructed circuit, the identification information ion can be obtained by the current values ​​passing through the selector as shown in Table 1.

Table 1

In --------- 1 ------------------- 11

II fuse connectionJ | | ------- 1 ------- 1 ------- 1 identification | | | FU 1 [FU 2 | FU 3 | information |

<td>fast page mode 1 IN</td><td>connected</td><td>1 connected I</td><td>1 connected I</td><td colspan="2">II i +1 2 + 13 1</td>

<td>1 modem | |</td><td>melted</td><td>1 1 connected IN</td><td>1 1 connected |</td><td> 1 12 1</td><td> + 1 3</td>

<td>1 static column mode 1 IN</td><td>melted</td><td>1 1 melted IN</td><td>1 1 connected |</td><td> 1 1 1</td><td>I 3</td>

<td>1 other mode |</td><td>melted</td><td>IN | melted</td><td>1 1 melted</td><td> 1 1</td><td> 0</td>

In the _________ _______ _______ 1 1 _______ __ In: _______ In

FIG. 4 shows a modification of the identification circuit for identifying two or more than two types of semiconductor washers. In FIG. 4, the identification means 30 is connected to the voltage power terminal Vss and three input terminals IN1-IN3. The identification means 30 includes a voltage limiter step 32, a selector means 34 and a switching means 36.

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The voltage limiter step 32 is designed to limit the voltage difference applied between the input terminal IN3 and the voltage power of the voltage Vss to the logic level received in the internal circuit 10 and then divide the given logic level to generate a predetermined control voltage VR. The voltage limiter stage 32 comprises a plurality of MOS transistors MB1-MBn whose control electrodes are connected to the collectors of the same and a resistor R is connected to the MOS transistors, said plurality of MOS-1 transistors and the resistor being connected between the input terminal IN3 and voltage power. The voltage distribution between the two terminals of the resistor R is applied to the switching means 36 as a control voltage VR. The switching means 36 is connected in series with the switching means between the input terminals IN1 and IN2 for switching the current flow to be switched on by the control voltage VR of the voltage limiter stage 32. The switching means 36 consists of a plurality of MOS transistors MC1-MCn where the collectors of each of the transistors are connected; the control electrodes are supplied with the control voltage VR; and the emitters are connected to the corresponding fuses of the selector 34 described later.

In this embodiment, the selector 34 consists of a plurality of fuses FUA1-FUA, each of which is connected to the corresponding MOS-1 transistors of the switching means 36. . Here, the fusing of the respective fuse of the selector means during the manufacturing process is carried out by having the conductor washer to provide the required identification information.

In order to identify the conductor bridges provided with the identification circuit of the above-described embodiment, the input terminal IN1 is connected to a power source V with a predetermined voltage of, for example, 5 V, the input terminal IN2 is connected to an amperage meter A and a higher voltage source example. 15 V is connected between the input terminal IN3 and the voltage power terminal Vss. When supplying these power sources, current flows through the voltage limiter step 32 and a predetermined voltage is distributed in the resistor R, which generates the control voltage VR to be supplied to the switching means 36. Due to the control voltage VR, the respective MOS9 is switched on.

508 Thus, the current values ​​as shown in Table 2 are obtained in accordance with whether or not the fuses FUA1-FUAn are melted.

Table11 2

FUA 1 connected connected molten connected molten molten molten molten - - - - _ d_stand__! identification FUA 3 | inⁿ° F^RMAti °ⁿ t I t +12 +1 II l I

II _L connected connected connected melt

IN₂ +1

It is stated in Table 2 that the semiconductor trays can be written with the identification information that can identify four different modes of the semiconductor trays.

When the conductor chip is not in the semiconductor chip identification test, the ground voltage is applied to the control electrode of the respective MOS transistor MC1-MCn of the switching means 36 via the resistor VR, thus ensuring the normal operation of the semiconductor chip.

As described above, in accordance with the present invention, the identification information of the semiconductor chip is written by the voluntary provision of the connection or disconnection of this simple circuit during the manufacturing process for sheets of conductive material1. and the written identification information is detected in the test step during the ordinary semiconductor chip assembly process so that the same type of semiconductor chips can be detected and processed separately in the subsequent process.

In the semiconductor tray of the present invention, the identification test for the semiconductor tray is performed via existing input and output terminals and voltage power terminals in a different way than in the conventional process so that the conventional manufacturing system is utilized to the greatest extent possible without any modifications to it which is very economical and desirable.

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In addition, the semiconductor bridge of the present invention does not require any additional test and diagnosis capability and expensive laser equipment or the like for identifying the semiconductor tray.

It should be noted that the semiconductor chip of the present invention has been described as being useful for the MOS transistors in the above embodiments, but may also be adopted for various applications upon request. Thus, the present semiconductor tray can be modified in various forms within the scope of the present invention as defined in the appended claims.

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