Multiple carrier transmission system with channel data sent between two transceivers

(54) (56) (57)

Telia AB, 123 86

Mikael Isaksson,

Harry Erland Tonvall,

Tomas Stefansson, Luleå SE,

Gunnar Bahlenberg, Luleå SE,

SE, Sven Göran Ökvist, Luleå SE, Karin Lis-Mari Ljunggren,

Luleå SE, Tomas Nordström, Luleå SE, Lars-Åke Isaksson,

Luleå SE, Daniel Bengtsson, Luleå SE, Per Ödling, Luleå SE, Wen Ye, Märsta SE, Siwert Håkansson, Järfälla SE

Telia Research AB

Improvements to, or with respect to, multi-carrier systems

AGENT

NAME

CALLED PUBLICATIONS: - - SUMMARY:

The invention provides a multi-carrier transmission system, for example a DMT system, in which channel information is transmitted between two transceivers using a plurality of subcarriers modulated by symbols, each representing a plurality of bits, each of said transceivers including a receiver and a transmitter, in which a defined maximum value is determined on the number of bits for each symbol, and wherein the system is adapted to determine the bit capacity per symbol for each of said plurality of subcarriers, and to increase the number of bits represented by a symbol transmitted over those subcarriers having a capacity lower than the defined maximum value, to the said maximum value by adding channel coding bits. The defined maximum value of the number of bits for each symbol can be determined on the basis of the bit capacity of the subcarrier having the highest theoretical bit capacity and may be at least as large as said theoretical bit capacity.

wired network

Networking Device (NOW)

In downstream optical fiber

IjÖ £> e '.- 4 ikabel S

Network (plant) termination (NT) multimedia application

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upstream

The numbers mom parentheses indicate international identification! Od, INID code. Letters in clamps indicate international document code.

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The present invention relates to a multi-carrier transmission system in which channel information is transmitted between two transceivers using a plurality of sub-carriers modulated with symbols, and a method for transmitting said channel information.

The requirement to provide multimedia and other broadband services over telecommunications networks has created a need to transmit high bit rate traffic on copper pair conductors. This need has led to the development of a number of different transmission system proposals, such as ADSL and VDSL. One of the more likely modulation systems for all these transmission systems is a line coding known as discrete multitone, DMT (Discrete Multi-Tone), which bears some resemblance to orthogonal FDM (Orthogonal Frequency Division Multiplexing), and is a transmission technique based on spread speccrum technology. .

For discrete multitone transmission, the available bandwidth is divided into a plurality of subchannels, each with a small bandwidth, perhaps 4 kHz. Traffic is allocated to the various sub-channels depending on noise power and transmission losses in the respective sub-channels. Each channel conveys multi-level pulses (multilevel pulse jams that can represent up to 11 data bits. Poor-quality channels convey fewer bits, or can be completely turned off.

Since interference between pairs in copper pair cables is higher where data is transmitted in both directions, i.e., symmetric duplex, for a number of transmission proposals, the use of asymmetric solutions in which high

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640 data rates are transmitted only in one direction. Such solutions meet many of the requirements for high bandwidth services, such as video-on-demand, but in the long term, symmetrical duplex systems will be required.

VDSL technology is very similar to ADSL, although ADSL has to provide much larger dynamic ranges and as a result is much more complex. VDSL is lower in cost and lower in energy (lower in power), and VDSL units in real estate (premises) need to implement a media access control in the physical layer for multiplexing upstream data.

Four line codes have been proposed for VDSL:

CAP; Carrierless AM / PM, a version of QAM with suppressed carrier, for passive NTcore configurations, CAP would use upstream QPSK and a type of TDMA for multiplexing (although CA does not exclude a FDM solution for upstream multiplexing);

DMT; Discrete Multi-Tone, a multi-carrier system that uses discrete Fourier transforms (Discrete Fourier Transforms) to create and demodulate individual carriers, for passive NT configurations;

DMT would use FDM for upstream multiplexing (although DMT does not rule out a strategy of TDMA multiplexing);

DWMT; Discrete Wavelet Multitone (Discrete Wavelet Multi-Tone), a multi-carrier system that uses Wavelet transforms (Wavelet transforms) to create and demodulate individual carriers;

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DWMT also uses FDM for upstream multiplexing, but also allows TDMA; and

SLC; Simple Line Code, a four-level version of baseband signaling that filters and resets the baseband at the receiver, for passive NT configurations; it is most likely that SLC will use TDMA for upstream multiplexing, although FDM is possible.

Early versions of VDSL will use frequency division multiplexing to separate downstream from upstream channels, and both of these from POTS and ISDN. Eco-quenching may be needed for later generations of systems with symmetrical data rates. A fairly large distance, in frequency, will be maintained between the lowest data channel and POTS to enable very simple and cost-effective POTS splitters. Normal use would place the downstream channel above the upstream channel. However, the DAVIC specification reverses this arrangement to enable distribution of VDSL signals over coaxial cable systems in buildings.

When transmitting traffic using multi-carrier technology, for example orthogonal frequency division multiplexing (OFDM), the same number of bits is transmitted on all subcarriers. This is done despite the fact that it is theoretically possible to transmit several bits if the channel is known, which is the case, for example, when transmitting traffic on copper conductors. It is therefore desirable to provide, in a multi-carrier system, a method of transmitting different number of bits per channel, or subcarrier.

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Currently, bit loading is used to vary the number of bits per channel, or subcarrier, in so-called discrete multi-tone and OFDM transmission, both of which use multi-carrier technology on known channels. Thus, such systems provide a method for transmitting the correct number of (actual capacity) bits per channel. However, while this method transmits a varying number of bits per channel, or subcarrier, it would be advantageous to be able to transmit a fixed (fixed) number of bits per channel, or subcarrier, but with varying user data content.

It is an object of the present invention to provide a multi-carrier transmission system in which channel information is transmitted between two transceivers using a plurality of subcarriers modulated by symbols, each of which represents a plurality of bits, and in which each symbol has a particular (fixed) maximum number of bits, where the number of bits represented by a symbol transmitted over a subcarrier having a capacity less than said maximum value, is increased using channel coding bits.

Another object of the present invention is to provide, in a multi-carrier transmission system in which channel information is transmitted between two transceivers using a plurality of subcarriers modulated with symbols, each representing a plurality of bits, a method of transmission. of said channel information.

According to a first aspect of the present invention, there is provided a multi-carrier transmission system in which channel information is transmitted between two transceivers using a plurality of subcarriers modulated by symbols, each representing a plurality of bits, each of the aforesaid.

506 640 transceivers include a receiver and a transmitter, characterized in that a fixed maximum value is determined for the number of bits for each symbol, and that the system is adapted to determine the bit capacity per symbol for each of said plurality of subcarriers, and that increasing the number of bits represented by a symbol transmitted over the subcarriers having a capacity less than the defined maximum value, to said maximum value, by adding channel coding bits.

The defined maximum value of the number of bits for each symbol can be determined on the basis of the bit capacity of the subcarrier having the highest theoretical bit capacity, and may be at least as large as the theoretical bit capacity of the one of the subcarriers.

According to the present invention, there is provided a multi-carrier transmission system in which said transmission is effected by means of a plurality of subcarriers modulated with symbols, each representing a plurality of bits, in which said system is adapted to determine a defined maximum number of bits for any symbol, wherein said defined maximum value is at least as large as the bit capacity of that of said subcarriers having the highest theoretical bit capacity, and in which said system is adapted to increase the number of bits represented by a symbol transmitted over the subcarriers having insufficient capacity, to said defined maximum value by introducing a number of channel coding bits.

According to a second aspect of the present invention, there is provided in a multi-carrier transmission system in which channel information is transmitted between two transceivers using a plurality of subcarriers modulated by symbols, each of which

506 640 represents a plurality of bits, each of said transceivers including a receiver and a transmitter, a method for transmitting said channel information, characterized in that a defined maximum value is determined for the number of bits for each symbol, which determines the bit capacity per symbol. for each of said plurality of subcarriers, and increases the number of bits represented by a symbol, which is transmitted over the subcarriers having a capacity less than the defined maximum value, to said maximum value by introducing channel coding bits.

In a preferred method, according to the invention, the defined maximum value of the number of bits for each symbol is determined on the basis of the bit capacity of the subcarrier having the highest theoretical bit capacity. According to this preferred method, the defined maximum value of the number of bits for each symbol is at least as great as the theoretical bit capacity of the one of the subcarriers.

The method of the present invention is characterized by the steps of transmitting the channel information by means of a plurality of subcarriers modulated with symbols, each representing a plurality of bits, determining a defined maximum value for the number of bits for each symbol, that said defined max. value is at least as large as the bit capacity of the subcarrier having the highest theoretical bit capacity, and increasing the number of bits represented by a symbol; which is transmitted over the subcarriers having insufficient capacity, to the defined maximum value by introducing a number of channel coding bits.

The bit capacity of a subcarrier can be determined by measurement or value calculation (estimation).

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The channel coding bits can be used to reduce the bit error rate and / or to validate the channel information at a receiver.

The multi-carrier system may be a DMT system, or a DMT-based VDSL system.

According to a third aspect of the present invention, there is provided a multi-carrier transmission system in which channel information is transmitted between two transceivers using a plurality of subcarriers modulated with symbols, each representing a plurality of bits, characterized in that said system uses a method outlined in the foregoing piece for transmitting said channel information.

The foregoing and other features of the present invention will be better understood by the following description with reference to the accompanying figures, in which:

Figure 1 shows, in schematic form, an asymmetric communication system.

Figure 2 shows, in schematic form, a DMT system.

Figure 3 shows, graphically, the channel separations used in an asymmetric DMT transmission system.

Figure 4 shows, in schematic form, the foundations of a multitone carrier system modem as contemplated by the present invention.

Figure 5 shows, in schematic form, a partitioning of the multitone carrier system modem shown in Figure 4, which is used to facilitate implementation.

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Figure 6 shows, in graphical form, spectral allocation for copper pairs.

Figure 7 shows, in schematic form, the frame structure used in the multitone carrier system described herein.

Figure 8 shows, in schematic form, the analog interface of the multitone carrier system modem shown in Figure 4.

Figure 9 shows, in graphical form, the dependence of the signal-to-noise ratio (SNR ratio) for frequency in the multitone carrier system described herein.

Figure 10 shows, in schematic form, the FFT algorithm used in the multitone carrier system modem shown in Figure 4.

Figure 11 shows, in schematic form, the framework correlation principle used in the multi carrier carrier modem shown in Figure 4.

Figure 12 shows, in schematic form, the implementation of a correlator used in the multitone carrier system modem shown in Figure 4.

Figure 13 shows, in schematic form, the averager used in the correlator in Figure 12.

Figure 14 shows, in schematic form, a correlation position detector used for the multitone carrier system modem shown in Figure 4.

Figure 15 shows, in schematic form, an overview of the synchronization unit used in the multitone carrier system modem shown in Figure 4.

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Figure 16 shows, in schematic form, an overview of the FFT / IFFT unit used in the multitone carrier system modem shown in Figure 4.

Figure 17 shows, in schematic form, the use of a cyclic prefix.

Figure 18 shows, in schematic form, a decision directed channel value calculation and equalization system for use in the multitone carrier system modem shown in Figure 4.

Figure 19 shows QAM coding for b = 6.

Figure 2C shows, in schematic form, the realization of the calculation of bit charge and energy charge factors used in the multitone carrier system modem shown in Figure 4.

Figure 21 shows, in schematic form, an overview of the system controller interface used in the multitone carrier system modem shown in Figure 4.

Figure 22 shows, in schematic form, the manner in which two of the multitone carrier system modems shown in FIG.

Figure 4, are interconnected to create a multitone carrier wave transmission system.

Figure 23 shows, in schematic form, the vector management system used in the multitone carrier system modem shown in Figure 4.

Figure 24 shows BSI length.

Figure 25 shows, in schematic form, the NU SC load distribution for BSI506

640 interrupt for the multitone carrier system modem shown in Figure 4.

Figure 26 shows the SUS pattern of the multitone carrier wave modem shown in Figure 4.

Figure 27 shows the DAS pattern in schematic form, for the multitone carrier wave modem shown in Figure 4.

Figure 28 shows, in schematic form, wake-up signaling for the multitone carrier system modem shown in Figure 4.

Figures 29 to 31 show the setup sequence of the multitone carrier system modem shown in Figure 4.

Figure 32 shows, in schematic form, a network overview of a network interface for a VDSL modem application.

In order to facilitate the understanding of the present invention, a list of abbreviations is presented below

<td>used</td><td>in this patent application.</td>

<td>ADC:</td><td>Analog to Digital (A / D) Converter (Analog-to-Digital Converter)</td>

<td>AIS:</td><td>Alarm In Signal</td>

<td>ASIC</td><td>Application Specific Integrated Circuit</td>

<td>BPSK:</td><td>Binary Phase Shift Keying</td>

<td>BSI:</td><td>Basic Synchronization Range (Base Synch Interval)</td>

<td>BSI-D:</td><td>BSI for downlink connection (BSI for downlink connection)</td>

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<td></td><td> 11</td>

<td>BSI-U:</td><td>BSI for uplink connection (BSI for uplink connection)</td>

<td>CCH:</td><td>Styrkana1 (Control channel)</td>

<td>CM1:</td><td>Carrier Wave (Mode) 1; bit-loaded and used carrier (Carrier mode 1, bit-loaded and used carrier)</td>

<td>CM2:</td><td>Carrier mode 2, (removed) masked or spaced carrier (Carrier mode 2, masked out or disabled carrier)</td>

<td>CM3:</td><td>Carrier mode (mode) 3, carrier designed for noil bit charging, (Carrier mode 3, zero bit-loading enabled carrier)</td>

<td>CP:</td><td>Cyclic Prefix (Cyclic Prefix)</td>

<td>DAC</td><td>Digital to Analog (D / A) Converters (Digital-co-Analog Converter)</td>

<td>DAS:</td><td>DF3 frame sequence (DF3 frame sequence)</td>

<td>DF1:</td><td>Data frame, random (random) data parallel CCH, (Deca frame, random data parallel CCH)</td>

<td>DF2:</td><td>Data frame, random data and CCH (Data frame, random data one CCH)</td>

<td>DF3:</td><td>Data frame, fully charged with a CCH (Data frame, fully bit loaded one CCH)</td>

<td>DMT:</td><td>Discrete Multi Tone (Discrete Multi Tone)</td>

<td>DWMT:</td><td>Discrete Wavelet multitone (Discrete Wavelet Multi-Tone)</td>

<td>EMC:</td><td>Electromagnetic compatibility (Electro Magnetic Compatibility)</td>

<td>FEC:</td><td>Forward Error Correction</td>

<td>FEXT:</td><td>Far Cry (Far End Cross Talk)</td>

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640

<td></td><td> 12</td>

<td>FFT:</td><td>Fixed Fourier transform (Fast Fourier Transform)</td>

<td>FTTN:</td><td>Fiber to the Node (Fiber To The Node)</td>

<td>G1 MUSIC:</td><td>First generation, prototype system (VME-based) (Generation one, prototype system VME-based)</td>

<td>G2 MUSIC:</td><td>Three + two, ASIC implementation (Three + two ASIC implementation)</td>

<td>G3 MUSIC:</td><td>Two chips silicon implementation (Two chips silicon implementation)</td>

<td>IFFT</td><td>Reverse Fast Fourir Transformation (Inverse Fast Fourir Transformation)</td>

<td>HR:</td><td>Infinite Impulse Response</td>

<td>ISDN:</td><td>International Standard for Digital Networks (International Standard for Digital Networks)</td>

<td>ISI:</td><td>Interference between symbols (Inter-Symbol Interference)</td>

<td>JTAG:</td><td>Joint Test Action Group</td>

<td>LEX</td><td>Local Exchange</td>

<td>LP:</td><td>Low Pass</td>

<td>NT:</td><td>Network Termination</td>

<td>NOW:</td><td>Network Unit</td>

<td>OFDM:</td><td>Orthogonal frequency multiplex (Orthogonal Frequency Division Multiplexing)</td>

<td>RCV:</td><td>Optical Network Unit (Optical Network Unit)</td>

<td>PGA:</td><td>Programmable amplifier attenuator (Progammable Gain Attenuator)</td>

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<td>POTS:</td><td>Conventional Old Telephone Service (Plain Old Telephony Service)</td>

<td>QAM:</td><td>Quadrature Amplitude Modulation</td>

<td>SC:</td><td>System Controller</td>

<td>SDH:</td><td>Synchronous Digital Hierarchy</td>

<td>SF:</td><td>Synch Frame</td>

<td>SNR:</td><td>The signal / noise ratio (Signal-to-Noise Ratio)</td>

<td>10 STB:</td><td>Set Top Box</td>

<td>SWISH:</td><td>Synkroniseringsramsekvens (Synch Frame Sequence)</td>

<td>SUS I:</td><td>SF and DF1 frame sequence (SF and DF1 frame sequence)</td>

<td>SUS2:</td><td>SF and DF2 frame sequence (SF and DF2 frame sequence)</td>

<td>TAKE:</td><td>Time Advance</td>

<td>TDMA:</td><td>Time Division Multiple Access</td>

<td>UTP:</td><td>Unshielded Twisted Pair</td>

<td>VCXO</td><td>Voltage Controlled Crystal Oscillator</td>

<td>VDSL:</td><td>Digital subscriber lines for very high bit rate Digital</td>

<td> 25</td><td>Subscriber Lines)</td>

The system to which the present invention relates is referred, for simplicity, as MUSIC (MUlticarrier System for the Installed Copper Network Multi-carrier System for the Copper Network Installed). MUSIC 30 is intended to provide high speed communication on

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640 copper telephone cable for telephony to support broadband multimedia services.

The MUSIC system described herein (SE 9603193-5) and the patent specifications arranged in cross reference SE 9603187-7, SE 9603188-5, SE 9603189-3, SE 9603190-1, SE

9603191-9, SE 9603192-7, SE 9603194-3, SE 9603195-0, SE

9603196-8, SE 9603197-6 and SE 9603198-4, offer a cost-effective and robust customer implementation with silicon, providing 26: 2 or 13: 2 Mbit / s asymmetric copper cable transmission (&lt;1300 meters) for use in existing, local telephony network.

The MUSIC system can be accessed using the network concept known as Fiber to the Node (Fiber To The Node = FTTN), which uses optical fiber, which each serves many users, up to a switch cabinet near the users' homes. Thus, the cable length specification for MUSIC can be successfully limited to 1300 meters.

The MUSIC system is mainly intended for transmitting a high bit rate signal (26 Mbit / s) downstream to the subscriber, and a low bit rate signal (2 Mbit / s) upstream from the subscriber.

Figure 1 shows the MUSIC system. A network device, NOW, is connected to the fixed network through an optical fiber link, (FTTN). A network termination, NT, connected to a multimedia application, e.g. video-on-demand, is linked to the NOW via copper cable. The MUSIC system supports a high downstream data rate and a much lower downstream data rate.

In the MUSIC system described here, two specific bit rates (13: 2 and 26: 2 Mbit / s) are supported, where the lower bit rate 13: 2 Mbit / s can be implemented as a single bit rate.

506 640 extra options for use on poor, or extremely long, copper cables.

For network termination (NT), the connection consists of a set of standardized interfaces, such as POTS, ISDN, ATM25 and Ethernet. All the transfer protocols are supported by the (carried by) data flow in the modem, except for the POTS passively filtered service, so that it is independent of modem status. The network unit (NU) terminates in the fixed network.

MUSIC separates up and down link spectra by passive filtering in the analog sections.

The version of MUSIC described here is intended to provide opportunities for future functional upgrades. For this reason, the FFT / IFFT block is designed to support full functionality so that it can be reused in future system upgrades.

The MUSIC system is a DMT-based, multi-carrier VDSL system that uses discrete Fourier transform to create and demodulate individual carriers. This is shown in Figure 2, which shows two transceivers each having a receiver, Rx, and a transmitter, Tx, connected to a twisted copper pair. Data is transmitted between the two transceivers using a plurality of carriers, some of which may not be used, e.g. when the channel quality is extremely poor. The number of bits transmitted by each of the carriers can also vary, depending on channel quality.

A multi-carrier modulation technique such as DMT handles frequency-dependent losses and interference on twisted pair cable effectively. In the MUSIC system, the available bandwidth of 10 MHz is divided into 1024 carriers with a width of 9.77 kHz each. The assigned transmission power for the individual carriers depends on the interference power and transmission losses on each

506 640 one of the bands. Each carrier transmits multilevel pulses that can represent up to 12 bits of data (4096 QAM). The signal-to-noise ratio (SNR) of the individual carrier is calculated on the receiver side. If a carrier has a high SNR, up to 12 bits are placed on that carrier. For carriers with lower SNR values, fewer pieces are placed on the carrier. Carriers that are affected by narrow-band disturbance sources are switched off. Forward error correction and data interleaving are used to mitigate the effects of temporary bursts of impulse interference.

Asymmetric VDSL is implemented in this version of the MUSIC system, which means that the downstream speed is much higher than the upstream speed. Two determined downstream speeds (26/13 Mbit / s) are supported by the system; the selected speed depends on the current cable length (&lt;1300 m) and / or the quality of the channel. The upstream speed is fixed at 2 Mbit / s. Various frequency bands can be used in

The MUSIC system to separate the downstream channel from the upstream channel and both from the POTS, see Figure 3.

Alternatively, other duplex methods may be used, e.g. TDMA and / or a method where every other carrier is dedicated for the downstream and upstream channels.

Figure 4 shows an overview of a MUSIC modem to which the present invention relates. The most important hardware blocks are ADC and DAC, synchronization, fourier transform processing, channel value calculation / leveling, symbol mapping and detection, interleaving coding and decoding, network interface and system monitors.

The modem can be considered in the form of four basic function blocks, namely:

506 640 the digital receiver unit;

the digital transmitter unit;

the analog input (front end); and the system controller (PCI).

The analog input includes a hybrid transformer connected to an unshielded, twisted pair and POTS. On the receiver side, the hybrid is connected, via a low pass filter, LP, a programmable gain attenuator, PGA, to an analog to digital (A / D) converter. A voltage controlled crystal oscillator, VCXO, is used to power the analog to digital converter. On the transmitter side, the hybrid is connected to a digital to analog (D / A) converter via a low pass filter.

The digital receiver unit includes a fixed Fourir transform and rescaling unit, FFT, connected, as shown in Figure 4, to a synchronization unit and a channel estimator. The channel estimator is connected via a symbol detection unit and a de-interleaving and decoding unit, to a bit management unit and thence to a network application interface.

The digital transmitter unit includes a bit-handling unit connected to an inverted (inverse) fixed Fourir transform and scaling unit, IFFT, via a coding and interleaving unit and a symbol mapping unit.

The system control is connected to various functional units in the digital receiver and digital transmitter, and to the network application interface and a computer interface, as shown in Figure 4.

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The network (operational) interface connects the higher protocol level to the modem's layer one functionality. This block is responsible for providing the system with the data at the configured bit rate, and adds dummy frames if required.

The data is then channel coded and interleaved. The MUSIC system described here uses a convolutional code combined with interleaving. Using a depth of multiple (multiple) frames, a combined frequency / time interleaving is obtained (see later in this specification).

The symbol mapping block receives input data as an integer vector. This vector is mapped into the configured constellation depending on the current bitload value. The mapping unit uses a Gray coding scheme to reduce the probability of bit errors.

A real (real) vector multiplication is the first step in the IFFT block. This causes the system to scale the output power level of each carrier. The IFFT block then performs a real 2048 point inverted FFT on the input data, which modulates each carrier. As a final step, an address wrap is performed on the output data, where a copy of the first 128 samples is added at the end of the frame. This is called the cyclic prefix (CP).

The modulated signal goes to a DAC which converts the signal with a minimum true dynamic range of 84 dB. The DAC.-n is clocked by the 20 MHz system sample clock. To get rid of Nyquist ghosts, the LP filtered signal. The hybrid provides a balanced interface to the copper cable.

An overview of the MUSIC transmitter and receiver signal path is shown in Figure 4. The transmitter part uses the same hybrid construction as the receiver.

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At the receiver end, the splitter / hybrid transceiver separates the frequencies used by POTS, from 0 to 4 kHz, from the frequencies used by the system. It also extracts the low-level reception signal from the combined high-level transmission signal and the low-level reception signal.

To reduce Nyquist effects on the low-pass signal, the received analog signal is filtered before it is input into the Programmable Gain Amplifier (PGA).

The PGA is necessary to make the most of the dynamic range of the ADC. In this system, the dynamic range should be at least 66 dB.

After the signal has been converted to digital format, the synchronization and FFT blocks receive the data.

In the synchronization block, a frame clock is generated (for controlling the FFT buffers) and a control signal for the VCXO. Initially (retrieve) the synchronization block retrieves the frame clock from the sampled signal. The frame clock is then used to calculate frame synchronization value calculation (frame timing estimate) and is transferred to the VCXO feed back controller. The VCXO generates the sampling clock (20 MHz).

A sampling clock that is only controlled by frame time estimation is not accurate enough in a DMT system. Therefore, after the locking sequence, a dedicated pilot carrier is used to achieve high synchronization precision on the sampling clock.

A BSZ signal is also extracted from the pilot carrier.

BSI is the Base Synchronization Interval timing signal scm used to synchronize the transmitter and receiver CCH communication.

One of the new aspects of the MUSIC system is the algorithm

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640 used by the synchronization block, which is dealt with in more detail later in this specification.

A 2048 point real FFT is performed on the input frames of the FFT block. After this, rescaling, which is based on the energy charge parameters, is performed before data is transferred to the next block.

Channel value calculation and equalization is performed on the output data from the FFT block. All data frames are used to estimate the channel properties. These are then used to compute a bit-loading vector that determines the number of bits to be transmitted on each of the carriers. This information is then transmitted to the transmitter through the upstream control channel (CCH).

In the symbol detection block, a demapping is performed for each carrier according to the bit-loading mask.

After mapping, deinterleaving and error correction at reception (FEC, Forward Error Correction) are performed on the detected bit stream.

The data is then ready for the network (plant) / application interface block after bit handling. Dummy frames are removed in this block.

At the heart of the system, shown in Figure 4, is the system controller (System Controller, SC). The SC is a general purpose processor that interfaces with and controls the various subblocks using a local PCI bus. In the version of MUSIC described here, the CPU is CPU programmable. An external port is provided, through a JTAG interface on the motherboard (on-board), to facilitate programming.

The main tasks of the SC are to control system startup and behavior during runtime and to perform

506 640 bit charge and energy charge calculations. It communicates with the remote side of the modem through a dedicated control channel (CCH). This channel transmits data regarding changes in bit / energy charge and other system signaling.

To obtain a cost-effective product for high volume use, the digital parts of the system must be based on at least two ASIC circuits. Figure 5 shows how the system can be partitioned for chip design purposes. A chip contains the FT / IFFT core. A second chip contains frame synchronization, channel value calculation and equalization, symbol detection and symbol mapping. The analog block and the network interface block can be implemented on a third or fourth chip, respectively.

The system parameters used by the MUSIC system described here are shown in Tables 1 to 3 attached.

VDSL systems operate in the spectrum from 0 to 40 MHz. In this band, the MUSIC system described here occupies the lower 10 MHz, see Figure 6. A number of traditional bands exist in this spectrum, including POTS and some radio amateur bands. Various frequency bands are used in the MUSIC system described here to separate downstream from upstream channels. Since the MUSIC system described here uses 1024 carriers over 10 MHz, each carrier has a bandwidth of 9.77 kHz, with the first two carriers being allocated by the DC level and the POTS service. The last carrier is out of order because it is the Nyquist point. Other carriers (on radio bands) may need to be canceled. This is primarily a matter of immunity and radiation on the balanced copper pair.

By passive filtering of the POTS spectrum, this service can be done independently of the MUSIC system described here, runtime status, or power supply.

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There are two ways to provide ISDN services for a MUSIC modem connection. One way is to allow the POTSand ISDN systems to exist under the (below) MUSIC frequency bands. This can be achieved using a similar filtration process for ISDN band spectrum as for POTS. This filtering allows the service to be provided regardless of configuration.

The other way to provide ISDN is to have ISDN be a carrier service in the MUSIC system. This solution has the advantage in terms of spectrum efficiency. The use of 1024 carriers over 10 MHz gives each carrier a bandwidth of 9.77 kHz. The ISDN spectrum requires the allocation (1504) / 9.77 = 5 of these carriers. Depending on the channel characteristics, these five carriers must be selected to have the best SNR in the system. For a standard connection, this gives 5 * 100 = 500 kbit / s bandwidth.

Therefore, the optimal solution is to use the modem as a carrier, and allocate only 64 kbit / s, compared to 500 kbit / s for the total bandwidth of the 64 kbit / s ISDNtj end.

The result of the attenuation and FEXT (Far End Cross Talk) measurements on a telecommunications operator's network showed that it is possible to achieve bit rates higher than 100 Mbit / s if the cable is shorter than 200-300 meters. For longer cables, the attenuation at higher frequencies limits the maximum bit rate. For cables of about 500 meters, 40 Mbit / s can be achieved, and for a 1 km cable, 15-20 Mbit / s is realistic.

Another factor that reduces performance is EMC, which limits the power used. Some parts of the frequency domain may also need to be excluded.

A typical PSTN can be expected to have the following characteristics when it comes to pulse interference:

506 640 maximum duration 250 gs median interval 67 ms maximum peak amplitude 20 mV most of the energy under 200 kHz background noise -107 dBm / Hz

The main source for synchronization in the system is the sampling clock. The reference for the sampling clock is located on the NOW page and is common to all twisted copper pairs in a secondary cable. The frequency of the sampling clock is 20 MHz ± 10 ppm, with a phase jitter of less than 0.5 ns.

The sampling clock on the NT side is phase locked to the NU side. The logic for the locking uses frame synchronization value calculation (frame timing estimation) in a first stage, and then uses the pilot carrier to a :: produce a fine tuning of the locking. The locking logic controls the frequency of a VCXO via an 18 bit digital / analog converter. The requirements for the VCX0 are 20 MHz ± 25 ppm range and 10 ppm / volt sensitivity. The final locking shall have a precision of 1/100 sample, with a phase jitter of less than 0.5 ns.

The frame clock is 1 / (2048 + 128) of the sampling clock and controls the start of receiving and transmitting the frames. The frame clock, which is used for both transmission and reception, differs in phase on both the NU and NT sides.

The frame clock for transmission on the NT side is the master and controls the start of the signal intervals, see Figure 7.

The receiving frame clock on the NT side is obtained from the hardware function for frame sleep synchronization value calculation and controls the start of frame sampling period, see Figure 7.

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The frame clock for transmission on the NT side is the same as the frame clock for reception, but is a TA sample earlier in phase. TA is a parameter that is measured during system startup on the NOW side and is used to compensate for propagation delay on the copper conductor. This must be done to maintain the orthogonality, over the copper conductor, for the sampled periods, both on the uplink and the downlink. The frame clock for transmission on the NT side controls the start of the signal intervals, see Figure 7.

The frame clock for receiving on the NOW side delays a number of sample clock cycles (TA) relative to the frame clock for transmission, after the TA calculation has been performed. The delay before calculating TA in the startup sequence is determined by the frame timing estimation hardware function hardware and the value is accessible to the controller. The frame clock for receiving on the NOW page controls the start of frame sampling period, see Figure 7.

The BSI clock is used to synchronize parameter changes between the transmitting and receiving sides. The parameters may, for example, be bit charge, energy charge or control channel frequency. The parameters are updated by the system controller, on both sides, before the BSI clock initiates the switch for the new setup.

The BSI clock is 1/8192 of the frame clock. The BSI clock in the uplink delays half a BSI clock cycle relative to the BSI clock in the downlink.

A cross-pseudo-random (pseudo-random) sequence on the pilot channel is used for BSI synchronization between the transmitting and receiving side.

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The cyclic prefix is ​​an extension of the frames added by the FFT chip. In order to maintain orthogonality throughout the signaling period, the last 128 samples of the frame are copied and placed before the actual (actual) frame. This arrangement addresses problems associated with interference between symbols caused by time dispersion.

It is important that the part of the signaling period sampled only on the receiving side overlaps a signaling period in the other direction, along the entire copper conductor. TA is used to optimize this overlap period. The maximum cable length is limited by TA = 128 samples = 6.4 μβ propagation delay. This corresponds to 1280 meters (cm propagation delay is 5 ns / m).

The analog interface connects the received and transmitted digital data stream at the C1 chip to the telephone line. There are also connections to the Tlipset and the system controller for control purposes.

The analog interface is shown in Figure 8. The cable is connected to a hybrid transformer which is also linked to POTS. On the receiving side of the hybrid, the incoming signal goes via a low pass filter and a programmable gain attenuator to an analog / digital converter, ADC, and thence to the C1 chip. On the transmitter side of the hybrid, the outgoing digital signal is converted to analog by a digital / analog converter, DAC, and from there via a low pass filter LP to the hybrid transformer. A voltage controlled crystal oscillator, which operates both ADC and DAC, is connected to the T1 chip synchronization block.

An OFDM frame is a sum of sinusoidal carriers modulated in phase and amplitude and spaced in the frequency domain with a minimum separation distance between carriers. The assumption that

506 The 640 symbols within the frame are evenly distributed and uncorrelated in relation to each other, giving a signal in the schedule with an approximately normal distributed instantaneous amplitude. Thus, there is little opportunity for input data to interact with each other to create pulses with very high peak levels. However, the maximum amplitude must be limited to a lower amplitude than this so that there is a sufficient number of quantization levels in the DAC to handle average (average) signals.

Although the DAC has sufficient resolution to accommodate a high peak level in the transmitter, there are limitations on the receiver side (ADC). However, the consequences on the recipient side need not be as severe as they may appear.

A short cable has a lower attenuation in the high frequency range than a long cable, see Figure 9. This means that a temporary pulse can occur in the receiver almost unaffected by the cable characteristic. Therefore, a relatively large dynamic range in the receiver is required. However, this can easily be accomplished since almost equal damping does not require a large dynamic range. The ADC needs to accommodate the area indicated in Figure 9 by the solid, coarse, arrow-marked line.

The greater high frequency attenuation of long cables, however, requires a large dynamic range.

The high frequency attenuation also means that several large peaks from the transmitter would be required to build up high amplitudes in the receiver; a case that is even less likely to occur at the ADC input (input) than single peaks. Therefore, the headroom can be reduced and the ACC should accommodate the area marked by the rough, dashed arrow line in Figure 9.

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In summary, performance can be optimized by carefully adjusting the signal level at receiver ADC depending on the cable length.

The line splitter / hybrid has two main tasks, namely:

divide and combine telephone signal (POTS) and VDSL signal frequency bands; and preventing the transmitted signal from occurring at the receiver on the same unit by balancing the cable.

Since each transmission direction has its own frequency band, it is possible to optimize both sides with respect to their respective frequency bands to increase the overall performance.

The purpose of the low pass filter on the input signal is to reduce aliasing effects on interference above the frequency range used.

Low pass filter on the output side reduces the transmitted power on the stop band. These filters may form part of the division / hybrid module.

The best commercially available ADC today is Analog Devices AD9042 which has a signal to noise ratio of about 66 dB. It is recommended that either this ADC, or someone with equivalent performance, be used.

For this description, it is assumed that a DAC with 14 bit resolution is used.

The FFT and IFFT algorithms are built on 1024-point complex FFTs with data reorganization to allow computation of two real sequences at the same time. Accordingly, each of the FFT and IFFT are effective 2048 points. The hardware realization is based on a radix-32 kernel

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506 which calculates the result in three passes (see Figure 10).

The signal-to-noise ratio to the resolution of the algorithm can be expressed as:

SNR = 2^2b_v~¹ where b = number of bits, and v = 11 (number of effective radix-2 transforms). The solution for b provides 17 bits of resolution (based on ADC SNR), but since ADC is not the only source of analog signal degradation, 16 bits of resolution in the algorithm should be sufficient to maintain resolution throughout the system.

The VCXO generates the sampling frequency used in the NT part of the system. The control voltage is based on data from the synchronization unit. The clock frequency must be very stable and phase locked to the NU reference clock in order to maintain orthogonality between symbols.

To fully utilize the ADC's dynamic range, a programmable attenuator must be inserted before the ADC. The attenuation level is mainly a function of the cable length and can be determined by the value for timing advance through the system controller.

Attenuation resolution and range, and the relationship between the timing advance value and the attenuation level, must be determined. Equalization and variance values ​​can also be used in the calculations for improved results.

In a DMT system, a very precise synchronization between the transmitter and the receiver is necessary, especially when carrier waves are modulated with large constellations. In the embodiment described herein, a novel frame synchronization method based on correlation properties built into the structure of the received signal is used.

506 640

On the NOW side, a fixed frequency crystal oscillator is used as a reference for generating the sampling clock. On the NT side, a sampling clock is generated by a VCXO (Voltage Controlled Crystal Oscillator = Voltage Controlled Crystal Oscillator) which is locked in phase to the oscillator on the NOW side. The VCXO is initially controlled by frame synchronization value calculation (frame timing estimate). However, the resolution of the frame synchronization value calculation is not sufficient in the present application. Therefore, after a lock-in sequence, a dedicated pilot carrier is used to achieve a very high accuracy of the sampling clock synchronization.

Depending on the long symbol duration in a DMT system, interference between symbols caused by channel time dispersion can be eliminated by using a guard interval as a prefix to each frame in the time domain. In order to maintain the orthogonality of the frames, the content of each prefix is ​​a copy of the last part of the following frame, which makes the frames appear to be partially cyclic.

The synchronization method used to estimate frame synchronization uses the high correlation that exists between a prefix and the corresponding part of a frame. By continuously correlating samples of the received signal, separated in time by the (known) frame length, the passing of a protection interval will cause a peak in the correlation estimate. Therefore, these peaks will have a known synchronization relationship with the frames and can be used to create a frame start signal. The principle is shown in Figure 11.

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The correlator and peak time estimator use a system clock generated by a VCXO. This clock is divided by (divided by) the total number of samples in a signal interval (a cyclic prefix and a frame), to create a signal with the same period as the correlation peaks. The frame time deviation between these two signals is used as input to a feed-back controller that adjusts the VCXO frequency to the correct sampling frequency. However, the phase of this sampling clock is not precise enough to be used in a DMT system. Therefore, the frame synchronization value calculation is mainly used for a lock-in operation. It is also used to monitor frame synchronization to detect major deviations that will make a resynchronization necessary.

The correlation of the received data is calculated continuously. The time difference between the two signals is achieved by using a digital delay line on a frame length. The output of the delay line is multiplied by the non-delayed signal and integrated (accumulated) over an interval corresponding to the length of the cyclic prefix. The output from the integrator is the correlation function's value calculation (estimate).

Since only the synchronization information of the correlation value calculation is used, a simplified estimator is used which only uses the symbol (sign) of the input data. This hardware implementation has a greatly reduced complexity compared to using the full sample word length.

Computer simulations have shown that the use of synchronous averaging of a plurality of (several) signal ranges reduces the variance of the frame synchronization value calculation. Depending on it

506 640 reduced data word length used in the multiplier portion of the correlator, it is possible to implement such averaging function immediately after the multiplier.

A block diagram showing the implementation of the correlator is shown in Figure 12. The incoming signal X (k) passes through a delay with N = 1024, ie a frame, and to a conjugator. The output from the delay and the conjugator is then multiplied to produce a signal Y (k) which goes to an average value generator. The output of the mean value generator, Z (k) goes to a subtractor from which Z (k) delayed by L = 128 is subtracted. This gives a signal W (k) which goes to an accumulator which gives an output C (k).

The details of the averaging portion of the correlator are shown in Figure 13. The averaging comprises a series of delay elements combined with adder, as shown. The output signal can be expressed as:

Z (k) = Σ Y (k-iM) i = 0 where Y (k) is the input signal and Z (k) is the output signal.

In order to make the mean value synchronous with the frame structure of the signal, the delays are equal to the signal interval.

A detector for finding the position of the maximum size of the correlation function value calculation is shown in Figure 14. It is implemented using a register (# 1) for the senasue max value and a comparator. The register content and the correlation size are compared, and each time a value greater than the register content is found, the new value is stored in the register. The current value of a counter that counts sampling intervals

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506 (modulo signal interval), is also passed to a second register (# 2). When an entire signal interval has passed, this second register will contain an index to the maximum value set. found during this interval. This index is stored in a third register (# 3), once per signal interval, and the contents of the first register (1 #) are divided by two (using shift).

The irdex stored in register # 3 is interpreted as the deviation between the counter value and the current synchronization of the input frames. The feedback controller will have the mean of this deviation converge to zero. The counter value can then be used as a pointer to the signal range. The frame synchronization clock is generated using this counter value to indicate the frame start.

Value calculation of the complex representation for pilot carriers. in the frequency plane is performed using the FFT unit ser. is available in the system. The advantage of using this method is that the value calculation will be independent of the varying modulation of other carriers. This is due to the inherent orthogonality between the carriers. In order to achieve a value calculation with acceptable low variance, a certain average value formation is necessary. Dezta is performed using first-order digital IIR filters.

Unfortunately, the value calculation is represented as a complex number in rectangular coordinates, so the argument is not directly available. In the feedback loop, it is necessary to detect (detect) very small argument deviations. Therefore, the resolution of the argument must be high.

The feedback controller will have the pilot carrier argument act converge to zero. One

506 640 approximation of the argument, which is linear only in a small range around zero, is then sufficient to achieve acceptable performance. A useful approximation that is monotonic in almost all four quadrants, and also easy to implement in digital logic, is described by the expression:

A = M. [3 {C} - (l-sgn91 {C}) .K. 91 {C}. sgn.3 {C}] where C is the complex pilot carrier value calculation, M is a positive scaling constant, and K is a positive constant affecting the design of the function (here K = 2 is used).

The channel introduces phase shifts on the pilot carrier which can cause misalignment between the frame synchronization of the input signal and the pilot argument zero. To eliminate this problem, the pilot carrier estimator also passes through the frequency domain equalizer. The equalization parameter for this carrier is set under start sequences, when frame synchronization value calculation (frame timing estimate) has converged to its final value.

The choice of pilot carrier will be fixed, but logic for choosing other carrier as a pilot can also be provided.

The feedback loop actually has two controllers, each with its own input signal. The two controller outputs are added and fed via a D / A converter to the VCXO that generates the sampling clock. Both controllers are PI type (Proportional and Integrating).

Figure 15 provides an overview of the signal paths. The received data in the schedule passes through the correlator and peak position estimator to result in the frame clock. The complex pilot carrier in the frequency plane derived from the equalizer is fed to a pilot argument estimator.

506 640 whose output is passed to feedback controllers that also receive output from the tcpp estimator. The output from the feedback controllers is then passed to a D / A converter to provide a signal used to control the VCXO.

During the start sequence, only the frame synchronization controller is active. When the frame synchronization has stabilized, the pilot carrier equalization parameter is calculated and set (by the SC). This is done only once, and further updating of this parameter is suppressed. After this adjustment of the equalization parameter, the mean estimator of the argument estimator is given sufficient set time. Finally, the frame synchronization controller is stopped and the pilot argument controller is activated. When the frame synchronization controller is stopped, its last value is locked so that the azz VCXO frequency remains close to its final value.

The pilot carrier is also used to transmit the base synchronization interval synchronization information (BSI). The carrier argument is normally assumed to be constant. A short pattern BPSK is modulated on the carrier using phases 0 and π and leaving the carrier on phase 0 for the remainder of the BSI interval. If this pattern is only a fraction (&lt;1%; of the BSI interval), the perturbation of the pilot carrier argument value calculation is negligible. A correlator is used to detect the pattern and provide the synchronization signal for BSI.

The System Controller (SC) must have read access, for detection of synchronization lock and for monitoring reasons, to registers holding the estimator for frame time deviation and the pilot argument approximation.

506 640

To handle the initial equalization of the pilot carrier, it is necessary for the SC to read the average complex representation of the carrier and write to the equalization parameter memory.

An offset register to determine the relative synchronization between the input frames and the frame start signal is necessary and must be writable from the SC. This is used on the NT page.

The detected BSI event signals, for both reception and transmission, must be connected to the SC as interrupt inputs.

Alternatively, the pilot carrier can be recovered from the signal in the schedule, using a bandpass filter, and used directly for phase locking of a sampling clock oscillator. The frequency scheduling method described herein has the advantage that the pilot carrier estimator is independent of the modulation of the other carriers, depending on the orthogonal line. Another frame synchronization method would depend on introducing a known pattern into certain frames. This would reduce system capacity.

The frame length and length of the cyclic prefixes are fixed in the embodiment described herein. The method described above is designed to operate in a feedback loop with a VCXO. In a unit using a particular sampling clock oscillator, the performance of the frame synchronization estimator needs to be slightly modified. It is important that the VCXO has very low phase interference, since the feedback loop is too slow to compensate for such interference.

A discrete mulititon system (DMT) modulates N complex data symbols on N carriers (here we use N = 1024 carriers). This mapping is calculated as a reverse (inverse) discrete Fourir transform using Inverse

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Fast Fourier Transform (IFFT). In the receiver, the N carriers are demodulated by an FFT.

In the modem described herein, FFT and IFFT are performed by the same unit, using the same base (radix) 16, or 32 cores, in different phases. This process is shown schematically in Figure 16.

The main operation is divided into frames with lengths of 2048 real, or 1024 complex values. For each frame, this unit performs an FFT, IFFT, scaling, descaling, and adding cyclic prefix.

The FFT and the IFFT calculate 2048 points of real FFTs and work with a minimum of 16 bits of arithmetic.

For the network terminal side, (NT), there is a requirement for synchronization between the input frame start and the IFFT output start. (A synchronization between the upstream and downstream carriers). The transmitter must be able to start transmitting a frame before it starts to receive a frame, so-called timing advance.

A scaling should be provided before IFFT. This scaling is a multiplication between the real coefficients stored in this unit, and the input values ​​from the symbol mapper (SM). The coefficients are 16 bits each.

The coefficient memory consists of two banks of the same size (16x1024 bit). One bank is used while the other is updated. Switching is made possible by a PCI command and executed at the next BSI.

After the FFT, a rescaling must be performed before the data is transmitted for smoothing and symbol detection. This rescaling is a multiplication with the inverse value of the scaling values. The coefficients are represented by 16 bits.

506 640

An exponent (resulting in a post shift) of 4 bits may also be needed to maintain precision.

The coefficient memory consists of two banks of the same size ((16 + 4) Χ1024 bit). One bank is used while the other is updated. Switching is made possible through a PCI command and executed at the next BSI.

At the beginning of each frame, a cyclic prefix is ​​added. This process is shown schematically in Figure 17. The insertion of a cyclic prefix eliminates interference between symbols (ISI), and preserves the orthogonality between the tones, resulting in a simple input / output ratio that allows each carrier to be considered as a separate channel. . This cyclic prefix consists of a repetition of the last part of the frame.

Assuming the timing advance is used and the maximum cable length is 1300 m, a cyclic prefix of 12 = samples will be needed. Thus, the output of each frame will be sample:

1920, 1921,...,2046, 2047, 0,1,2, ... 2046, 2047

For each of the above components, there is a FIFO as an interface to the external world with FFT / IFFT input and output memories. Thus, there are a total of 4 FIFOs.

It is recommended that the FIFOs with interfaces to the analog side have a size of 384 words (16 bits) and the FIFOs that interface with Tl chips have a size of 448 words (32 bits).

Another DMT technology that does not use Fourir transform is Discrete Wavelet Multi-tone Transform (DWMT). This method was submitted to the ADSL standardization committee, which rejected it.

506 640

The precision required in this technique depends on the required dynamic range, which in turn is determined by the analog components (especially DAC). The FIFO size will depend on clock speed differences and the amount of timing advance used. The use of clipping is a compromise between dynamic range (quantization disturbances) and clipping disturbances.

Channel value calculation is performed using a decision-directed method, since all data frames are then used for updating the channel model. Known data frames are necessary only at startup. In some circumstances, interference on the channel can be calculated using all data frames. This is important for early detection of changes in channel transmission quality.

The basic principle of decision directed value calculation is that differences between received data and known transmitted data are used for updating a channel model. At some stage of this process, channel models are accurate enough to be used to equalize the received data, and the detector will produce the correct data. This output can then be used in the same way as the known data for further updating the channel model. Therefore, the predefined data frames are no longer necessary and random (random) data transmitted through the channel is used instead.

By using data taken after the equalizer as input, and data after the detector as the second input, an adaptive updating algorithm can be designed. It modifies the equalization parameters in small increments in such a way that the equalizer converges on a model of the inverse (inverse) channel. Figure 18 shows a block diagram of such a system. Input in the frequency plane enters the equalizer and is multiplied by the output of an equalization parameter update unit, EQ. The

506 The 640 resultant signal, U, then goes to a detector (quantizer) whose output is Y. Y then goes to a symbol decoder that produces a decoded data bit stream. U and Y also go to an input (input) of the equalization parameter update unit and to a variance estimator. The output of the variance estimator is W.

An adaptive algorithm for calculating the equalization parameters (EQ), which uses the equalized data (U) and the quantized data (Y) as input, is described by the following equation:

EQx., - EQ_k ___ .EQ_k.U_k'. &lt;Y_k- U_k) | uk |^! where µ is a positive constant (µ &lt;&lt; 1), which affects adaptation dynamics. A smaller value gives a slower adjustment than a larger value, but it also gives a greater insensitivity when there is interference with the input signals.

For implementation reasons, the division shown in the equation should be avoided. The expression µ / IU_k |² has a too large dynamic range to be replaced by a constant. However, it is possible to quantify this expression in a logarithmic manner as shown below:

integer (2nd log IUkI) + integer (log µ)

2

The exponent of the above expression can be produced using the absolute value of U_k as input in a binary priority encoder and exchanges (negating) characters on the output. Since the expression is an integer power of two, the multiplication is implemented in the algorithm by means of a barrel shifter.

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The interference variance on each of the carriers is calculated using the standard method of integrating the squared deviations from a mean. In this case, each quantized value, Y, is used as the mean of the range of data values, U, which is quantized to this Y. This method assumes that the symbol error rate is low enough for each data value to be associated with the correct mean. However, if suitable constellations are selected for the different carriers, this condition is met.

Figure 18 shows the variance estimator as part of the system. The algorithm used for the calculation of values ​​is described by the following equation:

w_{k + 1} = (ι-ε). W_k+ S. | Y_k-Uj²

The integration here is replaced by an exponentially weighted average value filter. The parameter ε is a small, positive constant (ε &lt;&lt; 1) that affects the dynamic properties of the filter. This is not a critical parameter, and choosing ε from integer potentials of two will suffice.

If a value of ε is chosen that gives a good variance value calculator (estimator), the algorithm will not be able to detect sudden changes in the interference level. Therefore, a separate algorithm that works in parallel with the variance estimator may be necessary for this task.

The System Controller must have both read and write access to the memory that holds the equalization parameters. Initialization of the parameters is necessary at startup. Monitoring of the parameters is also necessary to detect when they have leveled sufficiently close to their final values.

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The channel variance memory must be available for

The system controller read operations. Initializing this memory to all zeros can be linked to a system reset.

The parameters that affect the dynamics of the estimators must be available for writing from the System Controller.

The method described here requires a specific startup sequence, both for channel and interference value calculation. During normal execution, it is dependent on a suitable choice of bit loading which gives a sufficiently low symbol error rate.

It is important that the equalization parameters are initialized to unit value at the beginning of the start sequence, as the input to the update algorithm passes through the equalizer. The update algorithm is sensitive to scaling changes in the data path.

Any change in scaling in the transmitter must be compensated in the receiver. This also requires special care when using the analog gain control (gain control) on the input side of the receiver.

The symbol encoder maps a number of bits to a complex number (I, Q) that indirectly determines the phase and amplitude of a carrier. The mapping of all values ​​of a certain bit length is called a constellation, and is shown in Figure 19. The detection is the inverse function, ie from a complex value, the value of the bits transmitted on the carrier is determined. The number of bits transmitted on a particular carrier is determined by the bit load factor for it.

The design of a specific constellation is aimed at allowing each point to be moved as far as

506 640 possible from all other points. At the same time, the average energy should be as low as possible. Another restriction is that the mapping and detection units should be as simple as possible. However, the decision on which constellation to use will affect not only the symbol mapping and detection units, but also the bit-loading and possibly the adaptive equalizer.

For a given carrier, the encoder selects an odd integer point (I, Q) from the square grid constellation based on the b bits (v_b._LR v_b._{2 z}^v_xv₂) · For the sake of simplicity in the description, these b-bits are identified by an integer label whose binary representation is (v_b._xi v_b_₂v ....._xv₂). For example, for b = 2, the four constellation points 0, 1, 2, 3 mcc corresponding (v_xv₂) = (0.0), (0.1), (1.0), (1.1), respectively.

For even values ​​of b, the integer values ​​of I and Q are determined for the constellation point (I, Q) of the b-bikes (v_b._x v_b_ ₂v ....._xv₂) as follows. Divide V into VI = (v_b._xi^vb-3, v_x) and VQ = (v_b.₂_ v_b._4j v₀). Then apply the reverse Gray code to VI and VQ. This gives I and Q then I = 2Gray (VI) + 1, and Q = 2Gray (VQ) + 1.

Figure 19 shows how the binary pattern of V folders on I and Q when b = 6.

Before these values ​​are transmitted to the IFFT, they are normalized by shifting so that msb of these numbers becomes msb on the output (16 - [b / 2] steps remaining).

For a given carrier, the decoder uses a reference point (I, Q) to determine the b bits (v_b._Xi^vb-2,,^vin,^v2 ^ For the sake of simplicity in the description, these b-bits are identified by one

506 640 integer label whose binary representation is (v ^ v_b_₂ ,^V1,^V2) ·

It is assumed that the values ​​of I and Q are limited by saturation to the range (X, Y). To determine V, Gray encodes the values ​​I = (i₁₅,in₁₄..... II in₀) &gt; ^and Q = (Qis.qn ..... 3ι, 3ο)&gt; and then combined to V as V = (gii_S, GQ₁₅, g_14/GQ_14/.....), where the upper b bits are valid.

The number of bits each carrier transmits depends on their respective signal / noise ratio (SNR).

The signal-to-noise ratio is calculated for each carrier in the receiver. Based on the signal-to-noise ratio, bit-load factors for each carrier are calculated. Thus, the number of bits each carrier wave must transmit per transmitted symbol is determined. These bit load factors are calculated in an initial training session and can be updated if required. The MUSIC system uses 2-dimensional Quadrature Amplitude Modulation (QAM) on each carrier, with bit loading factors varying from 0-12 bits.

The number of bits transmitted on each carrier can be expressed by ·.

βί = bi + log₂ (L) = log₂ (1 + ^snr1 ) (1) r

where Γ, the SNR gap, is due to modulation, possible coding and a system margin, and L is the constellation expansion due to the extra bits needed for coding.

Use of QAM constellations and some form of coding provides:

[Q¹(Ps / 4)]²

- yd + / margin (dB) (2)

506

640 where P_s is the desired symbol error rate, y_d is the gain of coding in the system, Yn,_arginine is the system margin. The system margin is a factor used to compensate for non-modeled losses, impulse disturbances, etc. Equation (1) gives a bit-loading factor with infinite granularity.

The bit loading factors are rounded to give the supported factors (0-12 bits).

The rounding procedure will reduce the performance of the DMT system. If the energy distribution is allowed to vary, energy charge factors can be calculated for each carrier. This provides the ability to tune the energy so that (1) results in a bit charge factor supported by the system. Reconciliation provides:

(Βί-1) Γ

Ei ₌ 2 ^SNRi (3)

However, this can result in very large differences between carrier energies. In an environment with several different DMT systems, strange effects can occur if the different energies are allowed to vary too much.

The remote interrogation (FEXT) will vary considerably in such an environment, and some DMT systems may have the full cable capacity. To prevent these effects, only small changes in carrier energy can be allowed. Another limiting factor is the maximum energy allowed on each carrier.

The input to the bit-loading algorithm will depend on the selected frequency domain equalizer. If an adaptive DFE is used, SNR is obtained by:

SNR_in= W_in (4)

506 640 where W_± is the value-calculated interference variance described above.

For each carrier, a bit charge factor and an energy charge factor are calculated. The bit-loading factors can be represented by 3 bits, but to prepare the system for odd bit-loading factors, 4 bits are recommended. For energy charging, n bit is used to give 2ⁿ - 1 possible factors.

The implementation of the calculations of bit charge and energy charge factors can be done in four steps as shown in Figure 20. To achieve a given bit rate, an required SNR can be calculated and the system margin adjusted to achieve the desired bit rate. The process illustrated in Figure 20 includes the following steps:

First, SNR is calculated using (4).

In the second step, four comparisons are performed, that is, one for each of the four bits representing the bit-loading factor. The thresholds depend on L and Γ, and can be calculated. The first comparison determines if the bit-loading factor is greater than 7, and the result of this comparison controls the first of the four bits representing the bit-loading factor; it also controls the threshold for the next comparison. Similarly, this comparison controls the second bit and threshold for the next comparison. After the four comparisons, the bit-loading factor is determined.

The third step is to calculate the scaling factor for the transmitted energy so that the channel is used more efficiently. The energy is scaled according to equation (3).

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Finally, the scaling factor is quantized to n bit.

It should be noted that in order to implement a system with constant energy charge, only the first two steps are necessary.

The energy charge and shifting performed for normalization in the symbol mapping determines the scaling and scaling factors sent to the IFFT / FFT processor.

The purpose of channel coding is to reduce the bit error rate. The type of coding that should be used depends on the error pattern characteristic. Expected sources of error include random noise (which induces random bit errors), impulse disturbances (which induce error bursts) and clipping (which induces error bursts).

Faults caused by impulse interference mainly affect one or two bits per carrier. The probability of a single bit error on a carrier is always higher than the probability of 2 bit errors, which in turn is higher than the probability of 3 bit errors, and so on. This depends on the way in which the bits in the symbol are encoded (ie Gray encoding).

All coding depends on a synchronization to determine the start bit of the code words and / or interleaving blocks. In a system such as the MUSIC modem, simple dead reckoning will be sufficient, since a data flow slip error can never occur without loss of frame synchronization, or error setting during bit loading. These errors require a partial, or complete, system startup.

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The channel coding will also include interleaving to increase the ability to correct scour errors.

Interleaving should be as deep as possible to achieve optimum performance. The limiting factor in depth is the time delay that is introduced into the system.

The difference between time and frequency interleaving is of little significance since the coding and interleaving function is not sensitive to frame boundaries.

Reed-Solomon codes have the disadvantage that they are mainly scrub error correction over a small number of bits (usually eight), a so-called symbol. Scour errors from pulse disturbances generally introduce a single-bit error in some of the symbols. To take advantage of Reed Solomon codes, the most error prone bits must be concentrated on one, or a few, of the Reed-Solomon symbols.

The system margin as such (in itself) is a type of coding that uses each carrier's margin as the redundancy of the symbol. This redundancy per symbol should be converted to a shared redundancy that can be used by a larger number of symbols to handle scour errors. The higher coding rate this introduces can be used by certain types of convolutional codes.

The use of a convolutional code combined with soft information is therefore the optimal solution for a system with MUSIC channel characteristics.

The folding code should be combined with interleaving.

It is possible to use a top-level Reed-Solomon code, or some other scrubber-correction code, e.g. Firecodes, to detect / correct the remaining bit errors.

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This is especially useful as these errors occur in bursts as a result of the decoding of the convolution code.

When transmitting traffic using multi-carrier technology, such as orthogonal frequency division multiplex (OFDM), the same number of bits is transmitted on all subcarriers. This is done despite the fact that it is theoretically possible to transmit several bits if the channel is known, which is the case, for example, when transmitting traffic on copper conductors. Therefore, it has been considered desirable to provide, in a multi-carrier transmission system, a method for transmitting different number of bits per channel, or subcarrier.

Currently, bit loading is used to vary the number of bits per channel, or subcarrier, in so-called discrete multitone and OFDM transmission, both of which use multicarrier technology on known channels. Thus, such systems provide a method for transmitting the correct number of (real capacity) bits per channel, or sub carrier. However, while this method transmits a varying number of bits per channel, or subcarrier, it would be advantageous to transmit a defined number of bits per channel, or subcarrier, but with varying user data content.

In a multi-carrier transmission system, channel information is transmitted between two transceivers using a plurality of subchannels modulated with symbols, each representing a plurality of bits.

In the method of the present invention for transmitting channel information in a multi-carrier transmission system, such as the MUSIC system described herein, a defined maximum value for the number of bits for each symbol, as well as the bit capacity per symbol for each of the plurality of carriers, is determined. If it is determined

506 640 that some of the subcarriers have a capacity less than the defined maximum value, then the number of bits represented by a symbol transmitted over these subcarriers is increased to the defined maximum value by adding channel coding bits.

Thus, the number of bits represented by the symbols used to modulate the plurality of subcarriers is set to a defined maximum value, and channel-coded bits are used to increase the number of bits represented by a symbol transmitted over these subcarriers, which have a capacity, which is lower than the defined maximum value.

According to the present invention, the maximum value of the number of bits for each symbol is determined on the basis of the bit capacity of the subcarrier found to have the highest theoretical bit capacity. In practice, the defined maximum value for the number of bits will be at least as large as the bit capacity of the subcarrier having the highest theoretical bit capacity. In other words, the defined maximum value may be as large as, or greater than, the theoretical bit capacity of the best of the subcarriers.

Thus, in practice, the bit capacity of a subcarrier is measured, or calculated, and, for those subcarriers which do not have sufficient real capacity, a number of channel coding bits which increase the total bit number represented by a symbol transmitted over the affected subcarriers is introduced. defined maximum number of bits.

For example, if it is determined that the defined (maximum) number of bits for each symbol should be 16, and the number of bits represented by a symbol transmitted over

506

640 if a certain subcarrier, by value calculation or measurement, is found to be only 4 bits, then the number of bits represented by the symbol will, according to the present invention, be increased by the addition of 12 channel coding bits. However, if the number of bits represented by a symbol transmitted over another subcarrier is found to be 10 bits, then it will only be necessary to add 6 channel coding bits.

It is therefore apparent from the foregoing description that, according to the present invention:

a multi-carrier transmission system is arranged to transmit channel information between two transceivers using a plurality of carrier waves modulated by symbols, each representing a plurality of bits;

a defined maximum value is determined for the number of bic for each symbol; and the system is adapted to:

determining the bit capacity per symbol for each of the plurality of subcarriers; and increasing the number of bits represented by a symbol transmitted over those of the subcarriers having a capacity less than the defined maximum value to the defined maximum value by adding channel coding bits.

Therefore, the addition of channel coding bits to increase the number of bits represented by a symbol will

506 640 provide a multi-coded, multi-carrier transmission system.

As stated above, the purpose of channel coding is to reduce the bit error rate, and the type of coding will depend on the error pattern characteristic. Thus, the channel coding bits that are added to increase the number represented by a symbol to the defined maximum value will effect a decrease in bit error rate in a manner known to those of skill in the art. In addition, the channel coding bits are basically redundant bits that are added to the channel information transmitted between the two transceivers, in a controlled manner, to signal the validity of the information at the receiver.

Expected sources of error, as noted above, include random noise (which induces random bit errors), pulse disturbances (which induce error bursts), and clipping (which induces error bursts).

It will be readily apparent from the foregoing description that the method of the present invention can be used by any modem that transmits data on channels with relatively static channel properties and which uses multi-carrier transmission systems, or similar techniques, which distribute information on a number of subcarriers.

The System Controller is based on a micro controller, or signal processor, depending on capacity requirements. For the MUSIC system, the processor can be placed externally. A PCI bus interface is used to connect the System Controller and the various ASICs that make up the modem. The function of the System Controller is schematically shown in Figure 21, which shows the paths for interaction over a PCI bus, between the System Controller and the FFT chip, the data mapping system.

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506 and the detection chip, and the coding and decoding chip. Functions performed by the system controller are:

control channel signaling management;

calculation of bit charge and energy charge factors;

updating real-time system parameters; and system monitoring.

The System Controller, which is used for the modem described here, is programmable and accessible through an on-board JTAG interface.

As shown in Figure 22, in a modem context with the modem described herein, the two data paths operate independently on the same physical copper cable, terminating in the network (plant) unit (NU) on the network side, and the network termination (NT) on the user side. Both the transmitter Tx and the receiver Rx are controlled by the System Controller.

The System Controller calculates and updates, after start-up, bit-charging and energy-charging factors. This update must be done simultaneously starting from the same frame, on both the transmitter and receiver side.

The calculations are made and the update is initiated on the receiving page. The control channel, combined with the BSI clock, is used to secure the synchronization of the update.

The System Controller also supervises the system. Indications for system errors include starting the control channel to indicate errors, or receiving too many errors from the decoding channel unit.

<img file="SE506640C2_D0019.tif" />

initiate reboot

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levels;

506 640 for example, go back to idle mode, or do a full boot.

The control channel is a selected carrier used only for signaling between the two modems. The constellation on the carrier is initially 4 QAM and the data rate is about 16 kbit / s. The bit load can be changed to any other constellation to increase the data rate.

The protocol on the control channel is based in part on HDLC for the physical layer. This means that the messages are packaged as a number of octets using flag sequence and bit-stuffing. A 16-bit frame check sequence guarantees that every message is received correctly.

Flag-sequence, bit-stuffing and frame check sequence are handled in the mapping and detection chip hardware. The contents of the messages are handled by the System Controller.

The maximum message length is limited to 64 octets depending on the size of the buffers on the mapping and detection chip.

Higher level protocols can be partially based on CCITT

Q.921 recommendations.

In MUSIC modem SC, several different vectors are handled; these are shown schematically in Figure 23.

For the transmitter part there is the bit charge and energy scaling vector. Corresponding on the recipient side is the bit-load, re-scale and equalization vector.

As previously described, the pilot carrier delivers a transmitter / receiver synchronization by transmitting and detecting a specific pattern. This clock is used by the system to synchronize changes in the transmitter and receiver vectors.

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The time between pilot synchronization patterns is called Base Synchronization Interval (BSI) and is determined by the system response time, as shown in Figure 24.

This BSI is hardware dependent. Its length will not change, as the response time always remains the same.

When the system is running, synchronization will exist between the uplink transmitter and the receiver, through base sync interval uplink (BSI-U) and base sync interval downlink (BSI-D), see Figure 25. These BSIs are of exactly the same length but are shifted a half BSI interval.

The SC at the NOW, or the NT, will receive interruptions for both BSI-U and BSI-D.

For the NOW, there will be a broadcast BSI-Dav break and a receive BSI-U break. By switching BSI-U with BSI / 2, the SC charge will be better distributed over the BSI period.

The bit-loading vector provides the system with the modulation pattern for each carrier. This is a vector that needs to be kept and updated at exactly the same time on the transmitter and receiver side to provide a flawless connection. By using the BSI, the vector changes synchronously on the receiver and transmitter side.

The bit-loading factors, constellations used on each carrier, are handled by two memories for reception and two memories for transmission on the mapping and detection chip. Each of the four memories contains a 4-bit word for each carrier (1024x4).

The System Controller points out which of the memories will be used to transmit and which ones will be used to receive after the start from the next BSI interval.

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The bit-loading factor may have values ​​between 0 and 12, where 0 indicates an unused carrier; 1-12 indicates the number of bits in the constellation (eg 2 for 4QAM, 4 for 16QAM, 10 for 1024 QAM).

The energy vector keeps information on how the waves are scaled / scaled on energy. This is a vector that needs to be updated synchronously, otherwise it will generate a distorted channel value calculation and bit error. The scaling vector will also be used as a pattern (mask) for canceled carriers.

Scaling of the different carrier waves on the transmitter side is handled by a memory area on the FFT chip. The memory consists of a 16-bit word for each carrier (1024 x 16). These values ​​are multiplied by the vector for each carrier in the frequency domain (I and Q are multiplied by the value separately).

The memory is doubled to ensure a synchronous update. The System Controller points out which of the two memories will be used from the start of the next BSI interval.

A corresponding memory (duplicated) is implemented on the receiver side to rescale the carriers before symbol detection. If these memories contain a complex value for each carrier (32 bits / carrier), only the value will be used for rescaling.

The scaling and scaling factors have values ​​between 0.5 and 2.0. The value 0 is used for carrier cancellation.

The equalization vector is used to equalize the received frame according to the channel characteristic. This vector is periodically updated, regardless of the other side, when the channel value calculation is calculated by the receiver.

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Depending on the carrier's specific transmission characteristics, it will be assigned to one of the following modes (modes):

ordinary carrier - this carrier transmits data according to the calculated bit-load value and is transmitter-scaled and receiver-scaled;

canceled carrier - no energy is transmitted at this frequency and the scaling vector is therefore set to zero; or poor carrier; SNR is too low to transmit any data and therefore the bit load is set to zero.

In carrier mode 1 (CM1), the system operates normally. The receiver continuously smooths the channel.

Equalization changes are made for each new value calculation. Using the characteristic, the SC calculates the optimum bit-loading factor. This value is transmitted to the transmitter using CCH, and a synchronous change is performed.

In carrier mode 2 (CM2), the energy scaling / rescaling value is set to 0 to disable all out / in energy. The value of the bit-load vector is also set to zero to indicate that the carrier is disabled. For this carrier, no channel value calculation can be made.

In carrier mode 3 (CM3), the receiver has calculated a zero for the bit-loading factor. On the transmitter side, this means that no daca can be transmitted, and therefore no channel value calculation can be done at the receiver. To avoid this, the corresponding carrier value is transmitted from the synchronization frame and makes it possible to perform a channel value calculation at the receiver. The scaling / scaling value can be used to reduce the output power. Carrier scales are presented in Table 4.

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The basic functionality of the startup sequence in the system, ie cold and warm boot (boot), will now be processed.

Initially, the power supply in the system is considered to be turned off at one or both ends, NOW and NT. This occurs if the power supply is lost due to a power failure, or by unplugging the NT equipment. The most important thing to take into account at startup is, in addition to the connectivity function, to minimize the interference level of other modems that utilize neighboring (neighboring) cables.

The various frame types used by the system are discussed below.

1st The synchronization frame is used for channel value calculation. This frame maintains a definite modulation pattern for each carrier and thus enables simple channel value calculation. By having the modulation pattern described by a random sequence, the cross-correlation within the frame is kept low, so that the frame correlation used for synchronization is improved.

2nd Data frame 1, (DF1), transmits random data on all carriers except for four predefined carriers transmitting the control channel (CCH) in parallel. It is used at start-up when the CCH carrier is undetermined and allows the receiver to select the least disturbed carrier, thereby guaranteeing the CCH connection.

3rd Data frame 2 (DF2) transmits random data on all carriers except you, which carry the control channel (CCH). It is used when the CCH carrier has been determined, and the bit-charging facu- lars are not yet set.

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4th Data frame 3 (DF3) transmits data and uses the bit-loading function to maximize bandwidth.

A carrier is always dedicated for the control channel (CCH).

The system uses a special frame sequence, shown in Figure 26, at start-up and in idle mode, called start-up sequence (SUS = Start-Up Sequence).

The SUS can be composed using the various data frames, DF1 and DF2, which are hence called SUSI and SUS2. In the SUS frame sequence, the synchronization frames are used for channel value calculation.

After startup, the synchronization frames are replaced with data frames, as shown in Figure 27, and the channel value calculation process shifts from the use of synchronization frames to the use of the data frame. The type of data frame for this sequence is DF3.

At system startup, neither side transmits the modem,

NOW and NT, some energy over the copper pair.

The default setting for each page at this stage is to power the receiver, leaving the transmitter dead.

The receiver, on each side, attempts to perform a frame correlation to detect a frame start. This correlation is run through a threshold function that gives the receiver a distinct indication of when the other side starts transmitting. It is this indication that serves as a wake-up signal.

The wake-up signal is used only by the NT side. If the startup decision is made on the NOW page, the system goes directly to the set-up sequence described below.

This part of the startup procedure is subjected to time out if a transition to the set sequence is not detected.

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The basic wake-up signaling for the modem is shown in Figure 28. Initially, both modems search for frame correlation. One of the modems, to the right in Figure 28, sends a wake-up signal in the form of a SUSI. The second modem detects frame correlation and starts the set sequence described below.

When the wake-up state is passed, the web page (NOW) initiates the set sequence.

The set-up sequence will now be processed. This set sequence starts after the network side detects a wake-up signal, or the network initiates the set.

The first step in the set sequence is shown in Figure 29. In this phase, NOW starts to send the SUS115 pattern. NOW repeatedly sends a timing advance (TA) setting, with TA = 0, on the CCH. The master clock in the system is now the NOW transmitter frame and the sample clock in NOW. The pilot is continuously transmitted.

The NT receiver side, which looks for frame correlation, detects frames and can retrieve the frame and sample clock. It now starts the channel value calculation which at the current speed of synchronization frames makes an accurate value calculation within 300 ms. Using this value calculation, the receiver starts polling the predefined CCH carriers and, upon message receive, selects this carrier for the CCH. The NT transmitter now starts with TA = 0 for local synchronization and sends receipt (acc.) To the CCH carrier for each received TA selection message, repeating the received TA value. It also shifts the outgoing pilot with BSI / 2 from the incoming pilot so that the SC charge is distributed over time. When the NO now detects the frame correlation, the transition to step 2 of the set sequence is made.

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Thus, step 1 of the set sequence begins with the transmitter, in the network device modem, transmitting a SUSI and a TA message with TA = 0 at periodic intervals. Upon receipt of this, the receiver in the terminal modem will:

perform frame correlation and recover frame clock;

begin FFT treatment;

enable pilot decoding;

recover BSI.-n;

enable channel value calculation;

selecting a CCH; and decode the TA selection message.

The transmitter in the terminal unit then sends a receipt (acc.), SUSI, a TA = 0 message and a pilot alternated with BSI / 2. The receiver in the network unit is waiting for frame correlation.

Step 2 of the set sequence, see Figure 30, starts with the NOW page now calculating a timing advance value (TA). The CCH message is changed to the new, corrected TA value.

When the NT page receives the new TA value, it changes the local synchronization and continues to send the acknowledgment message, with a new TA value, for each TA selection message.

In the NU receiver, the frame clock is lost, as the NT transmitter changes (changing) frame clock, and the unit needs to re-correlate. After the frame clock is recovered, the CCH is decoded and, upon acknowledgment detection, containing the new TA value, terminates

506 640 the system TA message and goes to the third stage of the set sequence.

Thus, step 2 of the set sequence starts with the transmitter in the network unit, NOW, sending a TA message containing the correct TA, say X, together with a SUSI, in response to the SUSI and the TA = 0 message being sent from the transmitter terminal .

Terminal Unit, NT:

receives the new TA message;

- corrects the outgoing frame clock; and sends a receipt for SUSI and TA = X.

The network unit, NOW:

performs frame correlation;

recovers the frame clock;

- starts FFT data processing;

enables pilot decoding;

recovers the BSI;

enables channel value calculation;

chooses a CCH; and

- decodes the message.

The last set sequence, step 3, see Figure

31, handles the CCH selection for uplink and downlink. For the uplink, the NU receiver has selected the most suitable carrier and sends the ect CCH message containing this choice to

NT side. The message is transmitted repeatedly until it receives a kvicto (aka).

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On the NT side, the receiver decodes the CCH message and terminates the SUSI and sends a SUS2, that is, terminates parallel CCH transmission by transmitting only the CCH on the selected carrier.

The uplink CCH carrier has now been configured. For the downlink, the same step is performed in parallel, initiated through the NT page after receiving the first CCH selection message from NU.

Thus, in step 3, the network unit will:

transmit the selected uplink CCH;

wait for a receipt; and exit the CCH message.

The terminal device:

receives the CCH selection for the uplink;

terminates SUSI;

starts SUS2; and acknowledge each CCH selection.

The power supply:

receives the CCH choice for the downlink;

terminates SUSI;

starts SUS2; and

- acknowledge each CCH selection.

The terminal device:

sends the selected downlink CCH;

506 640 waiting for a receipt;

ends the CCH message.

Once these steps have been taken, the modem has reached idle mode, sending SUS2. With the use of CCH, the bit-loading factors can now be changed according to channel characteristics and DAS transmission is started.

The VDSL modem may have interfaces to different network elements, depending on the physical location of the modem, ie in the space for access nodes or in customer premises. In customer premises, the VDSL modem can interface with an active network termination equipment. At the access node, the VDSL modem will interface with an access-specific interface, see Figure 32, which shows a logical view of the network elements that interface with the VDSL modem.

The VDSL modem can be physically integrated with the network termination equipment, and the VDSL modem at the access node can physically be located in the cabinet in which the access node is located.

The NT (interface A1) and the access node (interface A2) require a layer 1 frame format of the VDSL modem. Integrated in the layer 1 frame, apart from the frame head and payload, there are a number of information fields for handling and control information. These management and control fields include various alarm indicators, such as SDH alarms, e.g. AIS (valid only if SDH is taken all the way to customer premises) measurements of bit error rate for performance monitoring, indications of whether synchronization is poor, or lost, equipment management alarm for power loss and high temperature, etc. The management fields also include activation of various loop tests, for operation and maintenance purposes.

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TABLE 1

System parameters for the overall system

<td>Orthogonality between modems</td><td>No</td>

<td>duplex method</td><td>Separate bands</td>

<td>Frequency gap between up / down data flow</td><td>Depending on the duplex filter characteristic</td>

<td>net bit rate, - upstream - downstream</td><td>2 Mbit / s 13 or 26 Mbit / s</td>

<td>Bruttobithasuighet, - upstream - downstream</td><td>Coding Depending Coding Depending</td>

<td>Cable length</td><td>&lt;1300 meters</td>

<td>Cable Bandwidth</td><td>10 MHz</td>

<td>Modulation, single carrier - upstream - downstream</td><td>0-4096 QAM 0-4096 QAM</td>

<td>Number of carriers, total</td><td> 1024</td>

<td>Bandwidth for each carrier</td><td>9, 77 kHz</td>

<td>Cyclic prefix</td><td>128 sample (carrier)</td>

<td>MODULATION</td><td>DMT</td>

<td>Access Technology</td><td>VDSL</td>

<td>signal Power</td><td>-60 dBm / Hz</td>

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<td>BER</td><td> 10'⁷</td>

<td>Interleaving delay</td><td>0.5 ms</td>

<td>System margin</td><td>6 dB</td>

<td>CCH - bandwidth - protocol</td><td>1 carrier, minimum 16 kbit / s HDLC</td>

<td>Sample clk</td><td>20 MHz ± 10ppm</td>

<td>Ram clk</td><td>20 MHz / (2048 + 112) = 9.19 kHz</td>

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TABLE 2

System parameters for the Transmitter

<td>Interleaving - deep - delay</td><td>2 x frames 0.5 ms</td>

<td>DAC resolution</td><td>84 dB</td>

<td>Clipping algorithm (Clipping algorithm)</td><td>No</td>

<td>IFFT</td><td></td>

<td>- type</td><td>Real</td>

<td>- points</td><td> 2048</td>

<td>- resolution</td><td>16 bit</td>

<td>LP filter</td><td>LP 10 MHz</td>

<td>Bitladdning</td><td>Yes, 0, 2, 4, 6, 8, 10, 12 bit</td>

<td>energy charge</td><td>Yes , 4 bit</td>

<td>BSI distance</td><td>1 s</td>

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TABLE 3

System parameters for the Receiver

<td>ADC resolution</td><td>66 dB</td>

<td>FFT</td><td></td>

<td>- type</td><td>Real</td>

<td>- points</td><td> 2048</td>

<td>- resolution</td><td>16 bit</td>

<td>LP filter</td><td>LP 10 MHz</td>

<td>Synchronization - jitter</td><td>&lt;0.5 ns</td>

<td>VCXO</td><td>± 25 ppm, 10ppm / V sensitivity</td>

<td>- DAC</td><td>18 bit, range 0-5 V</td>

<td>- resolution</td><td>1/100 of a sample</td>

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TABLE 4

Bärvågsmodes

<td>Fashion</td><td>Submit</td><td>Bitladdning</td><td>Equalize</td><td>Scaling</td>

<td>CM1</td><td>Data</td><td> 2-12</td><td>Yes</td><td>Yes</td>

<td>CM2</td><td>No</td><td> 0</td><td>No</td><td> 0</td>

<td>CM3</td><td>Sync info</td><td> 0</td><td>Yes, sink</td><td>Yes, low</td>

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