Interface circuit

(54) Designation Channel interface circuit (%) Publications cited: - (57) Summary:

A channel interface circuit (100) is used in a multiprocessor arrangement to provide a fast working interface between a processor (200) and a communication channel (101) connecting all processors (200) to each other. The communication channel (101) transmits data messages which contain a header field indicating source, destination and control information. The channel interface circuit (100) is programmable and is arranged to dynamically transform the header of the data message as it is received and thereby determine whether this data message should be stored in the processor memory (201). When the data message is to be stored, the channel interface circuit (100) immediately converts the header field to a hardware address which is used to activate a special location in the processor memory (201). The data message is then fed (via DMA) to this memory location, and the appropriate buffer displays are reset. Thus, the channel interface circuit performs all data reception operations, including message storage and linking, without the need for the associated processor (200).

DB 603415

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The numbers in parentheses indicate international identification code, INID code.

447 764

The present invention relates to an interface circuit for forming interfaces between, on the one hand, a processor and its associated memory and, on the other hand, a communication channel (101) which transmits data messages, each containing a header field with a destination address and a virtual channel number, wherein the processor contains data, address and control buses.

Previously known interface circuits connecting a processor to a communication channel are used exclusively as buffers. They have the task of storing data messages that appear on the communication channel and generating an interrupt every time a data message is received. The problem with this arrangement is that the processor devotes an unfavorably long real time to serving the interrupts from the interface circuit. A substantial portion of this real-time is required to decode the header of the data message to determine whether the data message is intended for the associated processor and, if so, where in the memory of the processor it is to be stored. Each data message that appears in the communication channel in some communication systems contains a header field that typically contains 14 bytes of information, all of which must be decoded. The decoding of this header field results in a substantial .POOR QUALITY

447 764 amount of real time is needed. Previously known interface circuits are in no way involved in this decoding process. In fact, most known interface circuits have very little built-in intelligence; they only serve as a simple buffer, and so it becomes the processor that must perform both the decoding of the header and the storage of the data message. This has so far not been a significant problem, since the processors are either not real-time limited or also work with batch processing. However, in business communication systems, this real-time uneconomical consumption is a significant obstacle to achieving good system performance.

The problem is solved according to the invention, wherein the interface circuit contains a local bus circuit (DATA) for transmitting data messages; a channel interface circuit which is coupled to both the communication channel and to the local bus circuit (DATA) and which is arranged in response to a data message appearing on the communication channel to deliver the data message portionwise to the local bus circuit (DATA) as received; a pattern comparison circuit which is coupled to the local bus circuit (DATA) and which is arranged to, in response to a data message supplied to the bus circuit to this bus circuit, portion-decode the header field of the data message as it is received and immediately generate a hardware address that identifies the location of the processor - the memory where the data message is to be stored after the header field is closed if the processor is the assigned destination of the data message; driver circuitry connected to the processor address bus and the pattern comparison circuit and arranged in response to the hardware address to immediately supply the hardware address to the processor address bus to activate the identified memory storage location in the associated processor memory; and wherein the driver circuitry is also connected to the local bus circuit (DATA) and the processor data bus and is arranged in response to the hardware address to directly store the data portion of the data message as it is received, while delivering the message from the channel interface circuit to the local DATA circuit , at the enabled memory storage location via the processor database.

The channel interface circuit in question acts as a message processing means which is arranged to constitute a high speed interface between a processor memory and a data com ₃ 447 764 channel of communication. The communication channel forwards data messages that have a header field indicating a source address, a destination address and control information. The channel interface circuit of the invention is programmable and is arranged to receive the dynamic portion of the header message while receiving the data message and thereby determine whether the data message in question should be stored in the processor memory. This determination is completed as soon as the header field is received. If the data message is to be stored, the channel interface from the header field immediately converts to a hardware memory address, which address is used to activate a particular location in the processor memory. The data message of the data message is then fed directly (hereinafter referred to as DMA) to this memory location as it is received, and the appropriate buffer pointer is reset. Only when a complete data message has been received and stored in the processor memory does the channel interface circuit produce a processor interrupt to notify the processor that a complete data message is now stored in its memory. In this way, the channel interface circuit in question fulfills all of the data reception tasks including message storage and linking without the need for the associated processor. This saves processor real-time and increases the speed of efficient data transfer between the communication channel and the processor, as there is no delay for the processor to gain access to each data message, decode the header field and, if the data message is to be received, either store it in its memory or provide address information that identifies the place where the data message is to be stored. Furthermore, because the channel interface circuit in question is programmable and the data messages contain source information, destination information and control information, it can selectively sort data messages from different sources, provide special processing of data messages, and carry out other tasks as will be described hereinafter.

The invention will now be described in more detail in connection with the exemplary embodiment shown in the accompanying drawing with Figures 1-8. Figures 1 and 2 show the channel interface circuit according to the invention. Fig. 3 shows how Figs. 1 and 2 are to be placed in relation to each other. Fig. 4 shows the structure of a typical data message. Figures 5-7 show typical inputs i

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447 764 shows the three direct access memories in the channel interface circuit in question, and FIG. 8 finally shows the channel interface circuit's interconnection with the processor and processor memory.

The channel interface circuit 100 shown in Figures 1 and 2 forms an interface between a communication channel 101 with a typical, generally used processor 200 and processor memory 201 via the address bus, data bus and control bus of processor 200 of Figure 8. It is assumed that communication channel 101 transmits data messages which has a header field indicating source address, destination address and control information. The channel interface circuit 100 checks the communication channel to determine whether any of these data messages are intended for the processor memory 201. In this case, the channel interface circuit 100 stores the received data messages from the communication channel directly in the processor memory 201 without having to process the processor 200 here.

The channel interface circuit 100 in question is connected to the communication channel 101 via the communication channel interface 102 which performs a variety of functions, i.a. clock signal recovery, bit recovery and frame generation. The communication channel interface 102 would be of an embodiment adapted to the signals appearing on the communication channel 101. The communication channel interface 102 would be either a data modem circuit, the communication channel 101 would transmit analog signals, or a digital interface circuit of a type well known to those skilled in the art if digital data would be transmitted on the communication channel 101. In this description, the communication channel 101 is assumed to be a serial data channel and that the messages appearing thereon are received by the communication channel interface 102 one bit at a time. The communication channel interface 102 therefore derives a clock signal in a well known manner by controlling the digital bits transmitted on the communication channel 101. These derived clock signals are transmitted from the communication channel interface 102 on the line CLOCK to the state controller 104 in the channel interface 100. The state controller 104 is a logic circuit which functions to convert this clock signal to the various timing and control signals required for harmonized operation of the other circuits of the channel interface circuit 100.

When the communication channel interface 102 receives the digital ones

447 764a 1a bits from communication channel 101, it converts these bits and converts the series data transmissions into a series of bytes (or other suitable width) with parallel representation of data. Once a complete byte has been received, it is output in parallel through the communication channel interface 102 on the DATA bus to the other circuits in the channel interface circuit 100. The data portion of each received data message is transmitted on the DATA bus to the DMA transfer unit 108, where the data is stored so that, if necessary, it is relocated to the processor memory.

Error controller 103 checks the bits transmitted on the DATA bus to determine if they contain any transmission errors. The error check means 103 contains a cyclic redundancy check circuit or another well-known error detection circuit, which circuit accumulates a continuous sum indication of bits already received, and this sum must correspond to the signal indicating the number of transmitted CRCs which occur at the end of the data message ( as shown in Figure 4) for data to be treated as valid. The results of this check are sent by the error check means 103 on the CONDITION line to the state controller 104, where the error state indication is used to either activate or pass the transmission of the received data message to the processor memory 201.

The hardware address generation is done as follows. The programmable pattern comparator 105 checks the header of the data message appearing on the DATA bus, determines whether the data message should be stored in the processor memory 201, and converts the header field to a particular hardware address if it is found that the data message is to be stored in the processor memory 201. The choice of hardware address is determined by the source address, destination address, and control information contained in the header field of the data message. This is accomplished when the header field of the data message is supplied by-bit to the bus DATA from the communication channel interface 102. As each byte of the header field is supplied to the bus DATA, the state controller 104 simultaneously emits a byte identification code on the bus BLOCK. The multiplexer 110 of the programmable pattern comparator 105 links both the byte code and the header byte to the address comparator 111, where the header field is compared by-bit with a number of (m) acceptable header patterns. The results of these byte-byte “-SP

447 764 comparisons are given by the address comparator 111 on lines D1 through Dm to AND gates 120-1 to 120-m. These AND gates 120-1 to 120-m together with the comparison register 112 indicate, immediately at the end of the register field, whether any acceptable heading patterns have been received. This conformity indication is given by comparing register 112 to an m-bit pattern on lines TYP-1 to TYP-m to show which of the m acceptable heading patterns stored in the address comparator corresponded to the received header field. This m-bit pattern is applied to the class encoder 106 which converts the m bits into a k-bit signal output on the CLASS-1 to CLASS-k lines to the DMA control table 107 to indicate which of the 2^k possible information classes that have been received. DMA control table 107 contains a cross reference between information classes and hardware address locations where this information is to be stored. Thus, when a class signal is received from class encoder 106 on wires CLASS-1 to CLASS-k, DMA control table 107 converts this class indication to a hardware address output on bus DMAA to DMA transfer unit 108. Since at least one match occurred between the header information of the data message and the header patterns stored in the address comparator 111, a match indication signal is generated by the OR gate 113 and sent to the state controller 104 on the CONFORMITY line. The state controller 104 will, in response to a predetermined error signal on the line CONDITION and the conformity signal on the line CONFIRM, at an appropriate time generate an activation signal on the line ACTIVATION, which causes the DMA transmission unit 108 from the processor 200 to request access to the processor data bus, . When access is allowed by processor 200, DMA transfer unit 108 outputs the hardware address received from DMA control table 107 along with the data portion of the received data message as it is received (a few of the first bits of this data have been stored in DMA transfer unit 108 ) to the appropriate processor buses. Processor memory 201 receives this address, control and data information on the associated processor buses and stores the entire data message at the specified hardware location. Once done, DMA transmission unit 108 generates a processor interrupt and supplies this signal to the processor control bus to inform processor 200 of the data message that is

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447 764 stored in processor memory 201.

In describing the channel interface circuit 100 in question, it has been assumed that the memory elements of programmable pattern comparator 105 (address comparator 111, class encoder 106 and DMA control table 107) all contain conversion information to recognize a match and then generate that address in the processor memory. 201 where this received data message is to be stored. These units are initiated and updated by the processor 200 by means of the processor control, address and data buses as shown in Figures 1 and 2. As will be described hereinafter, the processor 200 loads bit patterns into the memory elements of the programmable pattern comparator 105 (address comparator 111, class encoder 106, and DMA control table 107) to indicate the types of messages to be received from the sources currently of interest and also to specify where these messages are to be stored in processor memory 201.

Channel interface capabilities will now be described. The channel interface circuit 100 has the task of connecting the communication channel 101 to the processor memory 201. The reason for the introduction of this interface circuit is as mentioned above to relieve the processor from the task of monitoring the reception, decoding and storage of data messages transmitted on the communication channel 101 to the processor memory 201. As generally described above, the channel interface circuit 100 accomplishes this task by receiving the data message, generating a hardware address based on the header information contained in this data message, and then using this hardware address to provide access to a particular segment of memory in processor memory 201 and store the data message there. The channel interface circuit 100, when performing this task, has additional capabilities, which are not apparent from the generally provided description above. Specifically, one can say that three different classes of messages occur on the communication channel 101. These classes are special messages, collective messages and broadcast radio messages. Special messages are data messages that are addressed specifically to the processor 200 and which in turn are to be stored in the processor memory 201. However, there are many cases where the processor 200 desires to sort data messages from certain sources and therefore provides a selective listening connection to the communication channel 101. This possibility is included in po

447 764 channel interface circuit 100, as will be apparent from the following. The same selective listening option can be used in the other two data message classes. The collective message is a message that is sent to a class or subset of processors, all of whom are interested in the content of the data message. In these data messages, the destination address may very well be a generalized address indicating a large number of the processors connected to the communication channel. An extension of this message class is the broadcast radio messages which are sent to all processors having access to the communication channel 101. The channel interface circuit 100 has the ability to identify these different types of messages, to assign a priority to each of them, and to store them in different portions of the processor memory 201. To illustrate these capabilities of the channel interface circuit 100, it is appropriate to describe in detail the processing of a data message received from the communication channel 101 and its storage in the processor memory 201.

How the table charge goes is now described. It is logical to begin this description with channel interface circuit 100. It is a standard arrangement in processor technology that processor 200, processor memory 201, and channel interface circuit 100 are connected to each other via an assembly of processor buses as shown in Figures 1 and 2 ( address bus, data bus and control bus). The processor 200, the processor memory 201, and the associated processor buses are well known to those skilled in the art who operate in this system in a conventional manner. As can be seen in Figures 1 and 2, the programmable pattern comparator 105 of the channel interface circuit 100 contains three memory means: address comparator 111, class encoder 106 and DMA control table 107, all of which are shown as direct access memory (RAM) in the preferred embodiment. The memory means 111, 106, and 107 contain the tables which provide respective headline comparison / selective listening, class identification, and address generation functions. These tables are generated and kept updated by the processor 200 via the processor's control, address and data buses which connect these bodies to each other.

In particular, by supplying appropriate signals to the processor's control and address buses, the processor 200 may cause the memory means 111 to receive and store data from the processor data bus 447 764. The decoder 114 is coupled to the address and control buses of the processor and has the task of controlling detection of these processor buses with respect to address signals which identify the address comparator 111 and control signals which means that the processor 200 wishes to enter data into the address comparator 111. When these signals occur simultaneously on respective processor buses, decoder 114 will supply appropriate activation signals to the SELA and W111 lines. The signal on line SELA causes multiplexer 110 to connect the processor address bus to the address comparator 111 address lines. The aforementioned signal on line Will places the address comparator 111 in the write activation mode. Thus, processor 200 is directly connected to the address comparator's address and data lines via the processor's address bus and / or data bus, respectively. Processor 200 now loads the applicable quantities in address comparator 111 in a well-known manner. When this operation is completed, processor 200 supplies applicable signals to the processor control bus, which causes decoder 114 to remove the activation signals from the SELA and W111 lines. The removal of these activation signals causes the multiplexer 110 to connect the internal bus DATA of the channel interface circuit 100 to the address comparator 111's address lines, and by passivating the memory write activation line, new information is entered into the address comparator 111.

This memory charging operation described above is well known to those skilled in the art; a typical entry in the address comparator 111 is illustrated in Fig. 5, where the left column, with the heading "address, indicates a special memory location in the address comparator 111, while the right column of Fig. 5, with the heading RAM content", indicates the data stored in the address comparator 111 at the corresponding address location. Similarly, the processor can access the class decoder 106 and DMA control table 107, similarly loading it with data. Examples of this are illustrated in Figs. Figure 7. Use of this data and these memory means will be made clear to the reader in describing how a typical data message is processed.

Description should now be provided regarding the communication channel interface. This communication channel interface 102 included in the channel interface circuit 100 is directly connected to the communication channel 101 and has the task of receiving data messages appearing on this channel. As mentioned above, transfer_tPOOR QUALITY

447 The 764 communication channel interface 101 is digital data messages in serial form, and the communication channel interface 102 would therefore be an appropriate digital interface circuit of a type well known to those skilled in the art. In particular, Electronic Design Magazine, June 7, 1979, found an article entitled Data Communications: Part

Three, by Alan J Weissberger (pages 89-104) where a typical channel interface circuit is described. The receiver / transmitter circuit described in this publication is a well known circuit element which would be of the type used to implement the communication channel interface 102. This circuit is well known to receive the digital data signals appearing on the communication channel 101 in serial form, to convert these signals for use in the channel interface circuit 100 and to extract a clock signal from these digital data signals. The clock signal derived from the digital data message 15 is applied to the CLOCK line from the communication channel interface 102, and, as already mentioned, this signal is used by the state control means 104 to provide the timing and control signals for the channel interface circuit 100.

The state controller 104 is simply a logic circuit that uses the clock signal from the CLOCK line and the feedback signals on the CONDITIONS and CONFIRM lines to control the operation of the various components of the channel interface circuit 100. It would only be difficult to describe in this specification in the smallest detail the design of the state control means 104, since the design of this means is highly dependent on the particular, commercially available standard components selected to provide the various portions of the channel interface circuit. 100th The appropriate design of the state control means 104 is clearly within the competence of every skilled person in the field of circuit design, and it is therefore left to the designer to provide this circuit using the most economically available standard components. Analogously, the error checking means 103 is a conventional error control circuit which checks 35 the received data message for transmission errors and communicates the result of this control operation to the state control means 104 via the CONDITION line.

An account must now be provided for the programmable pattern comparator. When the serial message data 40 is received by the communication channel interface 102, the

447 764 to the programmable pattern comparator 105 via the DATA bus. This data message has been assumed to exhibit a data message structure as shown in Figure 4. Typically, the header of the data message contains six bytes in the source address field, six bytes destination address, and two bytes of control information to specify the message type. This is the header information used by programmable pattern comparator 105 to determine if the associated data message is intended for processor 200 and where it should be stored in processor memory 201. The data message data portion has arbitrary length and it does not matter to programmable pattern comparator 105. The data is therefore transmitted directly to the DMA transfer unit 108 via the DATA bus where it is temporarily stored in a buffer. The header decoding operation begins when the communication channel interface 102 receives the first bits of the first byte of the header field of the data message and generates a frame signal to mark the beginning of a message. The state controller 104 responds to the frame signal by activating line 1 SET and thereby resetting the comparison register 112 in programmable pattern comparator 105. The comparison register 112 is an m-bit register which is arranged to store the signals emitted by gates 120-1 to 120-m. The signal on

The 1-SET line causes the register 112 to be reset, and therefore a logical 1 output signal occurs on all lines ΤΪΡ-1 to TYPE-m. Each of these wires is connected to an input terminal of the corresponding AND gate 120-1 to 120-m, and this configuration serves as a memory element, since a logic 0 signal occurring on any of the wires D1 to Dm will cause the associated AND gate and bit position in the comparison register 112 to change the state to a logic 0, which signal remains until the state controller 104 again supplies an activation signal on the line 1-SET. How this circuit configuration is utilized will be apparent from the description given below.

The heading comparison is done as follows. As mentioned, the data message header field contains 14 bytes of information, and it is assumed that each byte consists of eight bits of digital data. One problem with this arrangement is that 14 is a cumbersome number to work with in the binary number system, so the described programmable pattern comparator 105 works with 16

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447 764 bytes (14 bytes heading fields and the first two bytes of data) to make the circuit design easier. You can omit the two data bytes if you want to omit them, so that you only decode the 14 bytes in the header field.

As the data message is received from the communication channel 101, the communication channel interface 102 outputs the header bit by bit on the DATA bus. The state controller 104 simultaneously outputs an address on the BLOCK bus, thereby delivering a 12 bit address: 8 bits (1 byte) on the DATA bus and 4 bits on the BLOCK bus, to the address comparator 111 via the multiplexer 110.

The need for twelve address bits becomes obvious when studying fig.

5th The address comparator 111 is shown in Figure 5 as a nxm RAM memory means, and n has been selected above with 12 bits. To give an illustrative example, it is assumed that m is equal to eight. Address Comparison 111 is therefore a 4K x 8 RAM memory or equivalent assembly of means (since 12 bits can be used to address 4K memory locations). In Figure 5, two segments of the address comparator 111 are shown, one labeled BLOCK 0 and the other labeled BLOCK 15.

The block number identifies the particular byte in the data message20 header, and as mentioned above, there are sixteen bytes decoded by programmable pattern comparator 105. In each byte of the header field there are eight bits, and these are shown in FIGURE 5 under the heading PLATS. The bits in question indicate the 256 possible bit combinations for the 8 address bits.

In operation, a twelve-bit address is supplied to the address comparator 111, the state controller 104 identifying the particular byte in the header via the four bits of information on the BLOCK bus. The first of the received bytes will be BLOCK 0000, and typical memory input data is shown in Figure 5 for the memory locations 01101000 - 01101011 in this block. In particular, for each address location, m bits (in this case 8) are stored in memory, and these m bits represent m possible comparison combinations. Thus, it can be seen that at the display locations, the column D1 in block 0 contains a stored 1 only at the memory location 01101011, which indicates that a match occurs only when this memory location has been identified in this byte of the header field. Since the first two bytes of the header field contain the destination address, this bit pattern in column D1 represents the situation where the data message is acceptable only when it is destined for the processor addressed by

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₁₃ 447 764

01101011th This situation can be compared to the input data in column Dm, where a 1 is the input date for all four of the memory locations shown. This shows that every message sent to a processor identified by the designation 011010XX will be received (where XX is providing modes for bits whose information content may be any). This is a typical collective or "broadcast radio" message, where any one class or group of processors can receive the data message.

To give an illustrative example, it is assumed that the first byte of the header field contains the bits 01101001. Since this is the first byte, the state controller 104 on the lines D1-Dm outputs the m bits (01110001) shown in Fig. 5 for the address 01101001. the line D1 to display a logic 0 signal, which signal causes the AND gate 120-1 to produce a logical 0 output signal. Analogously, line Dm will display a logic 1 signal, which signal causes AND gate 120-m to produce a logic 1 output signal. The state controller 104 now generates an activation signal on the line LADDN, which causes the comparison register 112 to store the signals emitted by the AND gates 120-1 to 120-m. As described above, this circuitry serves as a memory element which stores any non-compliance (a logical 0) as is the case with gate 120-1.

The devices for pattern comparison and class coding will now be described. The state controller 104 in turn changes the signals on the bus BLOCK as each consecutive byte of the header field is received until the last byte (byte 15) is received. Fig. 5 shows a typical table entry date for a last byte in the header field (block 15) consisting of the address bits 01111010. As mentioned above, there was a mismatch at the comparison combination D1 in the byte 0, so that a match for this byte in the block 16 is insufficient to change the logical zero stored in the comparison register 112. However, the comparison combination in column Dm shows a match, and assuming no mismatches occurred in the other received bytes, the comparison register 112 stores a logical 1 for this position, indicating a correct match for the comparison combination m. the state controller 104 via the OR gate 113

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447 764 and the applicable logic signal on the line COMPLIANCE. The state controller 104 responds to the positive conformity indication on line CONFORMITY by activating line READ, which causes it to be output from the comparison register 112 which has been added to class encoder 106 address lines via lines TYP-1 to TYP-m to be supplied to class decoder . This data, provided by the comparison register 112, indicates how many matches occurred and also the comparison combinations to which they related.

As illustrative example, it is assumed that the only match that occurred was in position m, so that lines TYP-1 to TYP-m display the following signal: 00000001. Figure 6 shows the table contents of class encoder 106 for different addresses. The class encoder 106 acts as a priority encoder as it converts the number of over 15 matches and match types into a class indication, identifying the region of 2^k regions in the memory or information classes stored therein, with which the received data message is associated. The class encoder has been provided by a multiple direct access memory (RAM), and as illustrative example, k has been selected equal to five, giving 32 different message classes, ie 2 In response to the above activation signal on line READ, class encoder 106 outputs the data stored on memory location 00000001, in this case 10101. This bit pattern is output on lines CLASS-1 to CLASS-k 'to the address lines of the DMA25 control table 107.

An account must now be provided for the hardware address and DMA control table. Fig. 7 shows some typical table contents of DMA control table 107, which circuit serves as a hardware address generator and in response to a class indication supplied to its address lines 30, delivers a 1-bit address. In the present example, 1 s is 8, and a class indication 10101 causes DMA control table 107 to output the 8-bit address 11011100 on bus DMAA to DMA transfer unit 108. The state controller 104 activates the lead ACTIVATION either upon receipt of the over 35 match signal or after the end of the data message and the receipt of the appropriate signal from the error control means 103 on the CONDITION line indicating reception of an error-free message. Here, two DMA operations are possible: either storing the data message as it is received, since the 40 programmable pattern comparator 105 completes the header field decode₁₅ 447 764 and address generation as soon as the header field has been received, or also performing a transfer to processor memory 201 only after the complete data message has been received. For this description, it is assumed that the data message is stored as it is received. The DMA transfer unit 108 is then ready to directly store the data message in the processor memory 201 as soon as the header field has been decoded. The DMA transfer unit 108 has already stored the initial portion (header portion) of the data message in an internal buffer and has received a hardware address via the DMAA bus. Thus, the DMA transfer unit 108 requests access to the processor control, address and data buses, and when access is well known by the processor 200, the DMA transfer unit 108 selects the identified portion of the processor memory 201 (address 11011100) and stores the data message therein as it is received. When this data transfer is completed, the addresses stored in DMA control table 107 and possibly also the table information stored in address comparator 111 and class encoder 106 must be updated. As described above, this is performed by processor 200. An alternative update method is to have DMA transfer unit 108 update data in the DMA control table to display the new data storage start addresses based on the data message just stored in processor memory 201. In this discussion, some performance of the DMA transfer unit 108 has been assumed, and these performances are well known to those skilled in the art. There are many different standardized DMA transfer units available in the market.

Each of the three memory means, namely, the address comparator 111, the class encoder 106, and the DMA control table 107, provides opportunities for the programmable pattern comparator not previously known to one skilled in the art. Specifically, the address comparator immediately decodes the header field and determines whether the message transmitted on the communication channel 101 is directed to the processor 200 and whether the processor 200 desires to receive this type of message from the source from which this data message originates. Class encoder 106 assigns a priority or class to the received data message, and DMA control table 107 generates a hardware address that is representative of both the type of the received message and the source of information. All this information processing is performed by batch, so that the hardware address at the end of the header field is directly available for

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447 764 use in storing data in processor memory 201. Processor 200 can continue its operation throughout this data message reception process.

Although a particular embodiment of the invention has been described, constructional detail variations within the scope of the appended claims are possible and have been considered. The intention is in no way to limit the invention to what is stated in the summary or in the detailed description provided here. The arrangements described are merely illustrative examples of applications of the principles of the invention. Other arrangements may be made by one skilled in the art without departing from the spirit of the invention or the scope of the invention.

447 764