Single channel bus communication system:digital data transmitted as short and long pulses for zeros and ones

(54) Description Device and communication method for transmitting digital information through a single channel information bus (56) Publications cited: - (57) Summary:

At a transmission facility for transmitting digital information via a bus line channel, pulses with substantially different pulse lengths are used for transmission of 0-bit and 1-bit respectively.

In a selected transmission example, the length of a 0 pulse is at least 2.1 times greater than the length of a 1 pulse, whereby the tolerance in the detection of the received pulse provides ample room for large frequency deviations of an RC clock generator, e.g. + 25% , for propagation time delays and for any other inaccuracy in the detection step when pulse flanks of small steepness must be used.

DB 603415

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446 486

The present invention relates to a municipality in the cation process for transmitting digital information through single channel information bus, the method comprising the following steps:

A. Connecting at least two asynchronously operating devices, each having at least one digital data processing portion and a clock signal generator for generating a periodic clock signal to the information bus solder,

B. arranged by associated controllers between the associated data processing portions and the information bus line, such that the transmission switch in the controllers forms an AND circuit in relation to the information bus line. The invention also relates to an apparatus for carrying out the method.

Communication methods of the above type are usually used in contexts where a number of devices have a transmission medium for internal communication. This can be communication between one or more intelligent terminals and a central computer in a laboratory, but the communication can also be for the control of household appliances, for example with the help of a so-called home computer, where audio and / or video equipment can be connected to the information bus line both for control of its apparatus and for supplying text data to a television receiver, this text data being provided by means of a teletext demodulator or a viewdata terminal, etc.

For the information bus line you can use multi-channel bus line through which digital information is transmitted in parallel.

When the average information density is low enough, a single-channel bus line is normally sufficient, whereby the information is transmitted in serial.

A transmission system operating according to the communication procedure above is known from the report Second Symposium on Micro Architecture Euromicro, 1976, pages 299-304, R Sommer: Cobus, a firmware controlled data transmission system.

This publication describes a transmission system with a single-channel bus line in the form of a coaxial cable, which in combination with associated transmission switches form an AND circuit suitable for transmitting information at a speed of about 200 kBaud, which means minimum wetting times, arbitrary prioritization, and including addresses, a net transfer capacity as well as about 10,000 information words about each 8-10 bits per second.

Since the bus line circuit forms an AND circuit, the bus line will be in the 1V supply only when all transmission switches have the output in the 11-1 state, which, when using transistors as a transmission switch, usually means that the transmission switches do not conduct current.

When a pulse is needed, the transmission switch is made conductive by current

446 486 is added to its base, the output taking from the state.

When at least one transmission switch emits a off pulse, the bus line enters the stand regardless of the states of the other transmission switches.

The bucket collector transmission switches are utilized, which form a wired AND function in combination with the coaxial cable.

The choice between on or off is arbitrary. In the said article, an AND gate circuit is utilized where the bus line is located in the ti 11 ”to 11 position when all the inputs are there. This definition will also be used in the following description. It is well known that this definition is the equivalent of an OR gate for off signals, i.e. the wired OR function.

Figure 2 of the aforementioned publication shows a simplified block diagram of a microprocessor controlled Cobus interface, which in the area is normally referred to as controller.

Said Cobus interface includes, among other things, a receiver circuit and a disturbance detector. By means of these circuits, it is checked whether any other controller simultaneously requests the bus line by checking the transmitted own address. A priority rule ensures that the device with the lower address is given priority.

In addition, the controllers include a carrier detector, i.e., a circuit for reconstructing the bit clock and a synchronization circuit. In startup modes, the bit rate is halved to reduce the impact of the synchronization problems due to, among other things, the signal propagation time along the bus cable.

A carrier detector is normally made up of a so-called freewheel oscillator or phase-locked loop oscillator (PLLO).

This necessitates a very stable clock generator which can be obtained only by means of a crystal controlled generator.

For the sake of synchronization, each word includes a start bit. Micro-synchronization as well as macro-synchronization is obtained on the start bit and on every other setting bit (page 300, right column, section 5.2).

Since a crystal controlled clock generator is needed at the transmitter side and a freewheel oscillator or a PLLO is needed at the receiver side, the circuits are relatively expensive. The same are suitable for the aforementioned laboratory applications but unacceptably expensive for use in simple systems. Furthermore, in the described system, it is impossible to connect devices that operate at widely different rated speeds to one and the same bus line. Finally, end-time tolerances necessitate well-defined and therefore steep pulse flanks, which means that a coaxial cable must be used as a bus line in order to keep the radiation spread to the environment at an acceptable low level.

446 486

An inexpensive twisted two-wire system is not useful in view of the conditions of interference created by post offices and similar bodies.

An object of the invention is to provide a municipality in a cation process that is inexpensive to realize, in which realization it is possible to use clock generators of a simple type, for example an RC circuit to determine the frequency, a cheap 2-wire bus line and means for connecting apparatus having a magnitude difference in nominal speeds.

According to the invention, a municipality in the cation process of the type described initially is characterized in that said transmission switch is switched for transmitting an 0 pulse during a part of an information bit period greater than half the information bit period and equal to more than two whole periods of the clock signal of the associated k the latch signal generator in the case of the associated device Transfers information bits over the information bus line, and is coupled to transmit a 1 pulse during a portion of the bit period which is at least a factor of 2.1 shorter than the pulse duration of a 0 pulse, the information bus line being driven to a logical OFF level by means of the switched transmission switch during both a 0 pulse as a 1 pulse.

Since a “0 and 1 gives rise to a pulse, the forward edge of a pulse can act as a starting point for a timing circuit, whereby synchronization through the clock generators 1 transmitting and receiving devices becomes superfluous. After detecting the pulse flank, the receiver apparatus, for example, determines, for example, about 3/4 of the bit period whether the pulse is terminated or not, i.e. whether the same represents a 1 "or" 0.

The large difference in pulse length between a 1 and 0 pulse enables reliable detection despite large time tolerances, which are caused by the following:

a) the use of RC clock generators which in practice exhibit a frequency tolerance of up to + 25%;

b) the use of pulse flanks with flank transition times from about 0.5 to 1.5 / US, which means that already small variations in a detection threshold can give rise to time errors of the order of a few tenths, ie sometimes more than a full clock period in the case of a 4 MHz MOS circuit, and

c) propagation time delays along the bus line of the same order of magnitude as mentioned in b).

All bit periods in the system are indicated in microseconds and are approximated by the controllers to the whole number of clock periods, these numbers being dependent on the nominal value of the clock frequency 1 of the apparatus in question, which generally means that the actual pulse lengths and the detection time 446 486 approximate the approximate number of the receiver apparatus. the defined time periods.

A number of advantageous embodiments having the features set forth in claims 2 to 9 will be described in more detail below with reference to the drawings, in which Fig. 1 shows a simplified block diagram of a transfer plant; Figure 2 shows a schematic view of the structure of an information packet to be transmitted; Figure 3 shows a wiring diagram for a portion of a control unit comprising transmission switches and a receiver portion; and Fig. 4 shows a simplified block diagram of a controller according to the invention.

Fig. 1 shows a bus structure with an information bus line 1 to which at the terminals 2 a number of devices comprising in each case a data processing part 3 with a control unit 4 are connected.

The figure shows only two of the devices 1-N, which are designated (1) and (N) respectively.

The actual number is usually much larger and dozens or hundreds of such devices can be included. The exemplary embodiment described below is based on 2 = 4096 addressable appliances, but this does not in itself constitute a theoretical or other limitation.

Although not all devices must be able to communicate with all other devices, each device will temporarily be in contact with one or more of the other connected devices. Some appliances will then only function as eavesdroppers or receivers not including temporary call or confirmation signals such as a washing machine. Other appliances will normally only function as speakers or transmitters, such as a fire and / or burglar alarm system. Other devices will sometimes function as transmitters and sometimes as receivers, such as a mini computer, a data vision terminal, etc.

In its simplest form, the bus line comprises a single transmission channel in the form of, for example, a light conductor, a coaxial cable or a pair of twisted wires (twisted pair).

Such a bus line system always requires an allocation control. A transmitter that receives the bus line must not be disturbed by other devices as this could cause interference with a transmitted message. However, that a line is busy can be easily detected by known means of other devices.

The situation becomes more complicated when two transmitters demand the use of the bus line simultaneously, with at the same time being understood at the same time within, for example, a few microseconds. Although this seems statistically highly unlikely in the first place, it often happens in practice. Thus, it is possible to

446 486 two or more devices wish to utilize the bus line at widely different times within a period when the bus line is busy a third device. As soon as the latter releases the bus line, the devices that are in the waiting state sense this simultaneously and everyone tries to acquire the bus line at the same time.

When an apparatus requests the bus line, it begins to transmit a message which message generally has the structure shown in Fig. 2.

During a test period 82, the controller checks whether the pulses are absent for a certain period of time and then adds a start bit 84. For other appliances, this start bit has the character (warning) that an information may be on.

A mode symbol 86 is then transmitted. As the master unit knows in which mode the intended slave unit can receive, the mode symbol corresponding to that mode will generally be transmitted. All low-mode devices that are eavesdropping in the waiting state must now release the bus line during the entire time slot designated 80.

If the bus line is not simultaneously requested by another device, then an identification 88 (master address) and then the address 90 of the intended slave unit is then sent. At the end of, for example, the slave unit bits, the master unit waits for a bit period for a confirmation signal indicating that the slave unit is ready to receive.

If the confirmation signal does not appear, this means that the slave unit in question is not connected.

If the master unit does not know the mode of the slave unit, it starts with its highest mode. The absence of the confirmation signal can then mean that the slave unit can only receive in a lower mode. The master unit starts the message again in a lower mode. Finally, if no confirmation signal appears even in the lowest mode, the master unit must determine that the slave unit is inaccessible, that is, it is not connected to the bus line or is disconnected.

Normally, the confirmation signal will appear and the rest of the message will be sent. Then, if necessary, certain control or control bits 92 may follow and finally the actual information transmission 94. At the end of the available slot 80, the bus line is again released at 96.

When two or more devices request the bus line, the choice is made when transmitting the mode symbol.

The following description, for example, relates to a bus line to which are connected devices having several widely different internal signal processing speeds. The invention is in no way limited to this embodiment. More complicated contexts as well as simpler facilities can work in similar ways. For example, if only one mode is present, the mode symbol can of course be omitted.

446 486

TABLE ι

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446 486

The following may serve as an example:

mod 0: clock frequency 0.55 MHz + 25 #; mode symbol 0 to 1: clock frequency 2.2 MHz + 25%; mode symbol 10 versus 2: clock frequency 4.43 MHz + 0.1%; mode symbol 110. Table I shows the approximate length of the bit periods for data information or other bits as well as corresponding pulse lengths. In this example, the time slots have been given an average length of 7 ms and a maximum length of about 10 ms.

The mode symbols have been selected so that when two or more devices request the bus line the device with the lower mode, ie the slower device, is given priority.

Since the bus line, which constitutes AND circuit, is OFF-dominated and the O pulses have substantially greater length than all the 1 pulses all tolerances have been calculated, so the bus line channel will also be O-dominated.

As soon as an apparatus, such as, for example, may have the mode symbol 10, starts in mode 1 and another apparatus with the mode symbol 0 simultaneously starts in mode 0, the mod-1 device will, as it tries to sense the first 1, on the contrary. it expects to detect 0 on the bus line and then immediately release the bus line in favor of the lower mode device. Similarly, an apparatus of mode 2, for example, will detect 10 instead of 11 (0) when a mode-1 apparatus simultaneously starts.

As two devices with the same mode try to coat the bus line, no distinction can be made with the help of the mode symbol. Both devices detect the mode symbol as correct during the test period and continue with the identification address, both still testing each bit simultaneously. Even in this case, the bus line is released immediately when a deviation is detected. In the case of an equal mother, this means that the device with the lowest address is given priority. For example, if the address of device A is 10100110 and the address of device B is 10100011, then device A will detect a 0 instead of a 1 when checking the sixth bit and will then release the bus line. The apparatus B senses a correct state on the bus line and continues its course. A must immediately release the bus line to prevent (1 this example) that its eighth bit, which is 0, would interfere with the eighth bit of B, which is a 1.

The device that detects its complete mode symbol and identification address on the bus line without interference can now occupy the bus line for the rest of the time slot.

It will be appreciated that, as soon as one or more devices are in the selection period, a third device which attempts to coat the bus line substantially later will detect either pulses belonging to the mode symbol and identify

446 486 or in a subsequent message and then have to wait until the bus line has been free of pulses for some time. The selection period is only needed in cases of simultaneous or approximately simultaneous calls.

In this example, it was assumed that the 4.43 MHz apparatus comprises a crystal1 controlled clock, for example, built on the basis of a standard crystal for the PAL television frequency equal to about 8.86 MHz, while the slower apparatus operates RC controlled clock generators.

When a mode 2 device sends a mode 1 or a mode O message, the control remains unchanged but first the clock frequency is simply divided by 2 and 8 respectively.

For the mode 2 apparatus, the length difference between an 0 pulse and a 1 pulse is about a factor of 2.4 in this example. For the slow apparatus with larger frequency tolerances, the tone factor equal to about 4 is selected. The method of operation is clearly indicated in the information given in Table I.

In a practical embodiment, the different time periods according to Table II (see below) have been selected by means of a computer program. The nominal times have been chosen so that the corresponding nominal frequencies always constitute a whole number of clock periods for each device.

Only the first part of Table II will be described in detail.

For example, when a Mod 1 device wants to start transmitting, a start bit 5 will be broadcast with the nominal length 249.2 / us. After a certain propagation time and part of a clock period for another device, this start bit can be received after about 10.8 / US.

Then, after 177.0 + 55.5 yus, 1 is given in the mode symbol at time 6 with the pulse length 4.1 + 1.8 = 5.9 yus. The receiver apparatus receives this pulse with confidence within 4.1 / US if it can operate in mode 1 and determine approximately

9.9 / us after the beginning of the received pulse whether the pulse is a 0 or a 1. The transmitting apparatus also performs this check at approximately the same time position 7. If this check results in the correct result, then the O pulse is output in mode.

1 signal with a pulse length equal to about 22 yus.

The master unit bits are then transmitted by means of the bits referred to as the master unit's identification address, but this must be interrupted immediately if the check shows that another device with a lower address must be given priority.

446 486

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446 486

Fig. 3 shows an example of a transmitter-receiver part in a control unit suitable for activating a symmetrical bus line channel. At points 10 and 11, the unit is connected to the bus line. The point 10 is connected to ground through a resistor 12 and the point 11 is connected to the supply voltage + through a resistor 13. The bus line is also connected to the inputs 14 and 15 respectively of a differential amplifier 16 for sensing with an output 17.

Thus, if no pulses are present on the bus line, the input 15 will be approximately at the supply voltage level and the input 14 will be approximately ground level. This is the state defined as the ON state on the bus line.

In addition, the bus line is connected to the outputs 18 and 20 respectively of the transmitter switch 21 and 22, respectively, which do not conduct current in the idle state.

Positive digital signals generated within a gate circuit (not shown) are applied to an input 23 of the transmitter portion. This input is directly connected to a control input 24 of the transmitter switch 21 and to a control input 26 of the transmitter switch 22 through an inverter 25.

As soon as a positive pulse occurs at the input 23, the two transmitter switches 21, 22 become conductive. In this example, these switches are realized through transistors for which resistors 13 and 12 also form collector resistors.

As soon as the transmitter switches 21, 22 become conductive, the switching point 10 is raised from ground to a level slightly above the supply voltage level, while the connection point 11 is given ground potential. This is the bus line's FREN-ti11 position.

Thus, the input polarity of the sensing amplifier 16 is reversed and a OFF signal appears on the output 17.

The ON state of the bus line can only occur when the outputs of all the transmitter switches are in the ON state, ie the switches are non-conductive, which means that the combination of the transmitter switches and the bus line de facto acts as an AND circuit for ON signals.

If the output 17 of the sensing amplifier 16 enters the OFF level while no positive signal is applied to the input 23, this can only occur when the transmitter switches in another control unit are conductive. This makes it possible to check whether another device sends a message or simultaneously requests the bus line.

Fig. 4 shows a simplified block diagram of a control unit according to the invention.

From a data processing part of an apparatus, information is supplied to the control unit at the inputs 50, 51 and thereby normally data to be transmitted to the terminal 50 and the destination address of the terminal 51. This connection can, for example,

446 486 is formed by a data bus line and an address bus line, respectively, in a microprocessor.

The information is fed to a logic unit 53 which monitors and controls in a manner known per se the information to be transmitted or received. For this purpose, a number of fixed program data, such as an identification address, are stored in a permanent memory ROM, PROM or similar device 55, which is connected to the logic unit.

The information to be transmitted is fed through logic unit 53 to a pulse former 56, which is constructed as a logic gate circuit, which ensures that the pulses are given the length required by Table I or Table II. For this purpose, the pulse former is connected to a clock generator 57, which constitutes a clock for the logic unit 53.

The pulse former 56 supplies the pulses of the correct length, calculated for a whole number of clock periods, to the transmitter switches 59, their outputs 18, 19 being connected to the bus line 10 and 11. For the corresponding elements, the same reference numerals have been used as in the previous figure.

A signal on the bus line is applied to a receiver 61 which is connected to an output buffer circuit 63 which has an output 65 for transmitting the information to the data processing portion of the apparatus. For this control, the output buffer 63 is also connected to the logic unit 53.

In addition, the output signals of the pulse former 56 as well as the outputs of the receiver 61 are applied to a comparison circuit 67 with an output 69 which is connected to an input 71 for a stop signal for the logic unit 53. This comparison circuit 67 generates a stop signal as soon as the outputs of the pulse former 56 and receiver 61 show a difference due to another device coating the bus line or because another higher priority device simultaneously requesting the bus line as above.

The actual structure and constituents of the various gate circuits, logic circuits, memories and buffer registers are of no significance to the idea of ​​the invention. These provide functions comparable to those needed for other circuits, such as, for example, the functions of the prior art described in the preamble of the specification. Every person with normal professional knowledge can and will realize these functions as needed.

The basic of the invention consists in the choice in the ratio of the length of a 0 to Γ pulse, which ratio is greater than 2.1 and, for example, may be 2.4; 4 or greater, thereby reliably transmitting information despite significant tolerances of clock generator 57 clock frequency, time differences in flank detection through receiver 61 for small steep flanks and exhibiting propagation time deviations on the bus line.

Through these measures it has proved possible to achieve information

446 486 tions transfer with the same speed and reliability as is known in the prior art, despite the fact that, especially with regard to the non-professional uses of housings 1, the cheapest means must be used, whereby considerable savings are obtained by using a cheap bus line consisting of a twisted wire pair without shielding, simple RC-coupled clock generators and by the omission of expensive sync devices on the receiver side.

The following results have been achieved in practical experiments. At the selected length of the time slot, the slowest device, in addition to the necessary extra bits consisting of the start bit, mode symbols and the addresses, can send an additional byte of information comprising, for example, 9 or 12 bits. At first glance, this may seem small but is fast enough to process information coming from, for example, a keyboard either directly or through infrared or ultrasonic remote control. Normally no more than one character will be added for every 100 ms (or much longer). This can be treated at a nominal 7 and a maximum of 10 ms.

An apparatus belonging to the Mod 1 group can already transmit about 16 bytes during a time slot in addition to the extra bits and a Mod 2 apparatus about 71 bytes. In the latter case, for organizational reasons, the transfer was limited to 2⁶bytes = 64 bytes per message.

At a clock frequency of 4.43 MHz used in this example, each byte consists of, for example, 8 bits of information and a parity bit and can be transmitted at a rate corresponding to 8.5 µs per bit, ie about 120 kBaud.

For the selected length of 64 bytes, this results in an average speed of approximately 10000 bytes / s including the extra bits . For a longer time slot corresponding to 256 bytes, the extra bits become practically negligible percentage way, which means that a transfer rate equal to about 13000 sumboles per second can be achieved, which corresponds to 120 kBaud.

However, the application of the invention is in no way limited to these speeds and the transfer rate in this example has been chosen with respect to the MOS logic utilized.

For edge delays amounting to about 15 µs, a bit rate of, for example, about 500 kBaud can be achieved and, when using steeper edges, a correspondingly greater speed can be achieved. In the latter case, shielding of the bus line is normally required, since noise must be limited.

The necessary electronic circuits, including the transmission switches, can be arranged in one and the same integrated circuit.

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