Computer having local ram

(24) Running day

Patent Office (62) National application number (86) International filing date (86) Filing date for European patent application (30) Priority information (11) Publication85-06-09 ^number 445 269

82-06-30 ®1^-12-29 Application received as

81-12-29

O Swedish patent application

Q completed international patent application with number □ converted European patent application with number

80-12-29 US 220902 (71) Applicant Wang Laboratories Inc, Lowell Mass US (72) Inventor A B. Barrow, H. Tsiang, Acton, North Andover Mass (74) Representative Ehrner's Patent Office (54) Designation Computer with Indexed local direct memory (56) Published publications: --- (57) Abstract:

A multi-task computer working with virtual memory consisting of a plurality of segments and comprising a physical memory with a relatively fast main memory (16) and a relatively slow secondary memory. A substantially varying subset of the contents of the secondary memory pages is copied over to the main memory side frames. When memory access is required during the work of the computer, a virtual address is generated, which must be translated into a physical address for addressing the main memory. The computer includes an indexed local direct access memory T / RAM (42) for storing previously translated addresses. T / RAM has a capacity of one input for each side of the virtual memory. Before a translation is performed, T / RAM is indexed by the virtual address; in the event of τ / RAM error, the translation is performed and the translated physical address is loaded in the indexed mode before restarting the memory operation. A subsequent reference to the same virtual address indexes the previously translated physical address, which is then used for addressing the main memory and is also transmitted for indexing a reference / change table (50). A stored monitoring / non-monitoring signal associated with each virtual memory segment controls the storage of referenced virtual addresses for monitored segments. After a task switch, the stored virtual addresses are transmitted for indexing the corresponding T / RAM inputs for fast, selective and partial emptying of the T / RAM.

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The numbers in brackets indicate the international identification code. INlD code Letter mom clamp indicates international document code

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The invention relates to a memory arrangement in computers.

More specifically, the invention relates to an improved memory arrangement in computers operating with a virtual memory.

In physical memories or storage devices for use in computers, the cost (per storage device) of memory is inversely related to the speed at which a storage device can be accessed. Very fast memories are significantly more expensive than memories that require longer access time. When attempting to design economic computers, many machines as a result are provided with a hierarchy of memories, in which some memories are slow but have high capacity, while others are fast but have little capacity. During the operation of the computer, the contents of the various memories are transferred or copied as needed.

Specifically, computers generally have a main memory, which is located in the machine and is directly accessible by the computer's central processor. This memory normally consists of dynamic direct memories^- (so-called RAM). In addition, computers generally have secondary memory (or files) arranged in external devices, such as magnetic tapes or disks. The access time to the main memory is normally 500 ns, while the access time for a magnetic disk is normally about 20 ms.

Finally, such computers normally have a control register, which can be separated from the main memory or form a read-only part of the main memory, and a very high-speed cache, which contains a time-varying subset of the contents of the main memory. The pocket memory is normally located in the central processor.

If the data (which may include a macro program) used by the computer requires more storage than is available

8107831-3 in the main memory, additional memory space is provided in the secondary memory. Prior to the development of so-called virtual memories, the programmer divided data into sections, called overlay segments, each of which were housed in the main memory, the overlay segments were stored in the main memory one at a time during the operation of the computer; some data entered at a later time was thereby written over previously stored data segments in the main memory. The programmer was responsible for splitting the data into overlay segments, whereby he had to determine where in the secondary memory each overlay segment 10 would be stored and to keep track of the need to input each new overlay segment and to provide the transfer of overlay segments between the main memory and the secondary memory, in general, the overlay segment must be stored. without help from the computer itself.

The development of virtual memories has made it possible to transfer this management to the computer itself, without the programmer having to control or even be aware of this process. According to this development, a large address space is defined which is addressable by the central processor of the computer and which is referred to as the virtual address space. The virtual address space can be much larger than the physical storage space available in the main memory. Data is stored in the secondary memory in blocks usually of the same size, called pages, and transmitted one page at a time to the main memory. The main memory is divided into blocks called page frames the same size as the pages. A data page is stored in an eidram, with its beginning and end oriented.

During the operation of the computer, as the need for memory access arises, signals representing a virtual memory address are generated by the central processor. The virtual address comprises a page number indicating which page contains the data element in question, and an additional address portion, called the offset portion, which indicates the location of the data element within the page. To provide memory access, the virtual address page number must be translated to the physical address page frame number, which references

8107831-3 to the physical space in the main memory. If the data in question is already in the main memory, it is obtained from the physical state, and the processing continues. (Sometimes an additional control step exists to determine whether the data in question is in the high-speed cache, and if so, it is obtained directly from the cache; however, the present invention does not refer to this additional step.) If said data is not in the main memory, the computer must obtain the page containing the necessary data elements from the secondary memory and transfer the data element to the main memory, after which the data element is obtained from the relevant page and the processing. continues.

Such a design is practical in that the logical workflow in most programs is such that the entire program does not need to be stored at any point in the main memory during program execution. For example, start and end routines are performed only once during the execution of a program. An exception procedure, such as a failure routine, is required only if the exception condition occurs. At a given time during the execution of a program, reference is only required to a subset of the entire program, and the elements of the subset are generally located close to each other. This is sometimes referred to as a distinctive feature locality of reference in such programs.

The creation of a virtual memory offers great advantages in memory management, freeing the programmer from the management of overlay segments and taking into account the overriding of the computer's available main memory capacity. In addition, a virtual memory computer can work with relatively large, fairly inexpensive (though slow) secondary memory, and a relatively small, rather expensive (but fast) main memory, thereby reducing the total cost of the computer.

However, the use of a virtual memory requires that operation time must be used to execute appropriate instructions for obtaining the physical address from the virtual address.

The translation of the virtual address to the physical address requires access to a page table, which is identified by segment number and stored in the main memory and which contains information regarding the location in the main memory for all pages in the segment in question of the virtual virtual space in question. The page table is addressed by a virtual page number for locating the desired input in the page table. Every item! the page table includes an error bit indicating whether the page has been transferred to the main memory. Furthermore, the element of the page table includes protection bits and the page frame number (referring to the physical main memory) where the page resides, if present in the main memory.

the translation process therefore includes the following steps, which must be performed by the processor (while executing a microprogram) or by the corresponding hardware in the processor: enter the page number location number for the page table, enter the virtual page number for addressing an element in the page table, obtain the element in the page table, check the status of the error bit and (if the page is in the main memory). combine the page frame number with the virtual address offset portion to form the physical address.

The translation process therefore takes a certain amount of time each time the process is carried out. If the process must be performed at each memory access, the computer's memory operation will be significantly delayed. Thus, it is desirable to reduce the necessary exercise time.

One way to solve this problem is to provide a small buffer register for storing signals representing newly translated addresses outside the central processor (in the memory controller). For example, such a buffer register has been designed as a set of eight to thirty-two associated registers, each containing two fields. One field contains signals that represent the page number of a recently translated virtual memory address. The second field contains signals that represent the page frame that currently belongs to the virtual one

8107831-3 memory page. Each time a virtual memory address is translated while executing an instruction, signals representing the virtual memory address number and the resulting real memory address frame number are placed in this buffer. An earliest-previous-use rule was used for selecting the register in which the new translation should be placed (to replace an older translation).

When a memory reference, indicated by a virtual address, is requested during the work of the computer, the eight registers are scanned simultaneously (in parallel). The signals representing the virtual page number in each register are compared to the signals representing the virtual page number of the virtual address for the memory operation in question. If compliance is found, the page frame number signals are taken from the register in question and combined with the offset signals to form the physical address. If no compliance is detected, the regular translation process is performed.

Such a structure involves several inconveniences. First, the circuit solution for such a scan is expensive, although parallel scanning (associative addressing) is fast. Furthermore, the addressing circuits are physically complicated, and the complexity increases rapidly with increasing number of registers to be searched. In practice, therefore, there is a strong limitation on the possible size of the buffer register, which is conditioned by both cost and complexity. Accordingly, only a very limited subset of recently translated addresses can be retained.

Furthermore, in a multi-task computer, the contents of the entire buffer unit (eight to thirty-two registers) must be emptied as the computer changes task. This happens very often. This requirement has two disadvantages. First, it takes time to empty the buffer unit. Second, no translated addresses are available after the buffer unit is emptied, so the buffer must be scanned for each subsequent memory access and then the newly translated address is entered into the buffer unit until this

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You have been filled. This requires additional time.

It is therefore an object of the present invention to provide a device for improving the efficiency and operating speed of a computer using a virtual memory, by reducing the total time required for address translation.

The invention thus relates to a device at a virtual memory multi-task computer 10 comprising a plurality of segments. The computer has a central processor comprising a latch, a memory address register and a memory data register. A control register is connected in to the central processor. One to the central processor in the connected bus comprises address signal lines which receive address signals from the memory address register and data signal lines which receive data signals from the memory data register and transmit data signals to the memory data register. The computer has a physical memory for storing data signals that represent data and macro instructions.

The physical memory comprises a relatively slow-access secondary memory connected to the bus, which holds a plurality of pages of uniform size (number of bytes), each side; contains a plurality of data signals, as well as a main memory connected to the bus with relatively fast access for receiving and transmitting data signals and receiving address signals. The main memory holds a plurality of page frames, each containing the same plurality of data signals that are housed on a secondary memory page and are addressable by physical address signals including page frame number signals and offset signals. The central processor, control register, and bus together constitute means for: controlling the copying of a plurality of data signals in the secondary memory into certain main memory pages addressed by physical address signals, and vice versa.

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The computer is configured to operate in dependence on certain data signals representing macro instructions stored in the physical memory;

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8107831-3 the central processor and control register work together in dependence on signals representing read and write memory access macro instructions for generating virtual address signals including segment number signals, page number signals and offset signals, and for delivering the virtual address signals to the latch. The central processor and control register further operate in dependence on the memory access macro instructions for performing a translation of the virtual address signals to the corresponding physical address signals. the translation comprises transmitting the segment number and page number signals to the main memory for addressing certain portions of the main memory containing the page number signals, and transmitting page number signals from the main memory, together with the offset signals from the latch, to the memory address register.

The central processor and control register further operate in dependence on the read memory access macro instructions for transmitting data signals from the addressed main memory page frames to the memory data register, and depending on the write memory access macro instructions for transmitting the side frame signals from the main data memory address register to the memory data register.

According to the invention, the computer comprises an indexed direct memory (random access memory, herein referred to as T / RAM or TranslationRAM) in the central processor with indexing means connected to some of the latch outputs. Furthermore, multiplexer means are provided with their outputs connected to the inputs of the memory address register and provided with two sets of inputs, the outputs of the direct memory being connected to the first set of inputs, and the outputs of the latch to the second set of inputs. The central processor and control register initially operate depending on a memory access macro instruction for transmitting signals representing the virtual address time number from the latch to the direct memory indexing means to output at its outputs the set of signals stored at the indexed location, including signals representing a page frame number and of two states.

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The multiplexer means operates in response to a first state of the error signal for transmitting the indexed page frame number signals from the direct memory to the memory address register for addressing the main memory, and operates in dependence on a second state of the error address bit for transmitting the virtual address signal from the transfer address memory register. The central processor and the control register further operate in dependence on the second state of the error signal for performing the translation of the virtual address signals and imposing signals representing the translated page frame number of the direct memory indexed location together with an error signal having said first state.

According to a further aspect of the invention, the central processor of the computer has a status register comprising a plurality of adjustable status bits for indicating the computer's operational status and index ignoring means comprising a reference and change table which provides an adjustable reference bit and an adjustable change bit for each side frame of the main memory. The reference and change table 20 is connected to the indexed direct memory output for indexing the table with respect to page frame numbers. The central processor and control register work together depending on a memory access macro instruction for setting the indexed reference bit, and depending on a write memory access macro instruction 25 for setting the indexed change bit. The reference and change table output is connected to the status register for setting certain status bits depending on the state of the indexed reference and change bits.

According to a further aspect of the invention, the computer comprises a monitoring bit in the main memory corresponding to each virtual memory segment and occupying one of two states, as well as a stack signal storage device in the central processor. The central processor and the controller work together depending on the second state of the error signal and the virtual address segment number signals during translation of the virtual address for addressing the monitoring bit of the segment and for control.

8107831-3 of its condition. The central processor and controller operate in dependence on a first state of the monitoring bit to transmit the virtual address id number signals to the stack signal storage device for storage.

The central processor and controller operate in response to a task switch during the computer's work for recovering the stored virtual address number signals from the stack signal storage device and for transmitting the stored signals for indexing the direct memory and setting the error signal in its second state.

Further objects, features and advantages of the invention will become apparent from the following detailed description, with reference to the accompanying drawings.

Fig. 1 schematically shows a computer according to the invention;

Fig. 2 is a simplified block diagram of the central processor of the computer of Fig. 1;

Fig. 3 schematically shows the virtual address space of the computer of Fig. 1;

Fig. 4 shows the format of an input into the translation RAM according to the invention;

Fig. 5 shows the format of a virtual address;

Fig. 6 shows the format of a page table entry;

Fig. 7 shows the format of a segment control register;

Fig. 8 shows the format of a physical address;

Fig. 9 schematically shows the control register and its outputs;

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Fig. 10 shows a circuit for deriving certain control signals from some of the control register's outputs;

Fig. 11 shows in detail the circuit of the T / RAM address bar;

Fig. 12 shows the T / RAM circuit in detail;

Figures 13, 14 and 15 show circuits for deriving certain control signals;

Fig. 16 shows the circuit of the T / RAM multiplexer in detail;

Fig. 17 shows the reference / change table circuit in detail;

Fig. 18 shows clock signals used to control computer operations;

Fig. 19 shows in detail various elements of the central processor relating to the monitoring function;

Fig. 20 schematically shows how monitored inputs are emptied into the T / RAM unit;

Fig. 21 shows in detail the memory address register multiplexer circuit; and

Figures 22 and 23 show the time course of accessing the T / RAM unit and loading an input into the T / RAM unit according to the invention.

The drawings, in particular in Fig. 1, schematically illustrate a computer utilizing a virtual memory. The computer 10 has a central processor (CPU) 12, which has direct access to a control register 14, which contains groups of control signals for controlling the operations of the computer hardware. Some groups of control signals are accessible depending on instructions input via external units or depending on current operating conditions in the central processor, in a manner well known in the art.

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The computer 10 further has a main memory 16 and a memory controller 18, the function of which is to provide memory access in the central processor and the external units. Among the peripheral devices are a secondary memory 20 and other devices such as a keyboard, monitor, printer, telecommunications interface and the like. The main memory is addressed by the central processor via a bus 15 (comprising data and address lines) and the memory controller 18.

The main memory 16 has a capacity of eight megabytes (8,388,608 bytes?) With a word size of 32 bits (four bytes). The main memory 16 is addressed by 24 lines, as a 24-bit physical address. The contents of the main memory 16 are considered as divided into side frames. The size of a side frame is 2 K bytes. Referring to Fig. 8, the 24-bit physical address format comprises a 13-bit page frame nun and an 11-bit offset indicating a byte within the page frame. (The (higher order) extra bit in the page frame number allows future memory expansion by a factor of two.)

The contents of the secondary memory 20 or files are considered as divided into pages, each page being the same size as a page frame in the main memory 16, ie 2 K bytes. Data is transferred between the secondary memory and the main memory in blocks, especially in silk units. The particular manner in which this is accomplished does not form part of the present invention.

Referring to Fig. 2, certain elements of the central processor 12 essential to the invention are shown in block diagrams in more detail than Fig. 1. In particular, the central processor 12 comprises an arithmetic unit (ALU) 22 of known embodiment having two 32-bit input buses, an A-bus 21 and a B-bus 23, and the output of which is connected to a 32-bit destination bus, namely a C-bus 24. The C bus 24, among other destinations, is connected to the input of a stack 30 comprising 256 32-bit registers, to one. C-bus / memory multiplexer 32, to a T / RAM address bar 38 (latch) and to a 24-bit virtual address register 26. Part of stack 30 is configured as monitoring area 34, including registers

8107831-3 containing 128 words about each 32 bits. As will be seen below, the monitoring area 34 is used to store a list of recently translated virtual addresses, the function of the monitoring area will be shown below, in particular in connection with the description of Fig. 19.

A further portion 36 of stack 30 is used for storing a set of signals called segment indicator table. There are eight segment indicators in the table, one for each segment of the virtual address space that is supported at all times by the machine product. The format of a segment indicator is shown in Figure 7, and its use will be explained in conjunction with the description of Figure 19.

The C-bus / memory multiplexer 32 is switched by memory control signals which are not related to the present invention for transmitting either data from the main memory 16 or data from the C-bus 24, and the outputs of the multiplexer 32 are supplied with a set of five memory data registers (0-4 ) 40. The outputs of the memory data registers 40 are either transmitted to a data buffer 44 and then to the main memory 16, or to a set of work registers and shift and multiplication logic, not shown in detail, since the arrangement does not form part of the present invention.

A 32 bit status register 46 is not connected to the A, B or C bus; its bits are individually set and sensed by the hardware of the central processor 12 during the operation. The particular status bits relating to the present invention are M2H and M2B, which are set by the circuit of Fig. 17, in a manner to be described below, and STATE, which is input to the circuit of Fig. 14. The STATE bit indicates either system status (STATE = 0) or user status (STATE = 1); the operating system runs in system status, while all programs run in user status. Some machine functions may be inaccessible in one or the other state; the details of this, however, do not affect the present invention.

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Main memory 16 is addressed via a set of three memory address registers (MAR 0-2) together designated by reference numeral 28. MAR registers 28 are loaded via a MAR multiplexer 52, shown in detail in FIG. 21. The three individual MAR registers have 24 , 32 resp. 32 bits. Each of the three memory address registers is selected for performing various functions of the central processor 21, but such choices do not affect the present invention and will not be described hereinafter.

The outputs of the MAR register 28 are connected to B-bus 23 and to a memory address block (not shown), from which the (physical) address signals are output for addressing the main memory 16 in a conventional manner (and thus do not form part of the present invention).

To provide an advantageous memory arrangement in accordance with the present invention, the central processor 10 further comprises a local random access memory 42, called translation RAM or T / RAM, comprising 4K (4096) 16-bit cells. T / RAM 42 is indexed by twelve lines which give a 12bit index. T / RAM 42 has one input per page (each page contains 2K bytes) for the entire virtual address space of real megabytes supported by the hardware at a given time.

In a multi-tasking computer, the virtual address space can be considered as divided into segments. In this computer described, the virtual address space is divided into eight segments, each comprising one megabyte. Referring to FIG. 3, in which the virtual address space supported by the hardware at a given time is shown schematically, segment 0 contains the computer operating system, segment 1 user program, segment 2 user data, and additional segments are available for expansion. Each user of the machine sees an eight-segment virtual address space, the operating system being in the segment 0 in each such space, although its own program and corresponding data are in the remaining segments.

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The 24-bit virtual address format is shown in Fig. 5. The first bit (higher order) of the virtual address signals is an invalid bit, which in a valid 23-bit address is equal to zero; if this bit is equal to one, the address5 is then greater than what is allowed. (The 24-bit virtual address format allows future expansion of the supported virtual address space). The status of the higher order bit VO is checked by the machine's hardware, as will be described below. The bits VI - V12 comprise a unit called the T / RAM index.

This part of the address is logically divided into two parts, a segment number and a page number, during the work of the central processor. However, no distinction is made in the hardware T-RAM index during the mapping of the virtual address to a physical address, as will be described. The remaining part of the virtual address (V13 - V23) is an 11-bit offset or bit group location on the page. This part of the address is not translated because it is the same for the virtual and physical addresses.

For storing signals in T / RAM or retrieving signals therefrom, T / RAM is indexed by the twelve T / RAM index signals output from the T / RAM address bar 38 which receives the twenty-four virtual address signals (as shown in FIG. 5) from the Cbus 24. During the work of the computer, T / RAM is loaded, with one input at a time from the virtual address register 26 in a manner that will be described below.

The format of a T / RAM input is shown in Figure 4. The entire input comprises 16 bits; bit 0 is an error bit, bit 1 is a read protection 30 bit (Read Protect, RP), bit 2 is a write protection bit (Write Protect, WP) and bits 3-15 include a page frame number. To return to Figure 2, the page frame number signals of an address input are read from T / RAM 42 to T / RAM multiplexer 54, which also receives an input from T / RAM address bar 38. The operation of the T / RAM multiplexer 54 will be discussed in connection with Fig. 16.

The page frame number portion (bits 3-15) of the output of T / RAM 42

8107831-3 is also transferred for indexing of a reference and change table

50, which contains a 2-bit input per page frame number. The use of a reference and change table is in itself well known and will not be described in detail in this context. The two bits include a reference bit and a change bit for each page frame; the reference bit is set high to indicate a reference to the page frame in question in the main memory; the change bit is set high to indicate that the corresponding input in the main memory has changed. As part of the cleanup work, the operating system refers to the change bit and re-writes the corresponding part of the secondary memory in order to keep it updated with the main memory. The reference or change bits are set only when a translation is performed, thus not with each memory reference. (The presence of non-translation memory references will be discussed below.) The reference and change bits are reset when the page frame is reused, ie when another portion of the secondary memory is loaded into the relevant page frame of the main memory, usually at a time when the computer is switching tasks.

With regard to the present invention, the memory address registers receive inputs in two ways. First, upon the occurrence of a T / RAM error, as will be described below, the (virtual) page number signals are received from the T / RAM address bar 38. Alternatively, when T / RAM errors are not present, they are received ( physical) page frame numbers from the T / RAM multiplexer 54. In both cases, the offset signals (11 bits of lower order) are received from the T / RAM address bar 38.

Referring to Fig. 9, the control register 14 contains control signals which are accessible in groups of forty-eight output signals on forty-eight parallel lines. The signal on each line may be either high (1) or low (0) and transmitted directly to the central processor 12's hardware to control its operation. Of the signals on these lines, only some have contact with the present invention. These are the signals 0-6, which are transmitted as a group to a decoding circuit (FIG. 10) for deriving either of the control signals which

8107831-3 is denoted by LT / RAM (load entry into T / RAM), TRCT (test reference / change table) and RRCT (reset reference / change table); signals 22 and 23, which select one of the three MAR registers 28 and whose function will be shown below; and the signals 7 29, which are transmitted as a group to a decoding circuit (Fig. 10) for deriving one or both of the translation control signals designated by WT (write-type translation operation) and TRAN (translate). the transmission of the derived control signals will be described below.

The general way of accessing certain groups of control signals in response to macro instructions and machine conditions does not form part of the present invention, but is well known in the art of controlling computers. However, the access of certain groups which are related to the present invention will be described below.

Referring to Fig. 11, the circuit of T / RAM address bar 38 is shown in detail. The bits 8-31 of the 32-bit C bus 24, which comprises the 24-bit virtual address, are input to the latch 38. The latch 38 is controlled by a signal input at CK which comprises a control signal and a clock signal; the control signal is one of the signals TRAN, LT / RAM, TRCT and RRCT, the derivation of which is shown in Fig. 10, while the clock signal is T2 (Fig. 18). Upon receiving a clock signal, the latch transmits bits 0-13, which comprise the VO bit (IVA) and the 12 bit T / RAM index (see Fig. 5) of the virtual address. The remaining outputs of the latch 38 comprise the II bit offset (see Fig. 5) and are transmitted to the MAR multiplexer 52.

In Fig. 12, the circuit for T / RAM 42 is shown in detail. The twelve T / RAM index bits from the latch 38 (Fig. 11) are applied to index the T / RAM for either inputs or outputs. Signals representing an input to T / RAM can be applied to T / RAM on the data inputs (DI) of the virtual address register 26 after applying the control signal LT / RAM (from the circuit of Fig. 10) together with the clock signal T2 (Fig. 18). The signals are stored in it

8107831-3 indexed position. Signals representing the indexed input are output at the data outputs (DO), and bits 3-15 (representing the page frame number) are transmitted to the T / RAM multiplexer 54 (Fig. 16), the operation of which will be described below.

Referring to Fig. 4, the signals stored as an input into T / RAM comprise said error bit (F), read protection bit (RP) and write protection bit (WP), and a 13-bit page frame number. As shown in Fig. 12, these 16 signals are output at the data outputs (DO) of T / RAM 42. Referring to Fig. 13, the error bit is transmitted, together with the IVA bit from the T / RAM address bar 38 (Fig. 11), the control signals CM 22 and 23 from the control register 14 (MAR selector signals) and TRAIN (from FIG. 10) to a translation error logic circuit 56, which generates either of two possible error signals TTO and TT1. These are both translation error signals; the difference between them depends on which of the memory address registers is to receive the address signals and has nothing to do with the present invention.

Referring to Fig. 14, the WP and RP bits from T / RAM 42, together with the STATE status bit (Fig. 2) and the WToch TRAN control signals (from Fig. 10) are transmitted to a protection error logic circuit 58. This circuit generates an error signal TT2. The use of protective pieces is well known and need not be described in more detail in this context.

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The three error signals are transmitted to the circuit 60 of Figure 15 which, if any error signal is not generated (i.e. if there is no T / RAM error or a protection error), produces no error control signal TT. The additional functions of the three error signals will be described in the following.

Referring to Fig. 16, the control signal TT, together with the clock signal T1, is transmitted to the T / RAM multiplexer 54 for selecting either of its two inputs (each input consists of a set of wires). If there are no error signals, the 13-bit page frame number portion is transmitted by the T / RAM 42 (physical address) read out

8107831-3 input by multiplexer 54 via lines TR 0 - 12 to MAR multiplexer 52 (Fig. 2). Alternatively, in the event of an error signal, the C bus bits 8-20 (virtual address) on the lines TR 0 - 12 are transmitted to the MAR multiplexer 52.

In Fig. 17, the reference / change table 50 is shown in detail. The control signals that control the operations in this table are WT (write-type translation operation), RRCT (reset reference / change table), RF (set reference bit) and TRCT (test reference / 10 change table), all from FIG. 10; TRAN (translate), from Fig. 13; TT (no errors) from Fig. 15; CM 22 (one of the MAR selector control signals) of Fig. 9; and CL 9 and CL 10, which are output signals from the T / RAM latch 38 (Fig. 11). The clock signals T1 and TA (Fig. 18) further control the work of the reference / change table. The signal RRCT resets a 2-bit input, indexed by the T / RAM bits 3-15, to 00 (both bits are set low). The signal RF sets the reference bit of the indexed input to high value. The signals WT and TT set the change bit of the indexed input to high value. The use of page frame numbers from T / RAM 42 to index the reference change table 50 provides increased speed and efficiency in the work of the computer.

The signal TRCT causes the status bits M2H and M2B in status register 46 (Fig. 2) to be set to the values ​​of the reference and change bits of the addressed input. The status bits are later checked by the operating system in order to determine which parts of the secondary memory must be rewritten to conform to the contents of the main memory. This procedure is well known in the art of computer technology and is not part of the present invention.

From Fig. 9 it can be seen that the error signals ttO, tt1 and tt2 access certain groups of control signals stored in the control register. How certain control signals perform the indicated functions in detail depends on the detail structure of the machine in which they are used, and it is within the ordinary skill of the computer designer to select such signals. Thus comes this aspect of the machine

8107831-3 work to be generally described without details of control signals, except for the signals required for T / RAM charging.

Essentially, the T / RAM error processing group of control signals controls the central processor CPU for copying, from the portion 36 (segment indicator table) of stack 30 to one of the memory data registers 40, of signals which represent a particular segment sensor indicated by the segment portion (three bits of higher order) of the virtual address signals T / RAM index, which has been transferred to a working register from the memory address registers 28 via the B-bus 23.

As shown in Fig. 7, each segment indicator comprises 32 bits, of which the bit 0 is referred to as the monitoring bit, the use of which will be explained below; bits 1-10 represent the length of the page table for the segment; bits 11-30 represent the address in the page table of the segment; and the bit 31 is a virtual / physical bit indicating whether the address is virtual or physical. If the page table address is physical, the address need not be translated; if it is virtual, it must be translated before proceeding.

The page table address portion of the segment indicator signals is used to address the page table in the main memory 16. The format for a page table entry is shown in Figure 6, and it can be seen that it is the same as a T / RAM input. The page table entry in the page table is addressed by using the side part of the T / RAM index part (bits VI - V13) of the virtual address signals (now in a work register). The signals representing the addressed page table entry are transmitted from the main memory to the virtual address register 26. The page table input PTE error bit is checked. If this error bit = 1, the page is not in the memory but must be transmitted in a conventional manner, whereby the error bit is reset to 0. If the error bit = 0, the control signal LT / RAM (Fig. 10) loads the side table input signals in T / RAM in the indexed position of

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I; 20 together with an error bit set to 0, and protection bits, the state of which is determined in a way that does not affect the present invention! invention.

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Referring to Fig. 19, segment indicator signals, the monitoring bit of the circuit 62 are checked. If the monitoring bit is found to be low, the interpretation of the macro instruction is restarted. If the monitor bit is found to be high, a control signal MOVE VA is output,¹ causing the virtual address signals to be transmitted from the work register to the stack 30. A stack address logic circuit 64 addresses a location in the stack's monitoring area 34; the virtual address signals are stored in the monitoring area. Up to 128 virtual addresses can be stored in the monitoring area. Counting is performed and used by stack address logic 64 when loading additional virtual addresses. After the virtual address signals have been stored in the monitoring area 34, the interpretation of the macro instruction is restarted.

The virtual address signals stored in the monitoring area 34 are available for use in emptying certain inputs into T / RAM 42. This can be accomplished in various ways, depending on operating conditions not related to the present invention. Thus, when the computer is switched from one task to another, monitored entries of the operating system are emptied in connection with other cleaning operations performed in conjunction with the changeover and which otherwise have nothing to do with the invention. With reference to Fig. 9, the task switching signal (from the operating system) triggers certain control signals in the control register for emptying the monitored inputs.

When emptying a T / RAM input shown schematically in Figure 20, the virtual address signals stored in the monitoring area 34 of the stack 30 are transmitted to the T / RAM address bar 38 for indexing the particular input to be emptied. The input bit of the highest order (error bit) is converted to high level, and the remaining bits are converted to low level in the indexed position for emptying the input. When using addresses

8107831-3 from the monitoring area, some monitored entries can be emptied quickly without necessarily emptying the entire T / RAM. At the same time, unattended entries (such as signals representing addresses of operating system segments) remain in T / RAM and do not need to be emptied or recharged at the next memory access. This saves additional operating time.

For example, consider the use of segment 1 in the virtual address space (Fig. 3). When the computer starts to work, there are no valid T / RAM entries for segment 1 in the virtual address space. Initially, the operating system loads the segment indicator for segment 1 with M = 1 (indicating monitoring; see Fig. 7). The task relating to segment 1 is then started.

Assume that the execution of a task causes memory references to nine pages in segment 1 before the task is interrupted. When each of these pages is accessed, its virtual address was translated by reference to the segment identifier and the page table; at each reference, the status of the monitoring bit is noted, and as each physical address is stored in T / RAM, the virtual address is stored in the monitoring area 34. When the task is interrupted, segment 1 of the T / RAM entries must be emptied. In this example, at this time, nine virtual addresses will be stored in the monitoring area of ​​the stack 30. Therefore, only these nine T / RAM inputs need to be emptied. In operation, the translation function is initiated during the operation of the central processor CPU 12 in response to a macro instruction, i.e., an instruction that is part of the program executed by the computer. CPU 12 interprets each macro instruction, and the central processor 12 hardware elements operate in accordance with the interpretation for performing the specified operation. Such hardware interpretation of macro instructions is well known in the art of computer technology and does not form part of the present invention except with respect to what is described below.

During the interpretation of the macro instruction, the central processor CPU 12, if it notes that a memory access operation

8107831-3, in response to this, is specified to output certain control signals from the control register 14, including certain signals on lines CM 27-29 (FIG. 10).

Not every memory access needs a translation operation. Often, successive memory operations occur at adjacent locations in the memory, and instead of generating an entire 23-bit address for each such memory operation, it is possible to specify, by counting or counting, an already generated address (already present in the memory address registers 28) subsequent memory operation. Such counting or counting measures are referred to as ripple operations, and in the computer described herein, the ripple function is specified by combinations of control signals on lines CM 27 - 29, other than those shown in Fig. 10. The choice of the ripple or translation group of control signals in the control register are determined by other aspects of the interpretation of the macro instructions from the central processing unit CPU 12, which do not concern the present invention.

If the next physical address is to be determined by translation, rather than by counting or counting down, then, depending on whether a read or write operation is to be performed, the outputs on the three lines CM 27-29 either an operation 25 read the main memory with translation (RTRAN ) or an operation write the main memory with translation (WTRAN). Two types of read operations RTRAN occur due to certain operating conditions which do not affect the present invention.

The group of control signals comprising the RTRAN or WTRAN combination of signals on lines CM 27-29 also includes Cbus destination control signals which give signals representing the virtual address at which memory access is to be performed to the C bus 24 and transmission from the C bus 24 to the virtual address register 26 and to the T / RAM address bar 38. The control signal TRAIN releases the T / RAM index portion of the virtual address signals from the T / RAM address bar 28 to T / RAM 42.

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The indexed T / RAM input signals are output at the data outputs of T / RAM 42. The error and protection bits (TR 0 - TR 2) are transmitted to error circuits in Figs. 13 and 14, while the side frame number bits (TR 3- 15) are transmitted to T / RAM. multiplexer 54 (Fig. 16). In the absence of errors, no one switches the error signal

The TT multiplexer 54 for transmitting the page frame number signals to the MAR multiplexer 52 (Fig. 2) which transmits these signals together with the offset f signals (V14 - 23) to the memory address registers MAR 28 which form the set of signals 10 representing the physical address. The indexed entry in the reference / change table 50 is updated at this time.

Alternatively, if a T / RAM error is present, an error bit (tr o) on the input to circuit 56 of Fig. 13 causes a translation error signal ttO or ttl to be generated. The output of circuit 60 (FIG. 15) switches multiplexer 54 to output the T / RAM address signals from C bus 24 to MAR multiplexer 52. the translation error signal triggers a certain group of control signals in the control register 14, which causes a segment indicator in the table 36 of the stack 30 to be used to locate in the main memory 16 the page table of the segment in question. The page table input is found in the segment page table, and the decoded control signal LT / RAM (Fig. 10) causes the page table input signals to be loaded into T / RAM 42 (Fig. 12), from V MAR 26, in the position determined by the T / RAM index signals from T / RAM Address Lock 38. the monitoring bit in the segment sensor is controlled by the circuit 62 and, if high, the virtual address signals are stored in the monitoring area 34 of the stack 30 for use in selectively emptying the T / RAM input at a later time. 30

The interpretation of the macro instruction is then restarted. The WTRAN or RTRAN control signals are again transmitted to the circuit of Fig. 10, and the indexed input signals are read from T / RAM 42. At this point, the error bit is = 0, whereby the translated page frame 35 number signals can be placed in the memory address registers MAR 28 or the write operation specified by the macro instruction. The reference / change table 50 is updated in that mode

8107831-3 which at this point is indexed by the page frame number signals (Fig. 17).

If a protection error occurs and is detected by the circuit 58 of Figure 14, the protection error signal tt2 triggers certain control signals in the control register 14 (Figure 9), which cause appropriate action in the central processor CPU 12 in a manner which does not affect the present invention.

The timing of the indexing of T / RAM 42 is shown in Figure 22. As shown in this figure, a cycle for the central processor (CP) comprises four time intervals TA, TO, T1 and T2 (these signals are generated in accordance with Figure 18). Each translation operation requires two CP cycles, one MOVE ”and one“ TRAN. The timing is the same regardless of any T-RAM error.

The time signal T2 is a signal to the T / RAM address bar 38 (Fig. 11) for transmitting the virtual address signals from the C · bus 24 for indexing T / RAM 42. The bits F, WP and RP in the output of T / RAM are applied to the circuits. in Figs. 13 and 14 for producing error signals, and the output of circuit 60 (Fig. 15) is transmitted together with time signal T1 to T / RAM multiplexer 54. In the event of a T / RAM error, the virtual address signals are transmitted to the MAR multiplexer 52; otherwise, the page frame number signals (the physical addresses) are transmitted. The output of the MAR multiplexer 52 (FIG. 23) is loaded into the memory address register 28 at T2. Finally, the reference and change table 50 are updated at the next T1 (if no T / RAM error exists).

As described above, in the event of a T / RAM error, an error signal is transmitted to the control register 14 for triggering appropriate control signals for the error correction. One of the signals thus triggered is LT / RAM (charged T / RAM, Fig. 10) which, as described above, causes the page frame number signals to be loaded into T / RAM. The time course of loading an input into T / RAM 42 after a T / RAM error is shown in Fig. 23.

Then, the computer has performed part of a first user's program, the machine is switched to execute another user's program.

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This normally means that new data must be transferred from the files (secondary memory 20, fig. 1) to the main memory. A page table (for each segment in the other user's virtual address space) is constructed by the operating system for inserting the special page frames into the main memory into which the secondary memory pages are inscribed. These page tables are used to translate virtual addresses into physical addresses for the virtual memory, as seen by the other user. The page table of the previous user's system is no longer valid (since the other user's program or data is now placed in the page frames previously used by the first user), and T / RAM entries referring to the first page tables must be invalidated.

The operating system responds to this task switching by performing a number of cleaning operations, including activating the new page tables by inserting new segment identifiers from the main memory to the portion 36 of the stack 30 for instruction to the page tables. During the execution of such operations, the operating system clears the monitored inputs from T / RAM, as shown in FIG. 20, using the virtual addresses stored in the monitoring area 34 of the stack 30 in the manner described above. However, not all entries in T / RAM are invalid and those relating to the operating system segment (segment 0) remain as valid. Such operating system parts are, for example, a schematic module, a page creation module, file management measures and database management measures. In such cases, the segment identifier of the segment containing the module in question has a low-level monitoring bit, and as a result, no virtual addresses are stored in this segment in the monitoring area 34. Thus, no T / RAM entries for this segment are emptied in connection with with a task switch. According to the invention, only the entries from the page table of a monitored segment are invalidated when a new task is to be performed.

Various modifications of the invention may be made by those skilled in the art within the scope of the inventive idea set forth in the claims.

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