Synchronizing pulse trains

(24) Expiration date (62) Application number (86) International filing date (86) Filing date for European patent application (30) Priority information (11) Publication date 08-08-26 ^nummf,r 44Q gjQ

85-07- 1 4

84-01-13

84-01-13

The application has been submitted as a Swedish patent application

O completed international patent application with number □ converted European patent application with number

KB 3-A4 according to SIS 61 30 13 allf 138 83109 aa (71) (72) (74) (54)

Applicant Telefon AB LM Ericsson, Inventor LK I. Skoog, Farsta Ombud Gamstorp B

Designation Method for synchronization of telephone systems

126 25 Stockholm SE of pulse trains in a digital (56) Published publications SE 409 271 (H04L 7/04) SE 321 696 (H04L 7/04) (57) Abstract

The system includes a switch (EX) to which are connected a number of telephone sets (TA)> The switch contains a central processor (EXCP), a number of line cards each and an Inhaling a number of line circuits (DEC) for adaptation between the switch and the connected telephone sets. Each telephone unit in turn contains a line crete (DIC) in which i.a. encoders and decoders for PCM-encoded information words. The system is fully digitized and transmits digital information in a time-separated form between the telephone sets. In order to achieve accurate synchronization of the pulse train between the different units while simultaneously reducing the rising jitter, the unit (DEC) is equipped with a counter (CTPy) which, under the control of a signal, seeds a comparison circuit (CO) at certain times, and then resets start counting whereby synchronization signals are transmitted over a line to a receiving unit (DIC) in a telephone set. The reset pulse is generated by comparing a seed central processor (EXCP) in a channel register (CHR) inscribed channel number and the contents of a seed processor and an oscillator (XI) controlled, channel counter (CR). In the unit (DIC), the synchronization window is received in a circuit (DIR) consisting of a synchronization detector (SD), a primer counter (CTR) and a time position counter (CTP γ) which receives and transmits pulse signals under the control of an oscillator (X2). The synchronization window, according to the example, consists of a positive logic one signal and a negative logic one signal preceded by a certain number of logical zeros. During the -1 pulse zero counters and 1 the transition between positive and negative pulse in the synchronization signal, the fast derivative is used at the switch to resume counting (zero reset). In this case, a jitter is obtained which can reach a maximum of 0.25 us under the conditions given in the example. In the unit (DEC) there is a circuit (DER) with the same content as the circuit (DIR). The circuit (DER) receives pulse eggs from the telephone set and treats them in the same way as described for the circuit (DIR).

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The numbers mom parentheses indicate international identification code, INID code. Letter mom pin indicates international document code

8400170-0

TECHNICAL AREA

The invention relates to a method for synchronizing pulse trains in a digital telephone system.

BACKGROUND OF THE ART

When transmitting digital information over relatively long distances and at the same time a high information speed, the maturity soon becomes of the same order of magnitude, or greater, than the information time of an individual information. The running time is limited by the light speed which is in vacuum about 300 m / yus. For example, the maturity of a pair in a cable or a four-screw conductor can amount to 140 m / yus. Since the information time in communication systems with, for example, PCM transmission (Pulse Code Modulation) to a telephone device is of the order of yus 10 (microseconds) and the wiring lengths can often be counted in 1000s of meters, the maturities can easily reach the order of 10s microseconds. Therefore, in order for secure information reading to take place, some form of synchronization must be used.

A common method is to retrieve synchronization information from the information flow itself, for example, by designing the information in such a way that data can be extracted from the same to facilitate the sensing.

Typical such systems work with so-called Manchester code and its various embodiments, where, for example, the digital information is designed so that whether the information is a logical one or a zero 0, there is always a polarity change. This polarity switch is detected and utilized to correct the frequency of, for example, a PLL oscillator (Phase Locked Loop). In modern transmission systems of the so-called burst type, information is transmitted in one direction for, for example, 1/3 of the time and in the other direction for another 1/3, the remaining time 1/3 must be unused to compensate for the maturity of the line.

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DISCLOSURE OF THE INVENTION

The problem with systems utilizing the Manchester code is that in such a self-correcting device an error is more or less presumed, whereby an error voltage is generated in order to correct the frequency and, when the error is corrected, the error voltage disappears and a new error arises. The system thus gives a natural tendency for the frequency to swing around the correct one and therefore rarely is exactly right. In addition, the digital information is affected by the characteristics of the management and the sequence of logical 1's and 0's, this latter especially if the information is not continuous. These conditions mean that the sensors do not become accurate in time but vary somewhat so that so-called jitter arises. This jitter 10 must be poured within certain limits so that sensing errors are not obtained.

Problems with the use of burst systems are, in addition to the synchronization information mentioned earlier, missing during 2/3 of the time, also that the beginning of the information package must be determined with great accuracy. The packet is thus characterized by a period of time with no signal, after which the signals 15 appear. Regardless of whether the signals are then DC symmetric (alternating + lor and -or), the first signals will be different in magnitude and with displacement in the zero throughputs. The first pulse in a pulse train starts with the wire in sleep mode 0 volts. The second pulse, on the other hand, is affected by the residual voltage from the previous pulse. This means that each individual pulse is thus Z * · dependent on the prehistory.

The present invention is characterized by the claims and solves the emerging problems by providing a method for indicating the onset of the pulse path, providing a reliable sensing independent of the prehistory of each individual pulse, minimizing jitter, and making the sensing independent of the number of pulses in the pulse state.

DESCRIPTION

The method according to the invention is described in more detail with the aid of an embodiment with reference to the accompanying drawing in which

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Figure 1

Figure 2

Figure 3

The system comprising the device is a digital telephone system comprising a central switch EX in which, inter alia, includes a central processor unit EXCP, a number of line cards each containing a number of line circuits DEC for adaptation between the switch and a number of telephone devices TA connected thereto. Each telephone set in turn contains a line circuit DIC which includes, among other things, encoder and decoder for PCM-encoded information words. The system is fully digitized and transmits digital information in a time-separated form between the telephone sets. For synchronization of the system, i.e., the present invention, accurate high frequency crystal oscillators, sync detectors and counters are used to decompose the oscillator frequency.

An example of such a system can be cited a fully digital speed telephone system with both loudspeaker and low-voice function.

PREFERRED EMBODIMENT

In the telephone system shown in Figure 1, information is transmitted between, connected to a central selectorless switch EX, telephone sets TA, in digital time-split form. For transmission between switchgear and appliances, PCM, pulse code modulation is used.

A switch of the type specified contains a central processor EXCP with associated data and program memory, a number of line cards L each containing a number of line circuits DEC for connection to telephone sets TA each containing 25 a line circuit DIC which has, inter alia, the task to encode and decode the PCM information. The switch further contains a number of Thai control unit cards CX, each containing a number of speech control units SC. Each shows a system utilizing the method according to the invention shows a device for detecting the start time of a pulse train and for minimizing jitter and showing the time delay for a pulse train at certain specific points in the system and at a line length of about 850 m (6, us) .

The S4ÖÖ170-0 line card L and voice control card CX also contain its own regional processor RP.

The control information between the central processor and the regional processors is transmitted via a common control bus SB for the processors. The PCM-encoded information (number) between the devices is transmitted within the switch on a separate internal communication bus TB.

Figure 1 only shows the units in the system that are important for clarifying the synchronization procedure. A central processor EXCP with associated high frequency crystal oscillator is connected in the switch to a line circuit DEC. In the line circuit, a channel register CHR, a 5-bit channel counter CR includes a comparison circuit CO and a number of time slot counters for the transmitter and receiver directions of the line circuit. The line circuit DEC is connected to the additional line circuit DIC, which also contains the time slot counter and high-frequency crystal oscillator, via the two-wire connections to the connected telephone set TA.

The central time division comprises 32 channels each comprising two time slots. The time slots of the various channels are not tied to each other or to any function or unit, but can be used, for example, for a voice connection. For loudspeaker functions, for each device two time slots are required, one for information to the device and one for information from the device. Thus, for a complete speaker connection, four time slots are required.

In the case of low-voice call connection (handset lifting), two time slots are sufficient, one for each speech direction.

One of the central (common) time slots is arranged for transmitting tone signal, another for eg music during work. The digital transmission is done by means of the previously mentioned burst signaling, ie the digital signals to and from a telephone set are transmitted in groups, bursts, at different times, separated by breaks.

Such a complete transmission including breaks occurs 16000 times per second, giving a time frame of 62.5 yus (microseconds) and a frequency range up to a maximum of 8000 Hz. The process starts from the switch side by the line section

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8400170-0 sends two synchronization bits which are accompanied by PCM samples for speech and two data bits. With the guidance of the synchronization bits, the telephone apparatus sorts out PCM samples and data bits and acknowledges by sending corresponding information, ie synchronization bits, PCM samples and data bits back to the switch.

The signaling according to the invention is illustrated by the type of signaling called Ternary, that is, three different information states can exist namely positive pulse (+1), negative pulse (-l) or no pulse (0). Zeros in a pulse path are thereby indicated as no pulse (0) and ones are transmitted as alternating +1 or -1. Thus, in this type of signaling, the pulse mode can have a very varying appearance, thereby placing the greatest demands on synchronization and sensing. The repetition frequency has been chosen 16 kHz (64 yus) with 32 time positions (pulse width 2 yus) and with a maximum of 10 units in the pulse train.

In Figure 2, a time slot counter CTP (Time Position Counter) is shown, as in the example a 5 bit counter with the possibility to enter 32 different time positions TP. Counter 15 is powered by a signal of frequency 512 kHz. The drive frequency is generated from an oscillator XI whose output has a significantly higher frequency, according to the example 8 times higher frequency, ie 4.096 MHz. The oscillator operates a 3-bit primary counter CTR which divides the oscillator frequency by 8, whereby said drive frequency to the time slot counter CTP is obtained.

Figures 1 and 2 show the principle of synchronization of one unit DIC (the line circuit in the apparatus) at a long distance from a second unit DEC (the line circuit in the switch) and synchronization of two units DEC and EXCP located close to each other, respectively. The two latter units, as mentioned earlier, consist of a line circuit in the switch and the central processor. The beginning of a pulse path is characterized by two synchronization pulses, according to Examples -1 and +1, preceded by a number of zeros, forming a so-called sync window. A sync detector SD receives the sync window and detects the change from -1 to +1 in the sync signal. By utilizing two synchronization pulses, certain advantages are obtained. The first sync pulse is used to give the conduit a definite output 3θ value for the start of the second pulse and the second sync pulse is used to provide the fastest possible derivatives for the transition between the pulses. By utilizing the fast derivative, the transition from -1 to +1 can be accurately determined. During the duration of the -1 pulse, the sync detector SD resets both counters CTR and

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CTP, at the change, the zero position ceases and the counters can begin to count. The primary counter has 8 positions (0-7) and any of these can be used to operate the time slot counter CTP. The example assumes that position 1 is used.

Since there is no synchronism, the 1-position can occur immediately or after up to 0.25 µs (microseconds) after the start of the clock pulse, thereby creating a jitter. This jitter can, under assumed conditions, amount to a maximum of z0.25 yus. By the freedom to choose from 8 different modes for the operation of the time slot counter CTP, the effect of the management on the sync pulses can be taken into account ζ ~ -.

the counter CTP can be increased in time in the most advantageous way for subsequent pulses. Up to 8 different strobe pulses can be selected from the primary counter CTR.

Since these are separate for only 0.25 yus, the internal time delay in the circuits can even be taken into account.

In Figure 1, two units EXCP and DEC are shown which are assumed to be so close that propagation delay, i.e. the time delay for a signal transmitted from unit EXCP until received in unit DEC and vice versa, can be considered zero.

The figure further shows a unit DIC in a telephone apparatus, which unit is connected to the other units via a line and at a distance from them corresponding to a delay of 6 / US. The neighboring units EXCP and DEC are controlled by the same clock signals, in the figure represented by Channel Clock 20 and Channelⁿ0 RESET. The clock signals are generated in the central pocessor unit

EXCP using said crystal oscillator XI.

The system according to the example comprises 52 channels and in a channel register CHR is registered Ϊ which channel the unit DEC is to operate, by the processor EXCP entering one of the same free channel number in the register. Using the channel register CHR and one of the central clock and channel 0

The RESET pulse controlled 5-bit channel counter CR is generated in a comparator CO in a known manner a DEC transmit counter reset which resets a time position counter CTP-j. in the line circuit DEC. From said counter CTP, a pulse packet (burst) is transmitted via a longer line to the line circuit DIC which in turn is provided with a unit DIR containing a synchronization detector SD and a crystal oscillator controlled counter device CTP / CTR of the same type and function described for Figure 2. . The crystal X2 in the unit DIC is of the same type and frequency as the crystal X1 in the unit EXCP. The unit DIC returns a pulse train (a burst) to the unit DEC whereby a unit DER

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8400170-0 inclining an additional 32-position time position counter CTPP, a primary counter CTR and a synchronization detector SD, are activated and function as described in connection with Figure 2.

In accordance with Figure 1, the central processor splits the EXCP channels

TO-T31, wherein the processor considers the start of channel 0 as system time 0 (zero). The processor assigns the connected line circuit DEC a channel number indicating in which channel the circuit DEC is to operate. The processor accomplishes this by entering the selected channel number in the channel register CHR in the circuit DEC. For example, DEC channel number 14 is assigned, which means that the circuit DEC works against the processor EXCP in channel number 14. In this case, the start time of DEC is

T14. For example, another circuit DEC, which is controlled by the same processor, can work against the processor in channel number 20, thereby obtaining start time T20 as seen from the processor.

A processor EXCP itself operates with 32 channels according to the example, and against a number of line circuits DEC. Each circuit DEC generates 32 proprietary time positions TPOTP31 against the telephone set. Therefore, to refer to the terms channels (EXCPDEC) and time positions (DEC-DIC), the abbreviation TP stands for time positions. The circuit DIC is, as previously mentioned, the line circuit in the telephone set.

The circuit DEC considers the start time T14 (T20) as its own start time 20 TPO (zero) against the telephone.

According to Figure 1, channel 14 is recorded in the channel register CHR. Where the processor's EXCP timer slot counted to channel 0, a reset signal to counter CR in the line circuit DEC. The counter is reset and starts counting again under the control of the clock signals mentioned earlier. In the comparison circuit CO, both signals from the channel register and counter CR are compared, and where there is a signal output to the time position counter CTPy From the line circuit DEC a pulse train (burst) is transmitted via the line to the line circuit DIC in the connected telephone apparatus. As mentioned, the pulse train consists of two syncets accompanied by PCM information and data bits. Due to the running time, caused by varying lead length, the pulse train arrives at different times.

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In Figure 3, the transmission and reception time relationships in the system are shown at an assumed time delay between DEC and DIC of 6 yus. For synchronization, as mentioned, both the line circuits DEC and DIC contain equipment in accordance with Figure 2.

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Figure 3 shows how the line circuit DEC transmits a pulse path which is received 6 yus later in the line circuit DIC. Then, according to the example, a hold of 4 jus (2 time positions) is made to differentiate between the end of reception in DIC and the beginning of transmission from DIC. After this pause, the circuit DIC sends a pulse train in return to the circuit DEC which receives the pulse train another 6 yus later.

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As described, in circuit DEC upon transmission to the line a new start time TPO is generated. The line circuit DIC utilizes the polarity switching between the sync chains as a sync indication for its own start time TPI (the device start time) and then sends it back to the circuit DEC. Upon receiving in the circuit DEC, an additional start time TP2 is created since the pulse train then again passes through the line. When generating new start times, the corresponding counter is reset and, as described for Figure 2, the desired synchronization and reduction of the jitter is obtained. Thus, the device according to the invention provides, in a simple manner, a fast and secure synchronization by separately setting a number of counters for each burst and the received bursts in the circuits DIC and DEC to reduce the jitter. with a significantly higher frequency than that corresponding to the frequency for division into time positions.

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