Automatic gain control circuit

(54) Designation Circuit for automatic control of gain applied to an input signal (56) Published publications: - (57) Summary:

An automatic gain control circuit has a section for coarse analog gain adjustment, which provides stand-alone gain increments in dB, and a section for fine digital gain adjustment. The digital section provides gain adjustment through a final gain increment in dB to achieve the exact gain setting. The output of the digital section is squared and compared with a reference signal for deriving an error signal, the value of which is fed to means which iteratively determines the settings of the analog and fine digital increments to achieve the desired desired gain setting.

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iNlD code The letter within the pinch indicates international document code

7908627-8

IN

BACKGROUND OF THE INVENTION;

The present invention relates to automatic gain control (AFR) circuits and more particularly relates to an AFR circuit having both analog and digital gain adjustment parts. The invention finds particular application in connection with digital data modems.

In modem applications of the above kind, it would be desirable to utilize a section for coarse analog gain control to bring the gain within the range of an analog-to-digital converter circuit and to have a digital gain control circuit at the output of the analog-to-digital converter to provide a stable, accurate digital level modem circuits utilized. However, the provision of such an automatic gain control circuit has posed a problem in how to achieve co-operation between simultaneous operational analog and digital gain control sections in order to achieve smooth and rapid progress to the desired gain level.

SUMMARY OF THE INVENTION;

Accordingly, it is an object of the present invention to improve automatic gain control circuits. Another object of the invention is to provide an automatic gain control circuit having both analog and digital sections. Yet another object of the invention is to provide an automatic gain control circuit for use in a digital data modem that allows interoperable, fast-acting, exponential adjustment or adjustment of both digital and analog gain control sections.

In accordance with the invention there is provided an automatic gain control circuit having a section for analog gain adjustment and a section for digital gain adjustment and means for generating first and second control signals which cooperate to adjust the gain provided by both

POOR QUALITY

7908627-8 the analog and digital sections to achieve the desired overall gain. A further feature of the present invention is the provision of coarse incremental analog adjustment and fine incremental adjustment over a continuous gain region around the desired gain along with first and second control signals arranged in conjunction to control the analog and digital sections.

BRIEF DESCRIPTION OF THE DRAWING:

A preferred embodiment of a circuit according to the invention will now be described in detail together with the drawing, in which Fig. 1 is a block diagram illustrating the preferred embodiment of the invention, and Fig. 2 is a functional circuit diagram illustrating the structure and operation of the circuit. the control circuit of Fig. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT:

The preferred embodiment of the automatic gain control circuit of the invention shown in Figure 1 comprises gain sections 11 to a number of four. These gain sections provide analog gain of 8A, 4a, 2A and 8A, respectively. A, where A = 2.17 dB.

The analog sections 11 are coupled into or out of the path of the unregulated input signal through a four-bit number which is stored in a register 13 and allows for sixteen different gain combinations. Said number comes from a gain control circuit 15, which will be described later (Fig. 2). The four analog sections 11 provide the coarse AFR adjustment. The output from here is fed to an analog-to-digital converter 17 · The output from the analog-to-digital converter is multiplied by a factor fA in a multiplier 19, where f is in the range of -1 to +1. The multiplication factor fA is determined by a 10-bit digital word coming from the AFR control circuit 15 ·

The control circuit 15 for generating the four bits comprising the word for controlling the coarse automatic gain control and the ten bits comprising the word for controlling the fine automatic gain control is illustrated in Figure 2.

In Fig. 2, the output of the fine automatic gain control circuit is squared through a squaring circuit 23 and fed to a first buzzer 29, where a reference level is subtracted. The squaring circuit 23 could be a full-wave rectifier. Optionally, the output of squared 23 could be provided

7908627-8 is delayed and subjected to averaging by circuits comprising delay elements 25 and an averaging circuit 27, the output 28 of which can be fed therefrom to the first buzzer 29. The output of the first buzzer 29 is an error signal. This error signal is fed to a multiplier J1, where the error signal is multiplied by an AFR speed control constant K. At larger constant K, the AFR speed will be higher, but larger errors will be obtained. Similarly, at smaller K, the AFR speed will be lower, but smaller errors will occur. It is desirable that the constant K be relatively large during the Initial course or Pivot and that the constant is made smaller under the stable state. The output of the multiplier J1 is defined as a. The index n indicates the sampling time during which the variable to which it is assigned is generated. This output a_n is fed to a buzzer 27 and summed with a magnitude G_n for providing an output signal S_{n &lt;}

The output signal S_n is passed to a block j4, where two quantities G_{n +}and determined. The magnitude G_{n +}^ is equal to S_n - (S._n/ C) · C and the magnitude H_n = (S / c), where C is a constant equal to 0.25 and the expression (S_n/ C) defines the integer part of A_n divided by C. A magnitude exp (-G_{n + 1}) is then calculated and also constitutes the gain in the part which gives fine AFR, ie. the ten bits comprising the number in register 21 for the next sample.^Gn + 1 is the residue when S_n divided by C and exp (0.25) equals 2.17 dB. G_nis initially set to zero for n = 0.

A summator J6 subtracts from F_n for providing an output signal.F_{n + 1}, which is the four bit number which controls the analog section during the next sampling time. F_n is divisively equal to 15 for n = 0. The output F_{n +}js a sampling time of a delay element J7 is delayed to provide the output F_n, which is fed back as a second input to the buzzer j6. The output signal F_n from the delay element J7 is the number that adjusts the analog portion of the automatic gain control, ie. the four bits comprising the number in register 1J, during the current sample time.

Digital circuit elements for carrying out the functions of the elements shown in Figure 2 are well known. The preferred embodiment is preferably realized with a digital microprocessor. Such a realization is well within the scope of what ihckmarrm in the field in question can implement with the support of the present POOR QUAIOT

7908627-8 description. The operation of the control circuit 15 can be illustrated by an example.

Starting from a desired AFR output level of 0.5, the level of the reference input signal to sumer 29 is selected as the square of the desired value or 0.25. Other initial states are K = 1, F_THE = 15 and G_q = 0 and an incoming signal level of 0.02. With these conditions, the first three iterations of values ​​determined by the circuit of Fig. 2 are summarized in the following Table I.

Table I

<td></td><td>F n</td><td>^Gn</td><td>exp (C_n)</td><td>AFR out</td>

<td>n = 0</td><td> 15</td><td> 0,0</td><td> 1</td><td> 0,9</td>

<td>n =</td><td> 15</td><td> 0,06</td><td> 0,94176</td><td> 0,50667</td>

<td>n = 2</td><td> 15</td><td> 0,06671</td><td> 0,95546</td><td> 0,50528</td>

The example illustrates the initial setting of the coarse adjustment with subsequent fine-tuning of the digital AFR part. With greater deviation from the desired value, several iterations may be required to initially set the coarse automatic gain control and show fluctuations around the final value of the digital setting in exp (-G_n) can happen. It can be noted that the exponential value exp (-G_n) can be approximated by an exponential series such as? -G_n + (G_n)²/ 2 in block 59 The above circuit provides a number of desirable properties. The analog portion provides the necessary coarse adjustment to obtain the required resolution for operation of the analog-to-digital converter. At the same time, a stable level is achieved at the output of the fine digital AFR circuit, which allows associated modem circuits to work properly. The digital AFR portion is utilized to compensate for the uneven nature of the analog portion. A key feature of the operation of the circuit is a synchronization provided between the digital and analog parts in order to provide a stable output signal. In other words, adjustments work together to allow the analog and digital parts to act as an AFR circuit. The action of block 54 produces a 2.17 dB hysteresis effect, so that only the digital fine automatic gain control is operable in the stable state. The exponential feedback provides rapid attack on the AFR-just7908627-8 ring.

As will be readily apparent to those skilled in the art, it is possible to carry out many modifications and adaptations of the just described preferred embodiment within the scope of the invention, as is apparent from the appended claims.

7908627-8

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