Input output control logical device

(54) Designation: Controls for input / output devices

3) LP Vergari

Fla in a data processing (56) Published publications

7704959-1

The present invention relates generally to digital computer systems and more particularly to the interaction between peripheral input / output devices and a central unit of the computer system.

The control of the data transfer between the memory of the central unit and the peripheral input / output devices via an input / output collector or link can be performed in many different ways. Among the various types of input / output control relating to data transmission are: direct program instruction control for each data transfer, initiation of data transmissions by a central unit, after which subsequent data transfer is performed under control of the peripheral device without the use of the central unit, and logic for management of interrupt requirements from peripheral devices to inform the central unit of the status of the peripheral device. In these various arrangements, control mechanisms are included to allow peripheral devices to initiate interrupt management in the central unit by

7704959-1 direct information from the central unit about the device and status requiring management, or the interrupt requirement may request the central unit to initiate a call signal to all connected devices in series to later allow the transmission of information to the central unit, which identifies the device and status, which causes interrupt.

In systems which utilize direct program control for each data transfer between a peripheral device and the main memory, connection links are used which, in response to the program instruction, require sequential transmission of device address orders and / or data to the peripheral device.

In data processing systems which provide not only directly program controlled data transfers but also cycle loan data transfers, different types of program instructions are normally required. Although different types of initialization instructions are not required, different types of peripheral device control information are required, which must be identified by the peripheral device controller and handled differently. Thus, each peripheral device controller must have specialized logic. Furthermore, if the input / output control system must also be able to handle asynchronous interrupt service requirements on the part of the central unit, additional circuits must be provided in the peripheral device controller.

During cycle loan data transfer operations, when a peripheral device controller has been fed with sufficient information for initiating and controlling further use of the link collection line to control the memory unit independently of the central unit, some emergency states may occur before completing the data transfer, which require special processing of the data transfer from the central unit. .

Normally, input / output control systems, which are arranged to handle direct program control, cycle loan or interrupt requirements transfers on a common connection link, must handle each of these situations exclusively on the link collection manager, preventing any other type of requirement from being addressed.

In prior art systems, poll or call logic has existed for answering an unknown interrupt requirement, which signals the priority of the interruption requirement. In / out control logic responds with a serial call signal, combined with identification from the central unit of the priority of the interrupt requirement being called, to effect selection through a proper peripheral controller for later use of the link collection manager. The priority interrupt requirement set by a peripheral device

7704959-1 controller, can be modified by a central unit. However, in these prior art systems, the modification of the priority level of a peripheral device controller could only be effected when the device associated with the peripheral device controller was not occupied with a previous order. Further, prior art systems combining cycle loan data transfers with interrupt claims management have had to provide separate logic within a peripheral controller and input / device logic for the central unit to be able to perform poll calls for both types of requested communications.

Prior art systems utilizing a serial call signal for the purpose of selecting one of a plurality of peripheral device controllers, all of which request service, necessitate the use of logic within each peripheral device controller for propagating the serial call signal to successive devices. In these prior art systems, it is obvious that, if a particular peripheral controller or device is physically located at a distance from the input / output collector, a properly functioning call propagation would not be possible.

Given the aforementioned lack of flexibility and the cost of providing separate circuits, it is a principal object of the present invention to provide a serial call mechanism for an otherwise parallel input / output wiring line, in which the logic of the peripheral device controller and the input / output controller logic common to allow calls to be made by multiple devices with respect to either interrupt requirements or cycle data transmission requirements.

Another object of the present invention is to provide a series call mechanism in which proper propagation of call signals to all peripheral device controllers can be effected by physically removing alternating peripheral device controllers on the link assembly line.

The above-mentioned and other objects are realized by providing common circuits in the input / output control logic of the central unit and in the peripheral device controllers. The logic circuit in the input / output control logic receives interrupt requirements at various priority levels and cycle loan transfer requirements and selects a call regarding either a cycle loan transfer requirement that is signaled on a particular preamble requirement from the piper device controllers, or a interrupt order requirement at a certain interrupt demand level. If the I / O control logic has determined that the call signal to be propagated should refer to an interrupt requirement, the call identifier collection manager is encoded with information that identifies

7704959-1 the interrupt level to which the call applies. However, if the in / out control logic determines that a bicycle loan transfer requirement should be subject to a call, the call identification signal lines are fed with a predetermined code that identifies a call for bicycle loan transfers.

Receiving the call signal and identifying a cycle loan call identification along with a cycle loan transfer requirement in the peripheral device controller causes the first peripheral device controller to receive the call signal to answer the call, prevent further propagation of the call, and generate a call return signal to the call sign device. Prevention of further call propagation and generation of the call return signal may also occur when the call identification regarding a interrupt requirement corresponds to the current interrupt level of a peripheral device controller which had previously set an interrupt requirement for the input / output logic.

Physical removal of alternating peripheral device controllers can be accomplished by influencing each peripheral device controller to produce a call propagation signal to subsequent peripheral device controllers, which in practice are two separate call signals. A first of the propagated call signals is presented to the closest physically adjacent and subsequent peripheral device controller. The second of the propagated call signals is transmitted to the next (second) physical peripheral device controllers. Each peripheral device controller generates an internal call signal when it receives both the generated polling signals from a first, next succeeding peripheral controller and a call propagated signal from the peripheral controller closest to the first peripheral controller. If a peripheral device controller is physically at a distance from the link collection line, the call propagation signal line that has been eliminated, the call receiving mechanism in the subsequent peripheral device controller may be held at a level representing the normal reception of a propagated call signal.

The foregoing and other objects, features and advantages of the invention as defined in the claims below will become apparent from the following, more detailed description of preferred embodiments illustrated in the accompanying drawings.

Figure 1 is a block diagram showing the main components of a data processing system utilizing the present invention.

Figure 2 is a representation of the physical configuration of

7704959-1 a data processing system utilizing the present invention.

> Figure 3 identifies the wiring of an input / output (I / O) link (I / F) wiring conductor, which is the interconnecting I / O control (channel) logic of a central unit (CPU) and a peripheral device controller (PDCU) of in accordance with the present invention.

Figure 4 is a block diagram showing the main components of a data processing system's input / output control logic.

Figure 5 illustrates certain registers and data collection managers in a central unit which are needed for collaboration with and completion of the present invention.

Figure 6 shows some registers and collection managers in a central unit which are used in conjunction with the present invention for handling address information.

Figure 7 is a representation of a data processing system's program instruction and device control block (IDCB) for initiating input / output operations in accordance with the present invention.

Figure 8 is a representation of information in a device control block transmitted to a peripheral device controller, and the time adjustment at that time.

Figure 9 represents the interaction between and the content of a processing I / O instruction (I / O), a data control block (IDCB), a data control block (DCB) and data transmitted in accordance with the present invention.

Figure 10 is a representation of the contents of a data control block and a control word within a data control block stored in the main memory of a data processing system for controlling I / O operations in accordance with the present invention.

Figure 11 is an illustration of I / O link collection lines and timing, which occurs when transferring data on a cycle loan (C / S) basis between a data processing system's storage unit and the peripheral device controller in accordance with the present invention.

Figure 12 shows I / O link collection lines and timing for calling peripheral device controllers in and for initiating further communication on the link collection line in accordance with the present invention.

Figure 13 shows how a serial call signal is propagated from peripheral device controller to peripheral device controller when selecting a device to utilize the link collection conductor.

Figure 14 shows the most important components of the present invention for receiving call signals from a previous peripheral controller, responding via the link and signaling thereafter back

7704959-1 to the data processing system's input / output control logic.

Figure 15 shows the most important components of a peripheral device controller connected to an input / output link conductor according to the present invention.

Figure 16 is a block diagram of the most important components of the channel link logic connecting the link collection conductor to the peripheral device controller.

Figure 17 shows the main components of a microprocessor used in a preferred embodiment of the present invention as part of the peripheral controller.

Figure 18 shows in block diagram form the connections between the various data collection leads of a microprocessor and the I / O link within the device control logic of a peripheral device controller in accordance with the present invention.

Figure 19 is a detailed logic diagram of the manner in which a peripheral device controller initiates an interrupt requirement for a central unit utilizing the link collection conductor of the present invention.

Figure 20 shows how Figures 20A and 20B should be arranged to form a detailed wiring diagram of the manner in which a peripheral device controller activates one of a plurality of interrupt requirements inputs within an I / O interleaver according to a priority level and compares the current priority level for a device with caller identification signals received on the I / O interleaver from a central unit's 1/0 control logic.

Figure 21 shows how Figures 21A and 21B are arranged to form a detailed logic diagram of the call receiving, propagating and responding means within a peripheral device controller in accordance with the present invention.

Figure 22 shows how Figures 22A and 22B should be arranged to form a detailed logic diagram of the priority interrupt determination logic within the I / O control logic of the present invention.

Figure 23 shows how Figures 23A and 23B should be arranged to form a detailed circuit diagram for the call sequence control within the I / O control logic of the present invention.

Figure 24 shows how Figures 24A and 24B should be arranged to form a detailed wiring diagram of the link gate control within the I / O control logic of the present invention.

Figure 25 is a detailed logic diagram of the control established by error states in the link gate control within the I / O control logic of the present invention.

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Figure 26 is a detailed logic diagram of the link control control within the I / O control logic of the present invention.

Figure 27 is a representation of the content and interaction of chained data control blocks, data and residual status information from a peripheral device utilizing bicycle loans.

Detailed description.

Data processing systems

The overall environment of the invention is shown in Figure 1. The present invention is utilized in a data processing system containing a central processing unit (CPU) 30, a main memory 31 for storing data, machine instructions and input / output (I / O) control information, and I / O control logic (channel)

32nd The invention relates to the control of the transmission of data and control information to I / O devices 33 via peripheral device controllers or I / O additives 34 utilizing an I / O link (I / F) collector conductor 35 which connects the various units in parallel. and for transmitting data, address information and control information. Furthermore, a call signal is shown on a line 36 connecting the peripheral device controllers 34 in series and for selecting a particular I / O device 33 to form an addition to the I / O link 35 during a certain transmission cycle.

A physical representation of the data processing system utilizing the present invention is shown in Figure 2. The physical arrangement includes a power supply unit 37, a tripod or card archive 38, and a plurality of pluggable cards 39 which contain the circuits which form the various units of the data processing system.

Three cards 40, 41 and 42 include circuits which form the central unit 30. Various parts of the input / output logic 32 are distributed on the central unit cards. A number of memory cards 43 are plugged into the card stand 38.

The number depends on the amount of memory you want.

The I / O accessory 34 shown in Figure 1 is represented by each card in a selected plurality of cards 44. If it is desired to connect additional input / output devices to the system, an energy distribution and isolation card 45 may be included. The card 45 has the task of supplying energy to an additional rack via the in / out link lines 35 and isolating the components shown in Figure 2, should additional stands lose their energy and thereby normally render the I / O link 35 inoperative.

Card 42 is a read-out memory (ROS) card, which contains a microprogram control mechanism for the data processing system. Address (ADDR) card 41 contains all software accessible hardware such as, for example

7704959-1 data and status registers and form addresses which are used for access to the storage device 31 and the input / output devices 33. The data card 40 performs all counting and logic operations and provides data feed to and from the I / O link 35 and the memory unit 31.

Dänkledningar

Figure 3 shows the I / O control logic for channel 32 distributed between address card 41, data card 40 and read-out memory card 42. Furthermore, an I / O add-on card 44 of Figure 2 is shown for a peripheral device 33. Linkage conductor 35 in accordance with the present invention can accommodate an arbitrary number of different devices 33. However, in accordance with a preferred embodiment of the present invention, each I / O auxiliary board 44, representing a peripheral device controller, has common circuits shared between the channel logic 46 and a microprocessor unit 47. The common circuits include device logic 48 which depends on the particular device. 33, which is to be controlled.

The following processing of the operation of a peripheral controller 34 in accordance with a preferred embodiment of the present invention will describe the operation of a microprocessor 47. However, the common circuits 46 and 47 may consist of only combined and sequential logic.

There are three basic types of communication between an I / O device 33 and the I / O control logic 32 which, depending on the nature of the device 33, may require the use of up to 81 wires on the I / O link 35. Two types of communication are initiated by a program instruction identified as enable I / O (OIO). These two types of communication mainly concern data exchange and are identified as direct program control (DPC) transmission or cycle loan (CS) transmission. In the DPC transmission type, each 010 instruction provides for the transmission of an information record between the storage unit 31 and the IO device 33 in either direction. The cycle loan transfer type is initiated by the central unit 30 and relates to the transmission of I / O information to the peripheral device controller 34 for later use and for controlling the transmission of a plurality of data items between the memory 31 and the peripheral device 33. This transmission is independent of and concurrent with other operations of the central unit 30. The third type of communication required between the central unit 30 and the device 33 is the initiation of program interrupt sequences in the central unit 30 in response to a peripheral service 33 requirements for central unit service.

The cooperation between the I / O control logic 32, the link collector 35 and the peripheral device controller 34 to perform these types of communication will now be described in detail.

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Each of the 81 lines of the I / O link 35 is now briefly described using the representation in Figure 3. There are two bidirectional bus conductors, which are essential for the function, and these are a seventeen bit address bus conductor 49 and an I / O O-data collection conductor 50 with 16 bits plus two parity bits.

The control of communication on the I / O header 35 in response to the decoding of an OIO instruction in and for transmission of data or I / O control information on the data collector 50 requires the use of the address collector 49. Other link lines needed to control the transmission, are the address gateway 51, the address gateway 52, the condition code-gatherer 53, and the data strobe 54, which are activated in the correct order for controlling the communication. During cycle loan (CS) communication, data transfer is performed on the data acquisition manager 50 and memory 31 address information on the address acquisition manager 49 from the device controller 34. Additional wires within the link collection conductor 35 required for this type of transmission include a service gate signal line 55, a service gate return line 56, an input / output indicator line 57, a word / byte indicator line 58, and a four-bit status acquisition line 59 distributed among the readout memory card 42 and the address card 41. If the central unit 30 and the memory 31 have a memory protection mechanism installed, the condition code collector 53 is used during CS operations to transfer a memory protection key from the device controller 34 to the memory protection mechanism. Normally, the transmission of cycle loan information between the I / O control logic 32 and the device controller 34 comprises a single transmission, followed by the selection of another device for further operations. A further type of transmission can be applied and would be identified by a signal on a line designated group return 60. The signal on group return line 60 establishes control in both the device controller 34 and the I / O control logic 32 to allow, in response to a selection of device 33 multiple transfers of cycle loan information to the I / O collector 35 before selecting another device.

A third basic type of communication contains the requirement to signal to the I / O control logic 32 that a certain device 33 desires to interrupt the central unit 30. The link 35 lines, which are primarily relevant, are a requirement-gathering conductor 61 and a call identifier collection conductor 62. Specifically, a device control unit 34 is assigned a certain priority interrupt level by means of a preparation order. The designated interrupt level can be one of four different levels, though

7704959-1, within the scope of the present invention, there is room for up to 16 different levels. When a device 33 requires interrupt service, a portion of the channel link logic 46 in the peripheral device controller 34 will activate a certain determined by the four lines within the interconnector 61 and indicate an interrupt requirement. The certain determined by the wires within the collector conductor 61, which is activated, is related to the assigned priority interrupt level. An additional lead in the collector conductor 61 is identified as at 16 and is activated to inform the I / O control logic 32 of a transfer requirement from a device 33 utilizing the cycle loan transfer form.

When a particular device 33 has signaled either a priority interrupt requirement or a cycle loan requirement on the assembly line 61, the interrupt control logic in I / O control logic 32 and the central unit 30 determines which of a number of priority levels or cycle loan requirements that can be recognized for establishing connection between the I / O control logic 32 and the device 33. The call identifier header 62 is coded with binary information to indicate which interrupt priority level is subject to recognition, or a certain binary code is signaled on the call identifier header 62 indicating that a cycle loan requirement is being recognized.

As part of the selection of a device 33 to be allowed to be connected to the I / O header 35 in response to an interrupt requirement or a cycle loan requirement, the I / O control logic 32 generates a call signal 63 and a call head signal 64. The call signals 63 and 64 is propagated in series through all device controllers 34, which are connected to the link collection conductor 35. As part of the device selection for use of the bus conductor 35, the call and call head signals 63 and 64 interact with the coded information on the call identifier bus 62 to cause a particular device controller 34 to be selected. When a peripheral device controller 34 identifies a call identifier on the collector conductor 62 that corresponds to its current priority cut-off level, or it requires cycle loan transmission and identifies the particular identification code and also receives the call and call head signals 63 and 64, selection is made and this / fact is returned. the control logic 32 on a call-back signal line 65.

A device controller unit 34 receiving the call and call head signals 63 and 64 provides, in the absence of identification of a correct code on the call identifier header 62, that the device controller 34 propagates the call and call head signals 63 and 64 to subsequent peripheral device controllers 34.

7704959-1

Additional signal lines within the link collector conductor 35, which have not been discussed previously and do not form part of the present invention, are included in the preferred embodiment of the I / O collector conductor 35. These wires comprise a stop or machine control signal line 65 for stopping a device, previously started, two wires 66 which are used for control and transmission during an initial program load from a device 33 to the memory 31, power supply to reset line 67 to cause all logic in device controllers 34 to be restored to a known state and a system reset line 68 to establish known states in response to central unit control.

In the remainder of the description and in the remaining drawings, the signal lines and collector conductors are identified as shown in Figure 3.

All references to a particular binary bit on a larger pool leader will be identified with pool leader numbers, hyphens and bit numbers. For example, the lead designated 16 on the header 61 will be identified as 61-16.

CPU - I / O control logic, general description

The main functional components of the I / O control logic 32 of Figure 1 are illustrated in Figure 4. A preferred embodiment of the present invention can be used in conjunction with a central unit 30 which has a logic mechanism to indicate the level of significance for a particular program which is below execution in the central unit 30. Any requirements for executing a program with more or less significance than the current level will determine the response of the processing unit 30 to such a requirement. As part of the I / O control logic 32, interrupt logic is available to compare the significance of an interrupt requirement from I / O devices signaled on the collection line 61 to the significance level of the current program in processing unit 30 indicated in a current-level register.

70th As with many other data processing systems, the ability of a particular interrupt to enter into force can be modified by using an interrupt mask contained in a register 71. The contents of the current-level register and the interrupt mask 71 can be modified by data on the central unit data collector 72 in accordance with programmed instructions. . In accordance with the settings of the current-level register 70 and the mask 71 as well as the level of the interrupt requirement of the interconnector 61, the readout memory control of the central unit 30 on a line 73 can be made aware of the requirement to influence the central unit 30 to interrupt the function at the current

7704959-1 level and initiate a break.

After necessary internal functions in the processing unit 30, the readout memory control mechanism will return a signal on line 74 indicating that a interrupt or cycle loan requirement specified on the collector conductor 61-16 may be recognized.

At this time, the central unit 30 and thus programs stored in the memory 31 do not know the identity of the particular device which has set the requirement which has been recognized. Therefore, the I / O control logic 32 further includes a call sequence control mechanism 75 which initiates a call signal on line 63 along with coded information on the call identifier header 62, which indicates whether a cycle loan requirement is being met, or identifies a certain priority interrupt level, which is acknowledged. In response to a signal on the call return line 65, indicating that a device 33 has responded to the call signal 63, the call sequence control 75 initiates the required signal exchange between the I / O control logic 32 and the peripheral device controller 34.

The control of the transmission of signals and the response thereto in the I / O control logic 32 is performed within logic equipment called the link gate circuit 76. If, as previously mentioned, a call sequence was initiated due to a break or cycle loan, the signal lines which are primarily activated and answered in the link gate 76 , the service gateway 55, the service gateway 56, and the data flow 54. If the selection has been made for cycle loan transfer, varying cycle loan status information on the collector conductor 59 is transmitted to the peripheral device controller 34, which information indicates different conditions for the cycle loan operation.

If the link gate controller 76 is to initiate and control information transmission, a signal on line 77 will be received from the instruction register in the central unit 30, which signal indicates the decoding of an instruction to enable I / O. Response to the signal on line 77 requires activation of and response to signal line address gate 51, address gate return 52 and data flow line 54. Further, responses to each OIO instruction are signaled from the address of the addressed peripheral controller 34 on condition code acquisition conductor 53, which information is entered into latches 78 and presented to the level status records in the central unit 30 on line 79.

If bicycle loan transfers take place, the memory protection key is sent to the memory protection mechanism on line 80.

7704959-1

The link control control logic 81 responds to and generates various signals which indicate the accuracy of the I / O control logic sequence function on a line 82, responds to other I / O device related errors on the I / O control line 83 and answers a signal on a line 84 which indicates that a parity error was detected during a cycle data transfer. The designation PSV refers to the central unit status word in the central unit 30. PSV can be detected by the program control for monitoring and indication of various errors and exceptions within the data processing system.

Control of the timing between the I / O control logic 32 and the memory unit 31 generally occurs on lines 85. The completion of an I / Sequence is signaled to the central unit 30 on a line 86, and the control of the gate circuits within the central unit designated A, B and C, which is needed to perform data transmission, signaled on three wires 87. The decoding of a stop I / O instruction at the central unit 30 is signaled to the link gate control circuit 76 on a line 88, and any requirements for resetting the I / O control mechanism are signaled on a line 89 from the central unit 30. An eventual parity error is signaled which is detected on the link when transmitting data to the memory unit 31, on a line 90. Various other lines to and from the central unit 30 have been included in Figure 4. The function of the wires is evident from the names, and no further description for the sake of the present invention is justified.

Figures 5 and 6 show different registers and collection managers within the central unit 30 for performing I / O operations. All displayed conductors and registers contain 16 binary bits. A number of other units are connected to the central unit collection manager 72, for example, the counter / logic unit, the local memory and the additional registers, which primarily have to do with the data processing functions.

Data from memory 31 is received on a collection line 91 and inserted into the memory on a collection line 92. Data received from memory 31 is received when it is to be used mainly within the central unit 30, in a central unit memory data register (CPU SDR) 93, and when data is transmitted. between peripheral devices 33 and memory 31 during cycle loan operations, it is entered into a cycle loan memory data register (CS SDR) 94.

Also shown in Figure 5 is an operating register 95 which receives program instructions from memory 31 on the collector conductor 91 and CPU SDR 93, which instructions are to be decoded to control the system's functions. Of particular importance to the present invention is the decoding of an instruction called activating I / O (OIO).

7704959-1

When the ΟΙΟ instruction is to perform a direct program controlled transfer of data from the memory 31 to a peripheral device 33, the data will be received from the memory 31 of the collector conductor 91, inserted into the CPU SDR 93, transferred to the central unit collection conductor 72 on an additional collector conductor 96, is inserted into one of the CPU registers 97 and presented to the I / O data acquisition manager 50 on a collection manager 98 in response (via line 99) to the activation of the IF gate A in response to control from the I / O control logic 32. Direct program control of data transfer from an I / O device 33 to memory 31 would be performed by presenting data on the I / O data collector 50 to the central unit collector 72 by activating gate circuits represented at 100, inserting the data into the CPU SDR 93 from a collector. 101 and transmitting the data to the memory 31 of the collector conductor 92.

Transmission of data during cycle loan operation from I / O device 33 to memory 31 includes transferring data from I / O data collector conductor 50 to CS SDR 94 on a collector conductor 102 by activating (via line 103) the IF gate circuit B followed by transferring the the data from the CS SDR 94 to the memory 31 of the collector conductor 92.

Cycle loan output transfers would include transferring data from memory 31 of collector conductor 91 to CS SDR 94 with subsequent activation (via line 104) of IF gate C for presenting the data to a collector conductor 105 for the I / O data collector conductor 50.

The generation of parity bits 106 to be inserted among data from I / O data acquisition conductor 50 or the signaling of parity errors on line 84 is accomplished in link parity control / generator 107 during I / O operations.

Figure 6 shows the collection conductors and central unit registers required for transferring address information between I / O devices 33 and memory 31. Addresses are presented to memory 31 on a collection conductor 108 from either a CPU Memory Address Register (CPU SAR) 109 or during cycle loan transfers from a bicycle lock memory address register (CSS AR) 110. As part of the present invention, selection of a particular I / O device 33 and transfer of orders to this device is effected using the I / O address acquisition manager 49. This information is presented to the I / O address acquisition manager 49 from an additional CPU register 111, which receives the information from the central unit collection manager 72.

OIO-IDCB-DCB shape and timing

Figure 7 shows the two-word (32-bit) OIO instruction activating I / O, which is decoded in the operation register 95 of Figure 5

7704959-1 and initiates all I / O operations from the central unit 30. It is a privileged instruction and can only be retrieved in monitor mode.

If this instruction is retrieved in problem state, a privilege infringement program check is established, and a class interruption is made.

The effective address generated by this instruction points to and addresses a device control block (IDCB) in memory 31. IDCB contains an order field (bits 0-7), device address fields (bits 8-15), and the direct data field (bits 16-31). ).

In the order field, the first hexadecimal number (bits 0-3) identifies the order type, and the second hexadecimal number (bits 4-7) is a modifier. The order types are: read, read ID, read status, write, prepare, control, device reset, start, start cycle loan status and stop I / O.

The device address field contains the address of the device 33. The addresses of the device 33 are selectable through switches or connectors on each I / O accessory board 34.

For direct program control (DPC) operations, the direct field of IDCB in memory 31 contains the word to be transferred from memory to I / O device 33 or the word from device 33 to be stored in memory 31. For cycle loan operations, it contains direct field address in memory 31 for a device control block (DCB).

The read order transfers a word or byte from the addressed device 33 to the direct field word in the IDCB. If a single byte is transmitted, it is placed in bits 24-31 within the data word. Read ID command transfers an identification word from device 33 to the direct field of IDCB. The device identification word contains physical information about the device and is used in diagnostic programming to set up a system configuration. This word is not related to the interrupt ID word associated with interrupt processing.

The read status order transfers a device status word from device 33 to the direct field of IDCB. The content of the status word is device dependent.

The write order transfers a word or data bit group to the addressed device 33 from the direct field of the IDCB. If a single byte is to be transmitted, it is placed in bits 24-31 of the data word, and bits 16-23 are left unanswered.

The preparation order transmits a word to the addressed device 33, which controls its interrupt level. The word is transferred from the second word in IDCB, where bits 16-26 are zeros, bits 27-30 are a

7704959-1 level field, and bit 31 is an I bit. A priority interrupt level is assigned to device 33 by the level field. The I-bit (device mask) controls device interrupt capability. If the I bit is equal to one, the device is allowed to cancel.

The control order initiates a control action in the addressed device 33. A word or byte group transfer from the direct field of IDCB to the addressed device may or may not occur depending on the device requirements.

The device reset order restores the addressed device 33. A pending interruption from this device is reset. The device mask (I bit) does not change.

The start order initiates a cycle loan operation for the addressed device 33. The second word or direct field in the IDCB is transmitted to the peripheral device controller 34. It contains a 16-bit memory address for a device control block (DCB) to be used by the peripheral device controller 34 for controlling further operations. .

The order cycle loan status order initiates a cycle loan operation for the addressed device 33. Its task is to collect status information in relation to the previous cycle loan operation. The direct field of the IDCB is transmitted to the peripheral device controller 34 and contains a 16-bit address for a DCB.

The stop I / O order is an I / O control logic 32-directional order, which causes all I / O activity on the I / O link 35 to stop. No data is associated with this order. All outstanding device interruptions are reset. Device priority interrupt level instructions and device masks (I bits) remain unchanged.

Figure 8 shows the contents of register 97, figure 5, and register 111, figure 6, and the timing of the signals on different wires within the link 35. The figure shows what happens initially when an OIO program instruction is decoded, whether for DPC -reading or writing, transferring the DCB address for cycle loan operations or transfer of interrupt level codes for a preparation order. The data collection manager 50 is activated with the data transmitted between the device 33 and the direct field within the IDCB in the memory 31, which was addressed by the enable I / O instruction.

Address collection leader 49 contains in bits 0-15 the first word of IDCB. The address gathering leader 49 is active prior to activating the address gate 51 and up to the passivation of the address gate return 52. Similarity between the wired device address and bits 8-15 of the address gatherer 49 with bit 16 constituting a binary one constitutes initial selection of a peripheral device controller 34.

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Bit 16 is added to the address gathering leader 49 by the link gate controller 76 of Figure 4 from a decoder 112 to distinguish the use of the address gathering leader 49 for I / O operations as opposed to other operations using this address gathering leader.

The signal on the address gate 51 is the output tag used to request the device 33 to answer the initial selection and begin the operation specified by the order (bits 0-7 the address collection line).

The signal on the address gate return 52 is the tag established by the peripheral controller 34 to notify the I / O control logic 32 that it has received the signal on the address gate 51, identified its address, and activated status information on the condition code acquisition conductor 53. This tag must occur within a certain time limit for the tag pulse on the address gate lead 51 from the channel output is considered. If not, condition code 0 is returned to the I / O logic 32, and the sequence is terminated. The signal level on the address gate 51 falls and the address acquisition 49 is reset.

Condition code-gathering conductor 53 is a three-bit field which is binary coded. The input / output device 33 transmits status to the channel of this header during the address gateway return tag time. The condition code bits are placed in the current-level status register (LSR) within the central unit 30. The condition code values ​​and meaning are shown in Table I.

Villkorskodvärde

7

Meaning

Device not connected Busy

Busy after reset Order rejected Rejection necessary Link data control Controller busy Satisfactory

On the data flow circuit 54 there is an output signal generated by the I / O control logic 32 and may be used by the data recording device transmitted thereto. The signal of the data flow line 54 falls as the signal of the address gate 51 falls.

Figures 9, 10 and 11 facilitate the description of further details of the cycle borrowing / exit operations. In Figure 9, the decoding of an OIO instruction with memory address 200 receives the central unit 30

7704959-1 to address and from location 200 in memory 31, access the two words of IDCB 113. The IDCB is transmitted to the peripheral device controller 34 selected by the device address portion of the IDCB in accordance with the sequence shown in Figure 8. The IDCB direct field identifies and provides the location address of a device control block (DCB) 114 in memory 31. The order cycle loan or start cycle loan status is decoded in controller 34 and initiates a first cycle loan operation using address information 500 into memory 31 for transferring DCB 114 to controller 34.

The DCB content identifies the address in memory 31 that has to do with the data transfer, and as shown in Figure 9, it is the address 800 in memory 31, thereby defining a data area 115. The amount of data to be transmitted is specified by a byte count field. Upon completion of the transmission controlled by DCB 114, an additional DCB, identified as a linked DCB 116, can be transmitted to controller 34 to provide additional control for the previously selected peripheral device 33. As illustrated in Figure 9, DCB 114 contains control information , which provides the address in memory 31 of the chained DCB 116 located in memory 31 beginning at address 600.

During cycle loan operations, each of the 8 words forming a DCB is transferred to the previously selected controller 34 on a cycle loan requirement basis. Figure 10 shows the contents of a DCB which is either housed in memory 31 or received by a controller 34 in response to the utilization of the IDCB information, which in turn is transmitted in response to the 010 instruction.

DCB is an 8 word control block, which is located in the memory 31 monitoring area.

It describes the specific parameters for the cycle loan operation. Controller 34 retrieves DCB using memory protection key 0. The contents of the control word within each DCB are described below.

If bit 0 is equal to one, a DCB chain operation is indicated. After satisfactory completion of the current DCB operation, the device makes no interruption (except PCI interruption). Instead, the device retrieves the next DCB in the chain.

If bit 1 equals one, the device presents a programmed controlled interrupt (PCI) upon completion of DCB retrieval. A pending PCI does not inhibit data transfers associated with DCB. If PCI is pending, when the device encounters the next interrupt causing state, the PCI state is discarded by the device and replaced with the new interrupt state.

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The setting of the bit 2 notifies the device of the data transmission direction. 0 = outgoing (main memory device) and 1 = input (main memory device). For bidirectional data transfers during a DCB operation, this bit must be set to one. For control operations without data transfer, the bit must be set to zero.

If bit 3 is equal to one, the data transfer takes place in group mode. This mode attaches to the device the channel and the I / O link until the last data transmission associated with this DCB has been completed.

If bit 4 equals one, an incorrect length record is not reported. The device continues the operation. The error length classes are: 1) a record that is longer than the specified value, and 2) a record that is shorter than the specified value. Incorrect length recording can be suppressed for one or both classes depending on the individual device.

The bits 5-7 are the bicycle loan address key. This key is presented by the device during data transfers. It is used to secure memory access authorization.

The bits 8-15 can be used to describe functions which are unique to a particular device.

Parameter words 1-3 are device dependent control words and are executed as required. If suppress incorrect length (SIL) is used by a device, parameter word 4 specifies a 16 bit memory address, called the status address. This address points to a residual status block which is stored when the following two conditions are met: 1) The SIL bit (bit 4 of the DCB control word) is set to 1, and 2) all data transfers for the current DCB have been completed without error.

The size of the residual status block varies from one to three words depending on the individual device. The first word contains the residual bit group sum. Additional words (maximum two) contain device-dependent status information.

If incorrect length suppression is not utilized by a device, the device parameter word 4 in its meaning is device dependent and has the same meaning as the parameter words 1-3.

If the DCB chain bit (bit 0 in the control word) is equal to one, parameter word 5 specifies a 16 bit master memory address for the next DCB in the chain.

If chain procedure is not indicated, this parameter word is device dependent.

The sum word contains a 16-bit integer without a sign, which represents the number of data bit groups, which will be transmitted for the

7704959-1 current DCB. The sum is specified in bytes with a range between 0 and 65 .535. It must also be smooth for starting the cycle loan status operation.

The data address word contains the starting master memory address for the data transfer.

The bicycle loan mechanism allows data service to or from a 1/0 device 33, while the central unit 30 performs other processing. This overlapped operation allows the initiation of multiple data transfers of an OIO instruction. The central unit executes the OIO instruction and then proceeds processing the instruction stream, while the I / O device borrows master memory data cycles when needed. The operation always ends with a priority break from the device. A call tag 63 is generated by the channel to resolve a competitive relationship between multiple devices requesting bike loan transfers. The call tag also resolves competition for priority interruptions at the same level.

All bike loan operations have certain capabilities, based on the design of the device:

1st group mode

2nd Order chain a

3rd Data chain a

4th Program Interrupted (PCI)

5th Memory addresses and data transfers bit by bit or by word.

All bike loan operations end with a priority break.

The Bicycle Loan Start Order is for data transfer. The Start Cycle Loan Status Order is intended to provide residual parameters from the device if the previous Cycle Loan operation is terminated due to an error or an exception condition. The DCB form is the same as for a normal cycle loan operation with the words 1-5 set to zero.

During start cycle loan status operations, data is transferred to main memory 31 beginning at the data address specified in DCB. This data consists of residual parameters and device-dependent status information. The first word transmitted contains the main memory address of the last initiated cycle loan transfer attempt associated with a start order. If an error occurs during a start cycle loan status operation, that address does not change. The residual address can be a data address, a DCB address, or a residual status block address and is reset solely by a power-to-reset. It is updated to the current bike loan memory address after performing bike loan transfers. For word transfers, the residual address points to the high position byte in the word.

7704959-1

Device reset, stop I / O, machine control and system reset have no effect on the residual address in the device.

The second transmitted status word contains the residual bit group sum of a device. The residual bit group sum is initiated by the sum field in a DCB associated with a start order, and is updated as each data bit group is successfully transferred through a cycle loan operation. It is not updated by bike loan transfers to the residual status block. The residual bit group sum does not change if an error occurs during a start cycle loan operation. It is restored by 1) power-to-reset,

2) system reset, 3) device reset, 4) stop I / O and

5) machine control condition. The content of the device cycle loan status word 1 is device dependent if the device does not: 1) apply suppressor incorrect length (CIL) or 2) stores a residual bit group sum as part of its cycle loan status.

Other device-dependent status words can be transmitted depending on the device type. Two states can cause bits to be set in the device-dependent status words.

1st The execution of an I / O order, which causes an exception interruption.

2nd Asynchronous states of the device, which indicate a fault or an exception.

The pieces are reset as follows:

1st For the first state mentioned above, the bits are restored by the acceptance of the next I / O order (except start cycle loan status), which follows the exception interrupt. These bits are also reset by a power-to-reset, a system reset, or execution of a stop I / O order.

2nd Second, the bits are restored on a device dependent basis.

Figure 11 shows the utilized link 35 lines and the timing of cycle loan operations. Prior to this operation, the device had sent a cycle loan claim (bit 16 on the claim-collection conductor 61) to the I / O control logic 32, which corresponds to the call sequence, and this device answered this call.

The service gate lead 55 level is raised by the I / O control logic 32 to indicate to the device 33, which answered the call 64 and signaled call return 65, that data transfer can begin.

When the device detects the signal on the service gate 55, it sends a signal on the service gate 56 to channel 32

770 / 4959-1 to indicate that it has placed the necessary data and control information on the I / O link 35. Data provided by the transmission device is activated at the latest on the pulse rise on this tag line. The level of this tag line may first fall at the pulse drop on the service gate 55 and the data strobe 54 as shown at the output of the 1/0 device.

The address acquisition manager 49 contains the memory 31 address utilized for the data word to be transmitted. The contents of the address collection manager are enclosed to the cycle loan SAR 110 within the address card 41. A memory cycle takes place, and the word is placed in the cycle loan SDR 94. The data collection manager 50 contains the word that is transmitted.

The condition code-gathering manager 53 contains the address key to be used during access to the memory 31. The condition-code bits 0, 1, 2 correspond to bits 0, 1, 2 of the address key. This bus conductor is activated as the pulse rises on the service gate return line 56 and is kept activated until the signal falls on the service gate line 55.

The data flow 54 is an outbound tag line and can be used by the device to record data transmitted to it. The signal on the data flow line 54 falls in connection with the signal drop on the service gate 55.

The status acquisition line 59 is utilized by the I / O control logic 32 to signal to the controller 34 in the event of a fault detection during cycle loan operations. The pieces on this collection line have the following

<td>meaning:</td><td></td>

<td>Bit 0</td><td>Memory data account11</td>

<td>Bit 1</td><td>Invalid memory address</td>

<td>Bit 2</td><td>Security checks</td>

<td>Bit 3</td><td>Länkdatakontro11</td>

<td>About this</td><td>collectors are activated, the device keeps information ·</td>

tion for presentation in an interrupt status bit group at interrupt time. The cycle loan operation is terminated and the device presents a final break.

If the device had already indicated cycle loan requirements for the next transfer or is in group transfer mode, it must complete an additional service via the link. This service is a blind cycle, at which no device-based parameters are updated or no status bits are accumulated.

If the input / output indicator tag lead 57 has a zero, I / O control logic 32 is indicated that the function originates from memory 31, while one indicates an input value to memory 31.

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When the word / byte indicator tag lead 58 has a zero, I / O control logic 32 is indicated, that a word transfer should take place, and one indicates a byte transmission.

Call

Figures 12 through 14 generally illustrate the call process in accordance with the present invention. The call logic is common to the selection of peripheral device controllers 34 in response to either interrupt requirements or cycle loan requirements. In accordance with the sequence shown in Figure 12, the claim collection conductor 61 is activated by any peripheral device 33 on the link collector conductor 35, which requires interrupt handling or use of the collector conductor 35 for cycle data transmission. The line designated as bit 16 within the claim collection conductor 61 is activated whenever a device requests cycle-rate data transmission. Remaining wires within the requirement-collection conductor 61 are each associated with a certain interruption level. The activation of wires in the claim-collection conductor 61 is at a constant value, as long as any device requests service for interruption or cycle loan transfer.

At the time when the I / O control logic 32 determines that one of the requirements of the claim-collection conductor 61 is to be acknowledged, the signal lines within the call identifier collector 62 are activated in a coded manner to indicate to all devices that a call and selection process is during initiation either for cycle loan transfers or interrupt handling at a certain interrupt level identified by the call identifier collection manager 62. After the bus conductor 62 is activated, a call signal 63 is generated in series to all peripheral controller 34 of the bus conductor 35 to resolve competition between controllers 34, which request interruptions at the same priority level and cycle loan requirements. Each controller 34 receives the call tag 63 and propagates it to the next controller 34 by transmitting the call propagation, if the device fails to answer the call. If a particular controller 34 has requested service of the type identified by the Poll Identifier Conductor 62, it responds with the call return signal on line 65, and the call signal 63 does not propagate to any additional controller 34.

Figure 13 shows three peripheral device controllers 34, all of which have pending interruptions. The first device indicates a requirement for interruption at level two, while the remaining devices require interruption at level one. The call identifier header 62 is coded to specify a call for any device that sets a requirement at level one. Since the call identifier collection manager 62 does not

7704959-1 responds to the requirement at level two of the first device, the call signal 63 will propagate to the next device.

The first device, indicating a level one requirement, answers the call and suspends the call propagation signal to the next devices. At the same time, the first level one device generates the call return signal 65 to inform the control logic 32 that the call has been answered. The I / O control logic 32 reacts with service gate signal 55 Fig. 4, and the device responds to service gate signal 55 with service gate signal 56 and starts utilization of the link collection conductor 35.

As shown in Figure 13, the call signal that is propagated in series from device to device is in practice two separate signals, called call 63 and call head '64. The internal logic for each of the peripheral device controllers 34 generates an internal call signal in response to the reception of a signal on both the call input line 63 and the call main input line 64. This arrangement permits proper operation of the call mechanism even though a particular peripheral controller 34 is physically remote from the link assembly conductor 35. In the extreme case, each peripheral controller 34 is a remote unit.

Figure 14 shows further details of the internal logic of the peripheral controller 34 used in receiving the call signals 63 and 64 and generating the call return signal 65. An AND circuit 117 receives both the call signal 63 and the call main signal 64, which occurs on a first and second call signal. a second entrance. The output of AND circuit 117 on line 118 is the internal call signal. An AND circuit 119 and a comparator circuit 120, based on the interrupt of the present device, determine the level or cycle loan requirement indication of a conduit 121 and the coded information on the call identifier conductor 62 whether or not the present displayed device responds to the call or generates a call return signal 35 from the AND .

The output of either comparator circuit 120 or AND circuit 119 at AND circuit 122 together with an internal call signal 118 gives rise to call return signal 65 and blocks the function of call propagation logic to a next device.

AND circuit 117 has at its first and second inputs a resistor 123 which is connected to a positive voltage. The call line 63 and the call main line 64 are normally maintained at negative, passive levels in the absence of the respective signal generation. If the preceding peripheral device controller 34 was removed from the link assembly conductor 35, the resistor 123 to the positive voltage source would hold

7704959-1 the first input to the AND circuit 117 at a positive level indicating a normal call signal on line 63. At this time, reception of the call head signal on line 64 comes from a controller 34 closest to the controller removed from the link collection conductor, to be combined with the retained first input to the AND circuit 117 and give rise to the generation of the internal call on the signal line 118. If the peripheral device controller 34 generating the call head signal 64 was removed from the interconnector 35, the second input to the AND circuit 117 would be retained and this AND circuit would respond to the call signal 63 from the previous device controller 34.

Peripheral device control unit

Figure 15 shows in some more detail the arrangement of the main parts within a peripheral device controller 34 of Figure 3. Channel link logic 46 is connected in parallel with other channel link logic to link 35 and also receives the serial transmitted call signal 63. In some cases, channel link logic 46 may contain all of the combined and sequential logic required for direct control of a device 33. However, in a preferred embodiment of the present invention, the base control for the peripheral device controller 34 is performed by a microprocessor 47, which has its own memory 124 for program, data, and peripheral device control information. The transmission of data, control and sensing information is performed by the data collection manager-125 of the data processing unit 47, data collection manager -in 126 and address collection manager 127. The instruction set of the microprocessor 47 includes OP codes and address information, the address information of the collector conductor 127 identifying particular registers, trigger circuits, latch circuits, and gate circuits within the peripheral device controller unit 34 for execution or sensing.

Figure 16 shows the most important components of the channel link logic 46, which are connected to the link collector conductor 35 and the assembly line of the microprocessor 47. The main units include data register byte 0 with parity check and parity generation and byte group 1 of the data register with parity check and parity generation. Interrupt and cycle loan sequencing are controlled by logic, which includes checking priority level and call identification. Further logic includes byte 0 in an address register which, as previously processed, carries the order of a device and therefore includes an order decoding mechanism. Another logic receives byte 1 in the address information, which, as previously pointed out, addresses a particular device that is compared to a wired

7704959-1 address of address connections. There is also logic, which contains the cycle loan status register, condition code generation and other reset and link control. Further, there is a decoder for the address information from the microprocessor unit which is capable of controlling and sensing various lock circuits in the peripheral device controller 34.

Figure 17 is a block diagram of the main components of a microprocessor 47 suitable for use in the peripheral controller 34. The aforementioned memory 124, the output and input data acquisition lines 125 and 126, and the address collection conductor 127 have been shown. The microprocessor is controlled by 16 bit instructions entering an OP register 128, the OP code portion of the instructions being utilized by the cycle controller 129 and a timing clock 130 to generate the necessary control signals within the microprocessor.

Access to memory 124 is provided by address information from a memory address register (SAR) 131, which receives address information from multiple sources. These sources contain address information in instructions that are contained in OP register 128, an instruction address register 132, a link register 133, and an instruction addressable data address register (DAR) table 134. In combination with the instruction address register 132 and the link register 133, an auxiliary register 135 and the riser 136 form the necessary means to control the execution sequence of programmed instructions, e.g., branch, branch and return, branch and link, etc. A further addressable register table 137 and memory data 124, presented via an assembler circuit or a multiplex circuit 138, can be stored in an A register 139 and / or B register 140. The registers 139 and 140 form inputs to the computing and logic unit 141 and are the registers which are used to transmit data using data collection manager-out 125 or data collection manager-126.

Figure 18 shows further details of channel link logic 46 discussed briefly in connection with Figure 16. As a result of a decoding in the central unit 30 of an OIO instruction, the I / O control logic or channel 32 must communicate with the peripheral device controllers 34 to utilize the link collection conductor. To transmit the Immediate Data Control Block (IDCB). Channel link logic 46, whether controlled by a microprocessor 47 in accordance with a preferred embodiment or by combined and sequential logic, must contain a plurality of base elements which include a 16 bit data register 142, address register 143, order register 144, and additive or device selection address comparator circuit 145.

7704959-1

As indicated earlier, the link address collector 49 feeds the first word of the IDCB, which contains the device order in bits 0-7 and the device address in bits 8-15. An initial selection of all peripheral device controllers 34 is made by bit 16 on the address gatherer 49 to distinguish the use of the I / O operations manager from other operations. The initial device or add-on selection is made by comparing the device address in bits 8-15 of the address acquisition leader 49 with the fixed device address 133 in the address comparator circuit 145 to provide an initial device or add-on selection signal on the lead 146. entered in the order register 144 and presented to an order decoder circuit 147. The microprocessor unit address acquisition conductor 127 is connected for decoding purposes to a decoder circuit 148. The output of decoder 148 is combined with the output of decoder 147 in the add logic 149.

In the data transfer operation, either a first or a second output signal on lines 150 and 151 will indicate a direct program control transfer or a cycle loan transfer.

The initial device or add-on selection signal 146 provides an activation signal to an AND circuit 152 which responds to the I / O control logic-generated address gate signal 51 with the generation of an address gate return signal 52. In response to the address gate return signal 52, the I / O control logic 32 is informed.

The 15-bit data register 142 is connected to the link data collector 50 through collector 153 and 154. The data register 142 communicates with the 8-bit microprocessor unit data collector output 125 or the data collection processor 126 during two separate cycles in response to control from the microprocessor unit. In the case of a direct program control read operation, the data register 142 will have received the data from the microprocessor data collection manager output 125 to present it to the link data collection manager 50 through the collection manager 154. 142 via the collection manager 153 for later presentation during two separate cycles for the microprocessor unit's data collection manager 126.

If the immediate data control block order portion has called for a start cycle borrowing operation, the contents of the data register 142 received by the collection manager 153 include address information to be transmitted over the microprocessor's data collection manager 126 to

Further, in response to the decoding of a start cycle loan operation, the contents of the order register of a collector conductor 155 are transferred to the microprocessor unit's data collection conductor 126 for storage in the memory 124 within the microprocessor. Therefore, the memory processor 124 of the microprocessor will be utilized as order memory and the address portion of the memory 31 for controlling subsequent cycle data transfer operations.

During subsequent cycle loan transfer operations, address register 143 will receive on memory bus 156 for two consecutive cycles from the microprocessor unit's memory 124 the previously stored address information of the memory unit 31. This address information for subsequent cycle-by-line data transfer operations is transmitted via a collector conductor 157 to the link address collector 49 to be presented to the address mechanism in memory 31 within the central unit. The data register 142 will contain a cycle loan transfer data whether for a read or write operation.

A third type of order received in the direct data control block is a preparation order signaled on a line 158. In response to a preparation order thus signaled, bits 11-14 of the link data collection manager 50 are stored in a priority level register 159 , and the aforementioned I bit 15 is stored in a trigger 160. The contents of the priority level register 159 indicate the priority level of the device when interrupt requirements must be set. An interrupt demand signal on line 161 initiated by the connected microprocessor 47 becomes operative on an AND circuit 162 if the I-bit stored in 160 is a binary one. This indicates that the device can interrupt at any level. If the device is able to interrupt, and an interrupt claim has been made on line 161, a level decoder 163 will be able to activate one of the signal lines on the interrupt claim collection line 61. The activated line is associated with the priority interrupt level, which is registered in the priority level register 159.

As previously discussed in connection with Figure 14, the I / O control logic 32 responds to each signal on the claim-collection conductor 61, whether for an interruption claim or a cycle loan requirement signaled on a line 61-16, by initiating a call sequence. The call sequence includes transmitting the call identifier on the collector conductor 62 to all connected peripheral device controllers together with the serial transmitted call signal 63. If the call identifier on the assembly line 62 indicates a call for a requesting device

7704959-1 a cycle loan transfer, a signal is generated on line 164. This enables AND gate circuit 119 to generate an output signal if the device shown in Figure 18 has requested a cycle loan transfer as indicated on line 121.

If the call identifier header 62 is encoded with a priority interrupt level that corresponds to the current level as indicated in register 159, and the device shown in FIG. 18 has requested an interrupt as indicated by an output of AND circuit 162, to be generated from an AND circuit 165. OR circuit 166 generates an output in response to an output of AND circuit 119 or output of AND circuit 165 to disable propagation of the call to subsequent peripheral controller 34, which signal is displayed at 167. Other logic in controller 34 of Figure 18 is signaled as to poll answer on line 168. Further, an AND circuit 169 is affected to cause the unit 34 to respond to the service gate signal 55 on the link 35 by generating the service gate signal 56 to control further transmission on the link collection conductor 35.

Figures 19, 20 and 21 show further details of channel link logic 46 processed in conjunction with Figure 18. The various logic blocks shown include AND (A), OR (OR), inverter (N), exor (EOR) and varying bistable storage elements in the form of trigger circuits, tilt circuits, lock circuits and priority holding circuits. Signal lines, which are approached by a certain logic block with a filled arrow or leave a logic block with a filled wedge, indicate that the line or block is in operation or true when the line has a negative voltage level. In the alternative case, the absence of an arrow or wedge means that the lead or block is in operation or true when the lead has a positive level.

In Figure 19, the signal line interruption claim 161 shown in Figure 18 is shown as derived from an OR circuit 170 which receives inputs from bistable devices 171 and 172. An inverter 173 delivers an inverted signal representing the interruption requirement to other logic in the channel link. A control strobe pulse from the microprocessor 47 samples an AND circuit 174 and an AND circuit 175, whose outputs set the bistable devices 171 and 172. The input 176 to the AND circuit 174 is a signal line derived from the decoder 148 of Figure 18, and the signal thereafter goes to the address processing 127 of the microprocessor unit and reflects the decision of the microprocessor units.

7704959-1 that the connected device requires attention from the central unit 30. As previously mentioned, certain data control blocks in a chain of cycle loan operation data control blocks may include a PCI bit, which indicates a program controlled interruption during chain operations to allow the central unit 30 to sample the continuous cycle operations. The microprocessor unit's detection of the PCI bit provides for activation of a signal line 177, which enables AND circuit 175 to set device 172. Each of these two cases, reflected by AND circuitry 174, 175, is capable of initiating a interrupt requirements from the peripheral device controller 34. An OR circuit 178 is capable of resetting the bistable devices 171 and 172 and receiving signal line inputs generated in response to a plurality of states requiring reset of the interrupt requirement. These states include the fact that the service gate pulse 55 on the link collector conductor 35 has fallen, indicating that the previously recognized interrupt requirement has been fulfilled or that the peripheral device controller has received certain other signals on the link collector conductor 35, e.g., stop I / O or system reset.

Figures 20A and 20B show, in the arrangement of Figure 20, further detailed logic within the aforementioned blocks of Figure 18, relating to the initiation of the interrupt requirement in the interleaver 61, inserting a priority level into the priority level register 159, and comparing the contents of the register 159 with coded information on the link call identifier collection conductor 62 in the comparison circuit 120. The register 159 in Figure 18 is represented by polarity holding circuits 180 through 183. The associated AND circuits 184-187 set via inverters in the polarity holding circuits 180-183 the binary state of the link data collection conductor 50, the bit positions 11-14, which are encoded with the priority level to be established in the priority level register in response to a preparation order.

The signal on line 158 indicating a preparation order is generated by the order decoder 147 in Figure 18 when the IDCB order calls for the insertion of priority levels into the priority level register 159. The data strobe signal 54 coming from the link collection manager 35 is fed to an AND circuit 188 for generating a signal on line 189 indicating that the level register 159 is to be filled.

Another condition required for the input of the priority level information is indicated by an output of the OR circuit 190 and the AND circuits 191 and 192. This condition is that the order is a write order and the device address in comparison has shown a device selection, and that the particular device control unit is not for present is

7704959-1 engaged in a bicycle breath data transmission.

An inverter 193 and the AND circuit 194 receive bit position 15 within the I / O data collection conductor 50, which is inserted into the lock circuit 160 previously mentioned in Figure 18 as being the I bit or interrupt activation bit of the peripheral controller. Trigger 160 is first reset by an OR circuit 195 and then set to binary state 1 or 0 of the data collection conductor bit 15. OR circuit 195 also receives an input which resets the I bit in response to a system or power supply reset from the link collection conductor 35.

The AND circuit 162 of Figure 18 is also shown in Figure 20 and receives the state of the I bit as well as the interrupt demand signal 161 derived from Figure 19. In the absence of a signal on line 196, which is designated block claim-gathering conductor fed to AND circuits 197 and 198, each of which receives the complement register values ​​for level register bit 0, a decoder 199 for interrupt-demand-gathering 61 presents an activation of a certain determined by the wires in accordance with the priority level introduced in the polarity holding circuits 180-183. It is the input of bit 0 to the decoder 199 that activates the decoder.

The signal on line 196 indicating that the claim-gathering conductor should be passivated or blocked is received from Figure 21 (which is discussed further below), indicating that the peripheral controller 34 has made a call response in response to an interrupt claim or a service gate response as a response on a bicycle loan requirement. In the absence of these two signals for blocking the activation of the requirement-collecting conductor 61, the demand-collecting conductor will reflect a continuous interruption requirement at a certain specified level. Since a preparation order and data strobe signal can be received by a peripheral device controller completely under control from programming in the central unit 30, the contents of the polarity holding circuits 180-183 can be modified at any time. If a previous activation of the AND circuit 162 due to an interrupt requirement should have existed, in the absence of a previous call or service gate response, the decoder 199 would remain activated and immediately changed in accordance with a new coding of the priority level introduced in the polarity holding circuits 180-183 .

Figure 20 shows the EXELLER circuits 200-203 which signal a comparison between the bits of the priority level register 159 and the bits of the call identifier assembly conductor 62, which are utilized in the logic of Figure 21 to provide a call signal response.

Figures 21A and 21B show, when arranged according to Figure 21,

7704959-1 logic within channel link 46 at a peripheral controller 34, which operates with reception of call and call head signals 63 and 64 and results of the comparison between the bits of the call identifier header 62 and the contents of the level register 159. This logic has the task of responding to the call signals 63, 64 with consequent generation of the call return signal 65 or propagation of the call signal to additional peripheral controller 34.

In FIG. 21A, there is also the AND circuit 117 of FIG. 14, which receives at first and second inputs the call signal 63 and the call head signal 64 in response to generating an internal call signal on line 118. This signal on line 118 is fed to a bistable polarity holding device 204. whose steady state is utilized to control the efficiency of an AND circuit 205 and an AND circuit 206, both of which receive the internal call signal 118. Depending on the state of circuit 204, AND circuit 205 will generate the call propagation signal, which is the call signal 63 for subsequent peripheral device controllers, or OR AND 206 will be capable of generating the call return signal 65 and to the internal logic of the call device of the latch 207.

The state of the polarity holding circuit 204 to be indicated in response to the internal call signal 118 is controlled by an AND circuit 208 which responds to the state of the polarity holding circuit 209 or the polarity holding circuit 210. In the absence of effective output from an OR circuit 211, indicating that if no call answer or service gate response has taken place, an AND circuit 212 and an AND circuit 213 are activated. AND circuit 212 responds to a cycle loan demand signal on line 214 from a trigger in the second logic within the channel link logic which is set by the microprocessor in and for activating the polarity holding circuit 209. Likewise, in response to a signal on line 215 from AND circuit 162 in FIG. Actuating the AND circuit 213 to activate the polarity holding circuit 210.

The requirement for a cycle loan transfer, indicated on line 214, is also capable of activating bit 16 in the claim collection conductor 61, which is presented for the I / O control logic 32. The control logic 32 responds to the cycle loan requirement by activating the call identifier collection conductor 62 with a special code combination. This code combination is identified by an AND circuit 216, which responds to the binary-1 state of the call identifier gatherer conductor 62 bit positions 0, 3 and 4. The base indication

7704959-1 for a cycle loan call identifier, bit position 0 of the call identifier header 62, which must be in the binary I state, when bit position in the call identifier header 62 has binary 0 state, the remaining bit positions are decoded to indicate a certain priority level.

When AND circuit 216 is activated in response to a call identifier collection conductor indication for a cycle loan call, the polarity holding circuit 209 will be activated by a signal on line 217 to indicate the presence of a cycle loan requirement on line 214 along with the identification of a call for cycle loan operations.

The polarity holding circuit 210 is activated by a signal on line 218 when AND circuit 219 is activated. AND circuit 219 is activated in the presence of a binary zero at bit position zero in the call identifier array conductor 62 and an output of AND circuit 220. AND circuit 220 is the logic that receives the outputs of the EXELLER circuits 200-203 in Figure 20 and is activated when the code on the call identifier header 62 is equal to the priority level indicated in the priority level register 159 of Figure 18.

Therefore, a larger portion of Figure 21 shows a call receiving means which either propagates a received call signal to subsequent peripheral device controllers or responds to the call by setting the lock circuit 207 when a cycle loan requirement has been set and the call identification collection leader indicates a call for a call request or a cycle loan request and the code on the call identifier collection conductor 62 is equal to the priority interrupt level of the peripheral device controller receiving the call signal.

The response of the call signal in the latch 207 is capable of blocking at the OR circuit 211 the claim collection conductor 61 by a signal 196. The call response signal 220 from the latch 207 is capable of activating a polarity holding circuit 221 which will later respond to an activation signal of an OR circuit 222 in response to receiving a data strobe pulse 54 or service gate pulse 55. The signal 223 from the OR circuit 222 is also capable of resetting the call response locking circuit 207 on an AND circuit 224 via an OR circuit 225. Receiving the signal 223 from the OR circuit 222 at the polarity holding circuit 221 enables this circuit to activate the service gate signal 56 The O-control logic 32.

The polarity holding circuit 221 supplies a signal 226 indicating

7704959-1 service gate response, which signal is utilized in the logic shown earlier in Figure 20, and operates via a series of inverter circuits, each of which produce a delay in and for generating a signal 228 designated service gate delayed. Until the polarity holding circuit 221 is reset by the inverter 229, a signal on line 230 is capable of maintaining signal 196 at the OR circuit 211 which blocks the activation of the correct signal on the claim-collecting conductor 61.

An AND circuit 231 supplies a signal on line 232 for resetting a previously set cycle loan demand trigger circuit, which will, upon detection, indicate to the microprocessor that the previously requested cycle loan transfer has been initiated, and that an additional and subsequent cycle can be initiated. As a result, a signal on line 233 from the decoding of a particular microprocessor unit instruction will be able to reset the polarity holding circuits 204, 209 and 210 in preparation for further call operations.

OR circuits 234 and 235 receive link signals indicating stop I / O 65, system reset 68, or power supply reset 67 to provide reset signals for the logic of controller 34 including a signal on line 236 operating at OR circuit 195 in Figure 20 for resetting the I-bit in the peripheral device controller 34 to prevent further interrupted requirements.

Thus, in Figs. 19, 20 and 21, detailed logic has been shown for a peripheral controller 34. Furthermore, the logic has been demonstrated within a peripheral device controller, which can operate independently of a link collection manager being utilized for direct program control of data transmission. A link collection manager configuration has also been provided in which the logic of a peripheral device controller is capable of interacting with information on the link collection manager in order to change the device priority interrupt level regardless of other operations, which may occur on the link collection manager, or operations initiated as previously directed in response to previous orders. to the connected device.

1 / O control logic

Further details of the I / O control logic 32 will now be treated with reference to Figures 22-26.

7704959-1

In a central unit 30 capable of operating at four different priority levels, the logic of FIGS. 22A and 22B (arranged in accordance with FIG. 22) will determine whether an interrupt requirement on the requirement-gatherer 61 specifies a requirement at a higher priority level. or lower than the level currently prevailing in the central unit 30.

The current level of operation of the central unit 30 will be marked on the central unit collector conductor 72, bit positions 14 and 15, and will be timed into the latches 237 and 238 by a program controlled signal on the line 239. The program can sample the current level for other reasons by activating a line 240 for sampling the AND circuits 241 and 242 in and for presentation of the bit positions 14 and 15 in the central unit assembly conductor 72.

The current function level constitutes an encoded representation in the lock circuits 237 and 238 and is decoded by AND circuits in a decoder 243 for activating one of the four output lines from this decoder to identify the current functional level.

The interrupt logic 69 in Figure 4 includes AND circuits 244-247, the outputs of which are input into an associated lock circuit 248-251, in response to a central unit controlled signal on line 252, indicating that any priority interrupt requirements may be sampled at this time. Only one of the AND circuits 244-247 is capable of setting a binary one of the associated locking circuits 248-251 at the time of the clock signal 252, depending on the output of decoder 243 and the activated or passivated state of bits 0-3 on the demand-gathering conductor 61. The level output conductors 253-256 indicate to the in / out control logic 32 which interrupt level to be called. The level to be called may be the current level stored in the lock circuits 237 and 238.

If, instead, the claim-gathering conductor is activated with a requirement at a higher level, the output of the locking circuits 248-251 will indicate the interrupt and call-up requirement for the higher level being requested.

A mask register consisting of lock circuits 257-260 can be set in binary 1 or binary 0 state from bit positions 12-15 of the central unit assembly conductor 72 in response to a central unit generated signal on line 261. The contents of the mask circuits 257-260 can be sampled via associated AND circuits through a central unit generated signal on line 262 in and for presentation to the central unit on the central unit collector conductor 72. The connection of the worm lock circuits 257-260

7704959-1 via associated driver circuits for the requirement-gathering conductor 61 serves to counteract the effect of a requirement signal on the associated conductor within the requirement-gathering conductor 61. Therefore, during central unit program control, any interrupt requirements at a certain level from an I / O device is rendered inoperative.

Many central units have the ability to mask all I / O interrupt functions. In this connection, a mask for interrupting at specified levels is illustrated in detail, and previous discussions regarding the peripheral device controller 34 have shown a third masking level in the form of the I bit transmitted together with a preparation order.

Call sequence control circuits 75 of FIG. 4 are shown in more detail in FIGS. 23A and 23B, which are arranged in accordance with FIG. 23. At a certain time during sequencing of the central unit 30, the readout control memory will decode a micro instruction indicating that an interrupt requirement will be recognized, which will signaled on line 263. The signal on line 263 is input to a latch 264 and is capable of generating an output of an encoder 265, which in turn is input to a pair of latches 266 and 267. The contents of these latches will be the binary encoded value of the one-level signal line 253-256, which is activated from the interrupt priority determination logic in Figure 22B.

The output of the lock circuit 264 on the signal line 268 is supplied as an input to the competition solution logic circuit 269. Regardless of the decision of the central unit 30 to acknowledge an interruption requirement, the competition logic 269 receives each cycle loan requirement of the claim-gatherer 61, bit position 16.

The call signal 63 is generated by the setting state of a call tag lock circuit 270. If this lock circuit is not set and thus does not generate a call signal 63, an AND circuit 271 and an AND circuit 272 will activate the competition resolution logic 269, an interrupt cycle lock circuit 27 and cycle lock circuit 27. If the call lock latch 270 is not active, the correct pre-cycle latch 273 or 274 will be set in accordance with competition logic 269, which inhibits further change therein.

An OR circuit 275 is activated by either an interrupt cycle or a cycle loan cycle to provide an input to an AND circuit 276, the other of which is the passive state of a trigger 277, which is set by either a call return signal 65 or a group return signal 60 via and OR circuit 278.

When AND circuit 276 is activated, the output signal will set one

7704959-1 the call start lock circuit 279 which, after a suitable delay, will effect the setting of the call bar lock circuit 270 to begin generating the call signal 63.

Before the delay of the output of the delay circuit 280 affects call bar trigger 270, the information on the call identification collector 62 will be activated according to the output of an encoder 281. Encoder 281 receives inputs from the encoded value of the interrupt level recorded in the lock circuits 266 and 267, as well as a signal 2 if a bicycle loan cycle is relevant for the call. As previously mentioned, the cycle loan call identifier on the collector conductor 62 is a predetermined code generated by the encoder 281 if a cycle loan call occurs. Otherwise, encoder 281 will deliver an encoded output to the call identification collection conductor 62 associated with the particular determined by interrupt level signal lines 253-256, which is activated, if an interrupt cycle is triggered.

Assuming that the service entry signal on line 56 has fallen from a previous function and that the latches have not been previously set, either a latch 283 or a latch 284 is set depending on whether the interrupt cycle lock circuit 273 or the cycle loan cycle latch 274 has not been previously set. The signal on line 285 or a signal on line 286 is generated to the additional logic within the I / O control logic. Likewise, the output of an OR circuit 287 is generated on line 288 to initiate a requirement for the link gate controller 76 of Figure 4 regarding generation of the service gate signal 55 to the peripheral device controller 34 to control the remainder of a link sequence for handling either a cycle loan or an interrupt claim.

When the call return signal 65 or group return signal 60 is received at the OR circuit 278, the call or group return trigger 277 is set. This makes OR circuit 289 capable of resetting the call bar lock circuit 270. The reset of the call bar lock circuit 270 causes, together with the termination of the call return or group return signal AND circuit 290, to reset trigger 277.

The link control circuit 81 in Figure 4 includes means for signaling the initiation of a call sequence which is not properly completed after a certain period of time. An OR circuit 291 generates a signal on line 292 which activates a call time end clock. An input signal comes from the lock circuit 279, which is set by AND circuit 276, which signal indicates the beginning of a call sequence. Another input to the OR circuit 291 comes from the call bar lock circuit 270, which at

7704959-1 reset, in turn, resets the correct components of the call end activation. A third input to the OR circuit 291 indicates that the call-back signal 65 has continued to be active for an incorrect period of time. It should also be noted that the group return signal 60, which signals the fact that a device has used the link for a long period of time for multiple data transmissions, does not contribute to the call time end activation signals 292, since a group cycle loan may be active for an infinite period. .

The setting of either the interrupt cycle lock circuit 283 or the cycle lock circuit 284 provides via the OR circuit 287 the setting of a trigger circuit 293. An AND circuit 294 is in the absence of a group return signal 60 capable of resetting the precycle lock circuit 273 or the circuit circuit otherwise the group circuitry may cause the circuit circuit 273 or 274. Otherwise not to be reinstated for responding to additional requirements.

An AND circuit 295 becomes active when the service gate signal 56 is received and the trigger generating the service gate signal 55 is disconnected, indicating a device acceptance of the service gate for initiating the cycle completion. This then gives rise to resetting of the interrupt cycle lock circuit 283 and the cycle loan cycle lock circuit 284.

Figures 24A, 24B and 25 show additional logic details of the link gate controller 76 of Figure 4. Competition logic 296 has the means necessary to resolve a competition between the service gate requirement signal 288 of Figure 23, which signal indicates a need to use the link collection conductor 35 for bicycle loans or interrupt handling. and the 010 signal 77 from the central unit 30. As soon as this competitive situation is resolved, logic 296 delivers an output to either a service gate enable latch 297 or 010 actuation latch 298. Assuming latch 297 is set, a signal is presented for service gate trigger 299 as a clock input. This trigger setting is presented to the link 35 as the service gate tag signal 55. It is also presented to an AND circuit 300 as a condition input to an interrupt end lock circuit 301 along with the interrupt cycle 285 and the reset OIO signal 89 from the central unit 30. Service gate triggers 299 provide an input to an OR circuit 302 which also receives input from The 010 activation lock circuit 298 and the service gate return signal 56 via the OR circuit 355 on line 306 to generate a gate time end activation signal 303 to the fault controllers. As soon as the service gate signal 55 is presented to the link, service gate triggers 299 are awaiting the arrival of the service gate signal 56.

7704959-1

The identification of a service gate signal 56 or an address gate signal 52 is performed by a return trigger 304. The logic of this trigger is such that both the address gate signal 52 and the service gate signal 56 must be passive, and then one of the two signals must arrive. This ensures that none of the signals are permanently active at the link, indicating an error state. This results in a time-end error as a result of failure to identify the service gate signal 56. Service gate triggers 299 would never be reset, so the gate-time-end enable signal 303 would remain active until the time period for signaling a fault had expired, which sets a machine control state in the central unit 30.

When the service gate return signal 56 goes to a logic state 1, return triggers 304 are turned on. The service gate signal 56 and the output of return triggers 304 are applied to an AND circuit 305 which generates an internal service gate signal 306. 56th The output of return trigger 304 is applied as an input to a delay circuit 307, the output of which is utilized for setting a gate delayed latch 308.

The output of the return trigger 304 together with the missing output of the delay 307 generates at an AND circuit 309 a signal 310 capable of clockwise the information on the condition code-gathering circuit 53 into the condition code lock circuits 78 of Figure 4. When the gate delayed the latch 308 is set, it supplies a clock pulse to a bike loan memory demand trigger 311. Memory demand trigger 311 provides an output signal 312, which is a bike loan memory requirement to the memory unit 31. Bicycle Loan Memory Requirement Trigger 311 is reset by a signal from the memory unit 31 on line 313, which signal indicates the end of the memory sequence of the cycle loan operation.

The inverted output of the latch 308 and the output of service gate triggers 299 are applied to an AND circuit 314 which is used to input the I / O address collector conductor signal to the cycle loan SAR 110 of Figure 6. This occurs whether the sequence is an interrupt or an cycle steal. The output of AND circuit 314 is also applied to an OR circuit 315 which controls the clocking of information in the cycle loan SDR 94 of Figure 5. The second input to the OR circuit 315 comes from an AND circuit 316, which receives a data strobe pulse 317 from the memory controller, the cycle loan cycle signal 286, and the binary state of *

7704959-1 output / input indicator 57 from the link.

The cycle loan cycle signal 286 and a binary I indication on the output / input indicator 57 are capable of activating, at an AND circuit 318, the link gate circuit C 104 in Figure 5 to cause the cycle loan SDR 94 pulse to be input to the I / O data collector. 50. AND circuit 319 is activated, when output / input indicator 57 shows binary 0, for generating a signal on line 320 indicating a cycle loan write data transmission. The inverted signal 320 generates a signal on line 321 to indicate to the memory unit 31 a cycle loan read operation. The output of AND circuit 319 is also presented to a OR circuit 322, which causes signal 104 on link gate C to provide input of data to I / O data collection conductor 50 in cycle loan SDR 94.

The other inputs to the OR circuit 22 are partly a signal on the interrupt cycle line 285 and partly the output of an AND circuit 323 which has received an indication of the line 324 concerning an OIO read decoding from the order decoder and partly the output from the 010 activation lock circuit 298. The cycle loan cycle signal 286 is also applied to an AND circuit 325 together with the binary state of the word / byte indicator 58 in order to indicate to memory 31 on line 326 whether the memory has to work with transmitting a byte or a whole word.

When cycle loan memory requirement 312 has been generated, the I / O control logic 32 waits for an indication from memory 31 that the sequence is completed. This is indicated to the I / O control logic 32 by activating the signal line reset cycle loan memory 313, which sets a cycle loan lock circuit 327. The lock circuit 327 is set when service gate trigger 299 is reset.

The interrupt end lock circuit 301 and the cycle lock lock circuit 327 supply inputs to an OR circuit 328. The output of the circuit 328 is applied to an AND circuit 329 together with the output of return trigger 304 and for resetting of service gate triggers 299. The output of OR circuit 328 is also presented. circuit 330, which supplies an output to a pulse generator 331, which produces the data stroke signal 54. The data stroke signal 54 is applied to an AND circuit 332 together with the internal service gate signal 306 to provide an input to the OR circuit 333 which generates the service gate signal 55, which is presented to the link 35. The second signal to the OR circuit 333 is provided by the service gate gate trigger 29. 313 arrive at the I / O control logic from memory,

7704959-1, the data strike signal 54 is generated and service gate triggers 299 are reset. However, the service gate signal 55 remains active until the case of the data strobe pulse 54. Both the data strobe pulse 54 and the service gate signal 55 fall simultaneously, which signals to the peripheral controller 34 that it can now drop its service gate signal 56.

When the data strobe pulse 54 and the service gate pulse 55 have been passivated, the I / O control logic 32 again waits for the peripheral device controller 34 to drop its service gate signal 56. When this occurs, the I / O control logic returns to a normal state, pending the next output of the competition logic 296 to start a signaling sequence.

When the competition logic 296 responds to a 010 instruction decoding signal on line 77 and sets 010 activation lock circuit 298, bit position 16 on the address acquisition conductor 49 is activated, which causes the initial selection of all peripheral controller 34 on the I / O collector conductor 35.

334, which, after a certain delay, sets an address gate lock circuit

335th The locking circuit 335 initiates the address gate signal 51 in the absence of the decoding of a stop I / O instruction, which is indicated on the line 88 at an AND circuit 336. The address gate circuit 335 is reset when either the OR circuit 337 is activated by either the data strobe 54 or the output signal. from a AND circuit 338. A delay circuit 339 makes AND circuit 338 active when return triggers 304 have received the address gate return signal 52, thereby resetting the address gate circuit 335.

In response to an OIO instruction, signals on a plurality of signal lines may be presented to the central unit 30 as shown in Figures 5 and 6, and for transmitting information in the IDCB to the I / O address acquisition leader 49 and I / O data acquisition manager 50. Therefore, Figure 24B shows a number of signal lines leading to different registers in the central unit 30 for this purpose.

Figure 25 shows logic for activating different bit positions within the cycle loan status collector 59. The cycle loan status information is presented to the peripheral device controllers 34 during cycle loan cycle operations, indicated on line 286. The signal on line 286 activates a series of lock circuits 340-343, each associated with a bit position on cycle line 59 . If errors are detected by memory 31 - for example, an invalid memory address 334, a memory parity error 345, or a memory protection check 346 - before the reset cycle loan memory signal 313 in Figure 24, correct wires would have

7704959-1 is enabled and affected in the status loop controller circuits 340-343 for presentation to the link on the cycle loan status loop 59. If the I / O logic 32 had detected a parity error during an input cycle for memory 31, bit position 3 would have been activated, and the activation of this status loop leader state would force to memory 31.

The sequence timing control portion of the link control control circuit 81 of Figure 4 is illustrated in more detail in Figure 26. Each of two timing adjusters 347 and 348 is a binary splitter chain. When the correct activation signal is not present, the chain is held at reset and progress is made impossible. When an activation signal occurs, the divider is allowed to count. The timers are allowed to count in response to a clock signal, whereby a decoder connected to the timers detects the accumulation of a specified number of values ​​and sets an I / O control state on line 83, which state is stored in the program status word of the central unit 30. If the activation signal to the timer would return to a passive state before the specified time has expired, the timer will be reset without signaling the error state. The timer 347 checks the correct timing of the call sequence, and the timer 348 detects the correct timing of the service gate signal and the address gate signal.

An AND circuit 349 provides a check for parity errors during interrupt cycles, and an AND circuit 350 provides a check or error indication when both the address gate signal and the service gate signal have been generated.

Rest Status Reporting

Figure 27 is a further representation of the function of the present invention with respect to cycle loan operations in which DCB chain is invoked, and status information shall be recorded without interruption by the central unit 30. The amount of data to be transmitted under control from a DCB is specified in the byte count field. .

An error condition may occur if the data that a device is to transmit does not match the sum. This error is called incorrect length recording (ILR).

Some devices such as, for example, telecommunication lines often incur ILR. The program in the central unit 30 which controls such a device needs to have some information about the transmission, for example how much data is transmitted. This determination can be made when ILR is detected

7704959-1 for each DCB in the chain. This would require the device to identify the ILR exception, disconnect the central unit, and initiate a transmission of the type of starter cycle loan status. This operation is time consuming and undesirable if - as indicated earlier - the ILR normally constitutes the condition rather than the exception to the device operation.

When the ILR is the norm and occurs frequently, the program may wish to suppress its detection and reporting as a failure.

This can be accomplished in accordance with the present invention by using the Flag Suppress Incorrect Length (SIL) flag located in bit position 4 of the control word in each DCB. When the SIL flag is up, the device dependent parameter word 4 in DCB is redefined as the residual status address.

As previously mentioned, the complete DCB is transferred from memory unit 31 to a peripheral controller 34 and the residual status address recorded in memory 124 within the peripheral controller microprocessor 47. When device 33 has completed its data transfers for this particular DCB, it will use the residual status address during subsequent cycle loan transfer operations to store the residual sum (the sum remaining after the data transfer) and up to two additional device status words in memory 31. The SIL bit, which is 1, has in practice defined ILR as no state of emergency. When there is no exception state to report, the device can use the DCB chain address information (if specified in DCB) to retrieve the next DCB in the chain and proceed. Since the information needed by the program in the central unit 30 is automatically stored, the program does not need to perform a boot cycle loan status transfer to the device after each DCB download and execution.

A desirable feature of this operation is the ability to have the residual status information stored in an independent location in the memory defined by the program and inserted into each DCB. Thus, DCB can remain a readout information block in the main memory at the request of the programmer. This also allows for the creation of a continuous block of status information during multiple DCB chain operations, which frees the programmer from having to sort the status information from individual data control blocks.

7704959-1

Patentkray

1st Controls for input / output devices in a data processing system, including a channel controller (32), a plurality of device controllers (34), and a link interconnector (35) connecting the channel controller with the device controllers and comprising information, order, control, address and status signal conductors, some of which signal conductors (50, 62, 63) transmit priority level signals to the device controllers; call signals and call identification signals, and of which other signal conductors (61) include a plurality of interrupt demand signal lines to signal to the channel controller an interrupt requirement on a particular determined by the interrupt demand conduits (associated with the peripheral device's interrupt control device, 181-183) for storing an interrupt claim status, means (199), which respond to the indicating means in and for activating one of the interrupt demand lines (61) associated with the stored priority level, additional indicating means (47) for storing a data transmission requirement status, means (121, 214), which respond to said additional indicating means for activate an additional line (61-16, fig. 18) on the header of and for signaling a cycle loan requirement to the channel controller, a receiver (117, 216) for the call signal (63, 64) and call identification signals (62), means (200-203) which are affected by the stored priority level and call identification signals in the and for providing an equalizer signal (218), a decoder (209) connected to the call identification signal receiver (216) to provide a bicycle theft call signal, and means (204, 206-208), which are affected by either said equal signal or said bicycle theft call signal and the call signal received (117) to provide an indication of the requirement granted.

2nd Control means according to claim 1, wherein another of the wires within the link assembly conductor transmits an interrupt mask with a binary state 1 or 0, characterized by a mask bit storage unit (160) for receiving the mask bit from the collector conductor and an inhibitor (162), connected to the mask bit storage unit and interrupt circuit breaker. which inhibitor is capable of preventing activation of the interrupt requirements when the mask bit exhibits a certain determined by the two binary states.

7704959-1

3rd Control means according to claim 1, characterized in that the device control unit comprises call propagation signal means (205) for transmitting a received call signal to subsequent device controllers, call return signal means (65) connected to and reacting to the means (204, 206-208). for signaling to the channel controller of the response signal response and means (205) connected to and responsive to the means for indicating the granted requirement; which means are connected to the call propagation signal means (63) for blocking the generation of the call propagation signal.

4th Controllers for input / output devices in a data processing system comprising a channel controller (32), a plurality of device controllers (34) and a link interconnector (35) connecting the channel controller with the device controllers and including information, order, control, address - and status signal conductors, some of which signal conductors (50, 62, 63) transmit priority level signals to the device controllers, call signals and call identification signals, and of which other signal conductors (61) include a plurality of interrupt demand signal lines to signal to the channel controller an interrupt requirement on a particular determined by the interrupt demand conduits which is associated with the peripheral device control unit ( -251), connected to the interrupt requirement signal lines for selecting an interruption requirement for recognition, cycle loan receivable and indicating means (269) which are connected to a further line within the link broker and indicate a requirement for a data transmission from any of the device controllers, call identification signal means (281), connected to the call identification lines within the link broker signal, call sign connected to an additional lead (63) within the link collection manager, and call sequence control means (263, 264, 266, 267, 279), connected to and responsive to the priority determinants and cycle borrowing requirements means and associated with and arranged to activate the call signal generating means (270) and the call side triggering signal means (281) so as to transmit a call signal (63) to the device controllers and a first call signal (63) and a first signal (63). any bicycle loan requirement or other caller identification signals, each of which is associated with a priority level and interruption requirement, which must be acknowledged.

7704959-1

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