Multiplexer

(54) Name: Method for transmitting information and multiplexing device for application of the method

i.nm when.nioo «nn international identification code. INID code. Letters in clamps indicate international document code

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The present invention relates to a method for transmitting information from various sources over a common transmission arrangement and to a multiplexing device for applying this method.

For transmitting digital information, there are two different types of switching: circuit switching (line switching) and storage and release forward switching, respectively. In circuit switching, a connection is established prior to transmission between two terminal stations by signaling and information exchange, which connection is then exclusively available and represents a transparent channel. Such connections are advantageous for continuous or synchronous traffic but not for intermittent or interactive traffic. On the other hand, no fixed connection is established during storage and release forwards. Data is arranged in blocks or packets and is transferred from access point to access point in a network and is each time stored in a buffer. Additional data such as, for example, details of the destination and source must be connected to the packets and must be transmitted and stored with them. The benefits of this kind

7504748-0 transfer are among others. better line utilization and shorter response times. However, the transferred data must meet certain conditions (no transparency), and alternating waiting times must be accepted.

In communication systems for different information categories, where large variations in traffic volume occur, an integration of circuit switching and storage and release forward switching or of synchronous and asynchronous transmission is desirable. In principle, it would be possible to provide parallel devices throughout the system for both transmission categories. However, this is very costly and yet does not result in optimal utilization when large variations in traffic volume occur.

Time division multiplex systems are known in the art, in which both synchronous data for circuit switched traffic as well as asynchronous, irregular behavior data can be transmitted over a line. In these systems, each time section contains fixedly designed time tracks, of which a number are permanently intended for synchronous traffic, while the others are intended for asynchronous traffic. However, in this arrangement, many situations are possible in which part of the transmission capacity is not utilized due to the fixed breakdown.

In another time division multiplex system known in the art, a matrix switching arrangement is provided between input lines and output lines, the individual switches being controlled in accordance with stored switching control data. In this system, connections with different bandwidths can be established so that different types of traffic can be provided. However, each individual connection - even a very short one - must be specially controlled, and free transmission capacity must be allocated for this. Furthermore, this system has to do with a switch and does not solve the problem of optimal channel utilization.

It is therefore an object of the invention to provide a method and a device which allow integration of different traffic categories for transmission and to achieve optimum utilization of the available transmission bandwidth. This objective should also be realized if large variations occur in the volume of varying traffic categories. Furthermore, it should be possible to establish circuit switching

7504748-0 connections with different bandwidth in accordance with current requirements without degrading its utilization.

Another object of the invention is to provide a method for transmitting information from various sources over a common transmission device, in which method data from a first subset of the sources is transmitted as circuit switched traffic in periodic time tracks within sequential time sections, which time tracks are temporarily assigned to the sources. wherein the size of a time track and its position within the section cycle is determined in accordance with the assignment; data from a second subset of the sources is stored as stored and dropped forward traffic in a buffer memory, then sequentially extracted and transmitted in the form of an intermittent data stream in the gaps left in the time section between the circuit switched traffic time track and a new time track assigned one of the sources in the first subgroup only, after such assignment, the channel capacity available for storage and drop traffic corresponding to the remaining gaps; not less than a certain minimum value.

A multiplex device for carrying out the method has

(a) a plurality of source registers, belonging to the sources of the first subgroup;

b) a buffer memory for storing and sequential delivery of data from associated sources in the second subset;

c) a combination unit for transmitting data from the source registers and the buffer memory to input means of the transmission arrangement.

d) first selector circuits for selectively activating the basement register outputs to effect delivery of data elements to the combination unit in accordance with control data stored in a control memory connected to the selector circuits; and

e) other select circuits for activating the buffer memory to cause this to output data elements to the combo, if no data elements are output from the source registers and if no synchronization or section control characters are output.

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The present invention enables high flexibility in the integration of synchronous and asynchronous traffic, although optimal utilization is achieved because both traffic categories automatically completely complement each other in the combination and because a free choice of bit positions within the time section is possible for each time track. The more detailed features of the invention are set forth in the following claims.

The above and other objects, features and advantages of the invention, which are defined in the claims below, will become apparent from the following, more detailed description of a preferred embodiment illustrated in the accompanying drawings.

Fig. 1 shows schematically a configuration in a communication network for which the invention is suitable.

Fig. 2 shows schematically the method of integrating synchronous and asynchronous (or circuit switched and stored and released forward switched) traffic according to the invention,

Fig. 3 is a diagram showing the variable assignment of total transmission bandwidth to both traffic categories.

Fig. 4 is a block diagram of a multiplexer device according to the present invention.

Fig. 5 shows schematically the process of assigning new time traces between other time traces already allocated in the time section for circuit switched transmission.

Method.

Fig. 1 schematically illustrates a situation for which the present invention is particularly suitable. Between two switching devices I and II there is a duplex transmission arrangement with two channels A and B for transmission in both directions. Connected to each of the two switching devices are continuous transmitting (or receiving) sources (C) and other sources (D), which supply (or receive) data on a temporary basis or at a low speed.

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The sources may be connected devices or wires on which data arrive from other switching equipment or switchboards. In the first case, Fig. 1 corresponds to a system with only two switching devices, through which subscribers at two locations distant from each other can be connected. In the second case, Figure 1 corresponds to a section of a larger network, where the two switching devices are merely two of a plurality of such switching points.

Transmission via a switched (circuit switched) connection is considered most suitable for the sources in Group C, and transmission in blocks or packets with intermediate storage (storage and release forward switching) is considered most suitable for the sources in Group D, which has already been explained in introduction.

What is now proposed is to combine data from the various sources in such a way as illustrated in Figure 2. Transmission occurs in sections which sequentially and periodically follow each other and are separated from each other by synchronization characters as is customary in time-division multiplex traffic. As needed, time slots (diagonally dashed) for circuit switched traffic (C), hereinafter also called synchronous traffic, are coated in the section, which time slots are then periodically utilized for transmission. The time slots need not be the same width. Their width depends on the bandwidth required for each channel. Nor do the time traces coincide, which means that they do not have to follow one another immediately. The allocation process will be further described below.

Data of the second traffic category (D), hereinafter also referred to as asynchronous traffic, is sequenced and stored in a shift buffer memory in the form of a pending queue of successive data packets. Of course, control and identification information (heads) must be added so that the data from different sources can be correctly separated and later distributed (at the receiving end). Furthermore, check · signs (P) and fill signs must be added. The contents of the buffer memory are continuously extracted in and for full filling of the gaps (horizontally dashed) left between the synchronous traffic time slots (diagonally dashed). In this way, the total capacity of a transmission channel can be utilized flexibly but optimally, ie fully.

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The combination of the data takes place in a multiplex device, which is described in more detail later.

Fig. 3 shows an important principle for the proposed solution. The length of the element represents the total available channel capacity (row a). Part of it is reserved as a minimum capacity M for asynchronous traffic (row b, left part), while the other part H is fully or partially available - depending on demand - for circuit switched (synchronous) traffic (row b, right part). The contents of the element of FIG. 3 represents an actual relationship: for direct (circuit-switched) traffic, as much capacity is required (diagonal line, right side). For asynchronous traffic (intermediate layered data packets), the entire remainder is available, that is, the part that is permanently reserved for asynchronous traffic (transverse) and also the part that is not currently used for direct traffic (white area).

Thus, a variable boundary has been established between the two categories of traffic, which is shifted depending on demand and traffic volume.

The minimum capacity for asynchronous traffic (storage and release forwarded) is maintained, so that this traffic is never completely interrupted. On the other hand, direct traffic (circuit switched) has the priority of using all the remaining part (H) of the channel capacity

However, the illustration in Figure 3 is merely a schematic representation. In practice, the cycle period is not divided into two parts but - depending on the current need - in time slots with intermediate gaps as shown in Fig. 2.

Multiplexer.

Fig. 4 shows details of a multiplex device suitable for carrying out the method according to the invention and corresponds to blocks MPXA in Fig. 1. An associative memory 10 is provided for storing information in time traces and their assignment information. The content of each row corresponds to a time slot. The left field contains the first bit position of the time slot in each section. The center field contains the width of the time slot in the form of a bit number. In the illustrated

In the example, the content of the center row corresponds to a time slot containing the bit positions 140-169. The third field, on the right hand side, contains the address or number of the input channel assigned to each time slot. The bit pair at the far right of each row has the task of indicating whether the row is active (11) or passive (00) and to mask the transition state (explained later).

The registers 12, 14, 16 and buffer memory 18 have the task of receiving data from different sources, which data is to be transmitted over a common line. The lines 22, 24 and 26 on which the data arrives, for which a synchronous connection is established, are connected to the inputs of the registers 12, 14 and 16. To the input of the buffer memory 18, the editor 20 is connected, the inputs of which are conduits 28, and 32, on which irregularly occurring data (stored and released forwards) arrive. The editor 20 arranges the data arriving on lines 28, 30 and 32 in a continuous sequence of data packets and adds identification and control information. The unit delivers a stream of continuous bits to the buffer 18. If temporarily no data arrives, fill characters are inserted to maintain the bit stream.

The registers 12, 14, 16 and the outputs of the buffer 18 are connected to an OR gate circuit 34 which, at its single output line, delivers a data stream to the line adapter circuit 36, which in turn is connected to the transmission line 38. A bit clock is provided for synchronization. In turn, it can be synchronized by a central clock signal. The registers 12, 14 and 16 and the buffer 18 have output gate circuits which can be controlled from associated control lines 44, 46 and 48 for delivery of data.

The control circuits, which are described below, have the task of generating control signals on the aforementioned control lines in accordance with control data contained in memory 10.

An input / output register 10a is connected to associative memory 10. A value entered in the left field (e.g., 140) is compared to the contents of all corresponding fields in associative memory 10. If similarity occurs, a selector belonging to it is activated. the current line. Thereafter, the contents of the second and third fields of the current row (030 and N, respectively) are passed to the input / output register 10a, and the output indicator associated with this register is activated.

A first counter 50 is connected to the bit clock 40 and a unit is advanced at each bit clock time. The output of the counter 50 is coupled via the gate circuit 51 to the first field of the input / output register 10 in such a way that, each time a control signal D is active on the line 52, the current counter value is transmitted to the input / output register. Line 52 is connected to one of the two complement outputs of control flip-flop 54. The other output is connected to line 56. The control rocker circuit further has a setting input with a line 58 and a reset input with a line 60. The line 58 is connected to the output indicator 10a of the input.

A second counter 62 receives input pulses from the gate circuit 64 via the control line 66. The gate circuit 64 is connected to the bit clock 40 and to the output line 56 from the control flip-flop 54. It outputs bit-clock pulses to the control line 66 when the control flip is set, ie when the control signal C is active.

A comparator 68 is connected to the output of the second counter and to the center field of the input / output register. It sends a reset signal via line 60 to the second counter 62 and to the control flip-flop 54, when the counter value is equal to the contents of the center field.

A decoder 70 is connected to the right field of the input / output register 10a and automatically receives the contents thereof. On each particular occasion, at most one of the control lines to the gate circuits 72, 74, 76, 80 and 90 is activated, which results in the forwarding of the bit clock signal from the line 66 to the corresponding of the gate circuit output lines 42, 44, 46, 82, 98. Each such signal causes delivery of data bits in the bit clock rate from the output of the respective registers (or from the gate circuit 92).

The shift register 84 contains the synchronization pattern, which is transmitted at the beginning of each section. The output of the register is connected to

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OR gate circuit 34, and there is a feedback connection to this input so that the synchronization pattern becomes available immediately after each readout operation.

The flip-flop 86 with the input line 88 has the task of determining a certain state (explained below), which is passed on as an indicator bit via the bit line 96, the gate circuit 92 and the line 94 to the OR gate circuit 34 and further to the line 38.

A gate circuit 78 is connected to the bit clock 40 and to an output (line 52) of the control flip-flop 54. Its output delivers the bit-clock signal via line 48 to the output of the buffer 18, when the signal D is active (the control flipch is reset).

Operation.

For each time track assigned to an input channel for synchronous transmission, the associative memory in one of its rows contains the position number of the start bit, the width of the time track in the form of a bit number and the assigned channel number and the register number (address), respectively.

Furthermore, there is a time slot for the sync character, and the second last line is assigned to it. The start bit position is 001 (second bit in the section), and the length x corresponds to the number of bit positions in the shift register 84.

Furthermore, there is an additional time slot, which contains only a bit position for an indicator bit, which represents the beginning of each section. The last memory line, which contains start bit position value 000 and length value 001, corresponds to this time slot. The significance of the start bit preceding the sync character is explained later.

The contents of the first counter 50 are incrementally increased by the bit clock signal. Its current content specifies the bit position in the section, which is just to be transmitted. The counter's capacity corresponds to the number of bits in the section, so it automatically returns to zero at the beginning of each section.

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It is now assumed that the current value in the counter is in, and that the 1st bit position is in a gap.

Therefore, the control flip-flop 54 is in the reset state (signal D active). Data is taken from buffer 18 and transmitted within the gap. The contents of the first counter 50 are incrementally increased. At the same time, an associative search is performed because signal D is active.

As soon as similarity is identified, ie when the next time track, which is assigned to an input channel, starts, the contents of the respective row are transferred to the input / output register and the control flip-flop 54 is set. The result is that signal D becomes passive and the search process is interrupted. Signal C becomes active so that one of the gate circuits 72, 74, 76 associated with the current channel is opened in accordance with the bit clock. Thus, during this interval of time, data bits depart from the correct register to the output circuits 34, 36, 38 in accordance with the bit clock. At the same time, the bit rate signals from line 66 in the second counter 62 are counted and the contents are compared with the width value found in the center field of the input / output register.

When the end of the time track is reached, comparator 68 outputs a pulse, thereby resetting counter 62 and control flip-flop 54. As a result, signal C is again passivated and signal D becomes active. The search process with the constantly changing contents of the first counter 50 begins again, while the gate circuits 72, 74, 76 (also 80 and 90) remain locked. In contrast, the gate circuit 78 is opened so that from the buffer 18 data bits are output in bit rate to the output circuits 34, 36, 38.

This output alternately of data bits from, on the one hand, a certain selection of registers 12-16 and on the other hand, the buffer 18 is now repeated until the end of the time section cycle and then starts again.

At the beginning of each time section, the last and the second last line of the associative memory are read out. This results in the gate circuits 90, 80 being opened and transmission being made partly of a status bit from flip-flop 86 (to bit position 000) and partly to the synchronization pattern from register 84 (to bit positions 001-x in the section).

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Signal D always becomes active if there is currently no assigned time track, ie during asynchronous data delivery. Signal C is active during the intervals corresponding to time tracks assigned to synchronous transmission (the two time tracks for transmission of the indicator bit and the synchronization pattern at the beginning of the section thus form part of it).

Demultiplexer.

At the receiver side of the transmission arrangement there is a demultiplex device (DMPXA in Fig. 1) which is analogous to the newly described multiplex device. The associative memory has the same content, and the received data bits are distributed either to output channel registers (circuit switched synchronous traffic) or to an output buffer (intermediate stored asynchronous traffic). The demultiplexer further contains a distribution unit corresponding to the editing unit, which first of all distributes - in accordance with the control and identification characters added by the editing unit - the bit stream from the output buffer to the output lines, the number of which is equal to the number of input lines 25-28.

Allocation of time slots (Fig. 5).

The time slots assigned to the input channels are determined by the insertion of the start bit position and the number of bits (width) in the associative memory. Corresponding entries are in a first list in a memory for this purpose within the overall system.

The available gaps between the time slots in the time slots utilized for transmitting asynchronous arriving and buffered data packets are similarly included in a second list according to starting bit positions and widths. This list is also housed in a memory dedicated to this purpose in the overall system. Furthermore, at a given storage location there is the minimum bandwidth M (the number of bits, see fig. 3) specified, which must always be available for asynchronous traffic, and at a second given storage location there is the sum L of all gaps, ie the total bandwidth currently available for asynchronous traffic. A third storage location contains data regarding the width S1 (bit number) of the currently largest gap (see fig.

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If there is now a requirement for assigning a time slot for transmission (circuit switched) with bandwidth W, a procedure is illustrated, which is illustrated in Fig. 5. Line a shows the current breakdown of the time section. Time traces, which are already allocated for synchronous traffic, are dashed.

First, it is determined whether, after assigning a time slot with the width W, the minimum bandwidth M for asynchronous traffic remains, ie whether LW LM. If not, the claim is rejected.

Next, a determination is made as to whether the requested bandwidth is smaller than the largest available gap, i.e., whether W is SI S1. If this is the case, the width W is compared with all gap widths Si, and the assignment is made, where the smallest positive difference exists. The values ​​for the new time slot (ie the start bit position and width) are entered together with the associated channel address in the first list and in the associative memory. The list of gaps and the value of the sum L for all gaps are updated accordingly. This corresponds to row b in Fig. 5.

However, if none of the available gaps suffices for the width of the requested time slot, i.e., for W> S1, a division is performed by distributing the request channel's traffic into two (or more) time slots. Compare row c in Fig. 5. The first of these time traces is made equal to the widest available gap (SI) and lists and parameters are updated accordingly. For the remaining bandwidth R, which is still to be allocated, the same procedure is followed as if a normal new request was received, ie row b or row c. The final result is that for one input channel, two (or more) time slots are utilized and thus two (or more) entries are made in the memories, the channel number (channel address) in all entries belonging to a group being the same.

When the time track (or tracks) assigned to a synchronous traffic channel is released, the corresponding entry in the associative memory is deleted, and the lists and parameter values ​​are updated accordingly. The resulting gap then becomes available again for asynchronous traffic.

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In addition to the principles described above, all required procedures are standard, so no further detailed description is necessary.

Procedure for allocation change.

When the bandwidth or time track assignment is changed, the contents of the associative memories at both sides of the transmission arrangement, that is, in both the multiplex device and the demultiplex device, must be changed in the same way. If, during the necessary signaling process, a delay occurs, the new contents of a row in the associative memory may become available in the demultiplex device some time-section cycles later than in the multiplex device. This would of course result in errors, e.g. that data from a synchronous input channel transmitted in a newly assigned time track is interpreted as asynchronous (store and release forwarded) data and consequently is transferred to the buffer memory for data packets.

To solve this problem, the procedure described below is applied. Some circuit completion required is shown in Fig. 4, to which reference is made hereinafter.

Four different states are defined for the associative memory rows, and these are represented by two additional bits (the transition mask): active = 1, passive = 00, transition from active (to passive) = 01, and transition to passive (from active) = 10.

As a new time track is established for synchronous traffic, associative memories are filled and activated as follows. First, the new line contents (3 fields = start bit position, bit number, channel number) are transmitted to the demultiplex device and fed there, along with the transition mask 10, into a free (passive) memory line. However, this data is left unanswered because of the mask 10. A confirmatory message is then sent to the multiplex device. There, upon receipt of the confirmation, the same row contents are placed in a free (passive) memory row together with the same mask 10. At the same time, a flip-flop (86 in Fig. 4) is set. The output of the flip-flop provides at the beginning of the next section cycle: a) insertion of an indicator bit into the section's first bit position for notifying the demultiplex device and b) a search process for finding transition mask 10

7504748-0 and subsequent change thereof to 11. Thereafter, the new row content is active in the multiplexer.

Within the same section cycle, the demultiplexer first receives the indicator bit with which a flip-flop is set. The output of this flip-flop also initiates a search process to find transition mask 10, which is later changed to 11. Thereafter, the new line content is also active in the demultiplexer so that the received data is conveyed correctly.

When a time slot is eliminated, the contents of associative memory need not be erased but merely passivated. The steps for this operation are the same as just described except that no field content (start bit position, etc.) is transmitted and entered and that the masks used are first 01 (line content still valid) and finally become 00 (line passive),

The necessary circuit extensions for the multiplex device are shown in FIG.

(for the demultiplex device, the circuit elements are analogous and therefore need not be shown separately). The two bit positions of the transition mask are visible in associative memory 10 and in the input / output register 10a on the right side. The flip-flop 86 is set when the mask 01 together with the new line content or mask 10 is set. This is caused by a signal T (transition) on line 88. For inserting the indicator bit into the first position in the next section, there are gate circuits 90 and 92, line 94 and the contents of the bottom row of associative memory. When the first bit (000) in one section is available, channel address Q is read out to open gate circuit 90 via decoder 70. Since gate circuit 92 is also opened due to line 96 being active, the signal from line 66 to line 94 is generated and causes generation of the indicator bit on line 38. The pulse on line 94 also resets the flip-flop 86 and additionally initiates the search and change process for the transition masks.

Then, when the second last line of the associative memory is read out, the synchronization pattern is transferred from register 84 to the transmission line as explained above. During this time, the search and change 7504748-0 process for the transition masks can be performed so that each memory row is activated (or passivated) already within the current cycle.