Microprocessor controlled signal pattern detector

KB 3-A4 according to SIS 61 30 13

<td>SWEDEN (19) SE ϋ</td><td>(12) PUBLISHING LETTERS 3 (51) International class</td><td>iBi (2D 7704964-1 G 11 B 5/02</td>

<td>now live i</td><td>(44) Application outsourced and outsourced 81 -05 - 1 8</td><td>(11) Publication 418 340</td>

<td>! W |</td><td>publication paper</td><td>number</td>

<td></td><td>(41) Application generally available 77-10-1031 (22) The patent application was submitted 77-04-29 (24) Running day</td><td>Application received as:</td>

<td>Patent Office</td><td>(62) Tribal application number</td><td>X Swedish patent application</td>

<td></td><td>(86) International filing day</td><td>. 'completed international patent application</td>

<td></td><td>(86) Filing date for the application</td><td>with number</td>

<td></td><td>on European patent</td><td>converted European patent application</td>

<td></td><td>(30) Priority information 76-04-30 US 682225</td><td>with number</td>

<td colspan="2">(71) Applicant: INTERNATIONAL BUSINESS MACHINES</td><td>CORPORATION</td>

<td>ARMONK, NY</td><td>US</td><td></td>

<td>(72) Inventor: J</td><td>D Dixon, Boca Raton, Fla.</td><td></td>

<td colspan="2">(74) 0mbuds: Gas lands</td><td></td>

<td colspan="2">(54 / Designation: Signal Pattern Detector</td><td></td>

7704964-1

The present invention relates generally to signal detection in and for detecting a particular pattern of signals and more particularly to the use of a programmed processing unit for sensing and detecting a particular pattern.

In magnetic recording - and especially magnetic recording on discs - a double frequency recording technique comes into use. Double frequency recording means recording magnetic flow transitions at a clock frequency, where binary data is represented by the presence or absence of a flow transition between clock flow transitions. This form of recording is a means whereby a variable frequency oscillator (VFO) can be made to respond to reproduced signals from the magnetic recording to synchronize and control the sampling of the recorded data.

In magnetic disk recordings, each latch is normally divided into a number of sectors, each sector containing different identification and control characters, intended for data detection in the sector. Control information for controlling further reproduction lens in a field, called address marking field. The fixed data content in an address marker field identifies the type of field that accompanies the address marker. The register controller is made to search for this particular data combination to control

7704964-1 use of the information subsequently identified. Since other portions of the recorded information may include normal data with the same data content as the searched address field, a further signal detection form has been included in the detection of the particular data field. Address mark detection is therefore a special form of magnetic recording, in which the binary data is mixed with normal clock periods. Instead of having a magnetic flux transition for each clock period, certain flow transitions at clock times have been eliminated from the recording. Therefore, a magnetic disk register controller will confidently identify detection of the address mark when the unambiguous data pattern is detected together with the unambiguous pattern of clock pulses and missing clock pulses within the eight bit character which is subject to detection.

Due to the high frequency with which the data and clock signals must be detected, previous registry controllers have necessitated special hardware and logic, which are used solely for this purpose. Even in such cases, when the magnetic disk register controllers have been utilized using programmed mini or microprocessor units, it has been necessary to include special hardware because the processing units did not have the design and instructional capacity necessary for high speed operation.

The object of the present invention is, therefore, to provide a single-circuit, microprocessor controlled microprocessor which is suitable for detecting the data and clock sequence of address markers.

The present invention includes a minimum amount of circuits in a magnetic disk register controller in addition to those circuits which receive signals from a register in the form of a double frequency recorded magnetic disk, and for generating clock and data signals according to double frequency reproduction technique. A programmed microprocessor unit with the task of detecting data and clock signals includes among its controlling instructions a sensing instruction, an out instruction, a branch at zero, a branch at a zero, and a branch and wait instruction. In the absence of the latter instruction, which will be described, the enumerated instructions can be used for sensing clock signals, missing clock signals and data, but under certain conditions cannot be performed at a sufficiently high speed to ensure correct sensing operations. The execution of the instruction branching and waiting in the microprocessor provides addressing and reading from the program instructions in the memory of the next instruction, which is identified by the address information in the instruction. When access to the next instruction is completed, the branch and wait "" instruction is able to stop the processing unit clock, which prevents the initiation of the execution of the instruction to which access has just occurred. Timing signals generated in the data and clock sensing circuits within the register controller are capable of restarting the clock of the central unit to initiate the execution of the previously accessed instruction, which provides immediate synchronization of the microprocessor to the signals being sensed.

The foregoing and other objects, features and advantages of the invention as defined in the following claims will be apparent from the following, more detailed description of a preferred embodiment illustrated in the accompanying drawings.

Fig. 1 shows how the magnetic recordings are placed on a magnetic disk.

Fig. 2 is a block diagram of the data flow of a programmed microprocessor used for use in the present invention.

Fig. 3 shows the logic of a disk register controller utilized for address mark detection.

In Fig. 1 is shown a magnetically recorded disc 10, comprising a plurality of recording grooves 11, each of which can be divided into a plurality of sectors 12. Each sector 12 has the appearance shown at 13.

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In each of the recording tracks 11 there is an index mark 14, preceded by a gap 15, which indicates the beginning of sector 1. The recorded parts labeled GAP are used for synchronization of the following data. The first significant field in a sector is the sync field, which contains 6 bytes (about 8 binary bits) of recorded binary zeros. The sync field is utilized to provide an initial indication that the next field is likely to be the address selection field 16 and further has the task of synchronizing the detection circuits. The address marking field 16 precedes a field containing a plurality of bytes of coded binary data, called the ID field, which is the identity of the sector to be compared with the identity of a sector being searched. The cyclic control field is an error detection code field for the ID field. The next sync field precedes a new address marking field 17, which is encoded with data, which identifies the next following field such as a data field or a control field. The next cyclic field, which follows the data field, refers to cyclic redundancy control and is generated for the previous data field. Gap 3 signals the end of the first sector.

In order to save time when searching for a particular sector, as soon as the register controller has received the identification of the requested sector, an immediate search will begin for the location and matching of the I D field. Since much of the information recorded in a particular block may have different shapes, it is possible that a character detected in a data field or any other field may in practice match the coded identification of the ID field of the sector, which is sought. Therefore, the register controller must be informed of the exact location of the magnetic display head to ensure that the information being sensed is indeed the ID field of a sector. The technology to ensure that the ID field is being detected requires it to be preceded by the address marking field 16, which in turn is preceded by the sync field, which consists of 6 bytes of zeros. Since again many similar forms of data can be recorded, it is conceivable that a data field may consist of 6 bytes of binary zeros, followed by encoded data, which could be identical to the data in the address selection field 16, and also accompanied by data that could be conceived match the encoded data in the ID field.

In order to ensure absolutely that it is the sync field, the address marking field 16 and the ID field, which are subject to detection, the address marking field is not merely encoded with a particular binary data sequence. In addition, normally occurring magnetic flux transitions at clock times have been skipped or failed. A feature of the present invention, therefore, is that necessary circuits are provided to first detect a sequence of binary zeros in the sync field and then to detect the data in the address selection field along with a pattern of clock signals and missing clock signals.

The representation shown at 18 in the magnetic flow transitions recorded on the magnetic disk to mark the address marking field 16. As mentioned earlier, dual frequency magnetic recording is used, and this is represented at 18, the representation C identifies flow transitions at clock periods. The symbol C indicates a missing clock pulse. In dual frequency recording, frequency F detection occurs when adjacent clock signals are detected without an intermediate signal, which ratio represents a binary zero. When flow transitions occur at a frequency 2F, a flow transition has occurred between two clock flow transitions, representing a binary one.

At 13, two address marking fields 16 and 17 have been shown. The data encoding of the first address marking field 16 is shown at 18 and consists of the hexadecimal binary coding FE, represented in binary form by 11111110. The representation FE identifies the address marking that precedes an I D field. The second address marker field 17 may precede a data field and is therefore coded with hexadecimal FD, and when the second address marker field 17 precedes a field containing control information, it will be coded F8.

A limitation on the use of clock signals and missing clock signals for address detection requires that, if missing clock signals exist, a binary one must be recorded on either side of the failing clock period in order to preserve the synchronization of the variable frequency oscillator.

Fig. 2 is a block diagram of the most important parts of a microprocessor unit used in accordance with the present invention. The base unit of the processing unit is provided by clock 19, which via the timing pulse generator 20 and the cycle control circuits 21 provides a number of control signals TO, T1-Tn. Signal Tn signals the end of the execution of a program instruction contained in an OP register and the decoder 22. Memory 23 contains data, a series of program instructions and other control information. Addressing data or program instructions from memory 23 takes place under control from a control address register 24. Memory address register 24 receives 12 binary bits of address information from multiple sources including an instruction address register 25 which, in response to a +1 increment 26, is capable of providing access to sequential instructions from the memory 23 for transfer to the OP register 22.

Instead of providing access to the next sequential instruction using the instruction address register 25, the branching instructions which are decoded in the OP register 22, the address information is entered into the memory address register 24 and to provide access to an instruction other than the one in the order. To allow branching tilt instructions in a new sequence and return to a previous sequence, a link register 27 and auxiliary register 28 have been provided. Another source of address information consists of addressable registers, called Data Address Registers (DAR) table 29.

The data path within the processing unit comprises a counter / logic unit 30, the output of which can be applied to a data register table 31. Data from the memory 23 is transmitted via an assembler circuit 32 to an A register 33 or a B register34. The registers 33 and 34 may be addressed by program instructions in and for the presentation of eight binary bits for an IO / data output collector 35, or they may be addressed to receive data on an I / O data input collector 36. The decoding of the I / O instructions in the OP register 22, eight binary bit rates are presented to an I / O address acquisition manager 37. The eight binary bits of address information on the collection manager 37 can be decoded in other devices, e.g. a register controller, in such a way that the information on the I / O address collector 37 can be utilized for identifying special registers, latches or individual logic circuits for control or sensing on the part of the processing unit.

A special program instruction, which is essential for address mark detection for utilization of the processing unit, is an instruction, such as potash branching and waiting (BAW). When this instruction is decoded in the OP register 22, it is capable of activating an AND circuit 38 which responds to the final control signal Tn in the branch and the waiting instruction by setting a lock circuit 39, which stops at 19. The lock circuit 39 is reset by a signal on the start clock line 40, which signal is received from the logic circuits in the disk register controller, to be processed in more detail later. Prior to setting the lock circuit 39 in response to the BAW instruction, other control signals have been able to utilize the address portion of said instruction in the OP register 22 via the memory address register 24 to provide access from the memory 23 of the program instruction identified in the BAW instruction. This instruction becomes available at the output of memory 23 at the time the latch 39 is set and stops the clock. When the start clock signal 40 is received at the lock circuit 39, the clock 19 is started, the instruction is entered in the OP register 22, and execution of the instruction begins.

Fig. 3 shows part of the logic in a magnetic disk register controller. which is controlled and sensed by program instructions from the treatment unit. The two base orders for logic, which are decoded by instructions in OP register 22 of FIG. 2, are out-order and sense-order. In connection with where

7704964-1 and one of these base orders appears on some signal readings described below, a hexadecimal representation of the information on the address acquisition 37. The eight binary bits of the address acquisition 37 from the processing unit are decoded and identify certain lock circuits or AND circuits to be controlled or sensed.

In Fig. 3, the reproduced magnetic information consisting of a sequence of clock and data signals is received on a register read data line 41.1 In accordance with well-known dual frequency magnetic recording technology, the sequence of clock and data signals in a variable frequency oscillator (VFO) 42 is used to provide self-timer adjustment. the signals received on line 41 in standardized data signals on line 43 and a standard clock signal on line 44. Oscillator 42 functions in such a way that the combination of clock signals and data signals provide synchronization. If a long series of data signals should fail - or in accordance with the present invention, clock signals fail - a flywheel effect is produced. Due to the flywheel effect, signals are generated on a line 45 at a frequency based on previous control, which is exercised by clock and data signals received on line 41. A trigger 46 is set and reset using the standard clock pulse on line 44 and flywheel power clock pulse 45 for generating at AND circuits 47 and 48 of data time pulses on line 49 and clock time pulses on line 50.

A register control clock pulse is generated on a line 51 from the output of an OR circuit 52 which receives inputs from an AND circuit 53 or an AND circuit 54. The register controller clock pulse on line 51 is utilized in other circuits within the magnetic disk register controller. The control clock pulse on line 51 is capable, when an AND circuit 55 is activated by latch 56, to generate the signal on line 40 in Fig. 2 which can start the clock 19 in the processing unit. The lock circuit 56 will normally be in the restored state, thereby preventing AND circuit 55 from generating the start processing unit clock signal on line 40.

When, according to the present invention, the address mark is sensed, an AND circuit 53 is activated via an inverter 57 when a clock gate lock circuit 58 is in the reset state. The lock circuit 58 is set by a signal on the line 59 from the processing unit when the register controller is used to write data on the magnetic disk. When the locking circuit 58 is in the setting state, pulses from a base oscillator on line 60 are transmitted via AND circuit 54 to provide the base control clock signal on line 51. This becomes the clock signal utilized in the system for entering information on the magnetic disk.

Before the logic of Fig. 3 comes into effect, the register controller, which includes the programmed processing unit, has been instructed to search for the sector ID field in a particular track and for comparison with the desired I D sector presented to the register controller. The programmed processing unit contains a program sequence of instructions, which are primarily used to compare the detected I D field from the magnetic disk with the requested I D field. However, one of the first instructions in this sequence causes the processing unit to be branched from the program that relates to ID field matching to the sequence of instructions used in connection with Fig. 3 to search for the address marking field associated with I D -field.

The first program instruction encountered by the processing unit to initiate the search for the address marker field 16 associated with an ID field is an out-of-order received on line 61. The expression in parentheses B7 represents the hexadecimal coding that exists. on the address collection conductor 37 from the processing unit.

In response to the signal on line 61, a number of lock circuits are set and reset, and these include the aforementioned start clock activation readout circuit 56 and clock gate lock circuit 58, which activate each AND circuits 55 and 53 respectively. This allows the generation of register controller clock 7704964-1 pulse on line 51 and synchronization thereof with signals received on line 41, and allows the requested start of central unit clock 19 on line 40 during the address mark detection period.

Additional latches affected by the signal on line 61 include a high gain latch 62, a data sync latch 63, a bit ring inhibitor latch 64, and an address mark (AM) search latch 65. Execution of the output order on line 61 makes the logic of Fig. 3. ready to respond to further instructions from the processing unit for detecting the sequence of data signals, clock signals and missing clock signals forming the address mark. This has the effect that, during the operation of the high gain lock circuit 62, the data sync circuit 63 and the bit ring inhibitor lock circuit 64, the processing unit is caused to respond to and sense the binary zeros sync field preceding the address marking field 16 in each data sector. The sync field consists as shown in FIG. 1 of six bytes of binary zeros, which, in accordance with the dual frequency recording technique, produce a sequence of pulses solely in response to flow transitions representing clock periods. The purpose of the high gain lock circuit 62 is to influence the VFO data separator 42 to synchronize as quickly as possible with the clock signals received on the line 41. VFO 42 responds to the reset state of data synchronization circuit 63 by identifying the fact that no binary 1 signals will be received on line 41 for ease of synchronization.

The output of the bit inhibitor lock circuit 64 controls a bit ring 66 having eight positions corresponding to the eight binary bits forming a single bit group character recorded on the disk. As will be discussed in more detail below, an AND circuit 67 is provided to respond when the bitrate has zero position, which is sensed by a signal on line 68.

In the search for the address marking field 16, a sequence of instructions is included in the processing unit, which sequence in turn includes an instruction identified as sensing them (BB), which generates a signal on a line 69, which signal at a AND circuit 70 of the processing unit on the data collection conductor 36 presents the state of the sensed data signals, either binary ones or binary zeros. The central unit program sequence is such that before the logic of FIG. 3 enabled for address mark detection, at least 16 binary zeros must be received from the previous sync field. Since the data field in any particular sector itself can also accommodate a long series of binary zeros, this search for 16 consecutive binary zeros is re-initiated if a binary one is detected, indicating that the sensing head is not within the sync field.

If at some point 15 binary zeros have been detected, a central unit instruction, designated out-order (BD), will be generated on line 71. The signal on line 71 is capable of setting AM search lock 65 and bit ring inhibitor circuit 64 and reset high gain lock circuit 62. 64 is set, the bit ring 66 is reset to position 7, ready to receive the tight binary bits in the address mark encoded data sequence. Furthermore, the locking circuit 62 is reset in preparation for the operation of VFO 42 to respond normally to received signals on line 41.

When the central unit has sampled a consecutive binary zero - as shown at 72 in Fig. 1, a sensing order (7D) on line 73 will sample AND circuit 74 which receives the standard clock signal on line 44, which signal is to be presented. This means, if the display head is actually reading the clock signal shown at 75 in Fig. 1, that it is the start of the address marking sequence. Otherwise, the binary zero detected by AND circuit 74 is saved, and the logic shown in FIG. 3 is ready to identify the first binary one, as visus at 76 in FIG. 1.16 binary zeros could have been detected.

7704964-1 very early in the sync field preceding the address marking 16. This makes the circuit of Fig. 3 ready for detecting the first data signal 76 in the address marking field 16.

When the first binary one, shown at 76 in Fig. 1, is detected on line 43 in Fig. 3, AND circuit 77 will produce an output which resets the bit ring inhibitor latch 64 and sets the data sync latch 63. The bit ring 66 will therefore be advanced. to the value zero detected by AND circuit 67, and the binary bits in the data portion of the address marking field 16 are sensed. To ensure that the data portion of the address marking is correctly accumulated, the bit ring 66 must exhibit character synchronization, which is sampled by the AND circuit 67 before allowing the remainder of the address marking detection to occur. The setting of the data synchronization circuit 63 of the first binary one 76 in the address mark's data portion results in the VFO data separator 42 being synchronized with the data signals received on the line 41 and the flywheel clock pulses 45 due to the fact that the sequence of pulse signals on the line 41 may now include missing clock signals.

The eight binary bits, which represent the data portion of the address mark, i.e. the sequence of binary ones and zeros, are accumulated in an eight bit serializer / deserializer (SER-DES) 78, which is one of the register controller. The data portion of the address mark, presented on line 43, is accumulated in unit 78.

As the data portion of the address mark is accumulated, a series of sensing orders (7D) on line 73 will sample AND circuit 74 for presentation to the central unit of the data collection conductor 36 of the state of the received clock signals. The central unit instruction sequence for sensing clock signals or missing clock signals, testing the state of the clock signals and continuing the address mark detection or re-initiating the detection requires a base sequence of instructions. The sequence includes the utilization of the aforementioned branching and wait instruction, the sense order shown on line 73, and a branching instruction which tests the state of the clock signal sensed as presented on the data collection line 36 from AND circuit 74. The testing of the state of the clock signal sensed by AND circuit 74 is performed by a branching instruction capable of providing access to a subsequent instruction from the central unit memory 23 if the state of the sensed clock signal is correct in accordance with the pattern shown. at 18 in Fig. 1. If the state of the clock signal sensed is not correct according to the sequence at 18, the branching instruction is capable of returning the program sequence to the instruction which, when decoding, generates the signal on line 61. This gives rise to the reset of the logic of Fig. 3 and the central unit's program sequence in and for renewed initiation of the search for the previous sync field and thus the address marking field 16.

As the correct detection of the sequence of clock signals and missing clock signals progresses, a processing unit instruction is executed to generate a signal on a line 79 to indicate that the detection has progressed to the point indicated at 80 in FIG. 1, which causes the reset of address mark search lock 65 and data sync 63. The program sequence proceeds in the manner previously described, but the reset of the data synchronization circuit 63 is capable of influencing the VFO data separator 42 to identify that it is now beginning to use clock transitions instead of data transitions for synchronization, as clock signals will now be present on line 41 as shown. at 18 in Fig. 1.

As the processing unit program sequence proceeds in response to receiving the correct state of clock signals and missing clock signals on line 41, a final test will be performed regarding the state of the sequence of clock signals and missing clock signals, which test examines the clock signal shown at 81. , reads the correct address mark

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sequence of clock signals and missing clock signals received. At this time, a final check for a correct address mark detection is performed by generating a signal on line 82 to enable an AND circuit 83 to transmit the data received and stored in the serializer / deserializer 78 to the processing unit for comparison with the expected data content FE , indicating that the detected address mark was indeed associated with an ID field Once this final check has been made, the program sequence will return to the origin sequence that was initiated for ID fide comparison.

For each clock signal to be detected and tested, access is made to a group of three program instructions from memory 23 in the processing unit. The first instruction in each sequence is a branch and wait, which stops at 19 in FIG. 2 after accessing the second instruction in the sequence, which is used to sense the state of the clock signal. The instruction sensing the kiosk signals or the missing kiosk signals is activated when the register control clock pulse 51 is generated to actuate the AND circuit 55 of Fig. 3 to generate the start kiosk signal 40. The sensing instruction will be executed for storing an indication of the clock signals state or , received on line 41. The third instruction in each of these sequences is branching at clock conditions which, when the state of the clock signal is as expected by the branching instruction, provides access to the next instruction, which is in turn. This will be the first instruction in a next group and is a new branch and wait. If the state of the clock signal does not match the expectation of the branching instruction, the address portion of the branching instruction will cause the program sequence to return to the instruction that generates the signal on line 61, which instruction in the order precedes the group of instructions consisting of branching and waiting, sensing and branching.

Above, the logic has been shown, which is used in combination with program sequences in a processing unit for sensing the correct state and the correct order of clock signals and missing clock signals. In the absence of an instruction such as, for example, branching and waiting, it would be difficult to synchronize the relatively slow processing unit with the higher rate of clock signals and missing clock signals. If variations are found in the synchronization of the two systems, clock signals or missing clock signals could be generated at a time during the processing unit cycle, when a particular clock display instruction would not be accurate in execution. Before a new sensing instruction can be subjected to access in the correct sequence, then the kfock signal for testing would have disappeared and give incorrect results.