Interference reduction circuit

(54) Designation: Interference reducing circuit t

The present invention relates generally to communication systems and more particularly to interference reduction circuits to provide separation in polarization in multi-channel systems at 3 frequency of the type where each polarization in a double-polarized communication link here has its information on the same radio frequencies.

By using two orthogonal polarizations simultaneously, an effective doubling of the bandwidth in a communication system is obtained. Even greater and more efficient bandwidth can be obtained at the satellite by utilizing multiple antenna lobes. which are separated by space separation of the lobes. Systems utilizing this technology are attributed to multi-channel systems at the same frequency and are particularly interesting in satellite communication systems. Depending on the polarization characteristics of the satellite antenna and the ground station antenna such as the non-ideal axial ratio of the feed, the antenna's depolarization, and the like, there is a certain amount of static transmission between the signals. In addition, due to factors such as Faraday's rotation, the position of the satellite and the depolarization of the signals due to effects from rain, there is a fairly large coupling between the signals which are of a dynamic (e.g. time varying) nature. Both the static and dynamic interference in cross-polarization contribute to seriously impairing the realization of systems where several channels utilize the same frequency. In the article in TrC5 BELL SYSTEM TBCIIliICAL JODBITAL volume 50, number 9, November, 1971, pages 5063-5069 of Ϊ.3, Chu with the title

7501940-6

Resboring the Orthogonality of Two Polarizations in Radio Communication Systems, I propose an orthogohalizing circuit applying differential phase shifts and differential attenuation to two signals to orthogonalize them.

In a reception system, the circuit described by Chu is arranged in the guide between the antenna and the receiver and the like. works directly on the fields in a double-polarized waveguide. The circuit is designed to provide a single correction that is applied over the entire received bandwidth and its effect on a channelized basis (e.g., separate corrections for different parts of the frequency band) would be difficult to realize.

A further object of the present invention is to provide a simple interference reducing circuit which enhances polarization separation and is intended for use at one end of a multi-channel communication link at the same frequency, which circuit can be arranged to follow the receiver either on a broadband basis or on a channelized basis to provide independent interference corrections for a variety of frequency bands.

Said and other objects of the invention are achieved by providing an interference reducing circuit which operates on two or more space-separated signals by cross-coupling the signals so that the interference signals are eliminated in each channel. In addition to a dual-polarized system, no elimination is achieved by adding polarized channel of a sampling of the same amplitude, but of the opposite phase, as the interference. The realization of the circuit in a constructive embodiment involves sampling a portion of the signal in each port on a dual-polarized system and feeding that signal back to the other port at a point where the signal in the latter port has undergone a time delay so that the unwanted signal is eliminated. in the gate in question. This technique can advantageously be used in multi-port systems by switching transmission from Each port to all other ports in such a way that the interference signals in the other ports are (at least partially) eliminated. All that is required is that there must be as many ports as there are desired signals and that there is at least one port at which a desired signal is stronger than the unwanted signal.

A presently proposed embodiment of a circuit having the specific structure of the invention and a context in which the invention is utilized will be described below with reference to the accompanying drawings, in which Figure 1 of the diagram shows separation degradation due to incorrectly directed polarization 5. a linear double-polarized system, Figure 2. shows a diagram of a series of curves indicating polarization separation as a function of the ground station's axial ratio;

Figure 3 shows a general set of two reused frequency signals that could be received in a reception system; Figure 4 is a block diagram of a circuit illustrating an embodiment of the interference reducing circuit according to the principles of the invention; Figure 5 shows a second general set of two reused frequency signals where the angle of incidence between the major axes is greater than 90 °; Figure 6 in diagram shows a series of curves indicating the value of the coupling factors as a function of incorrectly oriented angle required to obtain an infinite signal-to-noise ratio for the case where the carriers have equal axial ratio and equal amplitudes; Figure 7 is a graph of a series of curves indicating the additional attenuation as a function of misaligned angles for the signals having identical equal axial ratio and equal amplitudes and arriving at the interference reducing circuits; Figure 8 in block diagram form shows an alternative embodiment of the interference reducing circuit. utilizing active means, Figure 9 shows an alternative embodiment of the circuit for elliptically polarized signals, Figures 1OA-1OB show in horizontal and. Fig. 11 is a block diagram showing a possible realization of a variable power divider utilizing fixed couplers and variable phase shifters; Fig. 12 in schematic form showing a closed loop for obtaining elimination of cross-polarized interference in a channel. schematic form shows a possible realization of a detector for an amplitude signal amplitude signal utilized in the system of FIG. 12, Figure 14 in schematic form shows an analog-to-digital converter utilized in the system of Figure 12; Figure 1p in block diagram form shows a digital differentiator utilized in the digital noise network of the system of Figure 12; Figure 16 in block and logic schematic form shows a state controller utilized. in the digital control network of Figure 12, and Figure 17 in prino-schematic form, it shows the digital-to-analog converter of Figure 14.

In order to be able to place the need for the usefulness of polarization here in a suitable way

7501940-6 perspective, it would be instructive to refer to some sources of error that cause degradation in connection with polarization and the influence of their sources on separation. In a satellite ground link that is polarized double line; peas, the primary sources of degradation in the separation are the following:

a) Faraday rotation,

(b) the orientation of the satellite;

(c) the polarization characteristics of the satellite antenna; i

(d) the polarization characteristics of the ground station antenna; and

e) depolarization due to rain. ;

If the field vectors arriving at a ground station are orthogonal and if the ground station antenna is linearly polarized, the ratio of the desired and undesired received power (P 2 / P 2) at each port at the ground antenna is infinite. However, if, depending on one of the above listed sources of error, the incoming vectors are either non-orthogonal or are misaligned with respect to the field antenna's field vectors, the separation is degenerate. The effect of this effect is shown in Figure 1, which illustrates P / P in a channel in the ground antenna versus the misalignment of the incident field vectors. For example, if the incident vectors deviate from the orthogonal by 1 ° (or alternatively are orthogonal but misaligned with the ground antenna by 1 °), the separation will be reduced from infinity to 35.5 dB. A 5 ° misalignment reduces the separation to 22 d3. The graph of Figure 1 shows the vector orientations that equalize the ratio B_w/^Pu in each channel. If the ground antenna does not follow the polarization of the incoming wave, the ratio becomes P_w/ P_u for each channel different.

The situation becomes even worse in the event that the ground and satellite antennas have a finite axial ratio (eg because they are not perfectly linearly polarized). Figure 2 shows the ratio F_w/?_y the axial ratio of the ground station for a plurality of cases on the axial ratio and the deviation from the orthogonal of the main axes of the incoming waves where the orientation of the ground station is again set to equalize in each channel.

Pet should be mentioned that the degeneration of the ratio P_w/ I *_u is even more serious in circularly polarized systems based on the hardware capabilities of the present art. Sven in a complete system, the combined effects of separation of upper link and lower link will further reduce the P / P ratio.

vr u

The necessity of an antenna system that could compensate for these effects is obvious. Although the polarization direction is essentially of a time-varying nature, each compensation system should be dynamic (e.g., continuously controllable).

7501940-6

An idea has been developed in connection with the advent of the present invention which can significantly improve the ratio_W/ P_u in a double-polarized system with multiple channels at the same frequency and which can in principle also be used for multi-loop systems. Ultimately, the technique includes that a portion of the signal is sampled at each port in a dual-polarized system and that this sampled signal is fed back to the other port at the point where the signal in the latter port is affected by a time delay so that the desired signal is eliminated in the port. port. The idea can be extended to multi-port systems by coupling from each port to all other ports in such a way that the interference signals in the other ports are (at least partially) eliminated »

For the sake of clarity, the circuit description assumes that the incoming signal has identical amplitudes, although this is not necessary for the function of the circuit.

A general indication of two reused frequency signals that could constitute incoming signals in a reception system is shown in Figure 3. The behaviors E and E. represent the amplitudes on the principal axes of two non-orthogonally elliptically polarized carriers having the axial ratios r and 2 respectively. r ,. The sign of r is negative for left-hand rotation and positive for right-hand rotation (carrier return), or rather 1 <| r. Ask the orthogonal ports of the receiving device are indicated by x re3p. y. Bet is assumed that the orientation of the gate is as shown in Figure 3 so that the unit vectors shown in the figure have the following rectangular components u_A = cos ax + sin α y sin α x + cos cy

Λ

<img file="SE407001B_D0001.tif" />

-sin αχ + cos (ty = -cos α x + sin α y

The gate voltages and become thereby ^Ex ^{= (E}A ^uA ⁺ 3 ^rA^{_1 E}, vj · X + (EU + j _r -&gt; _B γ). * b “b 'b^Ey ⁼ ^^Eb ^ub * 3 ^rb^{_1 E}b ^vp 'y + (E_Q u + jr * 'E v) · (1) (2)

Betta gives:

<td>B_x</td><td></td><td>c 1 1</td><td>«Μ c 1 2</td><td></td><td>^EA</td>

<td>ey</td><td></td><td>c 2 1</td><td>C 22</td><td></td><td>^Eb_— M</td>

7501940-6 there

<td>c 11</td><td></td><td>COS</td><td>α</td><td> —</td><td> 3</td><td></td><td>its</td><td>α</td>

<td></td><td></td><td></td><td></td><td></td><td>_β</td><td> — 1</td><td></td><td></td>

<td>C ' 12</td><td>⁼</td><td>sm</td><td>α</td><td></td><td> 3</td><td>^rb</td><td>cos</td><td>α</td>

<td>C 21</td><td> =</td><td>its</td><td>α</td><td></td><td> 3</td><td>r ²A</td><td>cos</td><td>α</td>

<td>C</td><td> =</td><td>cos</td><td>α</td><td> +</td><td> 3</td><td>^rb</td><td>its</td><td>α</td>

(4) (5) (6) (7)

It is appropriate to express cij in polar form so. that there

<td> -</td><td>Εχ^ΕΥ _ -</td><td>ι</td><td>Α 1 1 Α 21</td>

<td>Α 1 1</td><td> = 1</td><td>C 1 1</td><td></td>

<td>Α 12</td><td>= I</td><td>C 12</td><td> • _</td>

<td>Α 21</td><td> « 1</td><td>G] 21</td><td> =</td>

<td>Α 22</td><td> » 1</td><td>c 1 22</td><td> -</td>

'33.

2

33,

A e ²²22

<img file="SE407001B_D0002.tif" />

»· · ' (8)

C / ~ cos²a + r ^²· Sin²ct sin²a + 3¾^-2. cos²ct sin²a -i · r ^² CCS²a ^, / cos²c £ + r ^² its² ο (9)

CIO} {11} (12} tan¹ tan¹ tan¹ tan¹ tan n •• a cot a _ ^rb_ cot α ^Atan α (13} (14) (15) the:

7501940-6

As shown in Fig. 4, the interference reducing circuit 4 comprises directional coupling means 3 »4, 5 and 6 with voltage 3 coupling factors k 1 and four variable phase shifters 7» 8, 9 and 10 with phase shifts given by φ.

1J

Each direct coupling means has two incoming ports and two outgoing ports with one of the incoming ports on the coupling means 3 and 5 terminated in a full load impedance and one of the outgoing ports on the coupling means 4 and 6 terminated with a full load impedance. An output port on the directional connector 3 is connected directly to an incoming port on the connector 4 via the phase shifter 7, while the other output port is cross-linked to an incoming port on the connector 6 via the phase shifter 8. Similarly, an output port is on the connector. 5 directly connected to one; Incoming port on the coupling means 6 via the phase shifter 9, while the other outgoing port is cross-linked to an incoming port on the coupler 4 · The connection voltages are applied to the incoming ports 1 and 2 in the circuit shown in FIG. Bet is then easy to show that the output voltages on ports 11 and 12 become ί^E, A = V ⁽¹ - ^k^{k 2}) E_v^{e 12} - kk E e ²ⁱ (17) ¹ 1^Λ V 1 2 λ 2 3 y

----- ~ -3Φ -jA (1 ~ k /) il - E_y e '· - k, B_x c&gt; * (IS)

Ask explicit expressions for the output signals are obtained by using the ones in Equations 17 and 18 for B and B as given by Equation 8. xy

Ε = E iA a

Vt¹' ^k (1 - k ²) A e ^¹¹'1 2 1 1 ί (β ~ Φ)

- kk A e ^{21 23} ia 2i

V⁽¹ "K ²) (1 - k ²) A e ¹V 1 2-12 (19 ^Φ12&gt;

(β - Φ) - kk A e ^{22 23}

3 22

Ε, = E äA a

V⁽ⁱⁿ - * k) (1 - k ²) A e 3 * 21 j (8 - Φ)

- kk A e ^{11 cb} &lt;i 11 (8 - φ)

1 3 «I + E.

V (I - k ²) (1 - k ²&gt; A e \ 3 * 22 j (B_ - Φ)

3 (8 - Φ ..)

3 &lt;t

- kk A e ¹² ** «ι 12 (20)

7501940-6

In order for the interference signals to disappear at all times to be eliminated in each channel, the factor for disappearance at the gate 11 is necessary, and the factor for E_A beyond the gate 12. The two equations that must be fulfilled become

<img file="SE407001B_D0003.tif" />

- k ²) (1 - k /) 1

<img file="SE407001B_D0004.tif" />

A

3 (β

- k ²) (1 - k ²) 3 &lt;1

<td>Φ)</td><td></td><td></td><td>3 (β</td>

<td> 12</td><td>r · k</td><td>k</td><td>A e</td>

<td></td><td> 2</td><td> 3</td><td> 22</td>

<td>Φ&gt;</td><td></td><td></td><td>j &lt;3</td>

<td> 3«,</td><td>- k</td><td>k</td><td>A e</td>

Φ&gt;

²³ - 0 (2ϋ φ)

1 “= ο (22}

By multiplying the equation 21 by 0 ^^ 12 ^ 12 ^ and the elevation 22 _e-j (&amp; 2i ~ Φ34) and require that the sleeves of both equations be real, the following state of the values ​​is introduced and φ = β ^T23 22 β + ό ± 2 m ir; m = 0,1,2, .., 12 12 φ = β * 1 «, 11 β + φ + 2m ir; ι »= 0.1,2, ... 213 *, (23) (24)

The phase shifts indicated by equations 23 and 24 can, of course, be achieved by varying the lengths of the transmission lines or by using variable phase shifters. In practice, the necessary phase control can be achieved with the phase shifters φ ^, and φ.. The phase shifters φ ^ are included in the circuit for a complete description.

Assuming that the determined phase shift values ​​are included, the elevations 21 and 22 will take the form

Vd - V) (1 - V)

A = kk A 1 2 2 3 22 (25) y (lk «) (1-k *²·)

A bkk A .21 1 * 11 (26)

In that, since there are four individual coupling means, a simplification can be obtained by boxing kg = k, and k ^ = k ^. By dividing the equation 25 by the equation 26, the ratio of said chin can be determined according to

Λ A k ²/ k ² = JJ_ J ± BQ² (27) ²¹ Λ A

2122

Qk (2S)

7501940-6

Substituting Equation 28 into Equation 26 gives a quadratic equation for k ^z ty (l - Q² k ² ) (1 - k ² ) A = k ² A '.1 I 21 111 (29) [_C k * lQ² - A ² / A ²* 11 21

The solution is obtained in the form there

-v [^J + Q^z k = 2 / H / G + (H / G)² - 4 / G

Η = 1 + Ό¹

G = Q² - A ² / A ²11 12 (30) (31) (32) (33)

The specific solution values ​​for said k are not interesting in themselves. The important thing to note is that for the incoming signal states of practical interest there is a solution for the k: n, which means that by using variable switching means and phase shifters in the circuit of Fig. 4, the ratio P_w/?_u be significantly improved.

It remains to be considered several special but very important cases that can provide great insight into the frequency curve characteristics of the correction circuit.

Case one where r = r.

ab

If the axial ratio of the two carriers is equal, the corresponding equations will be substantially simplified. An examination of the determined equations gives that in equation 27 Q = 1. Hence k₂ = k and all four coupling means have the same degree of coupling. Furthermore, from equations 2J and 24, 3 is obtained₉= whereby from equation 29 is obtained

A

1

Ä + A 11 21 (34) cos²ct + r ~² its²and sin²a + r² cos²A

POOR

QUALITY

7501940-6 (35)

When this value for k, together with those through equations 25 and 24, is inserted at the gate 11 given by the determined phase washers 3, the equation 19 is indicated, the output voltage '

- E.

(1 - k²)

<img file="SE407001B_D0005.tif" />

xi j

<td>Γα ² 1 1</td><td>-A * ²“2 X</td><td>« = E</td><td>A</td><td>- A</td>

<td>A L ix</td><td>+ A 2 X.</td><td>A</td><td>XX</td><td>2 X</td>

The factor of Ξ represents the gain (voltage) gain of

Sr.

3_Asignal (always less than zero). The additional attenuation in dB is therefore given

I »~“ 20 log

11.

"in

ÖB (3S)

Call 2. r = = r, ab

Since both carriers are linearly polarized, the equations are further simplified. The connection values ​​are all identical and the same applies to the lengths of the connection lines. The value of the coupling from Equation 54 is reduced to its q cos α + sin α and the output voltage of the port 11 becomes from equation (35) cos α - sxn α

The term co3 - sin, o

Case 5.

represents the additional gain.

(37) (38)

The foregoing results have been derived from two non-orthogonal signals for which the space angle between the main axes is less than 90 °. The adjustment circuit3 works similarly even if y&gt; 90 ° provided a 180 ° addition is included on the phase in one of the cross-connection connections. This can be shown by means of Figure 5 which shows two signals with A 90 °. As before, the gates are adjusted so that the ratio? „, /? leveled in both channels. The gate voltages are thereby

7501940-6 ^Ey ⁼'^BA ^Εχ = ^EA

<td></td><td></td><td></td><td> -</td><td></td><td></td><td></td><td> •</td>

<td>cos α + jr “^l its</td><td>α</td><td> -’· ^Eb</td><td>its</td><td>α +</td><td>3 -b¹</td><td>cos</td><td> 0</td>

<td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td>

<td></td><td></td><td></td><td> -</td><td></td><td></td><td></td><td></td>

<td>sin a - jr_A^-1 cos</td><td>α</td><td>+ E_b</td><td>cos</td><td>α -</td><td>3 A ”¹</td><td>its</td><td>A</td>

<td></td><td> .</td><td></td><td></td><td></td><td></td><td></td><td></td>

(39) (40)

The factors for E and B. are the same as indicated by c. in the equations ab 13

4-7 except that sinus &lt;1 is replaced by -sinus CL. The matrix expression for equations 39 and 4θ using polar form for the factors becomes

3«.

A e ¹¹11 j (δ + π)

A e ¹²12 j (5 + ir)

A e ²¹ A e ²² . 22 (41) where —i

Compare the equations (15 - 16)

Substituting Equation 41 into the outputs of the output voltage of the interference reduction circuit (Equations 17 and 18) will yield a number of phase relationships identical to Equations 23 and 24 with, replaced by the corresponding exponential terms in Equation 41 *, while the 1, 2 term for the above matrix contains an extra 1Γ term becomes the phase length of the ^ ^ compound

- (δ + 'τ;) + φ - 2m π (42) correspondingly x

^Φι « ⁺ * n ^(δ2’, ^{+ π) +} Φ₃₂ “^2m * (43)

In this way, the connections contain an added phase difference of 180 ° compared to the case where y &lt;90 °. The coupling ratios also remain unchanged for their values ​​for γ &lt;90 °. The most important point in this regard is that the circuit can not generate the most general types of non-orthogonal signals by utilizing variable switching means and variable phase shifters.

7501940-6

They should be instructive to calculate the coupling rates and the additional attenuation for different states. While the most general case involves signals having different axial ratios, a qualitatively high and far-reaching insight can be obtained in the circuit's way of working by considering the much simpler but very important case of two non-orthogonal signals having the same axial ratio. For this case, it should be noted that the coupling values ​​are given by Equation 34 and that the additional gain of the desired signal is obtained by Equation 38. These equations are outlined in Figures 6 and 7 as a function of · CL for varying values ​​of the axial ratio r.

For the case corresponding to CL = 0, the two carriers are space orthogonal but have finite axial ratio and the interference reducing circuit gives a finite ratio Ρ / ΪΡ in each channel with the following coupling degrees and the additional attenuations.

<img file="SE407001B_D0006.tif" />

Equations 44 and 45 represent the minimum coupling value and additional attenuation as the axial ratios of the two carriers are finite exhibiting the same amplitude and having the same degree of rotation. For a given value of Q, the lowest additional attenuation and the minimum value of k are obtained in case the signals are linearly polarized. The attenuation approaches infinity even if either Ct 45 ° or r -&gt; 1, since for these states the signals are parallel in the polarization space.

In the discussion so far, it has been assumed for practical reasons that passive switching means and phase shifters have been fully utilized. However, this assumption is not necessary and a practical application of the adjustment circuit utilizes active amplifiers and phase shifters as shown for example in Figure 8. However, the basic philosophy of interference reduction remains unchanged, ie. to cross-connect a number of signals to achieve interference elimination. As shown in Figure 8, the incoming signals are E and E. y from the system's receiving antenna coupled to incoming ports 13 and 12, respectively. 14th After amplification in the amplifiers 15 and 16, the signals are coupled to the power portions 17 and 18, respectively. the power portion 17 connected to the input of an amplifier 19 connected to a variable phase shifter 20. The second output of the divider 17 is connected to the input of

7501940-6 on amplifier 21 connected in series with. a variable phase shifter 22, in the case of the power divider 13, this has one output connected to a variable phase shifter 23, while the other output is connected to a variable phase shifter 24.

The outputs of the phase shifters 20 and 2j are combined with the power dealers 25 which are connected to provide an output signal at the output port a »and the outputs of the phase shifters 22 and 24 are combined with the divider 27 to provide the second output signal B port 28.

The extension to more than two signals is simple in principle and can be considered for two different situations, namely when the signals are incident from different space directions and when they are incident from the same space direction and can only be distinguished by their polarizations. As an example, three linearly polarized signals whose polarization vectors are separated by 120 ° can be mentioned. In both cases, it is assumed that there is at least one port for each desired signal and that at this port the amplitude of the desired signals is at least greater than the amplitudes of all other signals. at the gate in question. If a 3-signal matrix for an 11-port is considered, the above statement is equivalent to the requirement that the absolute value of the diagonal term of each row be greater than each of the non-diagonal terms.

The process of interference reduction is equivalent to diagonalizing the signal matrix. In the event that the signals fall from different directions of space, the degree of sodium will be the same as the number of directions from which the signals come. If all directions are different, each row becomes. in the matrix independent and the circuit which diagonalizes it has the effect of placing the pattern in the space directions in all the interference signals.

However, in the event that the signals come from the same space direction, the signal matrix is ​​fundamentally limited to being of the second order. If the number of signals is greater than two, then not all equations become independent and the matrix has at least an intrinsic value of zero. Betta means that it is not possible to utilize a single cascade network that interconnects all the desired signals so that respectively. has an infinite ratio Ρ ,, / Ρ ^.

However, Betta does not exclude the possibility of intially dividing each signal K paths. A number of networks operating in parallel can thereby be utilized to extract varying combinations of signals. Subsequent networks can in turn be used to seed the recombined signals so that each signal has an improved ratio^pw / -_u·

Another way of practical importance to approach the present problem is to almost diagonalize a given signal matrix. In this case, a routine,

7501940-6 in which a search is made for circuit element values ​​that optimize the ratio P, / P_u for each signal is subject to the restriction that the signal-to-noise ratio (s / lf) is maintained above the specified minimum value.

The previous analysis has shown that by using networks formed by variable switching means and phase shifters, interference elimination can be obtained for incoming signals which are optionally polarized. It should be noted that in the event that the signals are linearly polarized, all phase shifts are identical (except for a possible 180 ° difference in the cross-coupled connections) and, in addition, all switching means assume that the signals have equal amplitudes. This means that a fairly simple circuit can be obtained if the incoming i

The elliptically polarized signals are first converted to linear polarization. This linearization is easy to accomplish by inserting a specified amount of phase shifts for a particular part of each of the incoming carriers. The mathematical relations that must be fulfilled are derived here in terms of the polarization quantities that have already been defined.

For a carrier, for example in the form of 3_&amp; or as shown in Figure 3 is the ratio of left to right hand circular components ^EJ?^er

J 2T (46)

There r is the axial ratio and Τ 'is the angle of inclination of the main axis. The x-axis as a reference becomes Έ = cl for E and Τ '~ 90 ° - ¢ (, for E .. As before, o determines the sign for r rotation, (-) for left-hand rotation, (+) for right-hand rotation, Hereby becomes the ratio for the y component to the x component = Ε / E y 'x

<img file="SE407001B_D0007.tif" />

(47) the size of p is _(R2 + 1) - (r² + - 1) + (r²

1) cos 2 τ

1) cos 2 ^τ (48)

7501940-6

The phase angle for ρ · is obtained by plotting the equation 47 p-jfr - l)² + (, r + l)² + j 2 (r² - 1) sin 2T ((r - 1)^Z + (r + l)² + 2 (r² - 1) cos 2 T

Then arg (p) = tan

2r

Jr.⁴ - l) sin 2τ_ (49)

To linearize the fields, arg (p) and arg (n,) must be set to 0, For here3&gt; D the carriage B becomes r = r, ° aa * a, For the carrier r = r ^,

The state arg (p) = arg (p,) thus gives

SL · * O * tan ”} ·

<td> —</td><td></td><td></td><td></td>

<td>² r_A</td><td> - 4«.,.</td><td>^{2 r}b</td><td></td>

<td>(R_A² - 1) sin 2 α</td><td>- t an</td><td> 2 (^rb J)^{sin 2}(^α ·&gt; · T)</td><td></td>

<td>J</td><td></td><td> —</td><td> - </td>

The solution for .bl o = 1/2 takes »sin 2 γ (51) cos 2 Y

By fixing the x and y coordinates so that the conditions shown above are fulfilled and applying a phase delay of arg (p) to the signal component of the y axis, two non-orthogonal linear, polarized signals are obtained. Dassa can thereby be applied to the interference reducing circuit.

It should be of interest to note that if r = r., The value of exactly

3rd D that equals the ratio P_y, / P_u in each channel, i.e. the ports are arranged as in Fig. 3 «The complete interference reducing circuit has only one phase shifter linked in the signal path of the y port.

This alternating interference reducing circuit is shown in Figure 9 · Polarisa tower 29, which is a variable phase shifter for a polarization, receives the non-orthogonally elliptically polarized carrier waves B_&amp; and E ^, the output of the polarizer 29 is connected to a rotatable orthodontic converter J0_O The Polari7501940-6 satator 29 and converter 30 are independently rotatable so that the output signals

E and E fed to the inputs of the interference reducing circuit 32 2C form two non-orthogonal linearly polarized signals. The outputs of the circuit 31 are thereby constituted by the separated signals E ^ and E ^.

Other builds are possible. As an example of an extremely simple construction of the interference-reducing circuit for linearly polarized signals, Figures 10A and 10B show a band line design comprising printed circuit wiring directional couplers.

Figure: 10A is a plan view of the middle board of a sandwich-built band lead circuit 3 where solid lines indicate wires printed on the upper surface of short oats and the dashed lines indicate the printed wiring on the lower surface. It should be noted that the two conduits extending between the input ports 32, 55, respectively. the output ports 34 »55 pass through the printed circuit board at points 5 ^ and 57. The line thus starting at the input port 52 is printed on the top surface of the card and extends to the point 56 and is then printed on the bottom surface. The opposite applies to the conduit beginning at the input port 55. For example, the ratio of the middle board 58 to the conductors 59 and 40, which are printed on the upper and lower surfaces of a dielectric foil 41, with respect to the upper and lower dielectric foils 42 and 45 on the outer plates 44 resp. 45 is shown in FIG. 10B.

In Fig. 10A, the input signals E and E are connected to the input ports 52 xy and 55. Most of the power is transmitted directly from the input ports 52 and 55 to the output ports 34 and 55, respectively. 35, however, a portion of the power at the Input Ports 32 and 33 is coupled to the cross-connection lines 46 and 46, respectively. 47 at this cross junctions 4θ and 45 · This effect is then, after a suitable phase delay determined by the lengths of lines 46 and 47, connected to the direct input and output connections at the cross junctions 50 and 45 respectively. 51 to eliminate the interference signals in the two channels. As a result, the separated signals E and E och appear on the output ports 34 and 35.

In another embodiment, the interference-reducing circuit utilizes fixed coupling means and variable phase shifters to achieve the same power as with variable coupling means. A variable coupling means working with this idea is illustrated in Figure 11. This coupling means utilizes a fixed 3dB power divider, such as a Tee 52 tuning unit, variable phase shifters 55 and 54, and a fixed 3dB quadrature equalizer 55 · Any desired power sharing ratio can be obtained by appropriate selection of phase shifts φ between 0 ° and 9θ ° ·

According to this idea, an interference-reducing circuit as shown in Figure 4 can be designed to use only fixed switching means and variable phase shifters.

7501940-6

Such a circuit is desirable from the viewpoint that variable phase shifters can be electrically driven and therefore suitable for dynamic control.

So far, the practice of the invention has provided a knowledge of the axial relationship and the angles of inclination of the incoming waves. However, a practical implementation of the invention is desirable, so the condition is that interference reduction should occur despite no knowledge of the structure of the incoming ice rays. Beta may be achieved by utilizing pilot arrow signals associated with, respectively. communications signal. Circuits sensitive to such level signals are utilized to drive amplifiers or attenuators and phase shifts to reduce the amplitude of the level signals and thereby the associated interference communication signals to zero in the channel in question.

Bet is quite clear that the circuit is not limited to being placed between the antenna and the first receiving stage. The circuit can be applied to the HF amplifiers, follow each channel to a number of frequency bands, or even follow conversion to another frequency provided that the coherence between the desired signals in one channel and the interference in another channel is sufficiently protected. The structure associated with the necessity of obtaining coherence is well known.

In an illustrative embodiment of the invention, an applicable interference eliminating circuit is designed to dynamically compensate for the cross polarization interference. Since the interference on each channel in a dual polarization frequency recovery system works with a component of the signal on the opposite polarized channel, the interference signal available at the receiving end becomes relatively coherent with the desired signal in the second polarization 3 channel and in this case elimination can be accomplished by adding in a sample. of the signal from the opposite polarized channel of the same amplitude, but with the opposite phase in relation to the interference.

The structure of the elimination system is symmetrical. What is done to eliminate the interference on the left channel by adding in a signal from the right signal is repeated exactly to eliminate the interference on the right channel. Therefore, only one case is described here. Figure 12 shows the structure of the basic system for eliminating the cross-polarization of the interference on the left channel. An arrow signal is transmitted to the right channel somewhere in the band being corrected. The magnitude of the interference is simply measured by detecting the magnitude of the arrow signal appearing in the left channel as derived from the power divider 56. The coupling of the signal to eliminate the interference is performed at RF by a voltage controlled attenuator 57 and a voltage controlled phase shifter 53. The detection and control circuits

7S01940-6 coupling means t 59 and the coherence is not required between the two polarizations through each subsequent step '. The interference is minimized by detecting the magnitude of the level signal and drives the voltage controlled phase shifter 5θ and attenuator 57 until the size of the level signal is minimized.

Because the amplitude of the arrow signal is the important parameter, the first system block after receiver 60 is an amplitude detector 61, which output signal is usually a DC error signal E proportional to the size of the arrow signal. Both systematic minimization technique is obtained by first minimizing the phase control and then the amplitude control or vice versa and providing coupling and minimization to achieve and determine a true zero. This type of circuit is conveniently carried out with digital technology so that subsequent blocks in the system are an analog-to-digital converter 62 which converts the analog error signal B into a digitally usable form.

The following · system block consists of a digital atyr network 65 which determines which control to adjust (phase or amplitude) and in which direction adjustment should be made to achieve the minimum. This network generates two output signals, each comprising a 1-bit 3 word. One of these words represents the voltage to be applied to the damper and the other word represents the phase shifter control voltage. The undulating control network consists of two digital-analog converters 64 and 65 which change the digital control word to analog voltages suitable for driving the voltage controlled phase shifter and the respective voltage. attenuator,

The amplitude detector amplitude detector is shown in Figure 13. The input signal to this step is the arrow signal after it has been detected and downgraded to low frequency. The operational amplifier 66 is utilized to provide the amplifier signal gain. It is also utilized as a high impedance load for the receiver and provides separation from the remainder of the circuits. The potentiometer 67 allows the gain for this step to be varied from one unit to the gain of the amplifier opens the feedback loop, the potentiometer 68 is used to control the internal DC power from zero while such drive in this step would prevent the circuit from obtaining an absolute zero.

The operational amplifier 69 serves as two opposite half-wave rectifiers, which have in series resistors 70 and diode 71 and in series connected resistors 72 and an opposite polarized diode 73, each connected between the inputs and outputs. Amplifier 69 compensates for the 0.6 volts lowering across the diodes?

7501940-6

The operational amplifier 74 constitutes a unit amplifying buffer step for holding the differential amplifier 75 resulting from interaction with the rectifier. If this huffing step were present, the rectifier would not be able to maintain a zero voltage at point 3 during the positive half of the output voltage because the current of the differential amplifier would be forced to pass the resistance 72 to the reversed terminal of the rectifier amplifier 69.

The operational amplifier 75 is utilized as a differential amplifier for unit gain to generate a full-wave rectified version of the signal at its output. The operational amplifiers 78 and 77 are both utilized in two low-pole active filters. By cascading these two filters, a total filter with four poles is obtained. For higher frequencies on the beam signals, a four pole 3 output / orth filter can be used. The output of amplifier 77 constitutes a fault signal E soin has been affected to a minimum.

The analog-to-digital converter is shown in Figure 4 »This circuit converts the error signal B into a digitally usable form by means of differential voltage comparators 78. If the voltage at the negative input terminal of the comparator is greater than the voltage at the positive terminal, the output assumes a voltage level which is significant for a logical zero »About. the voltage at the positive terminal is greater than the voltage at the negative terminal produces the output of the comparator than significant logic zero.

The reference voltage is divided by the resistance voltage divider 79 to receive twelve references, with which the error signal is simultaneously compared. Thus, a twelve-bit word is generated.

As the error signal is made smaller, more and more bits become a logical zero starting with the most significant bit and ending with the least significant bit. The lens of the control system will, from a digital point of view, bring all the bits in the 12-hitter word to logical zeros.

The digital control network can be divided into two main sections. First, there is a digital differentiator that analyzes the direction of the change at the time of the error signal E; Second, there is a state unit that operates with four mutually exclusive states:

1) the amplitude increases,

2) the amplitude drops,

3) phase one increases, and

4) the phase decreases.

These states refer to the control being affected and the direction in which the control voltage is varied.

7501940-6

The digital dlfentator is shown in Figure 1? and includes a memory 30 and a comparator circuit 31. The twelve-bit error word is fed to the memory's data inputs. · and Q outputs constitute the twelve bits as they were when the clock signal was last high; 1, if the clock signal is high, the outputs remain in this state * During the periods when the clock signal is low, Q_x = ΰ_χ. However, this does not pose any difficulties since the information can be extracted at any time in the clock cycle.

The error word and the preceding error word are attributed to a 12-bit size comparator 81. Since the purpose is to minimize E, the relevant information about the word in memory is larger or smaller in size than the current error word or not. If the word in memory is smaller, this indicates that the direction of the correction is incorrect and would be reversed. Therefore, the only output of the comparator needed is the signal where B is greater than. A, which means a logical 1 if the word in memory is less than the present error word.

The state controller as shown3 in FIG. 16 determines the direction in which the control is acallically adjusted to effect an internalization. The flip-flop 82 utilizes the output of the size comparator to determine if the direction of the control voltage change is correct. The output signal BA becomes a logical one if the direction is incorrect and a logical zero if it is correct. Thus, said output signal applied to the input of flip-flop 82 will cause a directional correction for the change when the clock signal goes high and only if the direction is incorrect. The complementary output signals from the rocker, ie. Q and Q, one allows for utilization for enumeration control and the other for enumeration control.

The second flip-flop 83 is used to control the nature of the correction, phase, or amplitude. The output signals will change state whenever the input signals go high. This will occur under either of two conditions. The first state occurs when the output of flip-flop 82 changes four times, indicating that a relative minimum has been reached. This is easily detected using a four-bit counter 84 whose output becomes 1 after four counts.

The second state occurs when the main clock signal has pulsed sixty-four times as detected by the counter 85. This only works to find a limitation on the length of time added in each correction mode so that no one is neglected for too long.

OR gate 86 provides one when either of the above two states exists. One from the OR gate triggers the modification by changing the state of the flip-flop 83. At the same time, when the OR gate 86 turns to one, counts 84 and 85 are reset to zero.

7501940-6

The outputs of the flip-flops 82 and 85, together with the incoming main clock signal, are thereby applied to four three-input NAHD gates 87-90 The output of these NAND gates will become a logic zero if all three inputs are logical ones, and become a logical one. one if one or more inputs are. zeros. Thus, one of these four NAKD gates will have an output signal that follows the main clock signal and the other three NAIID gates will remain on logical one. These output signals: from the four UA1ID gates are applied to the phase and amplitude counter 91 and 91 respectively. 92, to generate the binary number representing the desired phase and amplitude control voltages, Because only one of the four NAND gates will follow the clock signal at any one time, only one counter will be pulsed and thereby in only one direction, which corresponds with the desired control function.

An example of the digital-analog converters 64 and 65 is shown in FIG. 17. These converters are designed for use in operation amplifier summing connections. The gain for each incoming signal is increased by a factor of two for each more significant bit. The conversion is done in two steps. The first two amplifiers 95 and 94 each convert four bits at each time. The output signals from these transducers are thereby summed to provide a step dividing of the control voltage range. The extension in the control range can be varied by using variable resistance 95 such as the feedback resistance of the operational amplifier 96 · The variable resistance 97 allows the addition of a direct current bias for placing this area anywhere within the supply constraint. These controls allow easy adjustment of the circuit to any voltage controlled phase shifters or dampers utilized.

It will be apparent to those of ordinary skill in the art that a circuit has been described in which the 3-signal interference ratios for non-orthogonal signals may be substantially improved. The general approach for clarifying the invention utilized in the above includes cross-coupling of non-orthogonal signals arrow such that the interference is eliminated. The idea is expandable, to several signals. It should also be apparent that the idea shown can be implemented inversely and, in addition, inversely when passive components are utilized. Thus, the circuit can generate non-orthogonal signals. This could be done, for example, at the transmitting end of a link to feed two signals in such a way as to compensate the propagation effects. In accordance with the above, therefore, the invention may be subject to modifications within the scope of the following claims.

7501940-6 . 22 . . -· .