Interlevel communication in multilevel priority interrupt system

(54) Title: Computer for performing tasks on the basis of a priority step hierarchy

The present invention relates generally to computer equipment and more particularly to the central unit of such equipment. The invention relates to such computer equipment which must process any of a plurality of service requirements which occur at random but are assigned special priority levels. The present invention is particularly useful on a computer in which a series of control elements are used for interrupt level processing with different priority in such a way that the highest priority group present at a given time exercises control of the common memory / arithmetic unit or other logic units at the expense of lower priority levels.

The central unit of a computer must often process randomly occurring service requirements from one of a number of sources of requirements. Priority levels are known to be assigned to these interrupt requirements as a function of the importance associated with providing a response to the requirement. In many previously known central units, there is an interruption requirement with a higher level than that, which is are processed, sufficiently to cause a reaction, whereby the status of critical registers and the interrupted level conditions are placed in a reserved area in the main memory so that they can be recovered and transferred to the controlling

7405128-5 elements after the higher level interrupt has been served. The response or response time delay associated with the total programming effort to perform this storage and recovery operation has been reasonably satisfactory for many data processing applications. However, the need to get closer to a real-time response is becoming increasingly apparent for some data processing applications, especially for example process control. Some successful attempts have been made to improve the real-time response of a central unit with a special focus on process control or data acquisition. Hereby, a redundancy circuit arrangement has been achieved in which the critical elements of a processing unit belonging to the execution of a program are duplicated for each of a plurality of priority levels, which configuration is sometimes called virtual. This arrangement allows the acceptance of a higher level debris requirement and treatment of this requirement, keeping the interrupted critical elements simply isolated until the higher level process is completed. With this arrangement, it is possible not only to avoid the program time loss associated with storage and recovery, but also eliminate the risk of a programming error recovering the interrupted program and re-initiating its execution.

The previously known computer, in which circuits several interrupt levels are embedded, provides an increase of a central unit's real-time responsiveness. However, the occurrence of interrupt treatment at a lower priority level, which itself has been interrupted, prevents a new interruption from being interleaved at this level for treatment until the level is cleared. It has been possible to prioritize between levels by means of the multi-level apparatus by assigning a relatively high priority to the initial interruption level for a given source, but once the interruption has been accepted, the processing of this interruption continues at a lower level. This has been accomplished by means of a program-initiated interrupt buffer setting, which effectively empties the higher level of the initial interrupt requirement and then places the lower-level processing of this requirement in a queue at least after the lower-level interrupt, which itself had been interrupted. However, there are times when it would be desirable to continue to postpone the interrupted program of lower level until the execution of yet another program at this same level has been completed. The only way this could be accomplished in prior art devices was to completely erase the contents of all the current registers at the lower level and force acceptance of the programmed interruption from the interrupt acceptance queue.

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The present invention provides means for reviewing a level of priority that deviates from the one being treated or determining its status. If the deviating level has been interrupted but yet another program is to be interleaved, according to the present invention there are means for determining that the lower level was running as well as means for storing the status of the critical registers and conditions for this level and means for initiating these registers, so that they are automatically prepared for work on the prerogative routine. The interrupted routine can later be returned to the registers to continue with its processing at a later date. Thus, according to the present invention, there are means for allowing interruption of processing at a current priority level in order to address a divergent level and storage of the contents of associated registers, if desired. The registers at the addressed level can be initiated by this same addressing mechanism. This makes it possible to review the status of an addressed interruption level register and to decide whether a pre-emptive routine should be allowed to enter before the completion of the interrupted routine.

Although the present invention is most useful for reviewing and pre-treating / resuming interrupt operations at a lower level than the present one, the invention can also be utilized to initiate treatment at a higher level interruption. Preferred, however, is that the higher level cannot be interrupted by a lower level.

Accordingly, the main object of the present invention is to increase the flexibility of a multi-level interrupting central unit through the consent of intimate-level communication.

Another object of the invention is to provide a method and apparatus for pre-treating a program in a multi-level central unit so that an intervening program can be executed.

Another object of the invention is to provide means for communicating with a deviating priority level from a current level in the organization of a multi-level central unit, so that the interrupted level can be returned to the current status after the completion of the priority program. The more detailed features of the invention are set forth in the following claims.

The above and other objects, features and advantages of the invention will become apparent from the following, more detailed description of a preferred embodiment illustrated in the accompanying drawings.

Fig. 1 shows the configuration with several priority levels for a central unit and associated channel, for which the present invention represents an improvement.

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Fig. 2 is a block diagram of important elements in connection with the central unit of Fig. 1.

Fig. 3 illustrates the manner in which the present invention can be utilized to extend the flexibility of a system similar to that shown in Figs. 1 and 2.

Fig. 4 illustrates an arrangement that responds to a particular instruction for permitting data acquisition from a central unit level that deviates from the current level, in collaboration with the circuit of Fig. 3.

Fig. 5 illustrates yet another arrangement that responds to particular central unit instructions for allowing activation of a central unit level circuit to give precedence to the use of these circuits in cooperation with the circuit of Fig. 3.

The general elements of a multi-priority operating unit are shown in Figures 1 and 2. The general functional relationships of the main elements of Figures 1 and 2 are briefly discussed below for background purposes.

The central unit 10 contains a main memory 11 and counting / logic unit and central unit control means 12 which are substantially equal to their counterparts in previously known central units. However, the illustrated central unit 10 is believed to be capable of providing interrupt service with four priority levels. For this purpose, each of the register and state circuits 13-16 contains sufficient logic equipment to operate with both the control means 12 and the main memory 11 in dependence on each other. The priority level control logic 20 responds to the present service requirements with the highest interruption priority by activating the register and state circuit 13-16 corresponding to this interrupt level while isolating all other register and state circuits. For example, if an interrupt level 2 is processed by the register and state circuit 15, the circuits 13, 14 and 16 are passive. If a level 1 interrupt requirement is received over the main conductor 21 from the interrupt demand lock circuits 31 in channel 25, the priority level control logic 20 will pass the circuit 15 whenever an interruptible point is reached in the processing, and activate the register and state circuit 14. Thus, the function of the memory 11 and the control means 12 together with either circuit 13, 14, 15 or 16 is equivalent to the function of four redundancy central units. This is an important part of what is sometimes called an organization with a virtual central unit.

Current level lock circuits 22 and start lock circuits 23 facilitate control logic 22 control of the central unit. The handling of a level-2 interrupt results in the setting of the level-2 lock circuit in the lock circuits 22. The occurrence of a service requirement from the level-1 lock circuit in the lock circuits 31 causes the logic 20 to clear the level-2 current level lock circuit 22, setting level-1-current level 7405128-5 locking circuit 22 and further setting level-2 running locking circuit 23. Later, the level-1 interrupt processing will be completed and pass-through of level 1 will be indicated to logic 20. The logic 20 then clears the level-1 current level-lock circuit 22 and examines the on-going circuits 23. In the present example, one would find that a level-2 interrupt processing itself has been interrupted, so that the level-2 current level-lock circuit will be set and the level-2 register circuit and state circuit 15 reactivated to recover the control of the central unit in and for continuation of this interruption level treatment. The relative relationship between the interrupt level register and state circuits and other elements within the central unit 10 will be apparent from the following description in connection with Fig. 2.

Channel 25 allows control of the central unit 10 in response to any of a number of possible states. So e.g. For example, an IN / OUT device can present its interrupt requirement via the main conductor 26. The IN / OUT interrupt requirement is then presented with its specified interrupt level together with some relevant information regarding the source of the interrupt source, device status and the programming subroutine to be called for processing this interrupt. The central unit 10 can compete for interrupt processing via the conductor 27. This means that a program which is under execution in the central unit 10 may indicate that it should be processed in competition with other interruption requirements priorities. Thus, the data corresponding to the interrupt priority level, the identity of the interrupt source, and the processing subroutine to be used would normally be input via the main conductor 27 into the program setting interrupt buffers 28. These interruptions then compete via the conductor 33 with any other devices which can request service, e.g. standalone devices, timers, etc. 32 via the conductor 34. Competition, stacking and requirements acceptance logic responds to the varying interrupt requirements that exist to determine which should be granted access to the interrupt buffer with register 30 via gate circuits 35 using a desired algorithm. For example, it may be determined that a program interrupt, set in buffer 28 at level 1, should have priority over any other IN / OUT interrupt, also assigned to level 1, which occurs on the main conductor 26. If desired, logic 29 can store a An indication that a program-level level 1 has been accepted or a pending level 1 interruption from another source must be accepted before a new program-level level 1 requirement is granted. Such an arrangement can be derived from the general principles of US Patent 2,543,242 entitled Multiple Level Priority System (Adams et al.). Critical data regarding the interrupt to be processed is entered sequentially at the correct level 0-3 within the interrupt buffer register 30, after which the interrupt demand lock circuit 31 for the correct level is set. Note that service requirements can be entered in the buffer register 30 even while an interrupt is being processed in the central unit 10.

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In a typical function, a program that performs monitoring functions and conducts initial information is loaded into memory, and initialization occurs by transmitting control information to the program interrupt buffers 28. Initially, there are no other competing interrupt requirements, so data can be transmitted under control from the monitoring program. Finally, interrupt requirements are received via the link connection 26, which can for example be derived from communication devices or other IN / OUT connections. As previously mentioned, these interruption requirements compete with standalone devices, timers, etc. 32 together with the program-interrupted interruptions in the buffer 28. Buffer 28 is illustrated with four interrupt priority levels. The logic 29 makes a decision to break a connection and assigns access to the interrupt buffer register 31 corresponding to the interrupt level associated with each requirement. Only one requirement can be accepted at a time, and it is loaded into the buffer 30 until the central unit 10 can accept an interrupt for this particular level. When an interrupt is granted for a given level, the data contained in the current buffer register 30 is transmitted to the appropriate control elements in block 12 and is additionally placed in the correct register and state circuits 13 -16 corresponding to that level. Furthermore, the interrupt demand lock circuit 31 for the accepted level is reset so that logic 29 can load a new requirement into the buffer 30 for this level. Although the arrangement of Fig. 1 is shown to utilize four interrupt priority levels, it is understood that greater or lesser number of levels can be utilized.

Fig. 2 illustrates some of the applicable elements of the central unit itself. Here is an instruction address register 40 which selects the particular instructions which are to be executed from memory in a well known manner. Other elements are the operation register 52, the memory address register 53, the memory data register 54, the mask register 56, the unit area 57, the Y unit 46, the register 1 * 7, the count / logic unit 44, the count / logic circuit 45, and the data register buffer 48, which substantially all have for the purpose of controlling the operation of the central unit in a manner well known in the art. Further, each priority interrupt level has an instruction address help register 41, designated IARB0-IARB3, corresponding to the four priority interrupt levels. Each priority level also has an accumulator and state and indicator memory section 42 assigned to it. The debris levels also have a plurality of index registers (XR) and status relief registers (SRB) 43, assigned to these levels. Thus, operation of the central unit under control from a third-priority interruption involves the use of IARB3, ACC3 and associated state and indicator memory together with XR1-3, XR2-3 through XR7 ~ 3 and SRB-3. Although these elements control the function of the central unit, the equivalents are maintained for levels

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0, 1, and 2 are all in the passive state of the priority level control logic, even though an interrupt requirement at any of these levels will interrupt the Level 3 processing when they occur, provided they are allowed by the interrupt mask register 56.

Each time a higher priority interruption occurs, the above mentioned registers, accumulators and the like are simply left for the lower level in the state where they were at the point of the interruption, and the control switches to the higher level. This allows a quick machine return to the lower priority level to continue its processing, once all higher-level interruptions have been adopted. From this it can be seen that IARBO, ACCO and associated state and indicator memory together with XR1-0 through XR7-0 all correspond to registers and state circuit 13 for level 0 in FIG. 1. Direct channel control 55 permits transmission of associated information, which is found in the interrupt buffer register 30 in FIG. 1, to correct register positions corresponding to an interruption requirement which is about to be adopted.

The interrupt level signal on line 49 permits the transmission of associated information encoded from the interrupt locking circuits 31 of FIG. 1 to correct register positions in the working area 57. These bits in the working area 57 are combined with the bits from the direct channel connection DCC55 to determine the starting address of the subroutine. as a result of the interruption.

The units 44 and 46 allow the selection of one of a plurality of main conductors to be the source of information to be transmitted to a single destination main conductor. The work area 57, the register 47 and the data register 48 are registers which are made up of a variety of lock circuits. They are used for temporary storage of information during the execution of an instruction. Unit 45 is a counter / logic unit which is generally known and used in existing computers for performing arithmetic and logic functions. 3AR53, SDR54, IAR4o, OP register 52, IM ”56, workspace 57, Y46, Y register 47, counting / logic units 44 and 45, and data register 48 occur only once in a multi-interrupt central unit and are shared by the aforementioned multiple interruption levels.

The present invention provides means whereby a program running at an interrupt level in a shared, priority priority central unit via the lines shown in Figures 1 and 2 can control, communicate with, and, if necessary, impede the function of a program on another priority level. In the past, there is a central unit, which for controlling the total circuit supply is controlled by a priority priority interrupt mechanism and furthermore has a complete set of registers and permits for each such interrupt level and for reducing the total work in connection with task switching, when av7405128-5

crimes occur. This has generally been described above for Figures 1 and 2. Such a system has certain advantages, but because of the very way in which instructional address registers, other registers and states are shared on interrupt priority level basis, it tends to exclude communication levels between. The only common medium for such communication is via the main memory. Thus, for example, at Level 1 software operating has no information as to the condition that Level 2 operating software has achieved. Nor can it, if required, cancel the execution at level 2. It should be observed that the requirement for level 1 to be able to cancel level 2 operation, start a new operation at level 2, allow it to be completed and then restart the level 2 operation is important for the application of such a shared system in time-sharing contexts.

As will be described later in connection with Figures 3, 4 and 5, the present invention provides the shared system of Figures 1 and 2 with the ability to perform these functions. In a multi-interrupted computer, the present invention allows for a program at a different hardware level, initiation of another program, and precursor to this program for re-initiating the original program without loss of data or continuity of the original program instruction string. In a computer with complete isolation between the various interrupt levels of the hardware as described for Figures 1 and 2, it is not possible to prevent the execution of a program at an interrupt level and then reinitiate it at a later time while retaining all data and continuity of the instruction stream . The present invention realizes this capability of providing support hardware for performing operation in response to instructions for granting this capability. These instructions will be labeled read IAR help (RIB), write IAR help (WIB), store indicators (STI) and branching and unmasked long (BUL). What is unique about the first three instructions in the previous paragraphs is that they have the ability to read or change the values ​​in registers or indicators at a selected interrupt level, which can differ from the current level. This is accomplished without resetting the selected level and allows this level to continue the instruction execution as it becomes the active level.

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The branching and unmasked long instruction performs a registerless branching during resetting of the summary mask and allows the acceptance of interruptions. This instruction allows the summary mask to be set prior to entry into a non-re-entering subroutine and left canceled, respectively, until the instruction is executed in and for return from the subroutine, thereby maintaining the integrity of the routine. The use of a registerless branch allows return from the subroutine with all registers initiated instead of a register needed for the return address.

Two additional instructions offer an alternative option for selecting the level and register, which should be read or changed. These instructions are to load the selected level register (LSLR) and store the selected level register (STSR). These offer a more general solution of the communication and internal level priority control objectives of the present invention.

The instructions RIB, WIB and STI are assumed for the described preferred embodiment to be arranged in a form compatible with the central unit operation register 80 illustrated in Fig. 4. The LSLR and STSR instructions are assumed to conform to the form shown for the central unit operation register 90 in FIG. 5, although it is observed that the registers 52 in FIG. 2, 80 in Figs. 4 and 9θ in Fig. 5 can all be the same register. For the preferred embodiment described, it is assumed that the operation records and associated instructions are 16 bits long, and the bits are numbered 0-15. A common bit configuration for the operation code using bits 0-4 indicates that one of the instructions RIB, WTB or STI must be executed. The particular instruction is identified by a unique bit configuration in the modifier field M, which may contain bits 12-15. For example, if M is hexadecimal 13, the instruction RIB should be executed.

If M is hexadecimal 14, the instruction WIB is selected, while an M of 0 indicates STI.

To execute the instruction RIB, the contents of the IARB register for the selected level may replace the contents of the register specified by the field R (bits 5-7). When the field R is only zeros, the contents of the IARB register for the selected level will be placed in the selection level accumulator. In fact, because an IARB register cannot be included for level 0 because it cannot be interrupted, execution of this instruction, when the specified level is 0, will result in 0 being entered in the register identified by the R field . However, the selected IARB register is unchanged. The level is selected by the binary coded value in bit positions 8-11, the level selection field in the instruction. The selected level is not reset, and therefore, if the selected level is pending, it automatically becomes the current level, when all higher levels are over.

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The output indicator for the output level is activated if the selected level is active or on hold and waiting. If the selected level is not active or pending, the output indicator for the output level remains passive. The arrow indicator is unchanged, but the output level output indicators change depending on the operand entered in the register, which is highlighted by the R field. The indicators for the selected level are unchanged, unless the selected level is the active level.

When executing the WIB instruction, the contents of the register specified by the R field replace the contents of the IAR help register at the selected level.

If the field R for the selected level contains unanimous zeros, the accumulator is used. The contents of the register marked by the field R remain unchanged. The level is selected by the encoded value in level selection position 8-11 within the instruction. The selected level is not reset, so if the selected level is pending, it automatically becomes the current level when all higher levels are exhausted. If a level 0 is selected, the instruction does not perform any operation (No Op).

When executing the STI instruction, the contents of the result, transfer and spill indicators are stored at the level indicated by the level selection field in the register designated by the field R, whereby a field R with uniform zeros again represents the current level accumulator. The level is selected by the encoded value in the sealing positions 8-11 within the instruction level selection field. The selected level is not reset. After this instruction is executed, the current level register, defined by the original R field, will contain the status of the selected level operation. Thus, a hit in this R-field defined register may indicate zero result indicator status for the selected level, another hit the negative result indicator, another hit the positive result indicator, one more bit indicator for even result, one more transfer indicator and one more spill indicator . The transfer waste and the performance indicators at the selected level are not changed. The performance indicators for the current level change depending on the operand entered in the register at the current level. However, the transmission and spill indicators for the current level do not change.

The instruction BUL, in practice, is carried out by the existing hardware, which is illustrated in Figure 2. This instruction contains an operation code that uniquely identifies itself. When the BUL instruction has been entered in the operation register 52, Fig. 2, a unique 16 bit address field is entered into the instruction address register ho and becomes the address for the next instruction to be executed. The transfer, spill7405128-5 and the performance indicators are not affected. The abstract mask is passivated, which returns the control for higher level interruptions to the contents of the interrupt snap register IMR 56, Interruptions are made possible depending on the value of the mask under this instruction. Accordingly, program execution can be interrupted prior to the execution of the following instruction. The R field, level selection and modifier fields are not used for this instruction.

The instructions LSLR and STSR have a common operation code but are separable from the logic because of identifier bit positions in the modifier field.

For the execution of the LSLR instruction session, the contents of the storage location in the main memory are entered as indicated by the effective address in the selected register at the selected level. The level is selected by the content of the current-level register specified by the R1 field in the operation register 90, Fig. 5. The R2 field selects a current level register containing a master memory address and, consequently, defines the master memory location which is either the target or source of data to be transferred from or to the register marked by the field R1, for the LSLR instruction, the field R1 a target register, while R2 addresses a source location in the main memory. The STSR instruction utilizes R1 to select a source register and R2 to address a target location in the main memory. The work area retains the contents of the R1-specified register during these transfers. This operation is described in more detail below. For LSLR, the register marked by R1 contains two bit positions, which select the target register level, and other bit positions, which identify the particular registers at this level. For example, they can select any of the seven index registers, the IAR help registers with the exception of Level 0, where it is IAR (if no IARBO exists) or level status helper register. Loading the level status help register at the current level does not initiate transfer, spills, performance indicators, bit address indicators, and security key at the current level. The transfer and spill indicators at the current level do not change, while the performance indicators at the current level change depending on the input operand. The effective address is the contents of the R2 field.

The content status bit register content bit position for bit position is as follows:

- byte address indicator # 0 (BAIO) j 01 - byte address indicator # 1 (BAI1)} 02 - zero result indicator (Z); 03 - negative result indicator (N);

0h - positive result indicator (P); 05 - even result indicator (E); 06 transfer indicator (C) j 07 - spill indicator (0) {and 12-15 - protection key.

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Note that the bit positions 08-11 are not used. Execution of this instruction is suppressed if the effective address exceeds the available memory size. In these circumstances, a response is invalid invalid address.

In this way, the system has previously been utilized.

The STSP instruction is executed so that the contents of the selected register at the selected level replace the contents of the storage address indicated by the effective address. The level is re-selected by bit positions in the register indicated by the R1 field. Bit positions 12-15 in this same register are used for selecting source registers at the selected bit level as defined under the STSP instruction specified above. Storing level status help registers for the current level does not store current state of the result, transfer, spill, byte indicators and the protection key. What is stored is the value left in the help register of the last pre-break break at this level. The transfer and spill indicators at the current level do not change, while the performance indicators change depending on the stored operand. The effective address is the contents of the R2 field. Again, the instruction execution is suppressed, and an invalid address indicator is highlighted if the effective address exceeds the available memory size. Furthermore, the instruction is suppressed if the effective address at access would override the memory protection mechanism.

The optional prevention of interrupt processing at a given priority level and the ability to access given registers and states at an addressed level are particularly advantageous, whenever time sharing, priority time sharing and so-called role in / roll out operations are desired in a shared central unit configuration. In such a system, significant parameters including the instruction address, arithmetic and logic states, and index registers are contained in completely separate hardware sets for each interrupt level. Such operations have not previously been available with prior art apparatus, in which a given program (the output level) does not have sufficient knowledge of the addressed program to permit the performance of the functions. The present invention now allows such operations to be performed. If an instruction is to be executed in order to prevent an interrupt process, during the execution of this instruction, a clock pulse will reset the input lock circuit 23 in Fig. 1 for the level (s) to be blocked. Under the influence of control arrangements in accordance with the present invention, data can be moved from the instruction address register at the addressed level either to the main memory or to a

7405128-5 index register or an output level accumulator. Similarly, the contents of the addressed level indicators can be moved to the main memory or to an index register or an output level accumulator. This saving of the value of the instruction address register and the indicators allows recording of the status of the canceled program. When a new program at the same level is to be initiated, the instruction address register for the addressed level is filled as well as the indicators for the addressed level either from the main memory or from an index register or an accumulator at the output level. The internal control of the index registers and the accumulators themselves can be handled by programming without hardware assistance.

Fig. 3 illustrates the relationships between the control means and block logic circuits required to provide interrupt level communication at such a multiple interrupt level computer, which has been generally shown and described in connection with Figures 1 and 2. Block 66 contains a plurality of lock circuits utilized for selection. of the current active level. Lock circuits 66 are generally equivalent to the current level lock circuits 22 of Figure 1. There is a lock circuit in this block for each interrupt level in the computer. Only one of these lock circuits will be in the ON state at any given time during normal operation. Block 66 affects the main conductor 69, which is activated by the inverting block 68. The main conductor 69 and the control line 68 are decoded by the selector / decoder 58. The selector / decoder 58 affects the main conductor 60. Main conductors 72 and 73 are merely extensions of the main conductor 60 and are used to select the sets of registers 61, indicators 62 or the IAR auxiliary register 63 by level indication. The register 6l represents a number of sets of registers, divided into N blocks of registers, marked as levels. Each level can have from one to X registers based on the computer requirements and may include index and level status help registers. Principal 72 selects which block of registers for the selected level is active at a given time. The main conductor 71 then selects the particular register within a level, which should be the source or destination of data on the main conductor 65. Indicators 62 represent one register per level for each of the N levels. The active set of registers, represented by a given level in block 62, is determined by the value of the main conductor 72. The active level in the IAR help register 63 is determined by the value of the main conductor 73.

To enable communication with a register at another interrupt level, alternating entry to the selector / decoder 58 is required. This illustration is interrupted by the main conductor 59 and the control line 67. When the control line 67 is active, the output of block 68 is blocked, which blocks the main conductor. 69. The control line 67 connects the main conductor 59 with the selector / decoder 58 and the result appears on the main conductor 60. Now the selection of the active level in register 6l, indicators 62 and IAR auxiliary block 63 is controlled by the main conductor 59 · The source / destination register within a given level is still controlled by the main conductor 71 in the normal way.

Fig. 4 illustrates a method for controlling the level selector lines designated the main conductor 59 in Fig. 3 and the main conductor 82 in Fig. 4. The level selector 67 is found at the decoder 83 in Fig. 4 and is called the level selector line.

84th The source / destination selector master 71 in FIG. 3 is driven by decoder 83 and is entitled Source / destination selector 85 in FIG. 4. The defined data flow and control is best illustrated by an example.

The operation to be performed for this example is to read IAR help from level 3 into register 5 on level 2, the now active level. The instruction read IAR help is read into the central unit's operationBregister 80, corresponding to the Op register 52 in Fig. 2, where the decoder 83 uses the Op code field and the modifier to determine that the level selector line 84 is active. The decoder 8l utilizes the level selector field to determine which level is to be selected and placed on level selector lines 82 and then the input main conductor 59 of FIG. 3. The selector / decoder 58 of FIG. Inverter 68 detects the transmission of gate circuit 67 and prevents main conductor 69 from being used by selector / decoder 58. Selector / decoder 58. presents the newly selected level of the main conductor 60, which is supplied via the main conductor 72 and 73 to the registers, indicators and IAR assistance. The decoder 83 places a value on the main conductor 85 which is transmitted by means of the main conductor 71 to the IAR auxiliary 63. The values ​​of the main conductor 73 and the main conductor 71 select the IAR auxiliary register for level 3 of the IAR auxiliary 63. This value is transmitted to the assembler and the temporary storage unit 64 The value is also placed on the main conductor 65. At a later time in the instruction cycle, decoder 83 utilizes field R to change the value of the source / destination master

85th In addition, the decoder 83 blocks the gate circuit 84, The block pulses used to achieve this change state are not illustrated because they are normal internal computer control pulses. The gate circuit 67 in Fig. 3 causes the selector / decoder 58 to block the main conductor 59 and activate the main conductor 69. The assumption

7405128-5 was made for the current illustration that the currently active level was level 2, so the active level lock circuit 2 in block 66 will be active and presented on the main conductor 69. The selector / decoder 58 now presents the current level 2 on the main conductor 60. new source / destination information provided by the decoder 83 is presented to the master conductor 71 and selects register 5 for level 2. The value of the master conductor 71 denotes register 5, level 2 as the destination. Therefore, the information remaining in the temporary memory 64 is presented to the main conductor 65 and set in register 5 on level 2 in register group 6l.

The above process has got the contents of the IAR help register at level 3 in block 63 to store3 in register 5 of level 2 in block 6l, the now active level.

This operation allows the program execution at level 2 to find out the address of the next instruction, to be performed at level 3, when level 3 becomes active.

If the decision has been made to change the execution of the level 3 program to another program, the value in the Level 3 IAR help register shall be changed. Modification of the Level 3 IAR Help Register performs the same function as a branch instruction in an instruction stream.

An additional function required for effective control of an interrupt level from another interrupt level is the ability to determine if the selected interrupt level is currently pending and able to become the current active level at a later time, ie. if this level was active at the time when a pre-emptive interruption occurred, which gave control to the higher priority level, which is now in progress. Without this information, it is impossible to determine whether the selected level can become the active level when the control is handed over to this level. To illustrate this, reference is made to Fig. 1. Current level lock circuits 22 perform the same function as current level lock circuit 66 of Fig. 3.

They determine which level is the current active level within the central unit.

Walk-lock circuits 23 are used to identify the levels above which higher priority interruptions have taken the lead and which will resume control when the higher priority interrupt levels have been released and control returns to lower priority levels. In the example of reading the IAR help instruction, the contents of the Level 3 IAR register, housed in block 16, were read from level 2 of block 16, the current active level. During the execution of this instruction, locking circuit 3 is tested in on-going locking circuit 23 to determine if it is in the ON state. If the locking circuit 3 in block 23 is in TILD state, an indicator is highlighted at the current active level to indicate that the level is pending. If the lock circuit 3 in block 23 is in the OFF state, an indicator is highlighted at the current active level in the OFF state to indicate that the selected level is not pending. In a particular application, it is the indicator of the current

7405128-5 l6 level, selected to represent this state, the transmission lock circuit. The transfer lock circuit needs no further explanation because it is a standard element included in most computers, the transfer lock circuit is shown in Fig. 1 as one of the states contained in the locks 13, 1h, 15 and 16.

In this example, the transfer lock circuit in block 15 would be set to the same value as the lock circuit 3 in block 23.

In some circumstances, it may be necessary to terminate treatment at a lower interruption level. In order to achieve this, it is necessary to switch off the start-up circuit associated with this particular interrupt level. For example, if it is desirable to terminate processing at interrupt level 3 from interrupt level 2, the locking circuit 3 in block 23, Fig. 1, should be set in the OFF state. This function is performed by instruction IIB. This instruction IIB uses the IAR help register at the selected level as the source and a register at the current level as well as the destination in the same way as the instruction RIB discussed above. In addition to this function, the issuing of instruction IIB causes the selected level to be blocked. This indicates that, if the selected level is level 3 and latch 3 in block 23 of FIG.

is ON, issuing an instruction IIB would cause the locking circuit 3 to be set in the OFF state. Thus, if Level 2 were the current level, Level 3 would not become active when the central unit is released from Level 2. Level 3 becomes inactive until it receives an external interrupt from the interrupt locking circuit 3 in block 31 of Fig. 1. If the locking circuit 3 in block 31 is in the ON position, the main conductor 21 becomes active, and the priority level control logic in block 20 determines whether an interruption of priority level 3 can be considered. If an interruption of priority level 3 can be accepted, the locking circuit 3 in block 23 is set to ON. In addition, the locking circuit 3 in block 22 will become ON, and level 3 becomes the current active level within the central unit provided that neither a higher interrupt level requirement nor a debris mask set for block level 3 is interrupted.

The states to which reference is made in hooks 13, 14, 15 and 16 in Fig. 1 represent special control lock circuits dedicated to each interrupt level within the central unit. Examples of some of these states include transfer, spill, and performance indicators, relating to arithmetic and logic functions at a given level. In order for the values ​​represented by the states at a selected level to be preserved, the instruction store indicator is executed. This instruction stores the contents of the state register to reach the level marked by the level field in the register specified by the R field at the current level.

7405128-5

The general description of this instruction can be found herein in connection with the description of the instruction store indicators. The instructions for the instruction are best illustrated by an example.

The example operation to be performed is reading the state register from level 3 into register 5 on level 2, the current active level. The instruction store indicators are read into the central unit operation register 80 of Fig. 4. Decoder 83 utilizes the Op code field and modifier to determine that the lock circuit is active. The decoder 81 utilizes the selector field to determine which level is to be selected and placed on the level selector lines 82 and thus on the main conductor 59. The selector / decoder 58 in Fig. 3 detects the transition state of gate circuit 67 and utilizes main conductor 59 as its input. Inverter 68 detects the transition of gate circuit 67 and prevents main conductor 69 from being used by selector / decoder 58. Select arena / decoder 58 presents the newly selected level of main conductor 68, which level is supplied via main conductor 72 to indicators 62. The decoder 83 places a value on the main conductor 85, which is passed through the main conductor 71 to the indicators 62. The values ​​of the main conductor 73 and the main conductor 71 select the level 3 register in the indicators 62. This value is transferred to the assembler and temporary memory unit 64. The value is also placed on the main conductor. 65. At a later time in the instruction cycle, decoder 83 uses field R to change the value of source / destination master 85. Furthermore, decoder 83 blocks gate circuit 84, Clock pulses, which are utilized to bring about this change, have not been illustrated because they are well known in internal computer control. The gate circuit 67 in Fig. 3 causes the selector / decoder 58 to block the main conductor 59 and activate the main conductor 69. For the purpose of this illustration, it has been assumed that the current active level was level 2. Therefore, the current level lock circuit 2 in block 66 will be active. and presented on the lead 69. The selector / decoder 58 now presents the current level 2 of the main conductor 60. New source / destination information, provided by the decoder 83, is presented to the main conductor 71 and selects register 5, level 2. The value of the main conductor 71 marks register 5, level 2 as the destination. Therefore, the information retained in the temporary memory 64 is presented to the main conductor 65 and entered in register 5 on level 2.

To illustrate the use of the instruction WSB, the following example is considered, which assumes that data from register 6 at the current active level 2 is to be transferred to the IAR help register reaching level 3. The instruction WIB is placed in register 80 in figure 4 by means of normal central unit operation. The Ορ code and modifier are decoded by decoder 83 and placed on main conductor 85. Data on

7405128-5 the main conductor 85 is transmitted to the main conductor 71 in Fig. 3, and its value selects register 6. The selector / decoder 5θ utilizes the main conductor 69, since the gate circuit 67 is passive. The current level lock circuit 2 signal is placed on the main conductor 69 and on the main conductor 60 by the selector / decoder 58. This value is placed on the main conductor 72 for selection of level 2 registers in block 6l. The value of the main conductor 71 specifies that register 6 is the source register, which is why the value in register 6 is placed in the temporary memory unit 64. At a later point in the cycle of the central unit, decoder 83 activates gate circuit 84, which causes gate circuit 67 at the input of selector / decoder 58 to be changed. The gate circuit 67 then blocks the main conductor 69 and activates the main conductor 59. The main conductor 59 contains a value from the decoder 81 which represents the value obtained from the level selector field in register 80. Therefore, the main conductor 60 and consequently the main conductor 73 select the level 3 IAR auxiliary register in block 63. The main conductor 71 marks the IAR auxiliary register at level 3 such as the destination register. The value from the temporary memory 64 is placed on the main conductor 65 and is thus set in the IAR help register at level 3.

The above two examples have been used to illustrate an application that transfers information from a register at the current active level to a register at another selected level or from a register at a selected level to a register at the current active level. Fig. 5 illustrates the control and data flow required to achieve a slightly different embodiment. This arrangement utilizes the contents of a register at the current active level for selecting the level and the register at that level as source or destination register.

When an instruction to load the selected register is executed, data is retrieved from the main memory and loaded into the register. During a storage operation, the data is transferred from the register to the main memory. This second method is more complex to apply but allows the re-entry code to be used and a shorter programming loop for loading and storing data in registers at a different level. The latter method represents a generalized way of solving the above-mentioned problems.

To illustrate the application of this more generalized method, reference is made to the following example: this example is to take the contents of a Level 3 IAR Help Register and preserve this information for later use. In this example, the information is taken from the IAR help register at level 3 and placed in a storage location. The storage location to be used is marked by a register at the current level. The R2 field in the instruction marks the register containing the storage address. For this example, it is assumed that the value in the R2 field is equal to 4. The value in the R1 field is equal to 6. Therefore, the contents of register 6 at the current level will be used for level and register selection as the source

7405128-5 for data, scm should be transferred to memory.

The generalized description of this instruction, which performs this function, is included in the description of the instruction store selected-level register. The details of the application of this instruction are given below. The central unit places the instruction in the central unit operation register 90 in Fig. 5. Decoder 91 utilizes the Op code, R2 field and modifier field 90 to determine the source register to be specified on the main conductor 93. This information is fed to the main conductor 71 in Fig. 3 for selecting the register containing the memory address. At this point, the main conductor 72 specifies that the current active level is in use, so register 4 from level 2 will be used as a source. The contents of this register are placed in the unit 64 and on the main conductor 65. This information is transmitted to the memory address register 53 in the central unit as illustrated in Fig. 2. The function of the memory address register 53 will not be described in detail, as it is well known and of secondary importance to the present invention. After this function is performed, the decoder 90 utilizes the Op code field, the R1 field and the modifier field 90 to select register 6 at the current level via the main conductor 93 and the main conductor 71 as source registers. The contents of register 6 at the current level are placed in the temporary storage unit 64. The contents advance via the main conductor 65 to the main conductor 95 and are placed in the working area 94 in Fig. 5 ·

At this time, decoder 91 utilizes the contents of working area 94 to determine the value to be placed on main conductor 93 and transmitted to main conductor 71. In addition, decoder 91 receives gate 9? to become active. The gate circuit 92 is connected to the gate circuit 67 in Fig. 3 and influences the selector / decoder 58 to use the contents of the main conductor 59 instead of 69. The selector / decoder 58 uses the value of 59 to determine the value that scm should be placed on the main conductor 60. The value placed on the main conductor 60 is transmitted via the main conductor 73 to the IAR auxiliary register 63. The level 3 IAR auxiliary register is selected by the contents of the main conductor 73 and the main conductor 71, and the contents are placed in the unit 64 and further on the main conductor 65 for transfer to the main memory. via the memory data register 54 of Figure 2. The central unit causes master memory write-up, and the value obtained from the Level 3 IAR help register is placed in the main memory location, which is marked by the memory address register 53, which the central unit previously loaded.

This example illustrates how the contents of a register at the current level can be used to select the level and register to be used as a source of data to be transferred to the memory. The same principle is applied when selecting registers at another level, which should be used as a destination for

7405128-5 data, which is entered from the main memory of the central unit. The general description of the instruction used for this purpose is included in the description of the instruction that is loaded elsewhere, loaded selected level register.

Here is a new example, whose purpose is to illustrate the use of this instruction. The intention is to take the contents of a storage location and enter it in the IAR help register at level 3 while code is executed at interrupt level 2. The R2 field in the instruction indicates the register containing the memory location address. For the present example, it is assumed that the value in field R2 is equal to 4. The value in field R1 is equal to 6. The contents of registers 6 at the current level are used for selecting the level and registers as the destination for data to be transferred from the memory.

The details for the application of this instruction are as follows: The central unit places the instruction in the central unit operation register 90 in Fig. 5. Decoder 91 uses the Op code, R2 field and modifier field 90 to determine the source register to be specified on the main conductor 93. The information is passed to the main conductor 71 for selecting a register containing the memory address. At this point, the main conductor 72 specifies that the current active level is utilized, so that Level 4 register 4 is used as a source. The contents of this register are placed in 64 and on the main conductor 65. This information is transmitted to the memory address register 53 in the central unit, FIG. 2. The central unit initiates a memory read operation. At this point, the decoder 90 utilizes the Op code field, the R1 field and the modifier field 90 to select register 6 at the current level via the main conductor 93 and the main conductor 71 as source registers. The contents of register 6 at the current level are placed in the temporary storage unit 64. It is transported via the main conductor 65 to the main conductor 95 and placed in the working area 94, Fig. 5. Decoder 91 utilizes the contents of working area 94 to determine the value to be placed on main conductor 93 and transmitted to main conductor

71st In addition, the decoder 91 receives the gate circuit 9? to become active. The gate circuit 92 is connected to the gate circuit 67 in Fig. 3 and influences the selector / decoder 58 to use the contents of the main conductor 59 instead of 6b. The selector / decoder 58 utilizes the value of 59 to determine the value to be placed on the main conductor 60. The value applied to the main conductor 60 is transmitted via the main conductor 73 to the IAR help register 63 · The Level 3 IAR help register is selected by the contents of the main conductor 73 and the main conductor 71. The contents of the storage location which is marked by the contents of the memory address register are placed on the main conductor 65. The contents of the main conductor 65 replace the contents of the Level 3 IAR Help Register in block 63. Thus, the contents of a storage location have been placed in a register at a different level than the current active level within the central unit.

7405128-5

The given example describes the entry in a particular register, namely the IAR Auxiliary Register at level 3, It should be noted, however, that by using a different bit combination in the working area 94, one can select any register at any level including the current active level in and for loading or storage according to the circumstances.

The present specification also defines additional functions which can be added to a multi-interrupt hardware-driven computer to provide the ability for an interrupt level to control and / or communicate with other interrupt levels. An important element in this context is the selector / decoder 58 of Fig. 3. This block provides several sources for the main conductor 60. By switching from one source to another during the execution of an instruction, the central unit can select which interruption level will be used as the source or destination for the data at each particular time. Although separate special instructions have been described for performing reading and writing relative to an addressed level, it is understood in the art that they can both be performed by a single special instruction, if desired, with appropriate modification of the support apparatus. For example, three fields or groups of data in such a special instruction may execute a sequence as follows: selecting a register at an addressed level, transferring the contents of the addressed level's register into register positions at the current level or in a main memory location, and transmitting the prerogative. program data to the registers at the addressed level. This can save the time required for at least one instruction execution. Also note that by monitoring the state of the start-up circuits 23 in Fig. 1 it can be determined that it is not necessary to read the registers at an addressed level, if no interrupted processing remains at this level.

According to the present invention, it is now possible, as described for the preferred embodiments, to inspect the state of another level during processing of a current level and decide whether to grant priority to the treatment. The treatment at the current level may require the execution of an interrupt treatment subroutine at another level in and for completion of the treatment at the current level. Under these circumstances, the state of the interrupted level is stored, and the group or set of control registers or the like at the interrupted level is taken into possession of data to perform the task needed to complete the work at the current level. The execution of the pre-routing routine at a level lower than the current level can be permitted by setting the interrupt worm register in and for isolating the current level until the pre-routing routine has been completed. Then the past is returned

7405128-5 routine to the interrupted level and can finally continue the treatment to the end without any adverse effect from the interruption.

For a time division operation, a timer can be used to specify the time interval to be assigned to each user. The interrupt response routine for responding to interruptions from this timer at the end of each time portion can effectively control a master memory queue of control register state for each user, the end user programs being executed at a level lower than the timer interrupt. When a timer interrupt occurs, the state of registers and control at this lower level is transferred to the end of the queue, and the data at the front of the queue is transferred to the lower level registers. Access to the central unit is thus granted on a first IN / first UT basis.