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Full description

Background of the invention

This application claims precedence to US Patent Application No. 986388/61, filed on April 30, 2014, entitled Methods and Apparatus for the Automated Manufacture of KERFLESS Wafers, and also claims priority to the protective elements of US Patent Application No. 011866/62, filed on June 13,

5 2014, entitled Techniques, methods and devices for the automated manufacturing of KERFLESS chips. Both have been integrated

Both documents are hereby referenced in their entirety.

Ideally, silicon wafers for solar cells are 156 mm x 156 mm and 180 to 200 microns thick. Because the highly refined silicon used to make these wafers is very expensive, it would be beneficial to use wafers

<p dir="rtl">10 Thinner, to reduce material costs. Also, with proper cell construction, relatively thinner silicon wafers have a higher relative efficiency than thicker silicon cells. Cell constructions that will show higher efficiency using thinner wafers are those that result in low surface recombination and good light trapping. The cell structure is often Passivated Emitter Rear Contact</p>

<p dir="rtl">15 (PERC) is a more reliable structure. (PERC stands for passive emitter back contact.) This higher efficiency is thought to be a volume combination due to the shorter distance in a thinner object than a thicker one, to the pn junction. The amount of increase in cell efficiency resulting from the thinner thickness depends on the structure Or cell design, and any electronic quality</p>

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for wafer wafer. In general, larger increases are associated with lower electronic quality of the chip. Therefore, there is a strong push to use thinner wafers, for lower wafer cost and increased cell efficiency. Also, there is an advantage of thinner chips, which is that the lower load injection level is higher for the unit size because the same number of photons are absorbed in less material for a higher injection level, and it includes a polysilicon material.

<p dir="rtl">5 Crystal multi-crystalline silicon material lifetime holder at higher injection levels.</p>

Silicon wafers for PV (photovoltaics) properties are ideally made by growing or casting a metal die and then by slicing slices of the metal die into wafers, ideally by wire sawing. Wire sawing can be used to produce thinner wafers. However, these chips were found to be the thinnest

<p dir="rtl">10 They break down during cell manufacturing, electrical interconnection, and packaging in a unit. For these reasons, after experimenting with thinner wafers (as thin as 120 microns), the industry has returned to the previous standard of 180-200 microns. For these ideal cell architectures that involve back-contacting a passive emitter device using polycrystalline silicon, making wafers thinner than 80 microns It also does not offer any profit in the event.</p>

<p dir="rtl">15 The excess fraction of thinner chips includes several assets. During cell manufacturing, wafers often break by propagating a defect from the edge of the wafer. Edge defects include cracks and thin spots. Also, during handling, cracks and defects are formed at the edges, because they are located at the sites of contact with other pieces of equipment during the manufacturing process. Edge cracks are a problem during cell and module manufacturing. Generally, it is found by machines and methods</p>

<p dir="rtl">20 Currently used, photovoltaic wafers thinner than 150 microns are damaged with a frequency that is unacceptable to be practical.</p>

Moreover, overhead wires and other electrical connections must be attached to the upper and lower electrodes of the cells to connect them together. These wires can be basic in cross-section to be able to carry the large currents generated by a solar cell.25 Example, an ideal common copper wire in a cell with...

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3 Universal wires, 1.6 mm wide and 0.15 mm thick. These wires can be attached to the metal on a cell by welding or using a conductive adhesive. The attachment itself creates pressure between the wire and the metal, especially in the case of welding. The thermal expansion coefficients for the wire and the silicon cell differ

<p dir="rtl">5 greater than the modulus of silicon) and thus changes in directing heat to greater pressures between the wire and the cell. Thermal bonding and expansion can lead to delamination of the wire and/or metals from the cell, especially near the edges of any cell. Also, universal wires should be bent from the surface The upper part of the cell is wrapped under the back surface of the adjacent cell. This bending wire also exerts cushioning stresses on the metal parts near the edge of the cell, when bent inappropriately</p>

<p dir="rtl">10 The wire actually touches the edge of the cell, thus causing or propagating edge cracks.</p>

According to another method of manufacturing, a semiconductor wafer is formed from semiconductor melt, generally using techniques disclosed in US Patent No. 8,293,009, issued on October 23, 2012, entitled Methods for Fabricating Semiconductor Bodies Effectively thin the molten material

<p dir="rtl">15 MOLTEN MATERIAL for solar cells and the like, by Sachs, et al., which is incorporated herein by reference. (The technology disclosed in this patent is generally the same as the Direct Wafer® wafer formation technology). In technology, a thin semi-conductor body, such as a wafer, is created from the melt of a semi-conductor material, rather than stitched from a metal casting mold, or</p>

<p dir="rtl">20 Growing it between threads, or another method.</p>

Briefly, according to the Direct Wafer (DW) wafer forming technology, differential pressure is applied across a porous mold sheet and a semiconductor wafer (e.g. silicon) on it. The relaxation of the differential pressure allows the wafer to be loosened. The mold sheet can be Colder than the magma. Heat is extracted through the thickness of the formed sheet in a parallel basis

<p dir="rtl">25 The liquid-solid interface with the molding plate. The temperature of the welded body across its width, which leads to...</p>

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To lower pressures, displacement intensity, and higher crystallization quality. The porous molding plate must be effectively permeable to allow gas to flow through it. It must not be too permeable to allow the introduction of molten material into the pore openings while providing differential pressure. Conversely, pores can become clogged and differential pressure may not be maintained. can enter

<p dir="rtl">5 magma into the slab by: contacting the entire area with the top of the magma; Contact crossing</p>

A partial zone of magma with a molding plate, either overhead, horizontal, or in between; By dipping the mold into the magma. Granular size can be controlled by several means. Differential pressure, sometimes referred to in the direct flake patent technique described herein as a differential pressure system, can be created by maintaining the magma surface at atmospheric pressure,

<p dir="rtl">10 And keep the back surface of the molding plate at less than atmospheric pressure. In another embodiment it is generated</p>

Differential pressure between the faces of the molding plate by venting the back face of the molding plate directly to the atmosphere, while the atmosphere on the forming face of the molding plate is maintained at a pressure substantially higher than the local atmospheric pressure. An advantage of this model is that a vacuum pump is not required. The mold face and the magma surface are in contact with each other for a period of

<p dir="rtl">15 Time can be referred to as contact duration. During at least part of the contact duration, a differential pressure system is provided. It will be useful to form a wafer from the magma, and will be considered as an invention of the direct wafer technology patent, and also one of the disclosed inventions, for forming a welded object in magma, and for forming such an object, such as a wafer, on a molding plate (or, in the case of The inventions disclosed herein do not need to be fired from a molding plate (or mold) to form</p>

<p dir="rtl">20 A valuable item for manufacturing. But also, the foil formed from the molding plate can be removed in a variety of ways. In some cases, the differential pressure regime can be removed, i.e., if vacuum is used, it can be turned off, and the chip is located. Or, the differential pressure system can be reduced i.e., the degree of vacuum can be reduced, or, the pressure difference can be reduced. Also, mechanical means can be used, such as stripping pins, frame stripping</p>

<p dir="rtl">25 frame, or other tool that mechanically contacts the wafer and presses it away from the die plate.</p>

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With respect to the porosity of the molding plate, in one embodiment, the porosity of the surface in contact with the molten material, the subsequently welded material, and the semiconductor material, shall be small enough on a scale where it can make it difficult for the molten semiconductor material to enter the pores. Ideally, the pore size of interest can vary from 0.1 to 10.0

<p dir="rtl">5 Micron. The pores are interconnected so that gas passing through the porous medium of the mold flows optimally in complex patterns, so local blockages are accommodated by finding circuitous paths around any blockage.</p>

The outer surface of the porous body, which is the surface facing and touching the surface of the molten material, can be slightly uneven (on a microscopic scale or larger

<p dir="rtl">10 (lightly), which thus allows the semiconductor melt to contact the die surface only at several specific, densely packed locations. With this structure, gas can flow slightly sideways between the melt and the porous die surface. This allows absorption to be provided by a differential pressure system to deliver Force on the chip surface across a very large proportion of the surface area, almost 100%. This is the opposite of the case where a smaller number of openings can be provided, where pressure can be provided</p>

<p dir="rtl">15 differential pressure through these openings, to create equivalent differential pressure. In the latter case, the differential pressure is localized by the relatively small surface area of the relatively small number of large openings, in contrast to the former case, for an effectively porous body. Because the gas can flow laterally, the differential pressure actually exists in a more distributed nature across the total surface area of the mold. And an attached chip. The word porosity is used here to describe the former condition, not the latter.</p>

<p dir="rtl">20 Wafers made using direct wafer formation technology involve certain features of wire-sawn wafers, for example there is much less waste than raw silicon, due to the lack of material being ground into powder and thus lost in sawing. Furthermore, the method by which they are manufactured, essentially by contact of a die to the surface of a molten material, lends itself to selective control of certain aspects of wafer fabrication, depending on what</p>

<p dir="rtl">25 Mentioned below. However, similar wire-cut wafers are wafers made by a method</p>

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A patented technique for direct foiling of standard thickness is less effective than thinner foils made by the same technique, for the same reasons of effectiveness mentioned above. Also, those relatively thinner wafers made using the patented direct-wafer technology are more fragile or, conversely, not as strong as standard thickness, relatively thicker wafers made using the same patented direct-wafer technology. Bonus

<p dir="rtl">5 Therefore, relatively thinner wafers made using the patented direct-wafer technology will process less raw semi-conductor material than will relatively thicker wafers made using the patented direct-wafer technology.</p>

Therefore, it will be required to reduce the costs of photovoltaic modules, and, in particular, to reduce the size and thus the cost of silicon required for each wafer, manufactured by any method, without sacrificing strength or

<p dir="rtl">10 Reliability or performance. It will be required to increase the strength of the manufactured chips, without increasing their cost, weight, stiffness or other properties. Wafers with a relatively higher efficiency than standard thickness wafers of 180-200 microns will be required. It will be required to allow electrical connections, generally with thin semi-conductor wafers, to be able to connect them to each other and to other components.</p>

<p dir="rtl">15 The researchers experimented with powder-based techniques, creating wafers that had some areas that were thinner than others, such as a thinner interior and a thicker periphery. See example US Patent No. 7,456,084 2B, as Jonczyk et al., method of using a gapped selector in the fabrication of a grid-shaped semiconductor wafer (patent '084). In making the selector, powdered silicon is provided in a mold (indicated referred to as specified in patent '084) in a required form,</p>

<p dir="rtl">20 It will be heated, which turns the powder material into magma and solidifies into a solid silicon body</p>

Multi-crystalline silicon. A fundamental difficulty with the technology disclosed in Patent '084 is that, with any powder technology, the interstitial oxygen content of the vacuum is unacceptably high for a semiconductor, particularly for photovoltaic use. This is because, without connecting supernormal steps, the original oxide particles lead to particles

<p dir="rtl">25 Powder to high levels of oxygen in the flakes. Relatively small particles lead to...</p>

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Relatively more oxygen in the final product. To achieve relatively thinner flakes, relatively smaller particles can be used. Therefore, to achieve relatively thinner wafers, proportionally more vacuum oxygen will be present in the wafer, if it is made of particles.

For example, the '084 patent discusses wafers that have a relatively large thickness range, between 300

5 And 1000 microns, made of powder. Based on the consideration analysis carried out by

Present inventors, it is believed that this will lead to chips having an oxygen content between 6 x¹⁷10 And 2¹⁸10 x corn/cubic, as it is size by Spectroscopy Fourrier to transform the inferior fever (Fourier Transform Infraray (, ASTM-F1188 method. As a theoretical for example, a 150 micron spherical port with oxide.

10 Native oxide with a coating 1 nanometer thick will have a total oxygen concentration of 1¹⁸10 x atom/cubic cm. In practice, silicon powder is &lt;2:1 non-spherical, having a larger surface area to volume ratio than the theoretical globules used in the previous estimate, and an even higher oxygen concentration. To achieve thinner wafers, having a thickness of less than 300 microns, smaller particles will be required, resulting in higher oxygen concentration.

15 higher. It should be emphasized that, although the '084 patent indicates a thin wafer of 100 microns, the '084 patent indicates that more ideally it would be 350,900 microns. Importantly, there will be no official examples, nor are you discussing including any actual chips according to the disclosed processes. The only wafers you discuss have thicker and thinner areas with a thickness of 900 microns at the thinnest parts, and there was no clear discussion of these wafers that were

20 Manufactured.

In general, it is believed that the particles used to manufacture thin wafers should be no more than 1/3 of the final thickness of the wafer. For example, to make a chip thinner than 150 microns, the powder particles must be smaller than 50 microns. Particles with such small dimensions will have a very large surface area relative to the volume of material provided. And large surface area

25 Relatively accompanied necessarily by a relatively large amount of empty oxygen, through the original oxide

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native oxide, hydrocarbons and metals. This very large amount of vacuum oxygen will potentially result not only in poor performance, but in the extreme, it could prevent the powder from properly melting and crystallizing. The oxygen on this powder will form huge amounts of SiO, which can condense into any liquid

5 A place in the furnace where it is slightly below the temperature of the magma.

It is known in Patent '084, at column 5, lines 1-10, that the presence of silicon oxide in the semiconductor material (or other oxides of other semi-conductors) are unwanted impurities, which are Relatively worse for smaller particle sizes, therefore, the minimum particle size is restricted, which determines the fineness at which it can

<p dir="rtl">10 Achieved in the final wafer, by the ability to stain with interstitial oxide. The use of a powder with a particle size of 50 microns, as required to make wafers 150 microns thick or less, will result in approximately four times as much oxygen on particles smaller than the powder as would be evident on particles used to make wafers 300-600 microns thick. Therefore, when using 50 micron thick particles (to achieve a 150 micron thick wafer) it will be</p>

<p dir="rtl">15 Expected to result in a chip of at least 3¹⁸10 x atom/cm3 of oxygen in air.</p>

It will be required to include oxygen levels at any value less than 6¹⁷10 x atom/cc, preferably less than 2¹⁷10 x atom/cubic cm. Achieving each degree of lower amount of oxygen per hour (e.g., 5¹⁷10 x atom/cc, 4¹⁷10 x atom/cc, etc., just to capture two separation points, and offer more advantages than larger quantities.

<p dir="rtl">20 It is hypothetically possible through thermal treatment, such as elimination of gas residue, to precipitate nearly vacuum oxygen greater than 2¹⁷10 x atom/cubic cm. Consequently, the empty oxygen decreases to approximately this value, but the total oxygen in the crystal remains relatively undetermined high, at least 8.75.¹⁷10 x atom/cc (=10 ppm weight), as measured by the IGA method, such as that provided by</p>

<p dir="rtl">25 LECO for St. Joseph, Michigan. However, oxygen levels will be required</p>

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My total is less than 8.74¹⁷10 x atom/cubic cm. Any value less than this value, preferably less than 5.25, will work¹⁷10 X atom/cubic) = 6 parts per million weight (by providing me. Achieve each degree of the lowest amount of total Agels), for example, 7¹⁷10 x atom/cc, 6¹⁷10 x atom/cc, only captures two breaking points, providing a better advantage.

<p dir="rtl">5 A problem associated with powder-based wafer construction, specifically with semi-conductors such as silicon, is due to the very high tensile strength of silicon. There is a thin wafer that cannot be made from a specific powder and technology if all the silicon is melted in any location at the same time. A certain minimum amount of unmolten silicone is required to break the surface tension. Silicone, in contrast, is composed of globules, rather than having a thin, flat structure.</p>

<p dir="rtl">10 The wafer process disclosed in Patent '084 involves partially melting silicon powder, which then crystallizes on one side, before melting the remaining unmelted powder on the other side and continuing to grow osmotically on the already grown silicon. See generally Column 7, lines 55 - Column 8, line 64, and Figure 1 and Figure 2. The text is based on describing the top-down heating and granular growth process. Figure 2 of the patent shows</p>

<p dir="rtl">15 '084 hours of heat is shed on the upper and lower parts of the magma, after which the body is welded and shows</p>

Figure 12 of the patent, column 15, lines 4-19, the same, plus a partially melted material 89, and above that there is a fixed particulate material (no reference numbers). This process is very difficult with a very thin powder layer. The full depth of silicon powder should be avoided at any location

<p dir="rtl">20 Conversely, a thin layer of melt will accumulate, leaving openings to form adjacent to the balling zone. Thus, with a given powder and technique, it is difficult if not impossible to obtain wafers thinner than 200 microns, with silicon (and any other semiconductor with a similar high surface occlusion) because it is difficult to melt only a portion of the shallow powder particles deep, Without melting all of the rest of its depth at another time, which leads to this region being semi-curved</p>

25 Molten semi-conductor.

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The process of manufacturing a wafer from particle powder presents another problem associated with steps of large thickness from one location to another, and this problem is caused by the fact that the powder is present at a density of 50%, and more ideally a density of 33%. Because of this problem, it would not be possible to have a region 20%-30% thicker than an adjacent region of the site without having an overall lack of monotonicity on the face 5 opposite the component body and a noticeably thinner portion at the transition between the relatively thicker and thinner regions.

(Shown variably, thickness ratios of adjacent areas are greater than 1.3:1, or can be equal by as little as 1.2:1, depending on particle sizes, desired body quality and dimensional consistency.) Powder density is about 1/3 the density of the material being welded. (The particle size has an effect on this fraction.) A limiter device is illustrated in relation to Figures 9 and 12 of the '084 patent. If the gap 73 in the limiter 70 is 10 it will be used to form a contour in the final product, which is created above

A thinner inner area, formed at area 74 of the limiter, both the gap 73 and the shallower area

74 It must initially be provided with total particle depth/size to form the final product.

Consider what will happen next. If the gap 74 in the limiter is 100 microns deep and the chip thickness is required to be 300 microns in the core inner zone, rather than in relation to the core 15 zone, it will be necessary to accumulate the powder over this zone to a depth of three times

Final thickness is 300 microns, for a total of 900 microns. This will mean that above the trench, the thickness will be 1000 microns. After melting, the thickness of the finished object will be approximately 1/3 the depth of the powder that was present above. Therefore, in the interior region, it will be 300 microns thick. Above the trench, it will be 1/3 x 1000 microns thick = 333 20 microns. However, the trench is 100 microns deeper than the interior. Therefore, you will

The thickness of the perimeter will be 333 microns as measured from the bottom of the trench, 100 microns below the center region, and the thickness of the interior will be 300 microns, as measured from the flat interior region. The back surface of the component body will be far from flat, due to the corresponding surfaces displaced by 100 microns from the trench. The distance 25 to the back surface above the trench from the bottom of the trench will be 333 microns. You will reach the distance from the level

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The bottom of the trench to the back surface above the inner portion area is 400 microns, because the thickness above the inner portion area is 300 microns, and the inner portion area is spaced 100 microns away from the bottom of the deep trench by 100 microns. Therefore, the areas of the back surface will be adjacent at the interface between the perimeter over the trench and the area over the interior at distances

5 differ from the bottom of the trench by 333 microns and 400 microns, respectively, leaving a vibration vibration of 67 microns between the two.

Due to the lack of monotony, there will be a thinner portion adjacent to the corner between the trench and the interior portion area. This thinner section can be weaker or form a pressure riser, which is generally not required. Lack of uniformity is bad for deeper trenches, provided to create larger tensile values around the perimeter. and this is

<p dir="rtl">10 Because of the distance due to the added tide that will be present in absolute terms, to the same degree as the added tide, but the powder added due to this tide will be compressed to 1/3 of the amount added. Therefore, for a trench circumference of 200 microns deep, the vibration difference at the back surface will be a difference of 124 microns (=300 - ((1100 microns/3) - 200).</p>

The above considerations can also be expressed in terms of the high volume ratio, and the extended portion of

<p dir="rtl">15 The thicker area, compared to the thickness of the thinner area. If the surface of the thinner region is taken to be a base plane, then with the limiter method, it will not be possible to manufacture a body with a riser extending beyond the surface of the base plane to such a degree that the ratio of the extension of the riser above the base plane to the thickness of the thinner region is greater than . 11. However, the '084 patent does not disclose any examples of objects with larger proportions. The only example disclosed here is his</p>

<p dir="rtl">20 A thin area of 900 microns, with a rising portion of at most 100 microns, resulting in a ratio of 900/100 = 0.11.</p>

Thus, an object of the invention here is a thinner semiconductor wafer, in some controlled regions, rather than a standard semiconductor wafer 180-200 microns thick, as thin in parts as substantially as 80 microns, and even in some cases as thin as 50 -60 microns, but any wafer is thinner

<p dir="rtl">25 They are stronger and rigid enough to be used in conventional or semi-photovoltaic applications</p>

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Traditional. Another object of his invention is a semiconductor wafer that is smaller in size than a standard semiconductor wafer of the same surface area. Another object of the invention is a method of making the foil thinner, but still strong. Still, there is another goal of the invention, which is a way to make a semiconductor chip that is smaller in size. Still, another goal of inventions is to create

<p dir="rtl">5 Three-dimensional design chips. It is also an object of the inventions to form such thin films with an acceptable vacuum oxygen content, for example at any value less than 6¹⁷10 x atom/cc, preferably less than 2¹⁷10 x atom/cubic cm. A related goal is to form these flakes with a total oxygen value of any value less than 8.75¹⁷10 x atom/cc (=10 ppm weight), preferably less than 5.25¹⁷10 x atom/cc (=6 ppm weight) as measured</p>

<p dir="rtl">10 By empty gas analysis. Another target is a semiconductor wafer that has regions of different thicknesses, where the region adjacent to the regions has a thickness ratio greater than 1.28:1. A related target to the above is a semiconductor wafer that has regions of different thicknesses, where the extension of the thicker region above the ground plane of the thinner region is more than 0.11 times the thickness of the thinner region. There is still another object of the invention where the semiconductor wafer includes areas of thickness</p>

<p dir="rtl">15 Various, where the thinner region is preferably thinner than 180 microns and in a particular embodiment, extends by at least 80% of the surface area and by 95% of the surface area.</p>

General description of the inventor

A general invention herein is that a semiconductor wafer has regions that are relatively thicker than other regions, and these thicker regions are located at specially designed or controlled locations of the wafer. There is a sister in general

<p dir="rtl">20 Another is a semiconductor wafer that has a generally flat surface, at a base level, with risers protruding away from the base plane. The risers will be specifically designed or controlled locations of the wafer. A more specific invention is a semiconductor wafer having a relatively thinner inner area and a thicker surrounding area, thus consuming less semiconductor material than a wafer of equal thickness, and also having a higher efficiency than a relatively thicker wafer.</p>

<p dir="rtl">25 across most of its surface area. Another, more specific invention is a chip with relatively thin areas,</p>

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and one or more distinct thicker areas, such as diverging ribs, anchors, strips, interfaces, such as rectangles, circles, other geometric shapes etc., thus providing reinforced areas for electrical and mechanical connections and other couplings. In general, her invention is a wafer thinner than 180 microns and can be as thin as 60 microns, more ideally.

<p dir="rtl">5 Also, thicker than 80 microns, and in a preferred embodiment, the thinner region extends over at least 80% of the surface area of the object. The inventions also include sections thinner than 180 microns, and thicker sections, where the ratio of thickness values is at least 1.3:1. Still another invention is a relatively thin foil, with relatively thicker parts, having a vacuum oxygen content of less than 6¹⁷10 x atom/cc, or better, has less than 2¹⁷10 x atom/cm³ Better yet, there is no empty oxygen</p>

10 Detectable. Also, these chips include less than 8.75¹⁷10 x atom/cc (=10 ppm weight), preferably less than 5.25¹⁷10 x atom/cc (=6 ppm) total oxygen as measured by vacuum gas analysis. Still another invention is a wafer with relatively thin parts and relatively thicker parts, where the relatively thinner parts have a thickness of less than 180 microns, with the relatively thicker parts extending beyond the thinner parts by at least 40 and up

15 To 120 – 200 microns.

Each of the above inventions may usefully consist of semiconducting material containing relatively small amounts, if any, of vacuum oxygen, for example less than 6¹⁷10 x atom/cc, preferably less than 2¹⁷10 x atom/cubic cm. Although the distance between these values may not be precisely distinct in practice, the distance between them will be greater than 6¹⁷10 x atom/cc and less

20 of this value, preferably less than 2¹⁷10 x atom/cc, will be characterized in terms of the resulting photovoltaic. Semiconductor for photovoltaic use with 6x¹⁷10 atom/cc or greater of vacuum oxygen produces lower efficiency and induced light degradation <2%, while wafers containing vacuum oxygen of 2¹⁷10 x atom/cc or less will preferably show an induced light degradation of >2%. All inventions can be created

25 The above-mentioned form of semiconductor has relatively lower amounts, if any, of oxygen

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Total, example less than 8.75¹⁷10 x atom/cc (=10 ppm weight), preferably less than 5.25¹⁷10 x atom/cubic cm (=6 ppm weight).

Additional inventions include solar cells composed of these wafers, some of which can be provided with electrical connections at relatively thicker areas, such as those mentioned above,

<p dir="rtl">5 There are also solar modules made up of these solar cells that are connected to each other</p>

Some cross these electrical connections and thicker wafer parts, which also takes into account the higher efficiency due to the overall thinness of the component wafers, as shown above. Additional inventions are methods for making any and all wafers, cells, and modules of different thicknesses.

In one embodiment, the thickness of the total area around the circumference of the foil can be thicker than the thickness at

<p dir="rtl">10 The inner part, or central area. For example, the interior area of a wafer can be approximately 100 microns thick, with a peripheral area of approximately 180-200 microns. Ideally, a thicker perimeter can extend to within approximately 1-3 mm of the edge as shown in Figure 1. In this way, the edge strength of the wafer will be similar to that of a wafer edge of uniform, normal thickness.</p>

As shown below, thicker edges can have many forms and textures.

<p dir="rtl">15 In another embodiment, specifically selected areas on the inside of the wafer may be proportionally thicker than other areas. For example, a chip can be made to have thicker strips in areas that subsequently receive interconnection bus bars. Figure 2 shows an example of a chip that has thick stripes. These strips provide sturdier and more crack-resistant areas to withstand the stresses of electrical connections, such as soldering, or adhesives to metal connectors.</p>

20 thicker metal conductors.

There are other models with combinations of circumference and relative internal thickness that are mentioned as the sister of Ar'at here, and are explained here. Embodiments where only portions of the perimeter or thick inner region are present are considered inventions herein and are described below.

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Another invention is a solar cell made using these areas of thick or thick-edged, thin inner wafers. They are lighter, less expensive, more powerful and more effective than solar cells that have traditional semiconductor wafers of uniform thickness as solar energy collectors. These electrical connections are required to connect one cell to another to manufacture

5 The module can be supplied to the chips with less risk of destruction.

There is still another invention, which is a unit made up of solar cells specific to the inventions, made up of semiconductor chips according to the inventions. These units exhibit higher efficiency, due to the thinness of the wafers, but are unacceptably fragile due to the force introduced by either or both a relatively thicker peripheral area and relatively thicker areas of the electrical connections.

<p dir="rtl">10 The inventions here are also methods for making these thin internal chips with thick edges.</p>

Or wafers that have selectively thick areas and other thin areas. This method is based on the Direct Wafer® manufacturing method, with distinct innovative modifications disclosed herein. A fully basic method is described in the patent for the direct chip technology referred to above. Certain modifications of direct chip technology methods are inventions and are described herein.

<p dir="rtl">15 Wafers made using the Direct Wafer® method have an oxygen content of less than 6¹⁷10 x atom/cc, ideally less than 2¹⁷10 x atom/cc Even a small amount of oxygen in empty air is undetectable. Also, these chips include less than 8.75¹⁷10 x atom/cc (=10 ppm weight), ideally less than 5.25¹⁷10 x atom/cc (=6 ppm weight) total oxygen.</p>

<p dir="rtl">20 The thickness of a wafer formed on a die by direct wafer technology methods depends on the amount of heat extracted from the molten and then solidified semiconductor material at the location of interest, and also somewhat on the rate of heat extraction (heat flux) at that location. The thickness of the solidified silicon has a limit Higher, which is based on the total amount of heat extracted. This is because a certain amount of heat must be extracted from the liquid that must be frozen. The amount is called the latent heat of consolidation.</p>

<p dir="rtl">25 Example, for silicon, the latent heat of fusion is 4.138 kJ/cc. Therefore, to freeze</p>

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For silicon volume, the local heat extraction should be 41.4 J/cm2 per 100 microns of wafer thickness. This assumes that all the heat extracted from the heat extracted from the magma is latent heat. There is another method mentioned, which indicates that the magma was already ready at its freezing temperature. However, if the amount of heat extracted is extracted too slowly

5 -Over a very long period of time - the heating process will be carried out in the solidified flake by the hotter magma underneath, thus reducing the net heat extracted from the melt, and thus reducing the thickness of the resulting flake. Therefore, in the case of slow extraction, even if the required amount of heat is extracted, the magma will rewarm the solidified material and thus will not freeze to the same extent.

<p dir="rtl">10 It has been specified, as one of the inventions, that relatively more heat is extracted at one area, compared to another area, which leads to the formation of a relatively thicker area chip at the location with relatively more heat extraction. Conversely, relatively lower thermal extraction in one comparative area results in the formation of a relatively thinner chip region at the location with relatively lower thermal extraction. In general, sites that experience greater heat flow involve more thermal extraction, including</p>

<p dir="rtl">15 Sites that experience less heat flow receive less heat extraction.</p>

For reasons that will be explained below, the methods used to form wafers in accordance with the inventions differ from the methods of the Direct Wafer® technology in an important way, as this is the object that leaves a shape on the wafer, corresponding to a die plate or die such as those terms that were used in the patent. Invents direct wafer technology, which does not work like a traditional mold. The body's function has been explained below.

<p dir="rtl">20 But, for this reason, it will generally be referred to here as a template, or, in some cases, as a pattern, rather than as a template.</p>

For example, considering a wafer configuration that has a relatively thicker circumferential area, this can be achieved by controlling the heat flow from the semiconducting magma into the matrix, so that there is more heat being extracted from the melt around the circumference, in areas where the wafer is considered 25 thicker, compared to the inner part area. The foil formed will be thicker around the perimeter than at

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Inner part. Similarly, for relatively thicker strips or other geometries, specifically to be connected by electrical connections, more heat extracted at locations that are required to be relatively thicker will result in a relatively greater thickness, compared to areas where there was relatively less extracted heat.

5 The following will discuss several methods for providing controlled, tailored differences in heat extraction from one specifically designed and positioned area to another, including, but not limited to: Providing one or more coating zones on the mold that retard (or, where appropriate, improves) heat extraction compared to uncoated areas; providing areas with different die thickness values at different die locations, and thus with more thermal mass or

<p dir="rtl">10 Lower at different locations, generally including thicker areas that have greater thermal mass and undergo more heat extraction, compared to thinner areas, with lower thermal mass and less heat extraction; Providing different amounts of differential pressure at different locations across the die surface; Providing different thermal properties locally in the same mold, such as by including voids, where there is less thermal mass, or inclusions of different materials, so that heat extraction differs at these different locations;</p>

<p dir="rtl">15 Providing different degrees of permeability in the mold at different locations, different degrees of heat extraction are thus provided, either because of the permeability itself, or because of the different degree of differential pressure resulting from the different degrees of permeability.</p>

The following will discuss the construction of semi-conductor wafers for primary photovoltaic applications, for example in the construction of a solar collector wafer. The chips are perfect

<p dir="rtl">20 An area of 156 mm x 156 mm square, forming a solar collecting surface, which is generally level. They include thicknesses, perpendicular to this level, which are generally 180-200 microns thick. The thickness dimension is the primary focus of the following discussion, and the terms thin and thick will be used here in reference to the volume of structures in this dimension perpendicular to the plane of the solar collector. Structures that have a dimension in the plane of the solar collector surface are described. is used</p>

<p dir="rtl">25 The terms broad, narrow, and the like, are generally used to refer to the size of these structures at a surface level</p>

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Solar assembly. It will be possible to configure chips for other uses. The examples given here are for photovoltaic use for illustrative purposes only, and should not be taken to limit the inventions claimed herein to only photovoltaic uses, unless otherwise specified in the claims.

5 Flakes made according to direct magma methods here include the required low oxygen levels, which have an empty oxygen content of less than 6¹⁷10 x atom/cc, ideally less than 2¹⁷10 x atom/cc and even as little as no detectable empty oxygen. Also, these chips include less than 8.75¹⁷10 x atom/cc (=10 ppm weight), ideally less than 5.25¹⁷10 x atom/cc (=6 ppm weight) total oxygen.

10 The objectives of these and other inventions disclosed herein will be understood by reference to the figures, where:

Brief explanation of the drawings

Figure 1 is a schematic representation of the wafer according to the invention, having an inner region with a thickness of 100 microns and a peripheral region with a relative thickness of 200 microns. The inner region is thinner than the wafer.

15 Standard photovoltaic silicon is 180-200 microns thick, the thick circumference is approximately 2 mm wide, and has a sloped inner edge;

Figure 1a is an enlarged view of the perimeter region of the chip according to Figure 1 at A;

Figure 1b is a cross-sectional view of the chip according to Figure 1 along lines BB

20 Which shows that the circumference is thicker than the inner part area;

Figure 2 is a schematic representation of a wafer of one of the inventions herein, having a 100 micron thin inner region and 200-300 micron thicker regions including common wire conduction strips

bus-wire;

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Figure 2a is a magnified cross-sectional view of the foil according to Figure 2 along lines AA, which shows that the foil is thicker than adjacent interior areas, and its edges are curved;

Figure 3 is a pictorial representation showing the relationship between cell efficiency and foil thickness of a back contact cell structure for a passive emitter device;

5 Figure 4 is a schematic representation of a wafer of one of the inventions herein, having a relatively thin inner region approximately 100 microns thick, a relatively thicker peripheral region approximately 150 microns thick and 1.5 mm wide and regions including strips, relatively thicker than the interior, approximately 150 microns long 2.7 mm wide;

Figure 4a is an enlarged view of area A according to Figure 4;

10 Figure 5 is a schematic representation of a wafer of one of the inventions herein, having a relatively thin inner region of 100 microns and a relatively thick periphery of 200 microns, the thick periphery being approximately 1 mm wide, and having a sharp corner at its inner edge;

Figure 5A is an enlarged view of a circumferential area of the wafer according to Figure 5 at A;

Figure 5b is a cross-sectional view of the chip according to Figure 5 along lines AA,

15 Which shows that the circumference is thicker than the inner part area;

Figure 6 is a schematic representation of a wafer of one of the inventions herein, having an inner region 60 microns thick and a thick periphery region 200 microns thick, the circumference being approximately 2 mm wide, and having a sloping inner edge that is a transition of 0.4 mm;

Figure 6A is an enlarged view of a circumferential area of the wafer according to Figure 6 at A;

20 Figure 6b is a cross-sectional view of the foil according to Figure 6 along lines AA, which shows that the perimeter is thicker than the inner part area;

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Figure 7 is a schematic representation of a wafer of one of the inventions herein, having a relatively thin inner region of 100 microns and a relatively thick peripheral region of 200 microns, moving from a thin inner portion to a very gradual thick periphery, where this thicker region is approximately 2 mm, with a A transition of about 2 mm to the thinness of the inner part;

5 Figure 7A is an enlarged view of a circumferential area of the wafer according to Figure 7 at A;

Figure 7b is a cross-sectional view of the foil according to Figure 7 along lines AA, which shows that the perimeter is thicker than the inner part area;

Figure 8 is a schematic representation of a wafer of one of the inventions herein, having a 100 micron thin inner region and a relatively thicker, spaced bus-wire reinforcement means.

<p dir="rtl">10 anchoring reinforcement that is approximately 2.4 mm wide, extending inward from a 200 micron thick circumference at the edge to the thickness of the inner portion area, with no generally thicker peripheral area other than the edges of the landings;</p>

Figure 8a is an enlarged view of area A according to Figure 8;

Figure 9 is a schematic representation of a chip of one of the inventions herein, which has a relatively thin internal area

<p dir="rtl">15 100 microns, and relatively thicker, edge area approximately 150 microns thick and 1.5 mm wide, spaced from bus-wire landings approximately 2.7 mm wide, extending inward from the thicker edge area, tapering from the thickness of the edge area at the edge, to Thickness of the inner part area;</p>

Figure 9a is an enlarged view of area A according to Figure 9;

<p dir="rtl">20 Figure 10 is a schematic representation of a wafer of one of the inventions herein, having a relatively thin inner region approximately 100 microns thick, and a relatively thicker, edge region approximately 150 microns thick and 1.5 mm wide, spaced from a common wire anchoring means approximately 2.7 mm wide, extended Internally from the thicker rim zone, tapering from the thickness of the rim zone, approximately 150 microns at</p>

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edge, to the thickness of the inner part area, such as 100 microns, and also, interconnected bus-wire segments spaced across the width of the wafer to support bus-wires;

Figure 11 is a schematic representation of two wafers like those shown in Figure 11, with docking means, interface parts and a thin internal part, provided with the metal parts and interconnected with two

5 From public wires;

Figure 11a is a schematic representation of an enlarged view of Part A according to Figure 11, which shows part of one universal wire and the metal parts, the landing device and the island;

Figure 11b is a partially enlarged view of the enlarged portion of the wafer shown in Figure 11a, with

Remove the vertical conveyor element to expose the metal parts underneath;

10 Figures 12a, 12b, 12c, 12d and 12e show schematically the stages of applying the functional layer which are applied in two steps to provide a wafer that has a thin interior and a thicker perimeter, with:

Figure 12a which shows a die with a first functional layer introduced across its overall surface;

Figure 12b which shows the template according to Figure 12a with a mask around its perimeter;

Figure 12c shows the masked die according to Figure 12b with a second functional layer placed in the part

15 inner mask;

Figure 12d shows the template according to Figure 12c with the mask removed, which shows two layers.

Packaged functionality for different surface areas; And

Figure 12e, which shows the mold according to Figure 12d, is upside down so that the magma chamber side is facing down, as it would be in ideal use;

20 Figures 13a, 13b, 13c and 13d show, schematically, the stages of use of the two layers

Overlapping with:

Figure 13a shows a single block;

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Figure 13b which shows the mold according to Figure 13a with a first overlapping layer covering its entire surface;

Figure 13c which shows the die covered according to Figure 13b with an additional overlapping layer covering the interior, to produce a wafer that has a thin interior and a thicker perimeter; And

Figure 13d shows the mold according to Figure 13c, upside down so that the magma chamber is directed to

5 bottom, as it will be during use;

Figure 14a shows, schematically, a mold covered with slices of a functional material, either placed in powder or

other fluid form, or as free standing interstitial bodies; And

Figure 14b shows the mold according to Figure 14a, upside down so that the magma chamber is directed to

bottom, as it will be during use;

<p dir="rtl">10 Figure 15 shows, schematically, a partial cross-sectional mold with two functional material layers and a foil formed on the magma chamber surface of the mold;</p>

Figure 16 shows schematically a partial cross sectional wafer according to Figure 15, separated from the die;

Figure 17 shows, schematically, a die that has different thicknesses at different areas, with the inner area being thinner

and a thicker peripheral zone;

<p dir="rtl">15 Figure 18 shows, schematically the partial cross-sectional die with different thickness, and the chip is composed</p>

On the surface of the magma chamber of the mold;

Figure 19 shows, schematically, a block having different thicknesses at different areas, such as at Figure 17, with a thinner inner area and a thicker peripheral area, and also with thicker inner areas to form a stripe, anchorage and interface;

<p dir="rtl">20 Figure 19a shows, schematically, a cross-sectional template according to Figure 19 along lines AA;</p>

Figure 19B shows, schematically, a cross-sectional template according to Figure 19 along lines B-

B;

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Figure 20a shows, schematically, the partial cross-section of the mold with different thicknesses, shown in Figure 19a, with a chip formed on the magma chamber surface of the mold;

Figure 20b shows, schematically, the partial cross-section of the mold with different thicknesses, shown in Figure 19b, with a chip formed on the magma chamber surface of the mold; And

5 Figure 21 shows a die with openings equipped in the inner part, to provide a die with different thermal properties in its inner region, compared to its peripheral region, with the openings shown schematically, to simplify the explanation.

Detailed description:

The disclosed inventions relate to semiconductor chips and methods for constructing these chips. It can be applied to semiconductor wafers for use in photovoltaic assemblies, and methods

10 To manufacture these wafers and assemblies, although they can be used to form wafer-like materials for other uses. Silicon wafers are disclosed as an example, but the inventions are not limited to silicon as a semi-conductor material. Similarly, although the photovoltaic uses mentioned are examples, the methods disclosed are with any semiconductor element made from a volume of molten material, using a porous body such as a mold

15 It is described here where it is required to include areas that are thinner than others, thicker, and also, specifically, where the thin areas are very thin, and are therefore strengthened to a certain amount by the presence of the thick areas.

As described above, the inventions disclosed herein may generally relate to thinner wafers, in most surface area, rather than standard photovoltaic wafers, which are generally 180200 microns thick. Wafers according to the inventions also include thicker areas, which can help provide the greater strength found with a wafer having a uniform thickness of less than 180 microns, such as

Thicker perimeter areas, thicker strips, interfaces, extended ribs, anchorages, control patches or other electrical connection geometries. There can also be non-strong features with thicker structures, such as improved stiffness of an electrical connection. As used here, when a wafer is stated to have a thinner interior area, it will be intended that most of the interior area be

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Thinner, except that these geometric shapes, such as strips, interfaces, etc. In general, at least 50% of the interior area will be thinner, and more ideally greater than 80% or 90% of the thinner size. In general, the wafers according to the inventions include internal areas thinner than 140 microns, and preferably, thinner than 100 microns, up to 60 microns. It could be possible, with

5 Special measurements are taken, to produce wafers even thinner than 60 microns. In general, the ratio of relatively thicker areas to relatively thinner areas is between 1.3 to 1 and 3 to 1, however, it can be smaller or larger. In most general cases, it will be believed that for photovoltaic use, the thinnest area will not be thinner than 50 microns, and the thickest area will not be thicker than 250 microns. A wafer that includes both of these maximum thickness values is possible in the future, although it is possible

<p dir="rtl">10 All these limits must be present on the same chip in accordance with current practices.</p>

The meaning of thicker areas and thinner areas as used here requires some explanation due to the natural variations in conventional wire-cut PV chips. Wire-cut wafers ideally take on a wedge shape, in the cutting direction. Because the cutting wire enters the guide edge to mold it from the wafer, the cutting slurry, for example SiC, breaks and also carries eroded Si.

<p dir="rtl">15 With it, which causes a change in the thickness of the kerf as the wire moves to the existing edge of the die</p>

which is cut. Therefore, more material is removed from the die at the running part of the cutting path instead of at the guided part. The ideal thickness variation for a cut chip will be between 10 and 30 microns, with the thickness varying in nature from one edge to the other. The thickness of the chip can be parallel to the length of the cutting wire approximately equal to one end of the wire to the other. The difference arises in

<p dir="rtl">20 The direction along which the wire moves. In general, the difference in thickness in the chip due to these cutting-related reasons is less than or equal to 20% of the thicker part.</p>

As used herein, when it is stated that one area of the foil of one of the inventions herein is thicker than another area, it will be intended to be a localized difference in thickness that has been specially designed and created. The displacement of the differences is designed. The process of stabilizing the differences and the control is designed

<p dir="rtl">25 in it specifically. The term thicker is intended to mean somewhat different than the difference due to cutting</p>

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As mentioned above, from the guide edge to the diameter edge of the saw cut. In proportion, the difference in chip thickness due to specially designed controlled differentials is ideally greater than or equal to 20% of the thickness of the thickest part.

As used herein, zone thickness means an average thickness, such as that measured using an artefact sensor

5 Capacitive thickness from the surface of one wafer to the surface of the compared wafer, which is an xy map with thickness by position. Example: Consider a wafer having a large, thin inner region, and a second thicker region (either a continuous region such as a perimeter, or a non-contiguous sector region such as interfaces or anchors, as described below), such as an x-y map of the surface of the wafer that can subtract The second zone (thicker). There can be differences in thickness in the thinner zone

10 The first. (For example, an ideal TTV or Total Thickness Variation calculated as a maximum minus a minimum of all points on a map of wafers made in accordance with the inventions can vary from 40 to 80 microns with a thickness of 200 microns) but the average thickness of the first zone will be significantly (&lt;20%) less than the average thickness of the second zone.

In the case of the narrow perimeter of the second zone, the measurement method to determine the thickness can be different, such as 15 by edge vision cameras, due to the capacitive sensors.

Capacitive sensors have a spot size of ~5 mm and cannot detect narrow edges.

The following will discuss several different types and geometries of chips according to the inventions. We will then discuss the methods of creating these chips.

20 Figure 1 shows, schematically, a wafer 100, having an expansion 110 of an internal area 120, thinner than 180 microns, for example approximately 100 microns. The circumferential region can be 130 thick, eg 180-250 microns, which includes within its range the total thickness of a standard photovoltaic silicon wafer. Therefore, the thickness ratio of the thicker part to that of the thinner part is at least 1.8:1. This ratio would not be achieved by a powder-based technology, such as

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Disclosed in patent '084. The thicker circumference 130 can ideally extend 0.5-3 mm inboard from the edge, as shown in Figure 1, preferably 1-2 mm. Hence, the width can be approximately 1-3 mm. The inner corner 134 is sloped, from the upper thicker perimeter 130, to the thinner lower inner corner 120. The edge strength 132 of the foil will be 100

<p dir="rtl">5 Similar to the edge strength of a normal wafer. The pattern shown in Figure 1 has a perimeter width of 2 mm, with a gradual transitional region from thicker to thinner of approximately 0.4 mm.</p>

In fact, in some ways, a thicker 130 edge perimeter will be the same thickness as a wafer of uniform thickness in the normal state. For example, when the chip is 100 for one of the inventions

<p dir="rtl">10 Here, with a relatively thin center 110 and a relatively thick edge 132, hitting it against a wafer carrier or other piece of equipment, it will do so with less force than a uniform wafer thickness, because the thinner 100 average wafer will have less mass and therefore less torque. , thus requiring less forces to stop. Also, a wafer with a thinner inner section can withstand more deflection and bending in this inner region than a standard thickness wafer. So you can edge area</p>

<p dir="rtl">15 The thicker one can withstand greater bending than a whole sheet of the same thickness can, because the former bends like a rod, while the latter bends like a plate, as is understood from the former field of mechanical properties of solids. Therefore, the thin inner, thick periphery of the wafer is generally harder and stronger than a natural wafer of uniform natural thickness, or a thin wafer of uniform thickness (although thinner).</p>

<p dir="rtl">20 Furthermore, this wafer, due to being relatively thin, includes other thicker areas at its perimeter etc., higher efficiency in the cell structure which results in a combination of low surface area and good light trapping, such as the back contact of a negative emitter device mentioned above. This thick edge (or thick regions) and a thin inner part of the wafer are composed of a material with a lower semiconducting capacity than a conventional thick wafer with the same or worse strength, the same or worse efficiency, or both.</p>

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Therefore, this wafer of the invention here has lower material costs because it is composed of less semiconducting material than a wafer of uniform thickness. Example, a wafer with the dimensions listed above, 100 microns thick on the inside, 200 microns wide , and 2 mm wide around the perimeter, is composed of approximately 60% or less of the semiconductor material that would be required for a wafer of uniform thickness of

5 200 microns.

Example, a standard wafer, which has a thickness of 156 mm x 156 mm x 200 microns, has a volume of 4.87 cc and a mass of approximately 11.2 g. This wafer, which has a central section that is 100 microns thick and a 2 mm edge width of 200 microns, has a volume of 2.56 cc and a mass of approximately 5.88 g, providing approximately 50% of the mass of a standard wafer.

<p dir="rtl">10 As used herein, a perimeter region is essentially an area surrounding the entire border of a wafer of any shape, and can be square, rectangular, circular, or other shape.</p>

In another embodiment, certain areas on the inside of the wafer are made thicker, for certain functional reasons. For example, as schematically shown in reference to Figure 2, the wafer 200 may include stripes 240a, 240b, 240i (intermediate stripes not shown), 240c,

<p dir="rtl">15 Of greater thickness, placed in areas of the wafer 200 that will subsequently receive interconnection bus bars. Strips 240a-240c are set in an internal region 210 that is conversely thinner than a wafer of normal thickness of 180-200 microns, for example having a thickness of 100 microns. Strips can be as thick as 250 microns, although they are not required for this purpose. The thickness of the electrical connections is believed to be between 150 and 250</p>

<p dir="rtl">20 Useful microns. Therefore, the ratio of the thickness of the thicker portion to that of the thinner portion will be at least 1.5:1, a ratio that would not be achieved using a powder-based technique, such as that disclosed in Patent '084.</p>

The thickness of the surrounding areas and any inner areas can be chosen to be thicker relative to the thickness of the central area. Ideally, the thickness ratio of thick areas to thin areas is between 1.28 to 1 and 3 to 1, but

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It can be as large as 5 to 1 for some ideal uses. A different method has been mentioned, in terms of the ratio of the volume of the extension of the thicker region beyond the base plane of the surface of the thinner region, to the thickness of the thinner region, and this ratio is ideally between 0.28 and 4.

As determined in the art, for certain types of cell structures, the efficiency of a solar cell containing a relatively thinner foil can be higher than a solar cell containing a relatively thicker foil. Types of cell structures that are true include, but are not limited to: passive emitter back contact (back contact with velvet emitter) and PASHA. In the PASHA structure, the back of the cell consists of a heavily dipped region, creating a back surface domain, which, as is known in the art, repels minority carriers toward the front of the cell. The conductor is on the back of the cell conductor in the form of fingers, rather than an entire area of metal. The silicone surface can be passivated between these fingers, which in turn with the back surface field, provides global passivation. Infrared light reaching the back of the cell can encounter a good optical reflector and re-enter the cell. This particular structure may be particularly suitable for a thin wafer, because less metal coverage on the back will result in less curvature of the wafer due to expansion mismatch.

Thermal insulation between the silicone and the metal back. This follows many physical reasons.

By using a thinner wafer, the efficiency of a cell made on this wafer can be increased by increasing both the open circuit voltage and short circuit current I._sc(current). The open circuit voltage increases because there is less mass, precisely because the chip is thinner. The current can also be higher. This is because of the carriers generated by the light, which For infra-red photons to be absorbed near the back of the cell, they do not need to be transmitted to the p-n junction at the front of the cell. Consequently, there is less of these light-generated carriers lost to rebinding) and thus, more arrives at the junction capable of generating an extracellular current.

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To take advantage of these improvements, the cell must preferably achieve excellent light trapping, so that infrared light is bounced back and forth in the cell and can be available to be absorbed. Specifically, it should preferably have good optical reflectivity at the back of the cell. This exists with back contact of a back negative emitter device, known in the art. This increase in

5 The efficiency that comes from reduced thickness is actually greater for a material that has a lower carrier life – a basic measure of electronic quality. This is because with a material with a shorter lifetime, carriers generated by light generated at the back of a cell are more likely to recombine before reaching the front of the cell, compared to a similar situation with a material with a longer lifetime. Therefore, shortening this distance the carriers produced by light should travel further

<p dir="rtl">10 It is due to a material with a shorter lifespan.</p>

Figure 3 shows, schematically, the relationship between cell efficiency (top scale) and chip thickness (horizontal scale). This image was created from an induction program known as PC1D, which is widely used in the photovoltaic industry. It assumes a back contact with a negative emitter device. Rear with 96% optical reflectance and surface retouching amplitude of 20 cm/s curve set

<p dir="rtl">15 In general, a standard foil with a thickness of 180-200 microns has a tau of approximately 150 microns, and has an efficiency between approximately 19% and 19.1%. Reducing the thickness of this standard foil to As high as 100 microns this effectiveness is approximately 19.3%. Conversely, a lower tau chip, for example 35 microns, which, at a standard thickness of 180-200 microns, will include an effectiveness of approx.</p>

<p dir="rtl">20 by 18%, and could have a much higher efficiency, closer to 18.4%, if it were only 100 microns thinner. Therefore, reducing the thickness of wafers with relatively lower tau implies a greater benefit to the efficiency gain of those wafers with lower tau than does reducing the thickness of wafers with relatively greater tau. Another advantage of thinner wafers is that the injection level of less carrier material is higher per unit volume because the same number of photons are absorbed in a smaller volume of material.</p>

<p dir="rtl">25 Resulting in a higher injection level. Due to multi-crystalline silicon material</p>

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Silicon material and the Direct Wafer® method are manufactured to have a lower carrier life with a higher mass which increases at higher injection levels. A thinner wafer will in practice achieve a higher tau.

Therefore, the advantages of a thinner wafer as described above include both increased efficiency and a reduction in cost from using less silicon. To get these benefits with a chip that has a thinner first area the chip and the area

5 Secondly, for a thicker wafer, from a practical point of weighing the benefits over the increased effort that must be considered as manufacturing regions of different thicknesses, with the material costs and efficiencies of wafers made directly from a semiconductor body, the fracture area of the first region should represent most of the surface of the wafer. , preferably &lt;80% and preferably &lt;90%.

Thus, the above shows several basic examples of wafers with areas significantly thinner than 10. Manufacture of natural wafers with a thickness of 180-200 microns, over a significant period of their surface area, in order to

A few different basic geometric shapes, patterns and uses of thin and thick areas. Also included in the above are the revelations that these thinner flakes are more effective than thicker flakes (for the same tau), and also that these thinner flakes with thicker regions are selectively stronger than would be uniformly thin or uniformly thick flakes. Methods will also be discussed. The manufacture of these 15 thin wafers is also discussed below. However, before discussing the methods of making wafers, a wide range of...

Different styles of thin and thick areas.

Geometric shapes

An important aspect of one of the inventions here is to provide very thin wafers in the interior, ideally less than 180 microns thick. In preferred embodiments, the thickness will be less than 140 microns. in

20 For some models, the thickness will be less than 100 microns. In some specific models, it will

The thickness is less than 80 microns, although it is believed that efficiency gains will not exist with chips thinner than 80 microns, but also, material cost advantages will exist. In some very customized models, the thickness can be less than 60 microns. In the field, it will be understood that wafers less than 180 microns are generally fragile in handling and this is particularly true for wafers thinner than

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150 Micron. Also, it will be understood in the field that if wafers are very thin, they should ideally be handled by being mounted on a carrier material, which is often attached to the wafer and becomes part of the finished unit. Therefore, an essential aspect of the present invention will be to allow handling for values of foil thickness that would otherwise be impossible to handle, namely,

5 As free chips. To some extent, some wafers of the invention will be considered to be provided with an integral carrier portion, defined as a thickened border.

The basic embodiments shown in Fig. 1, for a 100 thin wafer with a 132 thickening perimeter, and shown in Fig. 2, for a 200 thin wafer with thick strips 240a, 240b, 240c, etc. have already been discussed. To connect to or carry vertical bus conductors or other electrical components

<p dir="rtl">10 elements. There are many possible combinations, variations and combinations as well.</p>

Figure 4 is a schematic representation of a wafer 400 of one of the inventions herein, having a relatively thin inner region 410, with a thickness of approximately 100 microns, and a relatively thicker peripheral region 430 with a thickness of approximately 150-250 microns, overall, having a width w of approximately 1.5 mm (Figure 4a). Additionally, areas 440a, 440b, and 440c, which are in the form of strips, are proportionately thicker than

<p dir="rtl">15 The overall interior is 410, has a thickness of approximately 150-250 microns and has a width r of approximately 2.7 mm. Thus, the wafer pattern 400 shown in Figure 4 has a thin interior 410 and subsequently both a relatively thicker perimeter 430 and relatively thicker bands 440a, 440b, etc. Edge 432 is also clarified.</p>

Figure 5 shows, schematically, a chip 500, having an expansion 510 of an internal area 520, thinner than 180.

<p dir="rtl">20 Microns, example approximately 100 microns. The circumferential region 530 can be thicker, eg 200 microns thick. This thicker circumference 530 extends approximately one mm inward from the edge 532 as shown in Figure 5b. Therefore, its width w can be approximately one mm. The inner corner 534 is a relatively sharp square, at the magnification shown, and thus the transition from thick to thin is obstructed. Figure 5b shows the chip according to Figure 5 at lines BB. Figure 5a shows a zoom</p>

<p dir="rtl">25 For the wafer according to Figure 5, at A. (None of Figures 5, 5A or 5B are shown to scale.)</p>

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Figure 6 shows, schematically, a wafer 600, having an expansion 610 of an internal area 620, thinner than 180 microns, for example approximately 60 microns. The peripheral region 630 can be thicker, eg 200 microns thick. This thicker circumference 630 is shown extending approximately two mm inward from the edge 632 as shown in Figure 6. Therefore, its width w can be approximately 2 mm. Corner

5 The inset 634 is skewed, from the thicker, upper circumference 630, to the thinner, lower inset 620. The pattern shown in Figure 6 has a circumference w of 2 mm, with a gradual transition zone from thicker to thinner approximately 0.4 mm. Figure 6b shows the foil according to Figure 6 at lines B-B. Figure 6a shows an enlargement of the foil according to Figure 6, at A. (None of Figures 6, 6a or 6b are marked to scale.)

<p dir="rtl">10 Figure 7 shows, schematically, a wafer 700, having an expansion 710 of an internal area 720, thinner than 180 microns, for example approximately 100 microns. The circumferential area can be 730 thicker, eg 200 microns thick. This thicker circumference 730 is shown to extend approximately two mm inboard from the edge 732 as shown in Figure 7. Therefore, its width w can be approximately 2 mm. The internal transition 734 is very smooth and gradual and more extended than the transitional areas of the models mentioned above, from</p>

<p dir="rtl">15 The thicker upper circumference is 730, to the lower, thinner inner portion of 720. The pattern shown in Figure 7 includes a circumference w of width of 2 mm, with a thicker-to-thinner transition region having a width s of approximately 2 mm. Figure 7b shows the chip according to Figure 7 at lines BB. Figure 7a shows an enlargement of the foil according to Figure 7, at A. (None of Figures 7, 7a or 7b are marked to scale.)</p>

Figure 8 shows an embodiment somewhat similar to that shown in reference to Figure 2. The 800 chip includes 20 short landings, or control patches 840a, 840b, 840c..., which are reinforcements for attaching global wiring to the 800 chip. Anchor means 840a, etc., have a greater thickness near the edges, such as 832, and taper down to the thickness of the inner part area 810 after a short length. Mooring means can also be referred to here as control patches. They are ideally specifically and intentionally placed in areas of the chip 800 that will

<p dir="rtl">25 The bus bars then receive the interconnect. Ideally, public wiring tends to be...</p>

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It is harder to pull on the chip near the 832 edges, and therefore, this is a location where retreading adjustment patches come in handy. The global wires are not pulled as forcefully from the edges 832, closer to the center 810. Therefore, the thickness of the interior of the wafer 810 can be as thin as 100 microns or less, as noted. It can be a means of strengthening the anchorage of a wire

5 Universal 840A, B, C, 200-250 microns thick, or even thicker, at the thickest section, although it does not need to be thick for all purposes. A thickness of electrical connections between 150 and 250 microns is thought to be useful. In an exemplary embodiment, the reinforcing anchorage means 840a, etc., may have a width, r, of approximately 2.4 mm, and will taper from 200 microns to a thickness of 100 microns over a distance perpendicular to the width, r, for example, by about

<p dir="rtl">10 20-18 mm. These structures can be referred to here as bus-wire</p>

landings, rebooters, or tuning patches. Figure 8a is an enlarged image of area A according to Figure 8.

Terms Anchorage and adjustment patch are used interchangeably here to refer to a raised area adjacent to the edge of a wafer, extending from the edge, to a relatively thin interior area. The anchorage itself is thicker than

<p dir="rtl">15 Inner part area. It should taper from the thickest part, near the edge, to the thinnest part, near the inner part, and this thinner part can be thinned as a thinner inner part. Also, the edge of the wafer can also be at least a certain amount thicker than the surrounding body of the wafer, and in fact, the overall circumference can be thicker. Therefore, the anchorage can extend from a thicker perimeter to a thinner interior, and the thickness of the anchorage can be equal to or thicker than that of the perimeter</p>

<p dir="rtl">20 Adjacent to the periphery, thin to the inner part, adjacent to the inner part.</p>

Figure 9 shows an embodiment somewhat similar to that shown in reference to Figures 8 and 1, which has both a thicker edge circumference 930 and also universal wire anchorage reinforcement means (or control patches). Wafer 900 includes anchorage means 940a, 940b, 940c, etc. , which are reinforcement landings for attaching public wires to the chip 900 similar to landing devices.

<p dir="rtl">25 840a, 840b, above. Anchor means 940A, etc., include greater thickness near edges, e.g</p>

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932, and tapers to the thickness of the inner part area 910 after a short length. They are intended to be located in areas of the chip 900 that already receive interconnecting bus bars. The overall overall thickness of the interior of wafer 910 can be as thin as 100 microns or less, as stated. Universal wire anchor strengthening means 940A, B, C, etc., can be 200-250 thin.

<p dir="rtl">5 microns, or even thicker, although it does not need to be thick for all purposes. Also, this embodiment has a thick circumferential area 930 at each edge 932 that, like similar embodiments mentioned above, can be 200 microns thick. In an exemplary embodiment, the reinforced anchorage means 940a, etc., can be approximately 2.7 mm wide, and will taper from 200 microns, the same thickness as the circumferential area 930, to 100 microns over a length of about 18-20 mm. Can include</p>

<p dir="rtl">10 The circumferential area is 930 w wide, as shown above by about 1 – 3 mm or smaller, with about 1.5 mm useful. Figure 9a is an enlargement of area A according to Figure 9.</p>

Figure 10 is a schematic representation of a wafer 1000 of one of the inventions herein, having a relatively thin inner region 1010, with a thickness of approximately 100 microns, and a relatively thicker peripheral region 1030 approximately 150-250 microns, having a width of approximately 1.5 mm. In addition, raised areas

<p dir="rtl">15 1040a and 1040b, which are in the form of anchorage devices or control patches that are relatively thicker than the part</p>

The inner tube, which is approximately 150-250 µm long and has a width of approximately 2.7 mm. Anchoring means or control patches 1040 tabsa, 1040b, for reinforcement at the ends of public wires, as shown above in Figure 4, anchoring means 440a, 440b. In addition, thick interlayers 1042a, 1042b are spaced from a region across the wafer, along the interior, in line

<p dir="rtl">20 (or lines) connecting the other side of the perimeter 1030. This means of anchoring 1040a, etc., and other inter-parts 1042a, etc., for receiving the public wire. Inter-parts 1042a, 1042b, etc., are thicker than the inter-part 1010, e.g. 150-250 microns long, similar to anchorage means 1040a, 1040b As used herein, the term interstitial means a relatively high area ideally surrounded by relatively thinner areas.</p>

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Figure 11 shows, schematically, a pair of chips 1000a and 1000b, as shown in Figure 10, connected by a pair of common bus-wires 1170a and 1170b. Figures 11a and 11b show an enlarged portion A according to Figure 11. The bus portion 1172 of the metal parts of a solar cell using the foil 1100a as a printed component can be observed as a continuous strip, which can undulate up and down across and between the docking medium 1040a, and islands 1042, interfaces 1042a.

etc., as shown in Figures 11a and 11b, such as a ribbon placed on a rough surface.

The universal wire itself 1170b may, however, be located more in a plane, with less undulation, and attached only to raised pads 1040 raised padsa, 1040b at the ends of the universal wire and at raised interfaces 1042a1, 1042a2, etc., along the turns of the inner part of the wire 10 global, leaving most of the global wire mechanically distinct and spaced at locations s on the surface

Chip 1000A. Figure 11a shows an enlargement according to Figure 11 at A, with the common wire 1170b.

I moved it somewhat to show the metal parts 1172 underneath, and Figure 11b shows this same section with the overhead wire 1170b in place. Figures 11a and 11b show that at locations s, there is a vertical void between the surface of the chip and its metal parts 1172, and the underside of the vertical conveyor

<p dir="rtl">15 1170b. In this way, incompatibilities in the thermal progress between a sheet of material can be established</p>

The silicon and copper bus-wire are somewhat compatible by means of gaps between the docking medium pads 1040a and interfaces 1042a, allowing the bus-wire to be somewhat flexible (e.g., stretch). This can create less stress on the wafer, Reduces the ability to cause cracks and other failures, such as separation of common wire layers.

<p dir="rtl">20 Thus, the embodiment of the wafer 1000 shown in Figures 10 and Figure 11 has a thin interior 1010 and subsequently both a relatively thicker perimeter 1030 and landing pads 1040 padsa, 1040b, etc. Intermediate parts 1042a, 1042b, etc.</p>

Figure 11 shows how the overhead wires 1170a, 1170b, from the top surface of one cell 1000a, must be inclined to wind under to the back surface of the adjacent cell 1000b. This wire

<p dir="rtl">25 Bending in addition to delamination stresses on metal parts at and near attachment points</p>

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Edge 1132 of cell 1000A. Also, when improperly bent, the wire can actually touch the edge of the 1132 cell, thus causing or propagating edge cracks. Therefore, providing thicker attachment points, such as anchors 1040b, interfaces 1042b1, and thickened perimeter 1030 improves the strength of the foil and reduces the chance of layer separation and cracks.

5 It will be understood that the embodiments shown herein with respect to relatively thinner portions and relatively thicker portions may also be described in terms of a foil having a common base level, for example considering the foil 100 of FIG. 1, the surface 120 and the rising portions extending from such base level portion, Like a high ocean130. Similarly, as shown in Figure 4, the chip 400 includes a base level at 420, from which rising portions such as strips 440a, 440b, etc. extend. And the ocean 430. In general,

<p dir="rtl">10 A slightly raised portion of 20 microns can extend beyond the base plane surface of the thinner portion, more ideally 40 microns, by 120 microns, for example in the case of a wafer with an interior of 60 microns and a circumference of 180 microns. In practical terms, this size of the extended part also depends on the thickness of the thinner part. In general, ratios of thicker to thinner values will ideally never exceed 5:1 and will more ideally be 3:1 or less.</p>

<p dir="rtl">15 Geometry and relative thickness values can be considered in terms of effectiveness, handling and electrical connections. In general, the effectiveness of a film will be controlled by how thin the surface area is, which is why having a thin interior of at least 80% of the surface area is important to achieve increased effectiveness. Similarly, depending on the types of machines currently in use, ease of handling is controlled by the thickness of the perimeter and the thickest part, which need not more than 5% of the surface area.</p>

<p dir="rtl">20 The surface of the chip, or less. Finally, the ease of electrical connection is controlled by the thickness of the foil at the locations where electrical connections need to be made, which is where buswires are made, such as ribbons, and/or in some cases, where more rigid connections are formed, such as at media outlets. Anchoring and interfacing.</p>

As described above, according to a relatively advanced method of wafer fabrication, a semiconductor wafer is formed directly from a semiconductor melt, generally using techniques disclosed in the patent.

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US No. 8293009, issued on October 23, 2012, entitled Methods for Making Thin Semiconducting Objects from Molten Material for Solar Cells and the Like, by Sachs, et al., which is incorporated herein by reference. (Reference is made to the technology disclosed in the patent' 009 is generally here as a Direct Wafer configuration technology^R. According to this technique, a thin semiconductor object, like a wafer, is formed from magma, rather than cut from a metal casting mold, grown between filaments, or otherwise

An other way .

As briefly defined above, the thickness of the foil formed on the die depends on the amount of heat extracted from the semiconductor material that is melted and then solidified at the location of interest and also somewhat on the rate of heat extraction. Resulting in more heat being extracted in one area,

<p dir="rtl">10 compared to another area, (if extraction occurs at a sufficiently fast rate) leads to the formation of a relatively thicker chip area at the die location with relatively more heat extraction. Conversely, relatively less heat extracted in one area compared to another results in a relatively thinner chip area at The location of the mold with relatively less heat extraction has been explained by referring to Figure 15, Figure 16, Figure 17, Figure 18, Figure 19, Figure 19a and 19b, Figure 20a and Figure 20b, and Figure 21.</p>

<p dir="rtl">15 It will be discussed fully below.</p>

Therefore, the intensity of the die area to extract heat controls the thickness of the chip that will be formed at the area in question. The following discussion explores various ways to increase the thermal recovery tendency of one specially designed, controlled die area, compared to another specially designed, controlled die area and thus, ideally, to increase the heat extracted and the chip thickness 20 formed at the location of the greatest heat extraction.

Before discussing these various methods of increasing and changing heat extraction tendencies, the merit of the inventions relating to vacuum oxygen and the total oxygen content of the constituent wafers will be discussed. As noted above, powder-based technologies suffer from undesirably high levels of oxygen in the final component wafer or other semiconductor body. This is because without performing the unusual steps, the original oxide will cause the powder particles to

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High levels of oxygen in the chips. Relatively smaller particles result in relatively more free oxygen in the final product. To implement relatively thinner chips, relatively smaller particles must be used. Therefore, to achieve relatively thinner wafers, proportionally more vacuum oxygen will be present in the wafer. For example, the '084 patent discusses wafers that have a thickness range between 350

5 and 1000 microns, they also discuss powder from 20-1000 microns. To achieve an accuracy of 350

Micron It will be necessary to use a powder with a size of less than 120 microns. It will be believed, based on analysis performed by the inventors, that this can produce wafers with a vacuum oxygen content of between 6¹⁷10 x atom/cc and 2¹⁸10 x atom/cubic cm.

Chips made directly from molten semiconductor material are not subject to this problem

<p dir="rtl">10 For oxides and vacuum oxygen contamination, because the feed stock of the melt does not need to be small particles with a relatively high oxide content. Consequently, the melt from which flakes or other objects are formed has a lower oxygen content and, consequently, the formed objects also contain less vacuum oxygen. Example: silicon wafers formed directly from fused semiconductor material using the methods described above ideally</p>

<p dir="rtl">15 It has an empty oxygen content of 2¹⁷10 x atom/cc or less, compared to at least three times or more for powder-based technologies. Also, these chips include less than 8.75¹⁷10 x atom/cc (=10 ppm weight) and ideally less than x 5.25¹⁷10 atom/cc (=6 ppm weight) total oxygen, compared to more than 8.75¹⁷10 x atom/cc for powder-based techniques.</p>

<p dir="rtl">20 Returning to the discussion of the various methods of increasing and changing the thermal extraction tendencies, we will consider, for example, a flake with a relatively thicker circumferential area such as shown in Figure 1 at 130. By controlling the thermal extraction from the semi-conducting magma in the matrix, there is more The amount extracted from the molten material around the perimeter, in areas where this foil will need to be thicker, compared to the interior areas, will be</p>

<p dir="rtl">25 The formed foil is thicker around the perimeter than it is in the interior.</p>

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Similarly, as shown in Figure 2 at 240a, 240b, for relatively thicker strips or other geometries, such as those shown in Figure 8, with universal wire anchoring means 840a, 840b, specifically to be connected to electrical connections, heat will The most extracted relative thickness at the desired locations is relatively thicker, to the relatively greater thickness at these locations, compared

<p dir="rtl">5 In most areas of the interior 810, there is a relatively smaller amount of heat extracted.</p>

There are many different methods for providing controlled, designed differences in heat flow and extraction in one zone compared to others which are described here, in detail. They include, but are not limited to: providing one or more functional layer areas, such as a coating, or free interlocking layer based on the mold, which retards (or in a small number of cases, improves) heat flow, and/or

<p dir="rtl">10 extraction; Providing a thicker matrix in some areas, thus involving more thermal mass and a greater tendency to thermal recovery, than in other areas that are thinner, with less thermal mass and a lower tendency to thermal recovery; Providing different amounts of differential pressure at different locations across the die surface; Providing different thermal properties in the die itself, such as by including voids, effectively makes the die thinner at void locations; Providing different degrees of porosity in the mold at different locations, thus saving</p>

<p dir="rtl">15 Different amounts of heat extraction and degrees of heat flow, either due to the porosity itself, or due to the different degree of differential pressure arising from the different degrees of porosity.</p>

To the extent that the geometry of the die or die treatment provides the greatest heat recovery at a location where it is located such that it is extracted by the die without formation or treatment, the formation or treatment is referred to herein as a heat recovery enhancer, or treatment providing a greater heat recovery tendency. Mold

<p dir="rtl">20 A treatment or composition that provides lower heat extraction, such as by providing a relatively thinner section, or</p>

A group of voids that reduce the thermal mass of the mold primarily at their location, or a coating that retards heat flow and reduces heat extraction and thus, the intensity of heat extraction, is here referred to as a heat extraction detractor.

Therefore, in general terms, the method of the invention is a method of producing a wafer by means of a wafer configuration

<p dir="rtl">25 On a mold that has areas with a relatively greater thermal recovery tendency, at areas where zones are formed</p>

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The required foil must be thicker, and the tendency for thermal recovery is relatively lower at areas of the die on which the required foil areas are made to be thinner. The mold of the invention herein is a mold having the relevant thermal extraction tendencies described immediately below. Larger sites or lower thermal recovery tendency are specially configured on the die at locations where they are required.

5 It will be noted that it is useful to form a flake from magma, and will be considered to be the invention disclosed herein, to form a solidified body in the magma, and to form such a body, such as a flake, on the mold of one of the inventions herein. The formed object does not need to be released from the mold to form a valuable item for manufacturing. But also, the chip formed from the die can be removed by a variety of methods. In some cases, the differential pressure system can be removed, i.e., if vacuum is used, it can

<p dir="rtl">10 Turn it off, and the chip falls out. Or, the differential pressure system can be reduced i.e., the degree of vacuum can be reduced, or, the pressure difference can be reduced. Also, chemical means may be used, either alone or in combination to reduce or eliminate the differential stress system, such as stripping pins, stripping frame, or other devices that mechanically contact the wafer and press it away from the board die. Any suitable means of separating the component wafer from the die will be acceptable and considered</p>

<p dir="rtl">15 However, it was acceptable and represents the invention here.</p>

Some methods for extracting more heat from one specially designated area of a mold compared to another area of the mold include, but are not limited to, the methods mentioned in the following sections.

To simplify the discussion, it will be assumed that it is required to include a thicker circumferential region, such as 130 at Figure 1, and a thinner interior region 110. Therefore, a thinner interior and thicker perimeter are discussed. however,

<p dir="rtl">20 The following discussion material will be required to apply to any style where thicker areas are needed, such as strips 240a, 240b, as shown in Figure 2, universal wire anchor reinforcement means 840a, 840b, as shown in Figure 8, and /or any of the other relatively thicker areas mentioned herein, as well as any relatively thicker areas of whatever form and for any purpose may be required in future structures made according to the methods of the inventions. In some cases, it will</p>

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Modify the methods described here to create thicker perimeters to create thicker areas when needed, other than the perimeter. (If a thinner circumferential area is needed, opposing operations will be considered.)

To control thermal extraction, a functional coating can be applied to the mold or to the melt surface in a pattern that defines the interior enclosed by the desired width perimeter.

<p dir="rtl">5 For the ocean fish. This functional layer can be of any of the types described in Direct Wafer Technology Patent No. 8293009. Functional layers are discussed that provide several functions, such as: improving release of the solidified body from the die, reducing nucleation sites Crystallization nucleation sites, increased frequency of crystallization nucleation sites, which locate nucleation sites at desired locations, among other reasons. Look</p>

<p dir="rtl">10 Generally at columns. 00101 and 00128-00141, from the direct chip technology patent. Figures 32a-32e and 33a-h33 of the patent for direct lamination technology 2 show various embodiments of methods using a functional layer placed on the magma surface.</p>

Specific elements of the inventions disclosed herein include a functional coating on the mold, of a type that impedes heat flow, whereby less heat is extracted from the magma in the mold area.

<p dir="rtl">15 Provided with a functional layer. (Hence, this functional layer is ideally a reducing unit.)</p>

Its presence creates a die region with a relatively lower heat recovery propensity, compared to an area that contains no or little or no thinner functional material with the same heat extraction propensity (existing). Functional layers can be provided as coatings on the die, Or as powder formation processes presented on the surface of the magma at the site it will be touched

<p dir="rtl">20 By template. These functional materials can be applied by methods known in the art including, but not limited to: curtain coating, spraying, slot die coating, meniscus coating, etc., as well as any suitable unknown methods, but then are developed or disclosed. Functional materials can also be provided as an interposer layer, a free-standing sheet placed between</p>

<p dir="rtl">25 The mold and surface are molten in some way.</p>

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A freestanding overlapping layer can be glued or, conversely, fixed to the template, or placed separately. These somewhat overlapping layers are free forms of functional layers. These nested layers are described in US Patent Application No. 990498/13, US National Phase of PCT Application No. 62914/11US/PCT, filed on December 1, 2011, which claims

5 Provisional applications filed on April 1, 2010, published as US Application No. 2014-1-A0113156, on April 24, 2014, entitled Making Semiconducting Objects from Molten Material Using a Free Interface Pad, full disclosure, which are incorporated herein by reference, shall take precedence. , which is referred to here as the overlapping layer patent application.

The process of positioning the thickness, or functional layer material on the mold can also be used as well

10 To control the thickness of the foil formed on the die. For example, as shown schematically in Figures 12a, 12b, 12c and 12d, a functional layer may be placed on the matrix 1200 itself, rather than on the magma surface. The functional layer may be applied in two steps: as shown in FIG. 12a, a first step is applied wherein a first step 1252 is applied uniformly across the overall surface 1250 of the die 1200; As shown in Figure 12b and Figure 12c, the second step is used

15 Use a mask 1253 to cover the perimeter 1230 of the template 1200 (so that it is completely covered with the first step 1252 of the functional material). Next, as shown in Figure 12c, an additional layer 1258 of the functional material is placed in the inner 1220 area of the template 1200. The mask is removed 1253 Then, as shown in Figure 12d, which leaves a functional layer covering the overall surface 1250 of the die 1200, with deeper and thicker regions of the functional layer 1258 in the interior 1220,

20 and a shallower and thinner area 1252 around the circumference 1230. The surface 1250 becomes covered with layers.

Functionality 1252 and 1258 of the magma chamber surface 1256 of the template 1200 as used.

The die 1200 can then be used to form a semiconductor wafer thereon. For example, depending on the use, it may be inverted vertically from the orientation shown in Figures 12a-12d, to that shown in Figure 12e, such that the surface of the magma chamber 1256, forming the original surface 1250, is covered

25 With the thicker two-layer functional layers, 1252 and 1258, the bottom faces, toward the surface of the material

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molten. This covered surface is then brought into contact with the surface of the molten volume, as shown in the direct wafer patent, for example at paragraph 0047 shown in Figures 3a and 3b (for embodiments without a functional layer).

The functional layers reduce the amount of heat extracted from the liquid silicone assembly

5 silicon, compared to an amount that would be extracted in its absence (thus representing a reduction in thermal extraction). Thus, in the region of the interior 1220, where the functional layer 1258 is thicker than the perimeter 1230, which carries only one functional layer 1252, a thinner portion of the wafer will form Adjacent to this center 1220 is the interior of the die, thus a wafer 100 such as that shown at Fig. 1 will result in a thinner inner region 120 and a thicker peripheral region 130.

10 Functional layers may be applied as a powder, spray, or other fluid material, as described above, or they may be applied as part of a free cross-layer, as described in the patent application for the cross-layer technology identified above. Figures 13a-13c show, schematically, an adjustment with a die 1300 (Figure 13a) and a first overlapping layer 1352 (Figure 13b) to create the degree of heat recovery for the overall surface chip, and then a second overlapping layer 1358 (Figure 13c),

15 Which is placed in the inner portion 1320 of the die surface 1300, such that the total thickness of the first overlapping layer 1352 and the second overlapping layer 1358 together in an area of the inner portion 1320 is greater (thicker) than the total thickness of the overlapping layer 1352 individually around the circumference 1330 of the die 1300.

The template 1300, as shown in Figure 13D, oriented as shown herein, will be used.

20 By flipping it from the orientation shown in FIG. 13C, such that the functional layers 1352 and 1358 are the surface of a magma chamber 1356, which is in contact with the surface of the body of the molten semiconductor material, as shown above. The back side 1354 of the mold 1300 faces away from the melted material. The relatively thicker layer of interlayers 1352 plus 1358 in the interior 1320, compared to the single layer 1352 in the circumferential region 1330, results in less heat flux.

25 There is less heat extraction in the inner part 1320, compared to the area around the perimeter 1330. Therefore,

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Forms the thinner inner area of the wafer on the die 1300. The process using free standing overlapping layers is similar to that used with powder or other fluid functional layers, but with overlapping layers, there is no need to use a mask, because the overlapping layer can be applied individually and directly by Mechanical manipulators. 5 No need to use a mask. Ideally, an overlapping layer also uses an extraction reduction unit

Thermal, which reduces the intensity of the mold's local area to extract heat.

Figures 14a and 14b show, schematically, a configuration to provide a die for producing a wafer having strips that are thicker than the inside of the wafer, such as those shown at Figures 2 and 4, and thicker anchoring means and/or interfaces, such as those shown at Figures 8, 9, and /or 10. A die 1400 is provided, having a surface 1456,

<p dir="rtl">10 which will become the surface of the magma chamber during use, which is covered with a first homogeneous layer 1452 of a functional material, the prepared cross section of which is shown in Figure 14. Seven batches of this first homogeneous layer 1452 of a functional material are shown in Figure 14a, as shown below. More details. By the surface of a magma chamber, it will be intended to be the surface that faces and then comes into contact with the magma during the formation of the flake. Functional material is presented</p>

<p dir="rtl">15 Additional in a third copy of the functional article areas 1465a, 1465b and 1465c (shown as article</p>

This results in a single layer of functional material covering template regions in strip images 1460a, 1460b, and, or a means of landing landing regions 1462a, 1462b or interstitials 1464a, 1464b. Additional functional material regions can provide (thereby leaving two layers of functional material in place) 1465a, 1465b and 1465c, e.g.

<p dir="rtl">20 Paints, such as through a mask of corresponding negative shapes, or as free interstitial elements</p>

.standing interposer elements

The die areas of strips 1460a, 1460b, etc., (covered only by one layer of functional material) will result in a die, which extracts less heat at the locations of two layers of functional material, shown without section preparation as 1465a, 1465b, 1465c, etc. From the heat

<p dir="rtl">25 In areas of the template that include only one layer of functional material, the prepared section is marked as at</p>

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1460a, 1460b, 1462a, 1462b and 1464a, 1464b, etc., will thus result in the formation of a wafer with thicker stripes at locations corresponding to strips 1460a, 1460b of a single layer of functional material. Similarly, the cross-sectional prepared areas of areas 1462A, 1462B, with only one layer of functional material, will result in short thick control patches in the formed material.

5 Wherein it is formed, the die surface interfaces 1464a, 1464b are covered only by a single layer of functional material, to the interfaces of a thicker wafer, as shown at Fig. 10.

Figure 14b shows the mold 1400, oriented as used, with the magma chamber surface 1456 shown oriented downward, such that this surface is presented with the patterned functional layers touching the surface of the molten material, facing the back 1454 of the mold 1400 which

<p dir="rtl">10 It moves away from the magma.</p>

The functional material can be presented in fluid form, such as a powder or liquid, either by direct displacement with a liquid or powder placement system, or by the use of a mask that allows the fluid functional material to be positioned, which protects selected areas of the mold surface 1454 of receiving the job material.

<p dir="rtl">15 Considering again an embodiment shown with reference to Figures 12d and 12e, ideally, for an effective difference in thermal recovery tendency, there is a thickness difference of about 20 microns between the thickness of the functional material 1252, which covers the total surface 1250 (Figure 12a) of the die 1200, compared The overall thickness of the functional material 1258 and 1252, covering the interior 1220 of the die 1200. This 20 micron thickness is small, but negligible, and can be detected visually or tactilely in the wafer.</p>

<p dir="rtl">20 Created by a template provided with a functional material. (The basal layer of the functional material can be thicker, thicker, or thinner. For example, the base layer could be 40 microns thick, with the outer layer 20 microns thick, for a total thickness of 60 microns. Or, functional materials can be made of different materials from each other.</p>

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It is illustrated schematically with reference to Figures 15 and Figure 16, which show a cross-section through one part of a wafer and a die on which the wafer is formed (left side, as shown in Figure 12e, corresponding to the left parts of Figures 1b, 5b, 6b and 7b,). The chip 1500 is configured against the die 1200, which is essentially the same as the die 1200 shown in Figure 12e.

5 The die includes a functional material having a first overall layer 1252 that covers the entire die 1200, and a second layer 1258 in the interior portion area. Therefore, the thickness of the functional layer is in the thickest inner part. The wafer component 1500 includes a thicker perimeter section 1530 and a thinner inner section 1520. The wafer is not flat on the surface 1556 facing the magma chamber surface 1256 of the die 1200. Also, the die-facing surface 1556 of the wafer 1500 has a hollow section 1557 (which may be

10 (better shown in Figure 16), which is due to the difference in height of the functional material regions embedded in the interior 1258 and the overall layer 1252. The overall layer 1252 is the functional material located only at the peripheral die region 1230. In an exemplary embodiment of a wafer according to one of the inventions herein, the This gap is approximately 20 microns deep (in the direction of the wafer thickness 1500), in the case of the wafer there is an inner sector 1520 that is approximately 100 microns thick, and a peripheral region

15 1530 with a thickness between 200 and 250 microns.

It can be seen that the circumferential region 1530 of the growing wafer 1500 is also required to be thicker than the inner part region 1520, and the circumference extends away from the base plane 1521 of the inner part sector. For the above sizes, the peripheral part forms a raised compared to the inner part region extending about 100-150 µm away from the 1521 core plane. (Figure 16,

20 (Other figures are not taken to scale.)

An important reason why the perimeter portion 1530 is thicker than and extends away from the interior 1520 is because the thermal recovery tendency of the coated template 1200 is greater at the perimeter 1230 than at the interior 1220, because there is less thickness of functional material around the perimeter 1230. (That is, there is only layer 1252 at the perimeter, but there is

25 Layer 1258 and also layer 1252 in the inner part), less resistance to heat flow and quantity

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Thermal recovery, from what is there in the inner part section 1220. Functional material layers 1258 and 1252 can be the same material and thermal properties, in which case the difference in thickness results in the difference in thermal recovery tendency. Layers 1258 and 1252 may also be of materials or strengths such that the thermal properties 5 are different, in which case they may be a thinner state of the functional material of the first material which

It will have a greater impact on thermal recovery from a thicker state of a functional material than from a second different material. This is discussed in more detail, in the context of discussing other die types and other ways in which the tendency of thermal recovery varies across the die surface.

A small gap due to the slightly thicker area of functional material will be needed in areas where a relatively thicker grown wafer is required, such as shown at

1557, will be present whether the functional material is presented as a coating, such as a fluid substance (either liquid particles) or as a free interfacing plate. It will also be present in the case of other chip geometries, such as those forming thicker strips, anchoring media and parts interfaces, as shown by reference to Figure 10 (for the wafer) and Figures 14a and 14b (which shows the die).

15 A mold with specially designed areas of different thicknesses

As shown schematically in reference to Figure 17, die 1700 can be provided with varying thicknesses across the surface area to further produce wafers with varying thicknesses at various controlled locations tailored to the wafer's surface area. This then includes a magma chamber surface template 1756 and a back surface 1754. By a magma chamber surface, it will be intended a surface that faces and then comes into contact 20 with the magma during formation of the flake. Ideally, when it contacts the surface of the magma chamber 1756 of the mold

1700 First with the magma, the surface of mold 1754 is at a temperature below the solidification temperature of silicon. Heat is extracted from the magma by conduction (through any functional layers present, as described above) in the die 1700. The die is heated and this limits the thickness of the wafer to it. This is because as the die is heated to the melting temperature of a semiconducting material, it can 25 solidifies against the mold at locations that rise to the melting temperature. The thicker area of the mold, the longer

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The time it takes for the area to heat up to this temperature, and the thicker foil material that hardens against the die at thicker areas, compared to areas with a thinner die. Therefore, a thicker mold area has more heat extraction power/intensity than a thinner area. Therefore, a thicker die area is a heat extraction enhancer, and a thinner die area is a reducer.

5 Thermal extraction.

Thus, in another embodiment of the method of the invention, shown schematically with reference to Figure 17, the thickness of the die itself 1700 can vary from one region of the die, e.g., an inner region 1720, to another region, e.g., a circumferential region 1730. If there is a proportionately lower thermal mass In the mold 1700, for example, by making certain areas, such as the interior area 1720, locally thinner than the

10 Others, such as in the circumferential region 1730, there is less heat mass, less heat extraction, and the interior 1720 of the mold 1700 will be heated to the melting temperature relatively faster, compared to thicker circumferential regions 1730, and thus, at thinner regions of the mold 1720, the Less silicon hardening, resulting in a thinner wafer locally, for example, in its inner region, as shown by reference to wafer 100 in FIG. 1 and FIG. 1A.

15 It will be noted that a new, non-obvious and non-obvious aspect is that the mold 1700 will be a flake such as shown at 100 according to Figure 1, having a thick perimeter 130 and a thinner interior 110, by essentially touching the plane of the mold, the surface of a magma chamber 1756 with a surface. Magma. As shown schematically by reference to Figure 18, showing, in cross section, a portion of the wafer 100, such as that shown in Figure 1, growing on a die 1700 as shown in

20 Figure 17, the flake 100 grows away from the surface of the magma chamber 1756 of the matrix 1700, in the magma. However, due to the tendencies of extracting the interior portion 1720 and the perimeter portion 1730 of the die 1700, due to the different thicknesses, as shown by the back surface 1754, the shown wafer 100 will have a thickness that reflects qualitatively (rather than quantitatively) the die 1700, with a thick periphery 130 and a thin interior portion 120. (The degree of differences in thickness values for the thin and thick parts of the mold will be:

25 The chips are different from each other, and Figure 18 is a schematic only, not drawn to scale.

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The uneven surface 154 of the component wafer 100 (facing the display unit in FIG. 1, shown in FIG. 1A), will grow and face away from the magma chamber surface 1756 of the die. Thus, the essentially flat surface 156 of the component wafer 100 forms on and is attached to With an essentially flat surface of the magma chamber 1756 of the mold 1700, while the uneven plane

5 Each wafer 100 (face 154) and die 1700 (back face 1754) are facing away from each other.

(It should also be noted that when implemented, the die will stop extracting enough heat to continue chip growth somewhat before the die temperature reaches the melting point of silicon.) The mold has a relatively small heat capacity compared to the molten silicon and the crucible, which is generally 10 at the temperature of the molten silicon, or higher, and the mold only cools the magma

Topically. As the mold heats up, the heat extraction rate decreases and is obtained to offset the return of heat from the rest of the magma, to cool a local layer of molten material to below the melting point and to overcome the heat of consolidation.

It will be noted that for each mold working with parts processed with a functional material, such as the mold

15 1200 shown in Figure 15, and the die that works with parts of different thicknesses, such as the die

1700, shown at Figures 17 and 18, magma chamber surface, surfaces 1256 and 1756, respectively, are essentially flat, and flakes also grow with nonflat surfaces, 1554 and 1754, respectively, trending away from the corresponding controlled casts.

It is also possible to provide a mold with different thicknesses in different areas corresponding to geometric shapes

20 For the other chips mentioned above. An example as shown schematically in Figure 19, would be of

It is possible to provide a mold 1900 that generally has a flat magma chamber face 1956 (not shown in Figure 19), a back face 1954, and a relatively thin overall interior area 1920. The thin area 1920 forms a basic level, from which the ascending parts, or promontory, extend, so that The thickness of the matrix at the sites of the burrs is thicker than at the base level, the thinner part is 1920. The bursa can be

25 In the forms and locations of the ocean 1930, one or more of: a bar 1960, a means of anchoring or a restraining patch.

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1940, and partly between 1942, etc., as described above. The back face 1954 of this die will be uneven, and the die will have greater heat extraction tendencies at the specially designed locations 1930, 1940, 1942, 1960, where the die is thicker. Therefore, the wafer formed on this die will include thicker regions at locations corresponding to said protrusion, in a manner similar to 5 the thicker circumference 130 of the wafer 100 which, when grown, includes the die 1700 having the thicker circumference

1730. The thicker parts of the flake grow in the magma.

In general, a small area on a thick die will have a larger surface area to volume ratio than a larger die area would, so that there is more blurring of heat extraction capacity at the perimeter. For example, to achieve a 200 µm thick perimeter and also to achieve a 200 µm thick micro-interface, which must have a larger surface to volume ratio rather than

perimeter, a designer will need to make the die region that is the thicker interface than the well-formed die region that will be the perimeter (or any region that is larger and has optimum surface area for heat loss per volume of bulk thermal capacity).

Figure 19a shows the 1900 die according to Figure 19, cut at sector AA, which shows the area

15 The thinner interior 1920, thicker peripheral region 1930, will cause the growth of the thicker periphery region 130 in the wafer 100, as shown at Fig. 1, or as shown at Fig. 10, perimeter 1030. Also shown in Fig. 19, is a thicker region 1940 of the die. , which provides a thicker anchor or setting patch, such as 1040a, 1040b, as shown in Figure 10, and also a thicker 1960 area of the die, which will result in a thicker strip, such as 240a, 240b, as shown in Figure 10.

20 Shown in Figure 2.

Figure 19b shows the die 1900 according to Figure 19, cut at section BB, which shows, as shown above, the thinner inner region 1920, the thicker peripheral region 1930 and the thicker region 1950, which gives rise to a thicker band. Between the thicker circumferential region 1930 and the bar region thicker 1960, there is a thicker region 1942, which gives rise to a thicker interlayer, such as the 25 shown at 1042a, 1042b in Figure 10.

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Figure 20a shows, in cross-section, the same portion of die 1900 corresponding to Figure 19a, associated with a cross-section of the portion of wafer 2000, which will grow on die 1900, which shows the thicker circumferential region 2030 corresponding to the thicker die region 1930, a setting patch or region A thicker docking means 2040 for the wafer and a thicker strip area 2060. Figure 20b shows

5 A portion of the die 1900 according to Figure 19b, is attached to a cross-section of the portion of the same wafer 2000, which can be grown on the die 1900, which also shows the thicker peripheral region 2030 and a thicker bar region 2060, and also a thicker interfacial region 2042. For the simpler die and wafer pair shown schematically Referring to Figure 18, it can be seen that the thicker areas of the growing flake grow away from the matrix, in the magma, where this flake grows in a mirror-like configuration compared to the matrix. )meant by

<p dir="rtl">10 Qualitatively, the thicker and thinner areas are adjacent/reflective to each other, but it does not mean quantitatively reflective (as the lateral amount corresponds along the length of the foil and are essentially equal in size, but these protrusions are far apart from each other and are unequal in size).</p>

Molds can be manufactured with basic and pro level. They can be manufactured in any possible way, such as by conventional fit, with milling, drilling or sawing processes. For example, one method is to drill a board

<p dir="rtl">15 A thin sheet of material is made by clamping it using a vacuum chuck, during conventional milling of a pocket in an area of the die that has a reduced thickness. Laser mapping is another alternative method that reduces fixture requirements by avoiding cutting forces.</p>

Another way to change the thickness of the component chip is application-specific to a different degree of pressure

<p dir="rtl">20 Emphasized contrast during chip formation. The patent for direct wafer technology discusses providing differential pressure across the die face, compared to a region at the magma surface, where the differential pressure is ideally a vacuum at the die face, compared to atmospheric pressure at the magma surface. It will be determined that having a greater differential pressure in one region of the die, such as a circumferential region, compared to a greater differential pressure in another region of the die, such as an inner part region, will result in more</p>

<p dir="rtl">25 Heat flow and more heat extraction at locations of greater differential pressure. Will be</p>

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This is believed to be due to the higher vacuum level leading to a higher rate of thermal transfer to the mold, thus faster silicone hardening and maximum thickness.

In fact, it has been determined that regions of greater differential pressure have a greater thermal recovery tendency, and also, it has been determined that the regions of the chip formed opposite these die regions of greater differential stress

<p dir="rtl">5 Relatively thicker areas of the growing chip adjacent to facing areas of lower differential pressure. In the above terms, a greater differential pressure is a heat extraction enhancer, and a lower differential pressure is a thermal extraction reducer. Therefore, a further object of the invention is to provide different levels of differential pressure instrumentation according to particular locations where it is desired to include different thicknesses in the component chip.</p>

<p dir="rtl">10 The patent for direct foil technology discusses methods for providing relatively greater differential pressure (such as a strong vacuum) at one location than at another. A method for doing this is illustrated at Figure 27 of the patent for direct foil technology, which is discussed in paragraph 00160, 00163 Here, to provide a dual plenum, with a first inner zone which is maintained at the first pressure, and a second blower for a peripheral zone provided with a different differential pressure, therefore</p>

<p dir="rtl">15 Introducing greater differential pressure in the circumferential zone, as greater differential pressure improves heat flow, so more heat is extracted from the magma in the circumferential zone, thus leading to a thicker flake in the circumferential zone. (The reason for the double blow mold mentioned in the direct foil patent is that it is completely different, will be used in a different way, and there is a reason why different differential pressure systems are created around the opposite circumference of the inner part, to create a thinner inner part.)</p>

<p dir="rtl">20 Another reason for the double blower mentioned in Figure 27 at paragraph 00114 is to aid in chip removal from the machined surface after it has formed, by preventing chip formation near the relatively sharp retaining edges of the die. Another reason, mentioned in Patent § 00118 for direct chip technology, is to help stabilize the molding plate itself with the vacuum blower assembly.</p>

.)plenum assembly

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Another way to change the thickness of the formed chip is to change the degree of differential stress applied, by introducing a functional material, such as coatings, that has different degrees of permeability at one area of the die, compared to another. This structure is discussed in the direct sheet technology patent at paragraph 00118, discussing an impermeable coating 2712 on the back side of the mold sheet.

5 2705 in the area where unloading is needed. Examples of these coatings include CVD SiN

(Silicon Nitride) or pyrolytic graphite. All functional material layers, such as those mentioned above, are permeable to a certain extent, but functional materials with different degrees of permeability but with inversely similar properties (thickness, thermal mass, thermal conductivity , etc.). They can be used to form different thicknesses. In the above terms, a functional material layer with greater permeability, which can lead to greater differential pressure, is an extraction enhancer.

Heat extraction enhancer, lower permeability, which can lead to lower differential pressure, is a heat extraction reducer. However, a relatively less influential property is expected for a functional material, such as a coating, relative to the thickness of the chip.

In another embodiment of the method of the inventions, the temperature of the mold can vary locally during a phase

15 Preheating phase before contact with magma. In areas where the die temperature is lower (cooled), the greater thickness of the silicon will be solidified, resulting in a thicker area. Therefore, to achieve a thicker circumferential area of the wafer, the periphery of the die will be maintained at a lower temperature than the interior of the die. (Or, stated differently, to achieve this thicker circumferential area, the interior of the mold will be heated or maintained at a higher temperature than

20 In the above terms, a lower temperature region of the die is a heat extraction enhancer, and a higher temperature region of the die is a heat recovery reducer. In general, the die temperature is an important mechanism However, to control thickness on a local basis sufficient to create the structures described here, it is believed that other techniques are more practical and cost effective, to the extent considered

25 The cost and weight of the impact on the die temperature adjustment balance can be achieved

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By traditional means, such as formed heating elements, heat shields or local cooling. The thickening effect at the periphery of the foil can be more gradual in the case of this method for a locally different heat recovery tendency, resulting in a smoother transition between the thicker periphery and the thinner inner region. Even with relative width, for example,

5 A 10mm edge area for a thinner, 76% of the central internal area of the wafer will be relatively thinner and will offer the benefits of less silicon usage and higher efficiency.

Another way to extract more heat from the peripheral area, and thus provide a chip with a thicker peripheral area, is shown by reference to Figure 21. It is to provide the different thermal properties of the peripheral area of the die, rather than its interior, ideally by providing openings, either in

10 The interior or perimeter, or both, with empty or partially filled openings, or a combination of the above.

A method of providing different thermal properties of one area of a die, compared to another, is described in Direct Wafer Technology Patent 00103-00104. (The method aims to produce chips with areas of different thicknesses, and not the possibilities mentioned. The in-plane lateral diffusion of a solid-liquid interface is targeted

15 liquid interface, without the need for dynamically stable meniscus. This is done by radically changing the rate of heat transfer in the molding plate by changing the properties and geometric shape of the mold.

Figure 20 of the Direct Laminate Patent shows spaced 2016 blanks (the reference numbers in this paragraph refer to shapes of the Direct Laminate Patent) in the 2005 body of the molding plate, where parts

20 The molding plate (at the voids 2016) is substantially thinner than the other parts of the mold (those locations between the voids 2004). The parts at the voids are essentially thinner than the other areas between the voids.

With respect to the present inventions, as shown schematically with reference to Figure 21 of the present application, it is possible to use a die 2100, provided with a field of openings 2102 placed on its interior 2120 but not around its perimeter 2130. In general, the openings can be small

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Very wide in diameter, and can be very far apart or close together. The openings can have, for example, center-to-center spacing on the order of the die thickness or smaller. For example, in a 1 mm thick graphite template (from the surface of a magma chamber to the back surface), the holes could be 0.5 mm in diameter, 0.6 mm deep, spaced 1 mm apart. Preferably

5 A hexagonal spacing arrangement is ideal, but it would be helpful to have a square arrangement as well. The diameter of the holes is similar on the order of the die thickness, or smaller. The slot depth, which can be any size, provides an effective change in the tendency of thermal recovery, which can ideally mean at least half of the die thickness, and, the upper limit is the same as the total die thickness.

10 The openings can be solid, meaning a partial pressure passes through the die thickness, with their open end ideally at the back face 2154 of the die 2100, directed away from the melt. The magma chamber 2156 faces the faces of the molten material and, at least for any of the openings, will generally be smooth (i.e., not perforated by any openings). Or the openings may pass all the way to the mold body from the back surface 2154 to the surface of the magma chamber 2156.

15 2156. Openings can be formed with solid holes and the openings can be hung with another open end at

Face the back of the mold, and then block the back face, such that there is an empty area retained between the 2 solid or filled areas, at least some of the openings.

If the openings are plugged, empty, with their intact end closed on the surface of the magma chamber 2156, facing the molten material, and there are open edges 2154, which point away from the molten material 20, and can be lifted, a thinner matrix can be formed. At their locations, which

It leads to less thermal extraction of magma at these locations, which makes the flakes have thinner bodies at those locations. Therefore, if the openings are empty and are sufficiently close and small for heat extraction purposes, to create a continuous area of thinner die in the inner portion, the die will effectively be thinner in the inner portion (corresponding to the inner portion area 1720 of die 1700 shown at

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(Figure 17) As a chip is formed with a die provided with a blank field, I will make the blended slots in terms of the inner part of a thinner inner area, such as is required, and shown schematically at Figure 1.

Therefore, providing spaces, or openings, is an alternative way to make areas of the mold that are relatively thinner than others. Therefore, there are a set of voids in the die area, which leads to a thinner die area and thus formation

5 Heat extraction reduction unit. Using slots, corresponding to the thinner region, such as at 1720 according to Figure 17, can result in a die that has less thermal mass, thus resulting in reduced heat extraction but additional mechanical strength rather than the continuous thinner profile shown in Figure 17.

Openings can be formed by mechanical machining means

<p dir="rtl">10 known. There can be a resulting method of drilling holes at the desired locations. Another method would be to provide a set of spaced parallel saw cuts with a circular saw blade that does not pass all the way through the mold, spaced apart from the required slot spacing. Next, a second set of parallel saw cuts can be filed, oriented perpendicular (or at least nearly perpendicular) to the first set, also the required slot spaced to the slot spacing.</p>

<p dir="rtl">15 (Also taking into account the amount of kerf of the saw cuts). This can lead to a set of pin structures located at the interfaces of the spaces between the saw cuts. The pins define thermal hardening to provide areas of the die that have greater gas permeability than other areas. Areas of greater permeability allow a greater force of relative pressure to be applied to form the body due to the differential pressure system, and thus heat extraction is greater due to the greater differential pressure.</p>

<p dir="rtl">20 The pressure gradient for viscous flow through a porous material is determined by the flow rate times the viscosity divided by the gaseous permeability of the material. This is characterized by a phenomenon governed by relationships known to experts in the field, such as Darcy's law.</p>

A way to do this is already described above, by providing functional materials that change gas permeability to locations where they can be introduced, or by providing functional materials with different permeabilities in

<p dir="rtl">25 Different sites. In some cases, providing a field of blind holes (or...</p>

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(open holes) by specifying greater gas permeability in the region where there are holes, compared to regions where there are no holes. Thus regions where there are blocked holes can provide improved heat extraction and, consequently, thicker semiconducting regions. Note that this effect is Corresponding to the effect mentioned above, where thinner regions are those with less thermal mass,

<p dir="rtl">5 Thus, the thinner parts of the wafer are formed adjacent to the slotted die areas. The effects of both greater permeability and lower thermal mass will be well defined and the expert in the field will be able to understand the relative sizes and will be able to determine and design the desired effect by a reasonable choice of opening sizes and locations. It will generally be thought that the effect on thermal mass is the dominant consideration, but the effects of permeability must also be considered.</p>

<p dir="rtl">10 It is possible to fill the openings with inserts of a material that has thermal properties so that more heat is extracted closer to the unadded areas of the mold. Therefore, the perimeter of the openings can be filled with this material, which can be more thermally massive than the core part of the die, so that the perimeter of the formed wafer is thicker, as desired, and as shown by reference to Figure 1. However, the methods of introducing the material will be In these slots is rather difficult.</p>

<p dir="rtl">15 When selecting mold materials, any mold fillers, and also when considering whether openings in the mold will be left empty or the size (depth, diameter) of their manufacture, the designer must consider that both thermal conductivity and thermal inertia (heat capacity) can It affects the hardening thickness. This corresponds to what was mentioned previously, in that heat transfer determines a thickness that has a transition side (thermal conductivity) and a steady state side (thermal capacity) – due to the fact that there is a combination between the heat that is drawn into the mold and the heat. Arra</p>

<p dir="rtl">20 That is plugged into the flake of magma below.</p>

The die, which has the crowns fitted in different patterns, can be used to produce other wafers as shown above. The slots may be left empty, to provide essentially thinner areas of the die at the empty hole locations, or they may be filled with a material having thermal properties to provide improved or retarded heat extraction compared to the core die body, thus giving thicker or thinner areas of the chip at their locations.

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Previously, thin films with thicker peripheral regions were described. The entire perimeter is outlined so that it surrounds the inset area, for example on four sides, as shown in Figure 1. It is also possible that a smaller amount of the overall circumference is thicker than the inset area. Example, 1, 2 or 3 edges (indicated by an edge, here) thicker. Or, change the edge area entirely, the thicker areas

<p dir="rtl">5 They must form parts of the individual edge.</p>

Also, the above description focuses on industry standard square wafers. This is the most common practice today, but the inventions disclosed herein are applicable to wafers of any shape, including non-square rectangles, circles, triangles, etc. What matters is that there is generally a thin area and at least one thicker area in at least one of the locations

<p dir="rtl">10 Predetermined, thickness values are measured in a direction perpendicular to the surface (square, rectangular, circular, etc.) of the wafer. The current industry (in 2015) tends to fully process solar cells from silicon wafers 156 mm by 156 mm square, taking into account the structure Supply infrastructure and standard equipment to handle this size, but cut into 156mm</p>

<p dir="rtl">15 Loss of resistance. To support this selection using the wafers disclosed herein with local thickness control, a central overhang can be provided along the line that intersects the work cells. The protrusion will be similar to strip 240b, as shown at Fig. 2. The foil can be dissected along the center-line of this protrusion, which will become part of the thickened perimeter of cells about two-half the size of the component cells.</p>

<p dir="rtl">20 In general, the wafers according to the inventions will include a relatively thinner portion and a relatively thicker portion. In a preferred embodiment, the relatively thinner portion extends across at least 80% of the surface area of the wafer, and preferably through at least 90%. This balances the impact and additional cost of producing a complex trace wafer with the material utility benefits and the cost and effectiveness gained from thinness and material savings. In general, the absolute thinnest part will be at least 50 microns thick, and, to achieve the gain in efficiency, it will be at least 50 microns thick.</p>

<p dir="rtl">25 Minimum 80 microns. The thickness ratio of the thickest part to that of the thinnest part is ideal</p>

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At least 1.28:1 (e.g. 180 micron perimeter with 140 micron interior) and can be approximately 3:1 or 5:1.

It is generally considered that the effectiveness of the thinner fraction is achieved at any size down to about 80 microns depending on the particular cell structure used. Standard foil thickness is 180

5 200 microns, therefore, the range of thicker parts in this thickness range will be

Useful model. Similarly, the thickest part can be 250 microns thick for added strength, and still be within a standard size range. Thus, one could make a wafer with a part as thin as 80 microns, and a part thicker at 200 or even 250 microns. This wafer will have a thickness ratio of more than 3:1, with the thicker portion extending 170 microns above the base plane of the thinner portion.

10 It is envisaged that the benefit could be obtained with an ultra-thin inner portion of about 50 microns, for the purpose of saving weight, and a relatively thick periphery of 250 microns, which is at the outer limit of current use. This foil will have a thickness to thinness ratio of 5:1.

It should be noted that the above ratios of thick and thin areas are given in the context of the industry standard for 156 mm x 156 mm silicon wafers, or perhaps wafers half that size. 15 Size considerations were developed taking into account the mapping and processes used for these chips. However, for non-photovoltaic applications, or those of standard wafer size, objects of any larger or smaller sizes can be made by patented methods of direct wafer fabrication, such as smaller or larger dimensions. For some uncalibrated volumes, thick-to-thin ratios can be more reproducible at the limitations of the stated range of 1.28:1 to 5:1.

20 Similarly, there are frequent uses of thin wafers near 50 microns in size, or thicker wafers, such as near 250 microns.

It will be noted that there are many previous techniques for providing a matrix with different thermal extraction tendencies at different locations. For example, a die having different values of thickness at different locations, either with a fairly uniform specific density, as shown in Figure 17, or, with a gap, the area of the 25 die being thinner or more permeable at their locations, which can be used in combination with each other and also with the placement of

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Functional layers, either as coatings or as overlapping layers. Any of several shapes can be used for the thicker areas shown on the die and the foil has any shapes. The above molds may include hot or cold zones or other processes to control or optimize the mold temperature. Mold geometries can also be used with multiple differential pressure values of varying degrees greater and less, either 5 components with more than one blower, or coatings with different permeabilities, or different porosity zones.

Different for the template.

The developed wafer provided may have areas of rising portions on both sides of the wafer, the surface showing the die face, and the surface showing the molten face, by providing functional layers such as shown in Figure 15, which produces a 1500 wafer, as shown in Figure 16, with

10 The rising parts extending from each of the surfaces of the chip. It is possible to provide functional layers with thickness

Fundamentally different (e.g. greater than 20 microns), such that the vibration 1557 in the thickness of the wafer is sufficiently large, compared to the thickness of the perimeter 1530 or other thicker areas. Or, functional layers can be used to create a difference in the height of the parts rising to the surface facing die, die thickness differences, differential pressure, etc. to provide the height of the parts rising to the surface of the chamber

15 Magma.

This disclosure further describes the invention. The inventions here are mentioned in the protective elements of these documents, not only filed, but also developed in the course of pursuing any patent application based on this disclosure. The inventors intend to claim protection for all of the various inventions subject to the limitations permitted in the prior art, as specified in advance. There is no property not described herein, but 20 will not be claimed in any claim of any patent based on this disclosure, and will be incorporated in any manner.

For example, the invention may be used using functional materials to control thermal extraction as stated alone, or in combination with any of the other methods, such as using molds with different local thicknesses, varying degrees of differential pressure delivery, varying degrees of porosity, different degrees of The different temperatures of the mold shown, and the different degrees of gas permeability. Similarly, using 25 dies with different spot thickness values can be used with any of the other techniques mentioned. any

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These geometric shapes can be used alone or in combination with other geometric shapes not mentioned. Thick perimeters may be used with any or all of the interfaces, anchors, strips, full or partial edges, and any or all of them may be used with any or all of the others.

The inventions have been described primarily with silicon semi-conductors

<p dir="rtl">5 For photovoltaic use. However, techniques can be used with any semiconductor material, for use. Photovoltaic wafers have been used as representative fabricated materials, although there are other semiconductor bodies with different types of electrical connections that can be made using bare-template-based methods.</p>

Certain assemblies of the device or combinations of steps are referred to herein as the invention. However, this is not the case

<p dir="rtl">10 A statement that any distinct combinations or combinations of inventions are patentable, specifically as defined by laws and regulations for the inventions to be examined in the patent application, or the unit of the invention. It is intended to be a way to mention one of the examples of the invention.</p>

A summary is provided here. The emphasis in this summary was to comply with the law regarding summaries that allow examination and other researchers in order to confirm the subject of the disclosure

<p dir="rtl">15 Technical. It was noted that the understanding that the perspective or meanings of the elements of protection, as defined by the role of the patent office, would not be interpreted or restricted.</p>

The above should be understood as illustrative and should be considered as being unrestricted in any way. While the inventions are specifically described with reference to preferred embodiments, an expert in the field will understand that obvious changes in form and detail can be made without leaving the spirit and perspective of the inventions as defined by the claims.

Corresponding structures, materials, procedures, and equivalents, in addition to the elements in the protections below, are intended to include any structure, material, or procedure for implementing the functions in combination with other elements to be protected as it is sought to be protected.

Aspects of the invention

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The following aspects of the invention are intended to be described herein to ensure that they are stated. They are called sides and although they are similar to protection elements, they are not protection elements. However, at any time in the future, applicants reserve the right to claim any and all of these and other relevant applications.

5 1Α. Semiconductor chip includes:

a. first surface; And

B. second surface;

C. a first zone with a first average thickness in a direction perpendicular to the first surface;

Dr.. a second area with a second mean thickness that is thicker than the first mean thickness and located at a controlled location 10; And

H. Vacuum oxygen content less than 6 0 x 7 atoms/cc;

And the. Total oxygen content is less than 10 x 8.75 atoms/cc.

2Α. Semiconductor chip includes:

a. first surface; And

<p dir="rtl">15 B.Second surface;</p>

C. a first zone with a first average thickness in a direction perpendicular to the first surface;

Dr.. A second area is located in a controlled location, with a second mean thickness, the ratio of the second mean thickness to the first mean thickness being between 1.28 to 1 and 5 to 1.

<p dir="rtl">3A. Semiconductor chip includes:</p>

20 a. first surface; And

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B. second surface;

C. a first zone with a first average thickness of less than 160 microns in a direction perpendicular to the first surface;

Dr.. A second area, in a controlled location, has a second average thickness of at least 180 microns.

5 4A. The semiconductor wafer according to aspects 1 or 3, has a thickness ratio of 2nd medium to thickness

The first average is between 1.28 to 1 and 5 to 1.

5A. In accordance with aspects 2-3, the film has a vacuum oxygen content of less than 6¹⁷10 x atom/cc and the total oxygen content is less than 8.75¹⁷10 x atom/cubic cm.

6A. The chip according to any of the 1-2 sides, the first average thickness is less than 140 microns and the thickness

<p dir="rtl">10 The second average is at least 180 microns.</p>

7A. Semiconductor wafer According to side 1, the second surface includes a fundamental plane and, in the region y y

Second, an emergent property of a second surface, extending from the second surface beyond the basic plane, a space between

0.25 and four times the first average thickness.

<p dir="rtl">8A. The chip According to any of the foregoing aspects, the chip has a vacuum oxygen content of less than 2x</p>

15 ¹⁷10 atom/cc.

<p dir="rtl">9A. Chip According to any of the foregoing aspects, the chip has a total oxygen content of less than 5.25¹⁷10 x atom/cubic cm.</p>

<p dir="rtl">10A. The chip according to any of the above aspects, the first zone has an average thickness of less than 150 microns.</p>

<p dir="rtl">20 11A. The chip according to which of the above aspects, the first zone has an average thickness of less than one of:</p>

<p dir="rtl">a. 120 micron,</p>

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<p dir="rtl">B. 80 microns, and</p>

<p dir="rtl">C. 60 microns.</p>

<p dir="rtl">12A. Wafer According to any of the foregoing aspects, the second area is selected from the group consisting of at least one of: perimeter; edge, inner band; mooring means; And an interstitial part.</p>

<p dir="rtl">5 13A. The chip according to any of the above aspects, the second region has a thickness of less than 250 microns,</p>

Preferably between 180 and 250 microns and preferably between 180 and 200 microns.

<p dir="rtl">14A. According to any of the foregoing aspects, the second region includes a stripe region, which also includes metal parts on at least part of the strip.</p>

<p dir="rtl">15A. The chip, according to Aspect 14, also includes a bus-wire in contact with metal parts.</p>

10 16A. On the wafer according to any of the foregoing aspects, the second area includes a mooring device area

.landing region

<p dir="rtl">17A. On the wafer according to aspect 16, the second region includes at least one interfacial part.</p>

<p dir="rtl">18A. The foil, according to aspect 17, also includes a metal piece coupled to the docking device region and the interface region.</p>

<p dir="rtl">15 19A. The foil, according to aspect 18, also includes a universal wire that touches metal parts at a means</p>

Docking and interface.

<p dir="rtl">20A. Foil According to side 19, the universal wire is placed in contact with the metal parts between the anchoring device and the interface.</p>

<p dir="rtl">21A. The foil according to side 19, the common wire is positioned to be spaced from the metal parts at</p>

20 Area between the anchorage and the interface.

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22A. The foil according to side 16, the anchoring medium has a greater thickness adjacent to the second zone and less adjacent to the first zone.

23A. Sheet According to side 22, the anchoring medium has a thickness that gradually transitions from greater to lesser thickness.

5 24A. The foil, according to any of the foregoing aspects, also includes a zone of fish transition between zones

From the first to the second region, the transition is chosen from the group consisting of: a sharp transition and a gradual transition.

<p dir="rtl">25A. The foil according to any of the foregoing aspects, the second zone includes a circumferential zone having a width and the foil also includes a transitional thickness zone from the second zone to the first zone, and this transitional zone also has a width 10.</p>

<p dir="rtl">26A. The chip according to side 25, the width of the peripheral zone is approximately equal to the width of the conventional zone.</p>

<p dir="rtl">27A. The chip according to side 25, the width of the peripheral zone is significantly larger than the width of the conventional zone.</p>

<p dir="rtl">28A. The foil, according to any of the foregoing aspects, also includes a coating of a material covering the second surface</p>

<p dir="rtl">15 The common wire and a second chip associated with the common wire.</p>

<p dir="rtl">29A. The foil According to any of the above aspects, the first surface includes essentially a flat surface</p>

flat surface

<p dir="rtl">30A. The foil according to aspect 7, the first surface includes a basic plane and an emergent first surface feature; The property of the first emerging surface extends from the first surface to a distance less than the distance extended by 20 the property of the second emerging surface extending from the second surface.</p>

<p dir="rtl">31A. The chip, in accordance with any of the above, includes a semi-conductor of silicon.</p>

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<p dir="rtl">32A. According to any of the foregoing aspects, the chip includes a chip including a photo-voltaic collector.</p>

<p dir="rtl">33A. The foil according to side 32, the first surface of the foil has a first side of length at least 156 mm and a vertical side of at least 77 mm.</p>

<p dir="rtl">5 34A. A method for manufacturing a semiconductor chip. The method includes the following steps:</p>

a. Providing a molten semi-conductor material, which has a surface;

B. Mold provided, porous body included:

<p dir="rtl">i. surface of a magma chamber;</p>

<p dir="rtl">ii. back deck;</p>

10 iii. A first template region has a first thermal recovery tendency;

iv. A second die zone has a second thermal recovery slope, greater than the first thermal recovery slope;

C. Providing a differential pressure system such that the pressure at at least part of the surface of the magma chamber is less than the pressure at the surface of the molten semiconductor material; And

Dr.. Touching the surface of the magma chamber of the mold to the surface of the molten semiconductor material of a part on

15 Less than a contact period, in which the surface of the magma chamber and the molten semiconductor material are in contact with each other, and a differential pressure system is provided, so that the body of the semiconductor material solidifies on the surface of the magma chamber. This component body includes:

i. A first thin body region, having an average first thin body thickness, the first thin body region formed adjacent to the first die region; And

20 ii. A second thicker body region has an average thickness of a second thicker body. The second body region is formed adjacent to the second die region. The average thickness of the second body is greater than the thickness of the first body.

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35A. The method according to aspect 34 also includes the step of separating the semiconducting material body from the die.

36A. The method according to aspect 35, the step of separating the component body includes reducing the degree of differential pressure system.

5 37A. The method according to aspect 35, the step of separating the component body includes mechanically applying a compressive force

On the component body.

38A. The method according to aspect 34, the first mold region includes an inner region, wherein the first thinner body region is an inner region.

39A. The method according to aspect 38, the second template region includes a peripheral region, and a body region

<p dir="rtl">10 The second fish includes a peripheral zone.</p>

40A. The method according to any of aspects 38 and 39, the second die region includes a strip region extending through the inner part region, and the second thicker body region includes a strip region extending through the body of the inner region.

41A. The method according to any of aspects 38 - 40, the second template region includes a method region

<p dir="rtl">15 Mooring, the second thicker body area includes a mooring facility.</p>

42A. The method according to which of aspects 38 - 41, the second die region includes an island region, the second thicker body region includes an interface region.

43A. Method According to Aspect 38, the second die area includes a circumferential region, the second thicker body region includes a circumference, the second thicker die region also includes one selected from the 20 group consisting of:

a. A stripe region extending across the inner part of the body, wherein the second thicker body region includes a stripe extending across the inner part of the body;

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B. An anchorage means area, wherein the second thicker body area includes an anchorage means; And

C. Interstitial region, where the second thicker body region includes an interstitial segment.

44A. The method according to any of aspects 41-43 further includes the step of providing on the component body, extending the metallization material from a first interfacial portion to at least one of a second interfacial portion 5 and an anchoring means.

45A. The method according to Aspect 44 also includes the step of providing a common wire extending from the first interpart to at least one of a second interpart and an anchoring means, the common wire touching the metal parts between the first interpart and at least one of a second interpart and an anchoring means.

46A. The method according to aspect 44 also includes the step of providing a common wire extending from the first interface 10 to at least one of a second interface and an anchoring means, the common wire spaced away from the metal parts between the first interface and at least one of a second interface and an anchoring means.

47A. The method according to any of aspects 41-43, the second zone including a strip zone, further including a provisioning step on the component body, the metal material extending along the strip zone.

48A. The method according to aspect 47 also includes the step of providing a common wire extending along the metal parts 15.

49A. The method according to any of Aspects 34 - 48, the porous die includes a die material having a first lower average thickness at the first die zone and a die material having a second greater average thickness at the second die zone, wherein the tendency of the greater thermal recovery of the second die zone compared to the first die zone is partly on Lower due to the larger average thickness of the material block for the second die area compared

<p dir="rtl">20 The average thickness of the material block for the first block area.</p>

50A. The method according to which aspects 34 - 49, the porous die has a functional material with a first greater thermal conductivity at the first die region and a functional material with a second greater thermal conductivity at the second die region, where the tendency for greater thermal recovery of the second die region compared to the die region

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The former is at least partly due to the greater thermal conductivity of the functional material of the second die region compared to the lower thermal conductivity of the functional material of the first die region.

51A. Method According to Aspect 50, the functional material includes the same compositions as the others, the first zone functional material having a first thickness and the second zone functional material having a second thickness, less than 5 the first thickness.

52A. The method according to any of aspects 50-51, at least one functional material including a coating

.coating

53A. The method according to any of aspects 50-51, at least one functional material comprising at least one interposer layer.

10 54A. The method according to aspect 53, the nested layer includes two nested layers

interposer layers The fascia is of different size.

55A. The method according to aspect 53, the overlapping layer includes a single overlapping layer having different thicknesses at different locations.

56A. The method according to which aspect 34 - 53, the porous matrix includes a matrix material having a first gas permeability of 15 at the first matrix region and a matrix material having a second greater gas permeability at the matrix region

Second, where the tendency for greater thermal recovery of the second die region compared to the first die region is at least partly due to the greater permeability of the material matrix of the second die region compared to the permeability of the material matrix of the first die region.

57A. The method according to any of aspects 34 - 56, further includes the step of coupling the first die area 20 to the first source of differential pressure, and the step of coupling the second die region to a second source of differential pressure, the second source of differential pressure providing a greater differential pressure than the first source of differential pressure, wherein the recovery tendency The higher temperature of the second die area compared to the first die area is partly on

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Less due to the greater differential pressure introduced at the second mold region compared to the greater differential pressure introduced at the first die region.

58A. The method according to aspect 49, wherein the first minimum average thickness at the first die region results from a plurality of openings provided in the first die region.

5 59A. The method according to aspect 58, openings includes blind openings that extend partially from the body

Porous surface back to the body Porous surface of a magma chamber.

60A. Mold, porous body includes:

a. surface of a magma chamber;

B. back deck;

10 C. A first region has a first thermal restoration tendency; And

Dr.. A second zone has a second thermal recovery slope, greater than the first thermal recovery slope.

61A. In accordance with aspect 60, the porous body includes a material having a lower first average thickness at the first region and a material having a greater second average thickness at the second region, wherein the greater thermal recovery tendency of the second region compared to the lower thermal recovery tendency of the first region results in part.

15 At least, the greater thickness of the second zone material compared to the smaller thickness of the first zone material.

62A. According to side 62, the surface of the magma chamber has a relatively flat surface, compared to the back surface, a second zone of greater thickness formed by ascending parts extending from a basic level of the back surface, away from the surface of the magma chamber.

63A. According to either side 60-62, the first zone includes spaced voids that extend 20 from the back surface toward the surface of the magma chamber.

64A. Die according to side 63, thousand blanks that have a center-to-center spacing on the order of or less than the average thickness of the die in the area in which it is located.

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65A. Die According to any of the sides 63-64, the blanks have a diameter on the order of or less than the average thickness of the die in the region in which they are located.

66A. Die According to any of the sides 63-65, the voids have a depth of at least 1/2 the average thickness of the area of the die in which they are located.

5 67A. The mold according to any of sides 63-66, the blanks include blocked holes.

68A. According to side 67, the blocked holes include empty holes.

69A. The matrix according to any of sides 60 - 68, the porous body includes on the surface of its magma chamber, a functional material having a greater first thickness at the first region and a functional material having a second smaller thickness at the second region, where the slope of thermal recovery is greater for the second region compared to the recovery slope 10 The lower temperature of the first zone is at least partly due to the smaller thickness of the functional material

For the second zone compared to the greater thickness of the functional material for the first zone.

70A. The matrix according to any of aspects 60 - 68, the porous body includes on the surface of its magma chamber, a functional material having a first lower thermal conductivity at the first zone and a functional material having a second greater thermal conductivity at the second zone, where the tendency for greater thermal recovery is to zone 15 The second compared to the lower thermal recovery tendency of the first region, at least partly due to conductivity

The thermal conductivity of the functional material of the second region is greater compared to the lower thermal conductivity of the functional material of the first region.

71A. Mold According to any of the aspects 69-70, the functional material includes a coating.

72A. According to aspect 71, the coating includes a coating applied by a method selected from

20 Set consisting of: cover paint, sputtering, slot die coating and crescent paint

.meniscus coating

73A. In accordance with Aspect 69, the functional material includes at least one free-standing overlapping layer.

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74A. The template according to aspect 73, the overlapping layer includes two overlapping layers packed to different surface areas.

75A. The die according to aspect 73, the overlapping layer includes a single overlapping layer having different thicknesses at different locations.

5 76A. Template According to any of the aspects 60-75, the porous body includes a material that has the first permeability

At the first zone and a material with a second greater permeability at the second zone, where the tendency for greater thermal recovery of the second zone compared to the tendency for lower thermal recovery for the first zone is at least partially due to the greater permeability of the material of the second zone compared to the permeability of the material of the first zone.

77A. Template According to any of the sides 60-76, the first region includes an inner region.

10 78A. The template according to any of sides 60-77, the second zone includes a circumferential zone.

79A. The mold according to either side 77 or 78, the second region includes a strip region extending through the interior part region.

80A. In the template according to any of aspects 77 - 79, the second region includes an anchoring device region.

81A. Template According to any of sides 77 – 80, the second region includes an island intersegment region

region 15

82A. Template According to side 77, the second region includes a peripheral region, one selected from the group consisting of:

a. A striped area extending across the inner part area;

B. mooring facility area; And

20 C. Intersegment area.

Relay list:

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A" period of life

"B" microsecond

"C" Impact %

“D” thickness = (µm)

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