Receiver for wireless communication network with expanded range

FIELD OF THE INVENTION

The present disclosure relates generally to communication, and more specifically to a receiver for wireless communication.

BACKGROUND

Wireless communication networks are widely deployed to provide various communication services such as data, voice, video, etc. These networks include wireless regional radio network (WWAN), which provide communication coverage for large geographic areas (e.g., cities), wireless local area network (WLAN) that provide communication coverage for a geographic region of medium size (e.g., buildings and campuses ), and wireless personal networks (WPAN) that provide communication coverage for small geographic areas (e.g., homes). A wireless network typically includes one or more access points (or base stations) that support communication for one or more user terminals (or wireless devices).

IEEE 802.11 is a family of standards developed by the Institute of Electrical and Electronics Engineers (IEEE) for WLAN. These standards describe the interface between the wireless access point and a user terminal or between two user terminals. The IEEE 802.11 standard edition 1999 (or simply "802.11"), which is entitled "Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications" (Part 11: Specifications protocol medium access control (MAC) layer and The physical layer protocol (PHY) for a wireless LAN), supports data rates of 1 and 2 megabits per second (Mbits / s) in the frequency range of 2.4 Gigahertz (GHz) using a spread-spectrum frequency hopping (FHSS), any extension of the spectrum by direct sequence (DSSS). The standard IEEE 802.11a-1999 (or simply «802.11a») is a supplement to 802.11, uses orthogonal frequency division multiplexing (OFDM) instead of FHSS or DSSS, and supports data rates up to 54 Mbit / s in the 5 GHz frequency band. Standard IEEE 802.11b-1999 (or simply «802.11b») is another supplement to 802.11 and uses DSSS to support data rates up to 11 Mbit / s. Standard IEEE 802.11g-2003 (or simply «802.11g») is another supplement to 802.11, uses DSSS and OFDM, and supports data rates up to 54 Mbit / s in the 2.4 GHz band. These various standards are well known in the art and are widely available.

The lowest data rate supported by 802.11, 802.11a, 802.11b and 802.11g, is equal to 1 Mbit / s. For 802.11b and 802.11g (or just «802.11b / g») to send a transmit (transmission data) for the lowest rate of transmission (data) in 1 Mbit / s using a special DSSS scheme and a particular modulation scheme. DSSS and modulation schemes for 1 Mbit / s requires a certain minimum level ratio signal-to-interference-and-noise (SNR) for reliable reception of the transmission (transmission data). The range of transmission (data transfer) is then determined by the geographic area within which the receiving station can reach the required or desired SNR. In some cases it is desirable to send a transmit (transmission data) to the range that is greater than the range for the lowest data rates supported by 802.11b / g.

Consequently, in the art there is a need in a wireless communication network and a station capable of operating with an extended coverage range.

SUMMARY OF THE INVENTION

This document describes a technique for detecting and demodulating a signal / transmission (transmission data) in the bad channel conditions (e.g., low SNR). In one aspect, signal detection is performed in multiple stages using different types of signal processing to achieve good detection performance. In an embodiment, signal detection is performed using time-domain correlation for a first stage, frequency-domain processing for a second stage and time-domain processing for a third stage. Signal detection for each stage may further be performed on the basis of the adaptive (adaptive) threshold value, which is output based on the received power for the interval (window) of characters to detection efficiency was less sensitive to the level of the received signal. The presence signal may be declared based on the outcomes of all three stages.

In an aspect of the first stage of input samples at a receiving station may be encoded using the despread code sequence to generate despread symbols. Then, a product of despread symbols for at least two delays, e.g., 1-symbol and 2-symbol delays. Performs correlation between the products for each delay and known values ​​for that delay. Then combine the correlation results for any delays, such as coherent or incoherent for a variety of alleged phases. The presence of the signal and the synchronization signal may be determined based on the combined correlation results.

In another aspect, demodulation is performed so as to achieve good efficiency under bad channel conditions. In an embodiment, synchronization of input samples is adjusted (e.g., by polyphase filter) to obtain the adjusted time samples. Frequency offset estimate and removed from the time-adjusted samples to obtain frequency-corrected samples, which are processed by the channel estimation (e.g., using a Rake (Rake) receiver) to obtain detected symbols. Phases detected symbols are corrected to obtain phase-corrected symbols. Then on symbols with phase correction performs demodulation to obtain demodulated symbols, which deinterleaves, and decodes to obtain decoded data.

The signal processing for each detection stage and for demodulation is described in detail below. Various aspects and embodiments of the invention are also described below.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and nature of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference numerals identify correspondingly throughout.

1 shows a transmitting station and a receiving station.

2 shows a communication processor in the transmitting station.

3 shows a PPDU structure, used by 802.11b / g.

4 shows a receive processor at the receiving station.

5 shows a first phase detection unit and acquisition time.

6 shows a second step of detection and acquisition unit frequency.

7 shows a third detection stage and channel estimation unit.

8 shows a phase correction unit.

9 shows a process for performing signal detection for the first stage.

10 shows a process for performing signal detection with multiple stages.

11 shows a process for receiving a transmit (transmission data).

DETAILED DESCRIPTION

The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

1 shows a block diagram of a transmitting station 110 and receiving station 150 in wireless network 100. Transmitting station 110 is equipped with a single antenna and may be an access point or a user terminal. Receiving station 150 is equipped with multiple (e.g., R = 2) antennas and may also be an access point or a user terminal. In general, each station may be equipped with any number of antennas that can be used for data transmission and reception. An access point is generally a fixed station that communicates with the user terminals and may also be called a base station, a base transceiver system (BTS) or some other terminology. The user terminal may be stationary or mobile and may also be called a mobile station, wireless device, user equipment (UE), or some other terminology.

At the transmitting station 110, transmission processor 130 receives traffic data from a data source 120, processes the traffic data in accordance with a data rate selected for transmission, and provides output chips. The following describes the processing of the processor 130 transfers. Module 132 transmitter (TMTR) processes (e.g., converts to analog, amplifies, filters, and upconverts) the output chips and generates a modulated signal, which is transmitted via an antenna 134.

At the receiving station 150, R antennas 152a-152r receive the transmitted signals, and each antenna 152 provides a received signal to a respective receiver unit 154 (RCVR). The antenna may also be called "diversity" and the R receive antennas provide a diversity multiplicity R. Each receiver unit 154 processes its received signal and provides a stream of input samples to the processor 160 receiving. Reception processor 160 processes the input samples from all R modules 154a-receiver 154r in a manner complementary to the processing performed by the processor 130 transmission and provides the decoded data to the data receiver 170. The decoded data is an estimate of the traffic data sent by transmitting station 110.

Processors 140 and 180 direct the operation of the processing units at transmitting station 110 and receiving station 150, respectively. Memories 142 and 182 store data and / or program codes used by processors 140 and 180, respectively.

Stations 110 and 150 can support 802.11b and / or 802.11g. 802.11g is backward-compatible with 802.11b, and supports all operating modes defined 802.11b. Stations 110 and 150 may further support a range extension mode, which supports at least one data rate that is less than the lowest data rate in 802.11b / g. Lower the speed (velocity) data can be used to extend the range of coverage, which is advantageous for certain applications, such as portable radios.

Table 1 lists the two lowest data rates supported by 802.11b and 802.11g, and processing for each data rate. Table 1 also lists three data rates supported by the range extension mode and the processing for each data rate in accordance with an embodiment. In Table 1, DBPSK denotes differential binary phase shift keying, and DQPSK denotes differential quadrature phase shift keying.

Table 1RezhimSkorost transmission dannyhKodovaya skorostModulyatsiyaKodirovanie with expansion spektraEffektivnost802.11b / g2 Mbit / snetDQPSKDSSS2 bit / simvol1 Mbit / snetDBPSKDSSS1 bit / simvolRezhim extension of diapazona1-Mbit / c1 / 2DQPSKDSSS1 bit / simvol500 kbit / c1 / 2DBPSKDSSS0,5 bit / simvol250 kbit / c1 / 4DBPSKDSSS0,25 bits / symbol

For clarity in the following description, the term "bit" refers to a quantity prior to modulation (or symbol conversion) at the transmitting station, the term "symbol" refers to a quantity after the symbol mapping, and the term "elementary signal" refers to a quantity after spectral spreading coding. The term "sample" refers to the amount of coding to spectral despreading at the receiving station.

Figure 2 shows an embodiment of transmit processor 130 at transmitting station 110. The transmitting processor 130 includes an oscillator 210, a pilot processor 240 for transmission DSSS 802.11b / g, DSSS transmit processor 250 for the range extension mode, and a multiplexer (Mux) 270 .

The generator 210 generates a pilot signal a pilot signal (also called a preamble or a reference signal) for 802.11b / g, and for the range extension mode. In the generator 210, the pilot symbol transmitter 214 receives pilot bits, maps these bits to modulation symbols based on BPSK, and provides pilot symbols to spreading apparatus 216. For the purposes of this document, a pilot symbol is a modulation symbol for pilot, a data symbol is a modulation symbol for traffic data, a modulation symbol is a complex value for a point in a signal constellation for a modulation scheme (e.g., for M-PSK or M-QAM) and a symbol is any complex value. Spreading apparatus 216 spectrally spreads the pilot symbols and provides output chips. In the device 216 the spreading code generator 222 pseudo-random number (PN) sequence of PN code generates. In some embodiments, it may be called a Barker sequence. Barker sequence of length 11 chips has a transmission rate of 11 million chips per second (Mcps), and is composed of the following 11 signal sequence {+1, -1, +1, +1, -1, +1, +1, 1, -1, -1, -1}. A multiplier 224 receives pilot symbols at a rate of 1 million symbols per second (Msps) from symbol converter 214 and the Barker sequence from PN code generator 222. Multiplier 224 multiplies each pilot symbol for all 11 chips of the Barker sequence, generates 11 output chips for each pilot symbol and provides a sequence of output chips for the pilot. The output speed of the transmission chip 11 times higher than the symbol rate of the pilot signal, or 11 Mcps. Each output elementary signal is a complex value, which must be sent to one period Tc chip, which is about 90.9 nanoseconds (ns) for 802.11b / g.

DSSS transmit processor 240 performs differential modulation and spectral spreading coding for 802.11b / g. The processor 240 differential encoder 242 receives data bits for traffic data, performs differential encoding of information bits for DBPSK or DQPSK, and provides differentially-encoded bits. For DBPSK data bit "0" results in a change in the phase 0 °, and a data bit "1" causes a change in phase of 180 °. For DQPSK pair information bits of '00' results in a phase change of 0 °, the pair of information bits '01' results in a phase change of + 90 °, the pair of information bits of '11' results in a phase change of + 180 ° and a pair of information bits " 10 'results in a phase change of + 270 °. In some embodiments, the converter 244 converts the differential symbols coded bits to modulation symbols based on BPSK for a data rate of 1 Mbit / s and the QPSK for the data rate of 2 Mbit / s. Nonetheless, other schemes may be used for modulation of transmission rates. Symbol converter 244 provides BPSK modulation symbols at a rate of 1 Msps for the data rate of 1 Mbit / s and provides QPSK modulation symbols at a rate of 1 Msps for the data rate of 2 Mbit / s. Spreading apparatus 246 spectrally spreads the data symbols from the transmitter 244 symbols and provides output chips for the traffic data.

DSSS transmit processor 250 performs forward error correction (FEC), symbol mapping, and spectral spreading coding for the range extension mode. The processor 250 FEC encoder 252 receives data bits for traffic data, encodes the information bits according to the FEC coding scheme and provides code bits. FEC encoder 252 may implement a convolutional code, turbo code, low density parity check (LDPC), block code, some other code, or a combination thereof. Block 254 repetitions / exclusion can either repeat or exclude some or all of the code bits to obtain the desired code rate. An interleaver 256 interleaves or reorders the code bits based on an interleaving scheme. The differential encoder 262 performs differential encoding of the interleaved bits, e.g. for DBPSK or DQPSK, and provides differentially-encoded bits. The converter 264 converts the differential symbols coded bits to modulation symbols based on a modulation scheme such as BPSK or QPSK. Spreading apparatus 266 spectrally spreads the data symbols from the transmitter 264 symbols and provides output chips for the traffic data. Devices 246 and 266 may be implemented by spreading as well as the spreading unit 216, and can extend each symbol with a data signal 11 using the Barker sequence to generate 11 output chips for that data symbol.

The multiplexer 270 receives the output chips from pilot generator 210, signal processors 240 and 250 DSSS transmission, provides output chips for the pilot at the right time, provides the output chips from processor 240 if the selected mode is 802.11b / g, and provides output chips from processor 250 if the range extension mode is selected.

For IEEE 802.11, data is processed by the protocol layer medium access control (MAC) layer as PDUs level MAC (MPDU). Each MPDU is processed by a physical layer convergence protocol (PLCP) and placed in a protocol data unit PLCP (PPDU). Each PPDU is processed by a physical layer (as shown in Figure 2) and is transmitted through a radio channel.

3 shows a PPDU structure 300, used by 802.11b / g. For PPDU structure 300, a PPDU 310 includes a PLCP preamble 320, PLCP header 330 and MPDU 340. MPDU 340 carries a traffic data for PPDU 310 and is variable in length. PLCP preamble 320 includes a synchronization field 322 PLCP (SYNC) field 324 and a frame start delimiter (SFD). SYNC field 322 carries a fixed 128-bit sequence that can be used by the receiving station for signal detection, acquisition, and other purposes. The bits in the 128-bit sequence are denoted by d0, d1, ..., d127. SFD field 324 carries a fixed 16-bit sequence that indicates the beginning of PLCP header. Header 330 PLCP includes a field 332 SIGNAL, which indicates the data rate for the MPDU, a field 334 SERVICE, which is set to "0" to indicate compliance IEEE 802.11, field 336 LENGTH, which indicates the amount of time (in units of milliseconds), required to send MPDU 340, and a CRC field 338, which carries a CRC value, generated based on fields SIGNAL, SERVICE and LENGTH. PLCP preamble 320 and PLCP header 330 are sent at 1 Mbit / s using DBPSK. PLCP preamble 320 contains a total of 144 bits which are processed to generate 144 BPSK symbols. Each BPSK symbol is composed of 11 output chips, which are obtained by encoding this spreading by BPSK symbol 11 chips of the Barker sequence. 144 BPSK symbols are transmitted in 144 symbol periods, each symbol period has a duration of 1 microsecond (us).

For the range extension mode can be used PPDU structure 300 or other structure PPDU. PPDU structure for the range extension mode may include a SYNC field, CHANEST field, which serves as a fixed carrier (for example, 32-bit) sequence used for channel estimation, one or more fields, and the signaling MPDU.

The receiving station 150 performs acquisition for detection of PPDU, sent by transmitting station 110. The acquisition mode to extend the range of more promising than usual acquisition for 802.11b / g as a result of the following differences:

1. Low SNR / diversity. The required ratio of bit energy to the total noise (Eb / No) below, for example for 802.11b / g it is approximately 8 decibels (dB) whereas the required Eb / No for the range extension mode is approximately 3 dB. The required symbol energy ratio of the total noise level at the diversity order (Es / No / div) is approximately -6 dB at the lowest data rate of 250 kbit / s. It is desirable to achieve better detection of 90% of the threshold Es / No / div in dispersive channel conditions.

2. acquisition frequency. Receiver standard 802.11b / g typically performs differential demodulation. Receiver mode range expansion can perform coherent demodulation to improve efficiency. To obtain a good channel estimate used for coherent demodulation, the receiver may need to determine the frequency error between the oscillators at the transmitting and receiving stations. The frequency deviation of ± 20 ppm (ppm) at the receiving station is interpreted in the frequency deviation ± 232 kHz to 5.8 GHz, which may degrade the efficiency.

3. Channel estimation. The noise power in the channel estimate should be much lower than the total noise power in order to achieve good efficiency for coherent demodulation.

Figure 4 shows an embodiment of receive processor 160 at receiving station 150 in Figure 1. The CPU 160 samples the reception buffer 402 receives a stream of input samples from each of the modules 154a-154r receiver. The processor 404 performs acquisition acquisition for PPDU. The processor 404 first phase detecting unit 410 and an acquisition time receives the input samples from buffer 402, detects and determines the PPDU timing of each detected PPDU. The second phase detecting unit 420 and an acquisition frequency and also detects PPDU further estimates frequency error in the input samples. The third detection stage and channel estimation unit 430 also detects PPDU and further estimates the response of a radio channel between transmitting station 110 and receiving station 150. Units 410, 420 and 430 may perform processing based on the 128-bit sequence in the SYNC field of the PPDU preamble, as described below .

5 shows an embodiment of the first stage and the detection unit 410, acquisition time, which performs signal detection using time-domain correlation. Block 410 produces the complex-valued input samples at a sampling rate which is greater than or equal to the chip rate. For simplicity, the following description assumes that the input samples are provided at the transfer rate of the elementary signal. In the following description «m» is an index for receive antenna, «n» is an index for chip period, «k» is an index for frequency bin, and «i» is an index for the 128 bits in the fixed sequence sent in the SYNC. The symbol rate is the bit rate for the pilot sent in the SYNC field. Coherent amount refers to the amount of complex values ​​and incoherent sum refers to the sum of the actual measurements (for example, the value).

At block 410, the correlators 510a-510r receive the input samples delayed by modules 154a-154r receiver respectively. The delay correlator 510a for antenna 1 (or m = 1) despreading unit 512a decodes by Barker despreading input samples with the 11 signal Barker sequence and provides despread symbols at the chip rate. For each period, n chip device 512a despreading by Barker multiplies 11 input samples for chip period n to n-10 to 11 chips of the Barker sequence, adds the multiplication results and provides despread symbols xm (n) for that chip period . Apparatus 512a by Barker despreading correlation is performed by a tunable reference signal Barker sequence with the input samples to obtain a despread symbol for each chip period (instead of each symbol period) and provides despread symbols symbol buffer 514a and a delay multiplier 520a.

Delay multiplier 520a generates 1-symbol and 2-symbol delayed product of the despread symbols. The multiplier 520a delayed despread symbols are provided to two series-connected blocks 522a and 522b delays, each delay unit provides a delay of one symbol period Ts, which is equal to 11 chip periods, or Ts = 11 · Tc. Blocks 524a and 524b provide a complex conjugate despread symbols from the blocks 522a and 522b delay respectively. Multiplier 526a multiplies the despread symbols for each chip period n by the output unit 524a and provides a 1-symbol product y1, m (n) with a delay for that chip period. Similarly, multiplier 526b multiplies the despread symbols for each chip period n by the output unit 524b and provides a 2-symbol product y2, m (n) with a delay for that chip period.

Delay correlator for each remaining antenna processes the input samples for that antenna in the manner described above for antenna 1. Each delay correlator provides 1-symbol product y1, m (n) with a delay of 2-character pieces y2, m (n) for delay associated antenna m. For each chip period n, a summer 528a coherently sums the product y1, m (n) for m = 1, ..., R R from all correlators 510a-510r and provides a product of the latency y1 (n) for that chip period. For each chip period n, an adder 528b adds the product y2, m (n) for m = 1, ..., R on all correlators 510a-510r and provides a product of the latency y2 (n) for that chip period. Compositions y1 (n) and y2 (n) may be expressed as:

, Ur. (1a) of Ur. (1b)

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Product 1-symbol y1, m (n) indicates a delay of the phase difference between two despread symbols xm (n) and xm (n-Ts), which are separated by one symbol period for antenna m. 2-symbol product y2, m (n) indicates a delay of the phase difference between two despread symbols xm (n) and xm (n-2Ts), which are separated by two symbol periods for antenna m. Figure 5 shows the use of 1-symbol and 2-symbol delayed products for signal detection. Generally, for detecting the signal can be used for any number of pieces of different delays (e.g., 1, 2, 3 symbol periods, and so on). The use of works for large delays can improve the SNR and detection performance. However, since frequency offset causes phase rotation in the input samples, the maximum delay may be limited by frequency drift. The delay also affects the complexity of differential correlators 530a and 530b. For example, there are 127 multiply and summation for delaying one symbol period, 126 multiply and summation to delays in two symbol periods, etc.

Differential correlators 530a and 530b receive product y1 (n) and y2 (n), respectively. In the differential correlator 530a works y1 (n) provides a sequence of alternating elements 532a and 534a delays. Each element 532a delays provides a delay of one chip period, each element 534a delays provides a delay of 10 chip period, each pair of adjacent elements 532a and 534a delays provides a delay of 11 chip period (which is equal to one symbol period), and the entire sequence elements 532a and 534a provides a delay of delay approximately 126 symbol periods. A group of 127 adders 536a is connected to the 127 delay elements 532a. Each adder 536a sums the input and output of an associated delay element 532a and provides an output signal y1 (n-11 · i) · y1 (n-11 · i-1) where i {0, ..., 126}. A group of 127 multipliers 538a is connected to a group of 127 adders 536a and also receives the 1-symbol differential sequence containing 127 known values. This sequence is formed by the works of the first bit-sequence d0 - d126 to the second sequence of d1-d127, where d0-d127 are 128 bits fixed sequence (or pilot bits) used for field SYNC. Since the pilot bits are valid values ​​for i {0, ..., 126}. Each multiplier 538a multiplies the output of the associated adder 536a to didi + 1. For each chip period n, an adder 540a adds the outputs from all 127 multipliers 538a and provides a result c1 (n) correlation for that chip period.

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The differential correlator 530b is similar to the differential correlator 530a. Compositions y2 (n) provides a sequence of alternating elements 532b and 534b delays which provide a delay of approximately 125 symbol periods. A group of 126 adders 536b is connected to the 126 delay elements 532b. Each adder 536b sums the input and output of an associated delay element 532b and provides an output signal y2 (n-11 · i) · y2 (n-11 · i-1) where i {0, ..., 125}. A group of 126 multipliers 538b is connected with a group of adders 126 and 536b also receives a differential 2-character sequence containing 126 known values. This sequence is formed by bit-product sequence d0-d125 with the sequence d2-d127. Each multiplier 538b multiplies the output of the adder 536b associated to didi + 2. For each chip period n, an adder 540b adds the outputs from all 126 multipliers 538b and provides a result c2 (k) correlation for that chip period.

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Differential correlator 530a performs correlation between the 1-character pieces y1 (n) from the delayed 1-symbol differential sequence. Differential correlator 530b performs correlation between the 2-character products y2 (n) with a delay of 2-symbol differential sequence. 5A embodiment assumes that the radio channel has a delay spread (i.e., dispersion, or contamination) from a small number of chips. The adders 536a and 536b are used for energy storage in this delay spread. Energy can also become heated in more chips for a larger delay spread or can be skipped if the radio has a zero or a very small delay spread (eg, strict path radio waves propagating in the line of sight).

Each differential correlator 530 provides a correlation result for each chip period. Phases results c2 (n) the correlation of the differential correlator 530b may not coincide with the phases of the corresponding results c1 (n) the correlation of the differential correlator 530a. The multiplier 542 multiplies each result c2 (n) the correlation of the differential correlator 530b to the complex vector for L different prospective phase and provides set of L rotated by phases of correlation results. For example, the estimated phases may be {0, 90 °, 180 °, -90 °} for L = 4, {0, 60 °, -60 °} for L = 3, etc. L prospective phase may be selected to cover a range of possible relative phases. For example, the maximum frequency offset can be 232 kHz frequency deviation of ± 20 ppm, and 5.8 GHz carrier frequency. The maximum phase difference between the 1 and 2-character character-delayed correlation is ± 232 kHz multiplied by 1 ms, which is approximately 90 degrees. Hence, if using the estimated phase of 0, 60 ° and -60 °, then at least one of the estimated phase is within 30 °. If the phase difference is greater (for example, through the use of a greater delay or more frequency drift), the estimated phase should cover a greater range, up to a full ± 180 °.

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Multiplier 542 rotates c2 (n) at the different phases. For each period, n chip adder 544 coherently adds the result c1 (n) correlation from adder 540a with each of the L corresponding rotated by phases of correlation results from multiplier 542 and provides L combined results zp (n) correlation for p = 1, ..., L . If K differential correlators are used for K different delays, where K> 1, then one differential correlator may be used as the reference (with no phase shift). Then one combined correlation result is obtained for each hypothesis corresponding to a specific phase for each of the K-1 remaining differential correlators. For example, if K = 3, then one combined correlation result is obtained for each hypothesis corresponding to a different pair of anticipated phases for two differential correlators. For LK-1 possible assumptions turn out up to 1 LK-combined correlation results. For each period, n chip unit 546 computes the squared magnitude of each of the L combined correlation results (for K = 2), determines the largest value of the square among the L values ​​of the quantities in square and provides this largest value Z (n) of magnitude squared . For each chip period n signal detector 548 compares the largest value Z (n) of magnitude squared to a predetermined threshold value Zth and announces the presence PPDU, if Z (n) exceeds the threshold, or Z (n)> Zth. Detector 548 continues to monitor the signal values ​​of the magnitudes squared for the search of the maximum value and provides the chip period for this maximum value as the initial synchronization tau for the detected PPDU.

Alternatively, the results of c1 (n) and c2 (n) correlation for each chip period may be non-coherently combined. This can be achieved by calculating the value c1 (n) in the square calculation value c2 (n) and the square of the summation of the two squared magnitudes to obtain Z (n). The threshold Zth may be set to different values ​​depending on how the output Z (n).

The threshold Zth, is used for phase detection can be an adaptive threshold that varies, e.g., with the received energy Erx for the 128-bit SYNC field. For example, the threshold Zth may be set equal to the received energy Erx, multiplied by a scaling factor S1, or Zth = Erx · S1. Use of normalized received energy for signal detection results in similar detection performance for a wide range of received signal levels. Computer modeling shows that the probability of detection of 90% and a false alarm rate of less than 1% can be achieved for a 2 equal uncorrelated Rayleigh channel at a total SNR of -3 dB using S1 = 22. The probability of detection refers to the credibility of the ad unmistakable presence of PPDU, when PPDU is sent. False alarm rate refers to the credibility of having a false ads PPDU, when nothing is sent. A compromise between the probability of detection and false alarm rate can be achieved by selecting a suitable value for the scale factor S1.

6 shows a second embodiment of the phase detection unit 420 and the acquisition frequency, which performs signal detection using frequency-domain processing. For this embodiment, unit 420 includes R units 610a-610r frequency offset estimates for the R receive antennas. Each frequency offset estimation unit detects the energy in different frequency bins to determine the frequency offset in the input samples from an associated antenna.

For receive antenna 1 (m = 1) symbol buffer 516a provides N despread symbols that are spaced 11 chip periods (or one symbol period) starting at the initial timing tau, provided by block 410 acquisition time. The first despread symbols, thereby time-aligned with the best guess of the phase synchronization acquisition time. In general, N may be any integer number being a power of two and does not exceed 128, for example N may be 32, 64 or 128. In block 610a estimates the frequency offset group of N multipliers 612 receives the N despread symbols from symbol buffer 514a and N corresponding pilot bits in the 128-bit sequence. Each multiplier 612 multiplies the despread symbols at its pilot bit to remove the modulation from this despread symbols. Block 620 N-point fast Fourier transform (FFT) receives the N outputs from N multipliers 612, performs an N-point FFT on these N outputs, and provides N frequency-domain values ​​for N frequency bins. Groups of N units 622 receives the N frequency-domain values ​​from FFT unit 620. Each unit 622 computes the squared magnitude of its frequency domain value and provides the detected energy for a corresponding element k frequency resolution.

After removing the modulation with multipliers 612 via N outputs from these multipliers may have a periodic component. This periodic component is caused by frequency drift in the oscillator at receiving station 150, which results in that the received signal is frequency downconverted exactly to DC. FFT unit 620 provides N spectral sensitivity of the output signals from the multipliers 612. Element frequency bin k with the largest detected energy indicates the frequency offset for the input samples from antenna m.

Frequency offset estimation unit for each remaining receive antenna processes the despread symbols for that antenna in the manner described for antenna 1. A group of N adders 632 receives R sets of N detected energies from R units 610a-610r frequency offset estimates for the R receive antennas. Each adder 632 adds the detected energies from all R units 610a-610r estimates a frequency offset for the associated element k frequency resolution and provides total detected energy E (k) for that frequency bin. The selector 634 selects the largest total detected energy Emax (k) among the N total detected energies for the N frequency bins. The detector 636 signals compares the largest total detected energy Emax (k) with predetermined threshold Eth, declares signal detection if Emax (k) greater than the threshold value Eth, and provides the frequency bin with the largest total detected energy as intended deviations kos frequency . The threshold Eth may be set to, e.g., the received energy Erx for the 128-bit SYNC field, multiplied by the scaling factor S2, or Erx = Em · S2.

6A embodiment uses an N-point FFT, where N≤128. If N = 64, that is the size of FFT, commonly used for 802.11b and 802.11g standards for OFDM, then the spacing between adjacent frequency bins is equal to 15.625 kHz symbol rate 1 Msps and inaccuracy in the estimate of the frequency offset is equal to half the distance between the bins or 7.812 kHz. This inaccuracy can be reduced by performing interpolation and / or using a larger 128-point FFT.

Processing gain for coherent accumulation by FFT is approximately 18 dB for N = 64. The worst loss of the coherent accumulation - about 4 dB, which occurs when the actual frequency offset is exactly between the two frequency bins. The minimum total combined SNR almost 14 dB can be achieved for N = 64. Most of the losses coherent accumulation may be reduced by adding energy to the detected pairs of adjacent frequency bins (eg, similar to the summation, the implementation of the adders 536a and 536b in Figure 5) before selecting the most common energy detection. The summation of the detected energy to adjacent pairs of frequency bins increases the probability of the price of a small increase in the incidence of false alarms. The probability of detection is better SNR 90%, equal to -7 dB and better than 99.9% when SNR, of -4 dB may be achieved using a threshold value S2 = 8. The probability of false alarm is less than 0.5% for the second detection step, resulting in a total false alarm rate is 5 × 10-5 for the first and second stages of detection.

Multipath can worsen the probability of detection because all the energy is not used in the second stage of detection (as a result of FFT, operating at a distance between the characters instead of the distance between the chips). In an embodiment, improved efficiency can be achieved for the second detection stage by performing a 128-point FFT, and hence integrating over the entire 128-bit sequence for the SYNC field. In another embodiment, one 64-point FFT may be performed for the first half of the 128-bit sequence as described above, another 64-point FFT may be performed for the second half of the 128-bit sequence and the detected energies for the two FFT can be incoherently summed by adders 632.

In another embodiment frequency offset estimation input samples are correlated with the known 128-bit sequence for different estimated frequency drift. For each candidate frequency offset input samples are rotated by the frequency offset, rotated sample correlated with the 128-bit sequence correlation result is compared with a threshold value again and announced the detection signal if the correlation result exceeds the threshold. Correlation may be performed in the time domain using a filter apparatus finite impulse response (FIR) or in the frequency domain using FFT-multiply operation-IFFT. Evaluation is determined by the frequency drift of hypothesized frequency errors, which leads to the largest correlation result exceeding the threshold.

In yet another embodiment frequency offset estimation input samples are first encoded with despreading to obtain despread symbols at chip rate, as shown in Figure 5. Despread symbols are then multiplied by respective ones of the pilot signal to remove the pilot modulation. The resultant symbols are used to generate 1-symbol and 2-symbol delayed products, for example, using delay multiplier 520a in Figure 5. Compositions with a delay for each delay are processed to generate a complex value for that delay. For each delay d, where d = {1, 2}, d-symbol delayed product with a given group of 10 series-connected delay elements separated chips (e.g., similar to delay elements 722 in Figure 7) to obtain d-symbol works with a delay of 11 chips of different intervals. d-symbol delayed product for each chip interval coherently summed over SYNC field (e.g., using switches 724 and accumulators 730 in Figure 7). 11 summarizes the results for the 11 slots chips can be combined (for example, using a weighted summation of the differential signal on each channel) to form a complex value Vd for the delay d. The phase difference between the complex values ​​V1 and V2 for 1-symbol and 2-symbol delays may be computed and used to derive the frequency offset. R receive antennas may be combined in various ways, such product may be combined with a delay by the antennas, as shown in Figure 5, the complex values ​​for different antennas may be combined for each delay d, and so on More than two delays and / or large delay might also be used for the frequency analysis. The large delay results in a larger phase difference, which provides better resolution for the frequency offset. However, a large delay may cause errors such as phase shift greater than 180 ° can be interpreted as a negative shift of less than 180 °. For a given number of delays and a given maximum frequency offset to optimize resolution without errors can be selected plurality of delays.

Regardless of the technique used for frequency analysis, the estimated departure kos from frequency unit 420 acquisition frequency typically contains residual frequency error. To estimate this residual frequency error, a first 11-tap channel estimate may be derived based on the first 64 bits of the SYNC (e.g. as described below), the second 11-tap channel estimate may be derived based on the last 64 bits of the SYNC, with both channel estimates output from kos excluded departure frequency. On the basis of product removal may be calculated second channel estimation and the complex conjugate of the first channel estimate. 11 resultant products may be coherently summed to obtain the phase difference between the two channel estimates. Comparing a threshold value may be performed on (1) each channel tap prior to computing the product and / or (2) each product prior to summing the products. Comparing a threshold removes channel taps with low energy below a predetermined threshold value. The residual frequency error may be estimated based on the phase difference between the two channel estimates and may be provided to filter 452 and / or frequency correction unit 454 and used to adjust the timing and / or frequency of the input samples (not shown in Figure 4). This update care kos frequency estimate of the residual frequency error can improve the efficiency of demodulation.

7 shows an embodiment of the third detection stage and channel estimation unit 430, which performs signal detection using time-domain processing. For this embodiment, unit 430 includes R units 710a-710r channel estimates for the R receive antennas. Each channel estimator may derive a channel impulse response estimate containing channel taps that are located at intervals of the sampling rate. For example, can be prepared up to 11 channel taps separated by one chip, if despread symbols are obtained at the transmission rate of the chip can be obtained up to 22 channel taps, separated by a half chip, if despread symbols are obtained at double the transfer rate of the elementary signal (or chip x 2), etc. For figure 7 embodiment, each channel estimator 11 outputs the branch channel impulse response estimate at chip interval for the associated antenna.

The channel estimation unit 710a for antenna 1 (m = 1) multiplier 712 multiplies the despread symbols for antenna m for complex vector Removal kos deviation frequency determination unit 420 according to an acquisition frequency. Multiplier 712 provides frequency-corrected symbols at the chip rate of the group of 10 series-connected delay elements 722. Each delay element 722 provides a delay of one chip period. A group of switches 11 connected to the output 724 of the multiplier 712 and the output 722 of delay element 10. The switches 724 are utilized for one chip period in each symbol period and provide 11 frequency-corrected symbols for that symbol period. The control signal for switches 724 is determined by the initial timing tau from block 410, acquisition time, and is formed such that the symbol with the frequency correction of the fifth element 722 delays (which for the central outlet 11 bypass channel impulse response estimate) corresponds best guess synchronization afforded step acquisition time.

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Channel estimation is performed for a predetermined time interval W, which is selected to achieve adequate SNR or quality for the channel estimates. Time interval W may be M symbol periods long, where M may be, e.g., M> 31. A group of 11 multipliers 726 receives the pilot bit di signal for each symbol period in which channel estimation is performed. Each multiplier 726 multiplies the output of the switch 724 corresponding to the bit di pilot removes the modulation by the pilot bit, and provides its output to a corresponding drive 730. The group of 11 disk drives 730 is reset at the beginning of the channel estimation. Each accumulator 730 coherently adds the output of multiplier 726 during a time interval of 11 W. The group of switches 732 is connected to a group of 11 accumulators 730. Switches 732 are utilized at the end of the time interval W and provide 11 channel taps hm, hm-0, 10 channel impulse response estimate for antenna m. This channel estimate may be used for data demodulation, as described hereinafter. A group of 11 units 734 receives the 11 channel taps, and each unit 734 computes the squared magnitude of its channel tap. The adder 736 adds the outputs from all 11 units 734 and provides the total energy for all channel taps for antenna m. Alternatively, the output of each block 734 may be compared with a threshold value and the adder 736 may sum only the outputs that exceed the threshold. The threshold value may be set to a predetermined percentage of the total energy for all 11 channel taps.

The channel estimator for each remaining receive antenna processes the despread symbols for that antenna in the manner described above for antenna 1. A summer 738 sums the common energy for all R units 710a-710r channel estimation and provides the total energy H for all R antennas. Signal detector 740 compares the total energy H and a predetermined threshold value Hth and declares signal detection if H is greater than the threshold value Hth. Hth threshold can be set to, for example, received energy Erx for 128-bit field SYNC, multiplied by a scaling factor S3, or Hth = Erx · S3.

The probability of detecting more than 99% and a false alarm rate of less than 10-5 at SNR can be achieved at -4 dB, using a threshold value S3 = 14. The total false alarm rate of less than 10-9 can be achieved with all three stages of discovery. This assumes that the three detection stages are uncorrelated because three phases are used for different types of signal processing.

For the above-described embodiments of signal detection can be achieved based on the correlation in the time domain (Figure 5), processing in the frequency domain (Figure 6) and processing in the time domain (Figure 7). All three types of signal processing can be used to provide good detection performance (e.g., high probability of detection and low false alarm rate) for poor channel conditions (e.g., low SNR). It may also be any combination of signal processing to detect the signal.

5, 6 and 7 show specific embodiments of signal detection, acquisition time, acquisition frequency and channel estimation that may be performed in other manners. For example, signal detection and acquisition time can only be performed using one-bit differential correlator 530a is delayed. Also a combination of techniques can be used. For example, the input samples may be rotated by a small amount (e.g., two) the expected frequency drift. The residual frequency error is smaller for one of the estimated frequency offset so that the coding on the Barker despreading (or coherent accumulation) may be performed over a longer duration (e.g., 22 elementary signal). Despread symbols from the longer coherent accumulation may be provided to the delay multiplier and differential correlator shown in Figure 5. Detection of the signal can be achieved for less action SNR, as the coherent integration is performed over a longer duration.

5, 6 and 7 show a typical signal processing units 410, 420 and 430 respectively. The processing may be implemented in various ways using hardware, software and / or firmware. For example, blocks 410, 420 and 430 may be implemented by dedicated hardware or may share hardware. A digital signal processor (DSP) and / or any other type of processor may perform the processing for units 410, 420 and 430 process the time division multiplexing. Sample buffer 402, symbol buffer 514 and / or some other buffer may be used to buffer data for processing.

Returning to Figure 4, after the PPDU is detected, a determination is made whether the received PPDU intended for 802.11b / g or the range extension mode, e.g., based on the PLCP preamble and / or PLCP header. DSSS receive processor 440 processes a received PPDU, if it is for 802.11b / g. DSSS receive processor 450 processes a received PPDU, if it is intended for the range extension mode.

DSSS receive processor 440 performs spectral despreading encoding and demodulation for 802.11b / g. The processor 440 Rake receiver / equalizer 442 encodes despreading input samples with the Barker sequence, corrects the despread symbols based on the channel estimates, combines signal components for R receive antennas, and provides detected symbols. A demodulator (Demod) 444 converts the detected symbols based on a modulation scheme (e.g., BPSK or QPSK), used for transmission, performs differential decoding, and provides output bits, which are estimates of the data bits sent by transmitting station 110.

DSSS receive processor 450 performs spectral despreading coding, demodulation and FEC decoding for the range extension mode. The processor 450 filter 452 filters the input samples for each receive antenna to remove out of band noise and interference. Filter 452 may also produce a resampled input samples for each receive antenna (1) for converting the sampling frequency of the sampling frequency in the chip transmission rate and / or (2) for offset compensation on the received PPDU synchronization. To 802.11g input samples typically have a rate several times higher than the chip rate of 20 MHz OFDM. In this case, the filter 452 may perform resampling from multiple times 20 MHz to either 11 MHz for a Rake receiver, the divided chips, or 22 MHz for a Rake receiver, the divided halves of the chips. Oscillator signal (LO) used for downconversion, and the clock signal used to generate the input samples are typically obtained from the same reference oscillator. In this case, the frequency error in the clock signal may be determined based on the deviation kos frequency determination unit 420 acquisition frequency signal LO. It may then be determined care synchronization input samples based on the departure frequency kos and the carrier frequency. Filter 452 may perform periodic adjustment ± Tadj based care frequency kos, where Tadj may be a part of the sample period.

In an embodiment, filter 452 is implemented as a polyphase filter composed of a block of N base filters, where N> 1. Each base filter is associated with a particular set of coefficients for a particular time offset. In a typical design of the filter 452 includes 11 filters, FIR, where each FIR filter has four outlet. To create each subsequent output sample can be used for another base filter. If the frequency offset is zero, then the 11 base filters may be cycled passed in unchanged order, wherein each 11th sample is formed from the same base filter. To compensate for the withdrawal of synchronization sets the base filter may be passed, but instead used the following basic filter, or one and the same basic filter can be used for two consecutive output samples. Adjusting synchronization may thus be achieved by selecting an appropriate base filter in use.

Block 454 removes the equalization frequency drift in the time-adjusted samples for each receive antenna. Block 454 can be implemented with a generator numerically controlled (NCO) and a complex multiplier, similar to multiplier 712 in Figure 7. NCO generates a vector rotating at the frequency kos care provided by block 420 acquisition frequency. A multiplier multiplies the time adjusted samples for each receive antenna and provides the vector to the sample frequency correction for that antenna.

Rake receiver / despreader unit 456 performs coherent detection with sampling frequency correction with the channel estimates and combines signal components at the receiving antennas and multipath. Rake receiver 456 multiplies the frequency-corrected samples for each receive antenna 11 channel taps provided by channel estimation unit 430 for that antenna. Rake receiver / despreader unit 456 also performs coding despreading with the Barker sequence, accumulates the despread symbols for all R antennas, and provides detected symbols. In an embodiment, channel estimates for the R receive antennas are derived once based on the SYNC field and possibly other fields of the received PPDU, and these channel estimates are used for the entire received PPDU. For this embodiment, a coherent RAKE receiver 456 is not tracking the received PPDU by radio. In another embodiment, the channel estimates are updated using hard decisions obtained from the detected symbols and / or decisions obtained by re-encoding and re-converting the output of FEC decoder 464.

Block 458 removes the phase correction phase error in the detected symbols. The phase error due to the residual frequency deviation, which is derived from the receiver 160 without a phase-locked loop.

8 shows a block diagram of an embodiment of phase correction unit 458. In block 458 a multiplier 812 rotates each detected symbol from rake receiver 456 to the coherent phase reference θref (t) and provides a corresponding phase-corrected symbol. Block 814 generates a hard decision (e.g., +1 or -1) for each symbol with a phase correction. The multiplier 816 multiplies each detected symbol on the corresponding hard decision and provides work for this detected symbol. Block 818 calculates the moving average of the works from the multiplier 816 and provides the average work. For each symbol period, unit 820 normalizes and conjugates the averaged product and provides the phase reference θref (t) for the detected symbol for that symbol period t. Reference phase thus can be outputted by determining average values ​​of the interval detected symbols. Determination of average values ​​may be intended to explain the fact that the phase information from the known pilot symbols in the SYNC field is more reliable but may not be current whereas the phase information for the detected symbols may not be reliable but is more current .

Returning to Figure 4, a demodulator 460 performs coherent demodulation of the symbols with the phase correction. For BPSK demodulator 460 may provide a real part of each symbol with a phase correction as a demodulated symbol, which is an estimate of a data symbol sent by transmitting station 110. For other modulation schemes, demodulator 460 may provide a modulation symbol that is most likely to be sent for each symbol with a phase correction as a demodulated symbol.

The deinterleaver 462 deinterleaves the demodulated symbols in a manner complementary to the interleaving performed by interleaver 256 in Figure 2. FEC decoder 464 decodes the deinterleaved symbols in a manner complementary to the encoding performed by encoder 252 FEC in Figure 2 and provides output data. The multiplexer 470 receives the output from processors 440 and 450 receive DSSS, provides the output data from DSSS receive processor 440, if the received PPDU is for 802.11b / g, and provides the output data from DSSS receive processor 450, if the received PPDU is for the range extension mode .

4 shows a specific embodiment of receive processor 160 for 802.11b / g and the range extension mode. Processor 160 may also be implemented with other designs, and this is within the scope of the invention. Generally, treatment DSSS receive processor 440 is complementary to the processing DSSS transmit processor 240 at transmitting station 110 and the processing DSSS reception processor 450 is complementary to the processing by the processor 250 transmitting DSSS. 4 shows a typical structure of processors 440 and 450 receive DSSS, which may include other and / or different processing units not shown in Figure 4.

9 shows a process 900 for performing signal detection for the first stage. Input samples is encoded by despreading code sequence to generate despread symbols, e.g., at chip rate (step 912). Formed product despread symbols for at least two different delays (block 914). Each product is generated based on the despread symbol and a complex conjugate of another despread symbol that is at least one symbol period earlier. For example, the 1-symbol delayed product and 2-symbol delayed product can be formed, as shown in Figure 5, with each 1-symbol delayed product, formed with two despread symbols that are separated by one symbol period, and each 2 symbol delayed product, formed with two despread symbols that are separated by two symbol periods.