Variable-speed serial decoder for code-division multiple access communication system

REFERENCE TO RELATED APPLICATIONS This application is related to copending patent application entitled "Method and apparatus for determining the transmission rate of data transmitted at a variable rate at the receiver", filed with Serial 08 / 079.196 18 June 1993, Butler (Butler), and al., and assigned to the present assignee. This application is incorporated here by reference.

BACKGROUND OF THE INVENTION 1. FIELD OF THE INVENTION The present invention relates generally to systems for decoding serial data streams in a noisy channel and, more specifically, to a convolutional code Viterbi decoder for sequential decoding at different, predetermined data rates.

2. Description of the Related Art In the art of digital communication is well known that data may be transmitted sequentially either continuous manner or in cycles of a constant time duration T, each cycle comprises a fixed number of bits N, the product of which is limited and transmission speed of the serial cycle time T. However, in certain communication systems need to transmit fewer than N data during selected cycles. One such system is a transmission system with multiple access, code division (CDMA), which uses a spread spectrum technique for direct sequence modulating a carrier.

U.S. Patent 5103459 in the name of the present applicant S.Gilhousen Klein et al. Discloses such a CDMA system for use in cellular communications. Patent 5103459 mentioned as references, are entirely attributable to the art. In a CDMA system, system capacity is limited overall interference within the transmitted frequency band. Common interference signals consist of other users, which consist primarily of vocoder data (speech, digitized). To reduce the user interference levels as much as possible to a greater extent in a CDMA system described Gilhousen et al., Used vocoder data transmitted with a variable speed and adapted to transmit data in cycles with a fixed duration in time.

In some rate reduction of vocoder data provided some margin in the cycle data to support the transfer of data through the entire cycle. Thus, for the cycle in which reduced overall data rate, the number of repeated characters of input data is less than N, which you must fill in a cycle of N symbols. Although repetition of data transmitted at a lower speed, causing the same interference levels as the full data rate at the same transmission power, but the supplementary information in the loop reduces the transmit power in accordance with an equivalent "information power" or energy per symbol. This technique reduces interference levels, thereby increasing the system capacity as far allow reserves vocoder.

Alternatively, the data repetition at lower output data can be transmitted at a rate of one time within one cycle without reducing transmission power. This technique allows full power during a separation cycle and does not perform transmission during the unused portion of the cycle. The data block to be transmitted in a loop can simply be placed in the beginning of the cycle or at any other predetermined position in the cycle. However, in a multi-user CDMA system requires a complicated procedure of placing blocks to evenly distribute the interference from many other users throughout the cycle. Unnecessary overlapped data transmission by many users is unacceptable increases the noise level of the system over the optimal average.

In US Patent Application Serial No. 07 / 846.312, filed March 5, 1992 and entitled "randomizer data packet" to the Gilhousen et al., Owned by the present applicant describes the complicated procedure of location unit to ensure minimum levels of noise within the full cycle, and this patent application is incorporated herein by reference, fully related to the art.

Example CDMA system can be understood after considering "PROPOSED EIA / TIA Interim Standard: Compatibility Standard STATION BASED ON BROADBAND DVUMODNOY mobile stations, the spread spectrum digital cellular system" Qualcomm, Inc., San Diego, California, April 21, 1992. This system CDMA standard defines five basic modes of data communication channel for traffic in both forward and reverse direction. There are three mode of direct communication and feedback are two modes. Depending on the particular data channel mode determined by one of two different convolutional coding algorithms. Two of these modes, continuous mode, and three of these are batch mode, where serial data organized in fixed intervals cycle. Three modes operate at only one of several predetermined data rates and two modes operate from frame to frame in one of four different predetermined speeds.

This variety of data rates and channel modes creates a need for any single decoding apparatus. The problem becomes more complicated due to the fact that the sequential coding in the channel with a wide range in real time. That is, the received signal must be detected on, recomposed and decoded in real time. There is space cycle suitable for the transmission of information about the original data transmission rate vocoder. There is a very small possibility of considering the received signal for several possible data rates to determine which of the specific speeds to be decoded for each new cycle. In addition, it is desirable to use the same decoding apparatus in all system channel modes to avoid rapid increases the number of components. The CDMA system described in the aforementioned patent in the name of Gilhousen et al. Used the orthogonal pseudorandom noise (PN) coding, time division multiplexing, binary phase modulation (VRSK) with orthogonal covering of each BPSK symbol while expanding covered symbols by PSK quaternary signals (QRSK) and convolutional coding for error correction. Each of these many coding techniques requires a certain effort for decoding on the receiving side of each channel mode. Therefore, there is a huge competition in the possession of resources for real-time sequential decoding convolution-encoded symbols transmitted for error correction.

Decoding method for convolutional codes are well known in the art and include the Viterbi algorithm for error correction, designed by AJ Viterbi ("Error Bounds for Convolutional Codes and an asymptotically optimal coding algorithm", IEE Trans. Ihform. Theory, Vol. 11-13, 2, pp. 260-269, April 1967) and reviewed by professionals, such as GD Forney, Jr. ("The Viterbi Algorithm", Proc. Of the IEEE, Vol.16, pp. 268-278, 1973) and JA Heller et al. ("Viterbi Decoding for Satellite and Space Communication", IEEE trans. Sommun. Technol., Vol . 11-19, 5, pp. 835-348, October 1971).

Businesses have improved the Viterbi algorithm in response to various specific requirements. For example, Hir osuke Yamamoto et al. ("Viterbi decoding algorithm for convolutional codes with repeated request" IEEE Trans. Inform., Theory, Vol. 11-26, 5, pp. 540-547, September 1980) examines the Viterbi decoding algorithm a quality metric for repeat request. Their system offers the same performance when a receiver can use a feedback channel to request retransmission as in the case of longer convolutional code constraint length without feedback. Yamamoto et al. Quality single bit added to the output of the decoder, which indicates the "quality cycle." If it is bad, then the retransmission is requested. They have shown that the reliability of the function of their algorithm is asymptotically twice better than the well-known Viterbi algorithm without repeat request.

Similarly, N. Seshadri et al. ("Generalized Viterbi algorithm for error detection by means of Convolutional Codes", GLOBECOM 89 Dallas, Texas, pp. 1534-1538, Nov. 1989) present two generalized Viterbi algorithm useful for using speech encoded in cycles of fixed duration. The high degree of mutual influence of adjacent cycles speech allows a useful estimate of the content of the cycle on the basis of adjacent loops in a situation where the contents of this cycle has unacceptable error levels. Seshadri et al. Have shown that this can be very sturdy intermenstrual redundancy by adding parity bits to the speech data for error detection by means of an external high-cyclic code block. Longer cycle is then encoded by an inner convolutional code and the entire block is then modulated and transmitted over a noisy channel. The inner generalized Viterbi decoder transmits a predetermined number of candidates for an encoded cycle, only one of which should have the correct parity information. If none of them has the correct parity information and if the information bits represent the cycle of sampled speech, it can be intracyclic re-evaluation, or if the available feedback, performed Automatic Repeat Request. If there is a correct choice among a predetermined number of candidates, a retransmission can be avoided.

Unfortunately, none of the above description is not provided a method of decoding in real time for transmitting a sequence of cycles having one of predetermined data transmission rates that may vary from frame to frame without transmission of rate information. Appropriate remaining unresolved problems and deficiencies apparent relevant art are resolved in this invention are described below.

BRIEF DESCRIPTION OF THE INVENTION The present invention solves the above problem by providing a Serial Viterbi Decoder (SVD), a special buffer having input and output device is formed as a superhigh degree of integration (VLSI). The Viterbi procedure is used to decode the stream synchronized and quantized code symbol in a continuous mode. It provides multiple output quality metrics ("error metrics") to determine the data rate. The preferred embodiment of the present invention, the SVD can decode the transmitted data at different speeds without providing information about the data rate.

The aim of this invention to provide automatic decoding of each frame at one of a plurality of predetermined data rates without transmission rate information. SVD of this invention performs this objective for each of a plurality of channel modes by making multiple ways to decode each frame at each of all possible predetermined data rates and by providing "error metrics" for determining the original data transmission rate. SVD advantage of the present invention is that it can be decode at an unknown data rate cycle of the plurality of predetermined data rates cycle provided that the convolution code is known and is known as a data packet mode (cyclic or continuous). Another advantage of the SVD of this invention is that obtained by several "error metrics" for all decoding cycles at each hypothetical predetermined data rate for use in obtaining the original data rate.

SVD of this invention provides one such error metric by recording the output stream of decoded data, comparing it with the input code symbol stream to estimate symbol error rate (SER) of the input stream. SVD of this invention may include other error metrics such as results of cyclic redundancy check (CRC), as well as a quality metric Yamamoto (YQM). SER metric estimates the error rate in the received code symbols. CRC results allow to detect faults in the original binary data. YQM indicates that estimated error conditions in the decoded frame exceed a predetermined threshold. SVD advantage of the present invention is that the receiver provides one or more of these "error metrics" as means for determining the original data rate without receiving rate information from the transmitter.

Another object of this invention to provide decoding in a single SVD device for all the necessary channel mode. SVD of this invention permits the use of a single VLSI device for both modes of the channel for both the forward and reverse CDMA communication system, the exemplary. For example, a preferred embodiment of this SVD provides high decoding performance that approaches the theoretical limit for rate 1/2 and 1/3 convolutional codes having a limited length 9, wherein code symbol data are processed in the data packets of N = 384 symbols (rate one • / 2) or N = 576 symbols (1/3). Packages cycles beginning and ending in any fixed state or a continuous code symbol stream of information can be decoded by SVD of this invention. For instance, in repeat mode CDMA channels operate so that each symbol is repeated as necessary to fill cycle and repeated symbols are accumulated into a single symbol in the SVD of this invention to reduce bit rate and power. In the data burst randomizer (DBR) and feedback CDMA transmitted only one symbol from each set of repeated symbols by using art arrangement dither cycle, which is described in the above patent application in the name of Gilhousen et al. Using the possibility of transmission rate selection of codes and modes repeat, SVD of this invention processes code symbol stream with any predetermined effective data rate in either repeat the message sent, or reverse DBR mode.

Another object of the present invention is to separate the internal decoding procedure from the external channel timing. SVD of this invention accomplishes this by providing a device for sending an interrupt to the channel microprocessor and by providing a buffer to isolate the microprocessor from the system timing cycle and to hold the decoded data and quality metric data. Besides SVD of this invention includes an input buffer that allows code symbols either to take in the SVD continuously at the channel symbol reception or transfer them to SVD as packets as packets cycles. Special input and output buffers allow the SVD of this invention to operate independently of external channel and microprocessor timing. A flexible microprocessor interface allows the SVD to use with different systems of microprocessors.

SVD of this invention includes five major elements as shown in Figure 5. Input Buffer (IB) stores more than one cycle of the data code symbol. In this lock mode allows SVD perform retransmission processing of data as many times as necessary to determine the actual data rate in repeat mode or DBR, used for that channel cycle. The Viterbi Decoder (VD) accepts soft decision code symbols from the IB and processes them in logic add-compare-select, well-known in the art. Results ACS process are stored in an internal path within the VD. Through the process of reverse unit using the memory the way back, it turns a single bit of data each set of code symbols after performing a reverse lookup in time through many words solutions. Each of these single data bits together with quality metrics such as the Yamamoto quality metric (YQM) are stored in the output buffer (OB), which is the third element of the SVD of this invention. In burst mode cycle, the code symbols are decoded for four different rates and the four final decoded data packets (including quality information) are stored in the OB and held for about half of the fixed cycle time to allow the microprocessor to carry out their reading. The fourth element is a Control Block (CB) that generates all internal timing signals necessary for the operation of the present invention, the SVD. These internal clock signals produced by clock generator CDMA system and by gating the clock signal external decoder. DVD of the present invention is started and controlled by the fifth element - microprocessor interface (MI), which is connected to the fourth CB element of this invention. The data can also be taken by the MI.

The above and other objects, features and advantages of the present invention will become more apparent upon consideration of the following description, appended claims and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present invention Referring now to the following detailed description of performances as described in the accompanying drawings, in which: FIG. 1 is a functional block diagram of the CDMA mobile receiver; FIG. 2 is a functional block diagram of a receiver board channel CDMA cell; FIG. 3, which comprises Figures 3A to 3E, a description of five CDMA channel types; 4 is a description of the setup parameters normal CDMA; 5 is a functional block diagram of a Viterbi Decoder (SVD) of the present invention; FIG. 6, which comprises Figures 6A-6B, illustrates the theoretical operation of a Viterbi decoder; FIG. 7 is a functional block diagram of the input buffer (1b) of the present invention; FIG. 8 shows how to select the symbols of the data burst randomizer (DBR) for the CDMA system; 9 is a functional block diagram of elements of a Viterbi decoder (VD) of the present invention; FIG. 10 is a functional block diagram of an output buffer (OB) of the present invention; FIG. 11 is a functional block diagram of the logic of quality metrics Yamamoto (YQM) of the present invention.

DESCRIPTION OF THE PREFERRED EXECUTION The problem of decoding the CDMA system to the description and review of the present invention is described in the context of an embodiment of a mobile CDMA system, which is described in the patent to the above mentioned authors: Gilhousen et al. However, it should be borne in mind that the present invention can be used for other types of systems communication such as private communications systems (PCS), wireless local area network, private branch exchange (PBX) or other useful communication systems. Furthermore, other systems employing other well known transmission modulation techniques such as multiple access with time division (TDMA), can also use the present invention. As described in the aforementioned patent in the name of authors: Gilhousen et al. In the exemplary embodiment, CDMA mobile communication systems imposes some requirements for decoding apparatus and procedures, these requirements still can not effectively meet the known technique a single decoder design. These requirements are given in abbreviated form for explanation.

FIG. 1 is a block diagram of a mobile receiver modem designed for CDMA systems. Serial Viterbi Decoder (SVD) 20 of this invention is shown in conjunction with the other elements of mobile modem 22. In operation, RF receiver 24 receives radio frequency signals and demodulated in the demodulator 26 with the participation of the analog processor 28 and under the control of the central processing unit (CPU) 30. The demodulated stream data re-compacted in apparatus TDM pulse signal 32 which generates a stream of successive symbols at the input 34. The synchronization signals SVD, timing and clock signals are transmitted to SVD 20 on the appropriate signal lines. SVD 20 is connected to the microprocessor bus 36 for communication with the vocoder 38, which reassembles the speech signals that have been decoded by SVD 20.

Figure 2 shows the same SVD 20 associated with the logic of the receiver modem channel card 40 on the side of the cell. CPU 42, the device time division pulse signal demodulators 44 and 46 from a functional point of view are similar to their respective portions of Figure 1. Just as in Figure 1, SVD 20 receives a stream of successive code symbols on decoder input 34 and transmits a stream of data in parallel microprocessor bus 36 for transfer to other elements (not shown) of logic 40.

For the CDMA system disclosed in the aforementioned patent authors Gilhouse et al., SVD 20 must operate in any of five basic channel modes to carry out all necessary data decoding both forward and reverse links. These modes are described in Figures 3A-3E. During direct communication with a mobile cell user uses three modes shown in FIGS. 3A-3C (sync, paging and traffic mode). Feedback from the mobile user unit uses two modes shown in FIGS. 3D-3E (access and traffic).

FIG. 3A describes sync channel modulation parameters direct connection of an exemplary example. Sync channel data are decoded from a channel that is convolutionally encoded at rate 1/2 way (constraint length K = 9) and each code symbol is repeated once. The data are transmitted at 4800 modulation symbols per second and SVD 20 receives a superframe containing 384 modulation symbols every 80 milliseconds for. Thus, SVD 20 can be aligned with a fixed rate of 1200 bit / s for that channel. Original information bits are encoded as a continuous stream without cyclic redundancy check code (CRC) at the frame boundaries. The equivalent bit rate is 1200 bit / s.

3B describes the parameters of the modulation of direct paging channel as an example. Paging channel encoded data from a channel that is convolutionally encoded at rate 1/2 way (K = 9) and each code symbol transmitted once, twice or four times, depending on the original bit data. The initial bit rate for that channel set and does not vary from cycle to cycle. Thus, SVD 20 can be aligned with a fixed bit rate of this channel. The data are transmitted at 19,200 symbols per second and SVD 20 receives a frame containing 384 modulation symbols every 20 milliseconds. The data is encoded in a continuous stream without CRC codes at frame boundaries.

3C shows the parameters of forward traffic channel modulation as an example. Traffic channel data are decoded from the forward link channel that is convolutionally encoded at rate 1/2 (K = 9) and each code symbol is transmitted up to nine times, depending on the original bit data rate selected for each cycle of the calling vocoder. The initial bit rate may vary from cycle to cycle under the control of the calling vocoder and SVD 20 must decode at all possible speeds for all cycles, since the given data rate can not be set. The data are transmitted at 19,200 modulation symbols per second (sym / s) and SVD 20 receives a new cycle of 384 modulation symbols every 20 milliseconds. These data are encoded as packets that begin and end in the zero state ("0" bits added at the end of each cycle before encoding) and a CRC code is expected at the end of each packet of 96 original bits and 192 original bits. No CRC code is expected for shorter (48 and 24 bit) packets because the lack of space makes the CRC quite expensive.

FIG. 3D parameters are the reverse traffic channel modulation as an example. Traffic channel data are decoded from the reverse link channel that is convolutionally encoded at rate 1/3 (K = 9). Each code symbol is repeated up to seven times (that generates the eight embodiment), but only one of the repeated code symbols are transmitted in a packet. Synchronization of the packet is determined by random number that is selected from the last few bits of the PN code for the preceding cycle. Code symbol repetition rate depends on the baud rate of the calling vocoder for each cycle. SVD 20 must simultaneously decode for all speeds and for each cycle as the original bit rate of binary data can be changed from cycle to cycle calling vocoder. Although SVD 20 does not know the original bit data rate for a particular cycle, but synchronization packet for each cycle of repeated symbols is performed based on the last few bits of the PN code from the previous cycle. The data are transmitted at 28,800 code symbols per second and SVD 20 receives a frame containing 576 potential code symbols of code in every 20 milliseconds. The data are encoded as packets that begin and end in the zero state as "0" bits added at the end of each packet. CRC code is expected at the end of each packet of 96 original bits and 192 original bits (just after the sequence "0" bits). Loops containing fewer than 96 original bits passed the CRC code to save space.

FIG. 3E presents exemplary access channel modulation parameters reverse link. These reverse link access channel are decoded from a channel that is convolutionally encoded at rate 1/3 (K = 9) and each code symbol is transmitted twice. The initial bit rate is fixed at 4800 bit / s and the SVD 20 for this channel adapted to operate at this single fixed rate. The data are transmitted at 28,800 code symbols per second and SVD 20 receives a frame containing 576 code symbols for each 20 milliseconds. The data are encoded as packets that begin and end with a "0" state (added "0" bits at the end of each packet) but no CRC code is provided.

SVD of this invention is suitable for any of the five examples described, the channel represented in Figure 3, because of its capability for continuous decoding speeds many possibilities switching from the continuous mode to a batch mode and switchable (1/2 and 1/3) convolutional velocity coding. Most importantly, SVD of this invention can decode the data channel as a forward and reverse traffic. This division of the forward and reverse channel traffic can be better appreciated after consideration of the above-mentioned patent authors Gilhousen et al. And the application for the invention.

4 is a table that summarizes all the functions of the control signals required for SVD of this invention in the case of each of the five channels, as discussed above with reference to the examples of Figure 3. Please note that the original bit rate channel of direct paging and sync channel recorded.

EXECUTION OF MONOLITHIC SVD Preferably, the SVD of this invention was made as a circuit with ultra-high degree of integration, (VLSI). 5 shows the five major elements of an embodiment example of SVD 20. The input buffer (IB) 48 stores 1.5 cycle data, thereby allowing multiple decoding paths for a single cycle, allowing later determine the proper repetition or data rate mode, data burst randomizer (DBR) for the cycle. The Viterbi Decoder (VD) 50 accepts the soft decision symbol from IB 48 on a 7-bit symbuf bus 52. These code symbols are processed by logic add-compare-select (ACS) and the results are stored as state metrics in internal memory (RAM). Solutions after ACS processing are stored in the internal memory pathways. The process of feedback circuit paths through this memory determines the single output data bits for each code symbol group after the reverse lookup time 64 levels words solutions to ensure that the path in question coincides with the most likely global path. These binary output data together with information about quality metric (QM) is stored in the output buffer (OB) 54 through the data line 56. After completion of the decoding by VD 50, OB 54 returns dekodirorovannye data bits for access by the microprocessor interface 58 via the bus decdata 60. In the batch mode, the code symbols are decoded at four different original bit data rates and the four resulting output data packets are stored in OB 54 together with the additional data Qm. This preparation provides the processor (not shown) about 10 milliseconds to read the data in OB 54. SVD 20 is triggered and controlled by the microprocessor interface 58 and the controller 62 which provide the necessary timing signals for SVD 20. The synchronization signals obtained from the signals of oscillator and gate signal decoder (not shown).

Viterbi decoding algorithm General theory of operation of the Viterbi decoder is well known in the art and can be evaluated after the call to one of the above links. Now, this theory will be briefly described to facilitate the assessment of the present invention.

Convolutional encoder converts a sequence of raw binary data (input bit stream) into a sequence of code symbols (the input symbol stream). For each input bit there are some output code symbols that are determined by this input bit and the previous (K-1) input bits, where K is limited to the length of the encoder. The number of code symbols created for each binary symbol is determined coding rate; that is, for example, two symbols for the rate 1/2 and three for rate 1/3 symbol. Each code symbol is generated by shift and implement an XOR operation on the input stream in accordance with a special polynomial code, such as code rate 1/2 G1, represented by the sequence x8 + x6 + x5 + x4 + 1 (octal value 05 618). The number of bits in the polynomial code is the same as the value of limited length, which is fixed at nine for the preferred embodiment of the present invention, the SVD. Actual codes (G0, G1) or (G0, G1, G2) are chosen based on simulation nonsystematic codes created for codes with superior properties in terms of errors in a mobile environment. The preferred convolutional codes used in the exemplary CDMA system, discussed above, have the following meanings for the forward link = 07 538 G0 and G1 = 05 618) and for the reverse link = 05 578 G0, G1 = G2 = 06 638 and 07 118. These convolutional codes provide a minimum free Hamming distance of 12 for the 1/2 coding rate and a minimum free Hamming distance equal to 18 for a coding rate of 1/3.

Viterbi decoding algorithm operates by determining the most likely decoding sequences for an input code symbol stream. First of all, calculate metrics states or the balance of the corresponding probabilities for each possible path. The most likely conversion for each state are stored tracks for all the states and then the decoder or viewing backward chain forms in time through the most likely sequence to choose each output bit. The main steps of this process are the establishment of the branch metric, the creation of the state metrics and determining the way back link. The characteristics of the decoder for a particular constraint length and speed are determined by three parameters: the step size and the number of quantization levels of the input code symbols, state metric normalization procedure and the depth of the current reverse link memory pathways.

Branch metric prices are functions that correspond to the logarithm of the probabilities that during converting each possible input bit conversion code symbols of the soft decision. Information about the sign and magnitude of soft decisions is scaled and combined to produce each branch metric. For rate 1/2, there are four possible metrics. For rate 1/3, there are eight and, for an arbitrary rate 1 / n has 2n possible metrics. Used to calculate and scale the metrics of equation branches are selected so as to obtain the best performance of the decoder for terminating the channel using experience and simulation. These equations are used in the SVD logic of this invention. Metric inputs are scaled by the symbol metric values ​​stored in the table of symbol metric (SMT) in VD 50. The level of "erasing" is ignoring the code symbol in the calculation of the branch metric. Erasing can be used to "pierce" the code that requires a higher rate channel for data transmission. In addition, deletion could be used to remove some of the channel code symbols that are part of a "hidden" data or control channel. Since the erased code symbol does not affect the value of metrics is a reasonable degree of erasure has no appreciable effect on decoding performance.

The convolutional codes can generate an unlimited sequence of code symbols but certain properties of the codes make it possible to reduce the number of symbol sequences. The first property is that the interest is the best (most probable) path to the state, because any global path through a state must follow certain best local path. The second property is that the convolutional code structure is repeated and is symmetrical code tree. Code sequences therefore must be converted into equivalent sequences generated by a finite number of unique bit stream patterns. For this limited length K has a 2K-1 possible patterns of binary data (referred to here as "states") that need to be evaluated in order to identify the most likely global path.

6 is a characteristic view of matching sequences or paths in a trellis diagram for an example of code K = 3 (1/2) based on G0 = 58 and G0 = 78. Necessary conditions for the conversion of the characters shown in the diagram. For each state is computed state metric (not shown) which represents the relative probability that a given path through that state should be. State metric calculation is performed by adding process-compare-select (ACS). State metric for each possible state preceding this state is added to the branch metric for the conversion of this previous state to the current state. These amounts are compared and selected the most likely transformation which corresponds to the lowest amount, and assigned to the present state as the state metric. Bit decisions for each ACS is the value of the least significant digit (the last digit) for the previous state from which to start the selected transformation. Solutions for all states in the trellis column are short memory pathways.

Since the first and last terms in the shaper of polynomials (G0 and G1) are unity, the hypothesis (i, j) for the transmitted symbols (G0, G1), two paths entering or leaving any state are complementary in the binary system. This relationship ACS states are depicted by a butterfly diagram in Figure 6B. Of course, the value of silent channel code symbols (G0, G1) are free of errors and their metrics states either zero or focused on the maximum value, and the zero state metric represents the state in the best possible way globally.

As shown in FIG. 6B, the branch metric from state x0 to state 0x is added to the x0 state metric to determine the first of two possible 0x state metrics. The second possible 0x state metric is determined by adding the branch metric from state x1 to the x1 state metric value. The last of these possible values ​​is then assigned as the new 0x state metric value. This process is repeated for the x1 state and for all other states in that trellis column. For each new set of code symbols, a new column, in accordance with a single original bit. The difference between each pair of state metric is compared to a predetermined limit value of quality (QT) for receiving a quality metric Yamamoto (YQM) or "q-bit" for the new state of the method proposed by Yamamoto et al., Cited above work and as described below, in accordance with Figure 12.

Once the matrix of local ACS decisions is stored in the memory of ways, the process of reverse link should be a path going in the opposite direction in accordance with this matrix. Chainback begins in the "best condition", said array of ACS, and then uses the solution for this state (binary address) of the memory word of ways to determine the previous best state (most likely). Reverse link passes through at least five or six solutions length limited to ensure that the route to be followed will merge with the most likely global path. For a limited length of 9 sufficient depth way back level equal to 63 states. The last decision at the end of the chainback is accepted as the best decision for that output bit obtained by the Viterbi decoder. For each of the following raw binary data creates a new word and a new decision on the basis of the best possible state of the ACS array is carried out repeating the process of reverse link from the new column array with the same path length. Thus, each new binary symbol window to drive forward and reverse link status 64 of the memory tracks in accordance with one column of the lattice.

In the above example, describes a cycle in accordance with Figure 3, for all modes of operation where the data is placed into packets, encoding begins and ends in the all "zero" state by inserting a tail of eight "0" bits at the end of data. Repeated decoding SVD forces the decision to introduce the bits in the memory pathways when the first eight columns of the lattice of each cycle is zero. This ensures that the selected path for each loop starts and ends in a general "zero" state for all possible data rates.

DESCRIPTION input buffer (IB) Further description of the functioning of SVD 20 of this invention relies on these exemplary definitions for various processing cycles.

Internal clock CHIPX8: it is the main clock for internal device and its frequency is preferably equal to 9.8304 MHz.

Computing cycles: the time to process the branch metric and each pair of previous state metrics through ACS pair 108 (Figure 9) and is equivalent to two internal CHIPX8 clock cycles.

Processing cycle: the time to process a single source of binary through a reverse link and is equivalent to 128 +3 computing cycles required to complete the processing of the metrics 64 branches through ACS logic 106.

Block Cycle: This is the processing of the packet cycle having one of four possible sizes and is equivalent to one of the following cycles: 192, 96, 48 or 24.

Loop buffer: it is time to process all four possible packet rates for the cycle and time to perform the final operations jump chainback and cleaning VD 50. This is equivalent to 432 cycles of treatment (192 + 96 + 48 + 24 + 72).

Cycle: This is the time window required to send all code symbols in a packet and is usually equal to 29 milliseconds except for the sync channel, where the cycles are stored in the 16.67 millisecond duration, for generating a superframe a duration of 80 milliseconds.

FIG. 7 is a schematic block diagram illustrating a preferred embodiment of an input buffer (IB) 48 of this invention. IB 48 receives code symbols on decoder input line 34 and transmits these code symbols selected and accumulated for all possible data rates on symbuf bus vocoder 52. As shown in Figure 4, IB 48 operates in repeat mode for the forward link channels and in either repeat mode or random mode data packets (DBR) to reverse link channels. In repeat mode IB 48 accumulates code symbols to transmit them on symbuf bus 52 with communication speeds accumulated symbols equal to 1/2, 1/4 and 1/8 rates of output code symbols for subsequent transmission of the initial full-rate. In DBR mode, IB 48 selects code symbols for the compilation of data packets with sizes 1/2, 1/4 and 1/8, which are placed in series according to a randomized code word derived from the last few bits of the PN sequence from the previous cycle for the subsequent formation Package unit full cycle. Input code symbols are transmitted via a decoder input line 34 are the same as for both IB modes. Binary code symbols are stored by DECSTB line 64 and then, after the IB 48 receives code symbols is sufficient for VD 50 decoding process, the ready signal is transmitted to a strobe VD 50 on INBUFRDY line 66. IB 48 then transmits the code symbols in sequence on demand VD 50 over symbuf bus 52.

Decoder mode is controlled by the control word mode DECMODE bus 68, which includes several control bits that affect the IB 48. The various IB 48 operating modes can be estimated after considering 4. Several signals DECMODE bus 68 except that define a clock signal for the gate signal line inbufrdy 66 to VD 50. One of these bits determines the code symbol boundaries for each of the four different packet sizes corresponding to the four alternate data bit rate described above with reference 3. Other bits in DECMODE bus 68 determines whether the repeated code symbols are accumulated by IB 48 before transmission onto the bus sumbuf 52 or whether they are simply selected in accordance with a positional code DBR.

Each input cycle for SVD 20 begins DECSYNC strobe signal line 70. The strobe signal line 70 is transmitted DECSYNC for at least 15 cycles of internal clock generator (CHITPX8) to receive a strobe signal on line 64 DECSTV to before the first code symbol packet implement exposure time required to start IB 48. After each strobe signal lines 70 IB 48 expects to receive either 384 or 576 code symbols are transmitted to the buffer 72 by DECSTB line 64. The rate of the convolutional code, (4) determines whether the expected 384 (= 2 • 192) or 576 (= 192 • 3) code symbols. Binary code symbols on decoder input 34 are continuously clocked and sequentially, starting from the most significant bit (MSB) to the least significant bit (LSB) SNIRH8 internal master oscillator (not shown). LSBs of each symbol is marked by a strobe signal on DECSTB line 64 and the entire code symbol is fixed to parallel symbol register 74. If the code symbols come from the decompression unit temporary pulse signals, the input symbols are clocked decstb line 64 at a speed of 384 characters per cycle. During operation in the reverse link channel, the code symbols received from the decompression unit temporal block, and the input code symbols are combined into a package in IB 48 at a speed up to reaching the maximum (one code symbol for every seven cycles of internal clock generator SNIRH8). Maximum packet transfer rate is limited to checking logic (not shown) which allows the reading of code symbols from the buffer 42 after filling. Buffer control logic 76 generates a signal to the INBUFRDY line 66 to inform controller 62 when to begin using symbuf bus 52.

INBUFRDY strobe signal on line 66 resets the two-bit "p-dimensional" counter (not shown) in buffer control unit 76. The contents of the counter p-size indicates the packet size for the code symbol symbuf bus 52, which may contain 24, 48, 96 or 192 original bits. The strobe signal line 66 starts the VD 50 and two bits DECMODE bus 68 (see FIG. 4) indicates a number of code symbols that must be taken by IB 48 before launch line 66. This selective delay line INBUFRDY strobe signal 66 to optimize processing delay in SVD 20.

After implementation of INBUFRDY line 66 strobe reset the read address of buffer 72 and a write address in the repeat buffer 78. Thereafter, the first code symbol of the buffer 72 is selected and fixed feedforward symbuf bus 52. The pointer to the read address buffer 72 and then increases after the pre-selection fixed the following character codes in the bus 52, which is responsible for the gate signal line symstb 80. Reading IB gate signal line 80 symstb limited to one cycle of reading in every seven cycles of the internal clock generator CHIPX8 for exposure time required to alternately perform read and write operations for buffer 72. The number of code symbols to be read for the current cycle is indicated by signal DEVMODE bus 68. After code symbols representing 192 original data bits are read from buffer 72 for the first cycle, packages containing 96, 48 and 24 bits, then read from repeat buffer 78 according to the selected and accumulated logic 82. The read and write addresses repeat buffer 78 are reset and incremented p-size (not shown) in buffer control unit 76 after reading the last code symbol of each packet. The contents of the counter p-size determines the address code word selected from the buffer 72 or 78 repeat buffer and controls the selection and accumulation logic 82 for the submission of correct code symbol tire symbuf 52. Index read addresses for repeat buffer 78 is increased after each reading, when the counter district size is nonzero. Write pointer for repeat buffer 78 is incremented by one after every other read from either buffer 72 or repeat buffer or from 78. The code symbols are output from IB 50 in the same sequence without regard to SVD 20 operating mode but VD 50 transmits idle packets during It operates at a constant repetition rate in the continuous mode.

As the code symbols are read from buffer 72 in repeat mode, each pair of code symbols is summed according to the logic 82 and stored into repeat buffer 78. The accumulator is set to the zero state when carried INBUFRDY strobe line 66, and after recording the amount of each pair repeat buffer 78. As you read the code symbols of the repeat buffer 78 are also summarized in pairs and written back into repeat buffer 78. The same operation is repeated on each pair of characters of the packages with 192, 96 and 48 characters. 7-bit word length repeat buffer 78 allows you to store without separation of up to 8 such code symbols. During mode DBR memorized code symbol is transmitted to an accumulator according to the logic 82 is reset so that the output of the logic 82 is a symbol transmitted from the buffer 72. The recording buffer repeat 78 is only valid for the characters, selected in accordance with the binary RBR codes (not shown). Register contents district size and the row address (transmitted slot number) control the selection of binary DBR, used to select characters. Set binary DBR is selected so that the binary codes DBR at any rate would be a subset of binary codes DBR for higher speed.

Forward link sync channel uses 26.67 cycle duration in milliseconds and with 128 symbols, these symbols are transmitted continuously at a constant flow rate of 4800 characters per second. IB 48 accepts three clock cycles from the temporary decompression apparatus 80 milliseconds to generate one decoder packet having 384 symbols, but only one is needed for the strobe signal on line 70 decsync temporal decompression apparatus for this "superframe". Each sync channel code symbol is repeated twice and the cycle duration of 80 milliseconds of 1200 bit / s channel is decoded as 96-bit packets with a symbol repetition factor of two. The sync channel operates in a continuous mode, but the output is delayed by 71 bits because of a delay in SVD 20. The first bit in each packet is the twenty-sixth bit packet sync duration of 26.67 milliseconds, which received 6 packets before the current package. These parts are supported by the synchronization controller 62 and microprocessor interface 58 (Figure 5).

The reverse link channels 576 may be transmitted symbol cycles in IB 48 with partial, reaching to the transmission frequency chips, which is one-eighth the frequency of the internal oscillator clock CHIPX8. The code symbols are written sequentially into buffer 72, which may be considered as a 32 row array of 18 columns. The code symbols are read and written by column. That is, the code symbols are read from buffer 72 in the same order in which they were recorded. After receiving the sixth character Package IB 48 can begin sending VD 50 on the three code symbols (representing a single original data bit) during all cycles until the end of processing the whole package. After dropping and closure of each buffer cycle, the bits selected DBR on decoder input 34 are continuously clocked by an internal clock in the DBR code register (not shown). The fourteen bits ending with DBR-13 at the strobe signals on line 70 DECSYNC are recorded as DBRCODE word for the next buffer cycle. These bits CODE DBR, from DBR-0 to DBR-13, are used to select code symbols to be written to repeat buffer 78 from characters having full rate transmission sent to VD 50 over bus 52. Once the full packet processing remaining in the buffer Repeat 78 package with a half-size processed in the same way. As the transfer of characters from the packet length to half VD 50 over bus 52 the characters that have been selected DBRCODE, re-written to repeat buffer as a fourth packet size. Package size and the fourth to the eighth subsequent packet size handled similarly.

8 shows DBRCODE symbol selection algorithm, which is used to determine which 16 slots (a pair of lines) are selected from buffer 72. For full rate operation, all 16 slots are transmitted (lines 32). Regardless of whether or not the transmitter is turned off during some intervals of transmission time at lower speeds. For example, the fourth speed is transmitted only one of the four slots as the first 36 code symbols. The code symbols are transmitted by row but the temporal demultiplexing apparatus sends them to SVD 20 by column. Since transmission DBR algorithm skips rows in the temporal demultiplexing apparatus, the fractional velocity for attaching substantially fewer rows. For the DBR 1/4 rate buffer 72 contains only eight rows of data and noise symbols in the remaining lines. In contrast to reverse link traffic, the reverse link access channel (Fig. 3E) operates in repeat mode at a 1/3 convolution code rate with code symbols by repeating twice to provide a factor of approximately 2.5 dB on the reverse traffic channel. Transmission DBR algorithm can be better appreciated after referring to the above-mentioned patent application Gilhousen authors and others.

In addition to functional logic, as shown in Figure 7, IB 48 also contains test logic to verify that the means of self-testing.

Element Viterbi Decoder (VD) of the present invention, FIG. 9 shows a functional block diagram for VD 50, which processes the code symbols are received on bus 52 from IB 48. VD 50 outputs a decoded binary data stream on rdata line 56 together with quality information. These functions are performed in the six submodules shown in Fig. 9. Two bits received from DECMODE bus 68 control the operation of VD 50 through line 84 and DECRATE PACKET line 86. The data table stored in the table of symbol metric (SMT) 88 is a programmable look up table to which converts the 7-bit code the tire 52 to the corresponding 4-bit scale for correct operation of the branch metric logic 90. SMT 88 provides flexibility needed for the various modes of operation. The control information for VD 50 is normally sent first packet processing call and is not changed during traffic reception. DECRATE signal on line 84 determines how many code symbols contained in the branch metric computations and RAKSET signal transmitted on line 86 causes the state metric values ​​creation beginning of each packet. The contents of SMT 88 is used to convert the 4, 5, 6 and 7-bit input code symbols on bus 52 received in the scaled four-bit input code symbols for branch metric logic 90 internal SMTSYM bus 92. These conversions include the necessary compensation for the doubling, squaring and erecting the fourth power of the code symbols accumulated in IB 48 for the lower data rate packets. Each code symbol is inputted via bus 52 provides address bits to lower order data SMt 88 and these addresses are then provided as the SMTSYM value on bus 92. SMT 88 stores individual data for each of the four rates in both repeat and in Mode DBR.

For each package VD 50 stores the next bit of quality, representing a quality metric Yamamoto (YQM). Bit quality for the best state (zero by definition) of the last process cycle of each packet size is stored in a YQM register 93 and is used later in determining the original data transmission rate.

Logic 94 symbol error rate (Ser) compares approximate solutions of i-th and j-th symbol with values ​​c0 and c1 received from the re-encoded output data to create a byte for each packet Ser SERROR bus 96. This value for the tire 96 reaches a limit at 255 and is also used later in determining the original data transmission rate.

SMT 88 includes memory (RAM) and the stored control logic for compacting a write address and a write strobe RAM. 7-bit input symbol SYMBUF bus 52 is used for LSB address for the value of 4-bit data, the type of which receives the output symbol tire SMTSYM 92. The amount of p-size bus district size 98 forms two MSV addresses of RAM and can choose a variety of different transformation compensation packages for the amounts of accumulation imposed by the IB 48.

Threads grids (6A) on which the Viterbi decoder operates are indicated by the pairs (c0, c1) for rate 1/2 code and triplets (c0, c1, c2) for rate 1/3 convolutional code. Thus, before any ACS operation must be calculated branch metric for each of the two possible values ​​(c0, c1) or the three possible values ​​(c0, c1, c2) for rate 1/2 and 1/3, respectively. These branch metrics are calculated according to the following equation 1. For instance, during each calculation cycle, branch metric logic 90 generates a new pair of metrics Rijk VMETR81S bus 100. All this is calculated on the basis of the input symbol (r1, r2, r0) SMTSYM bus 92 and the hypotheses for the transmitted symbol (c2, c1, c0) on the hyp bus 102 from the timing control logic 104.

(1) where C is the i-, j- or k-hypothesis bus 102 for the target ACS state, rx3 a sign of each code symbol bus 92 and rx2, rx1, rx0 are the three LSBs of each symbol metric SMTSYM bus 92.

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Each of the three-character metrics bus 92 representing a single original data bit is stored in a set of input latches (not shown), branch metric logic 90. The pair (or triple) code symbols of input information are adapted to the decoding rate 1/2 (or 1/3) for A four pairs of branch metric bus 100. The third symbol of the tire 92 is set to zero state if the line 84 DECRATE determine convolution coding rate equal to 1/2. Branch metric pairs on bus 100 are transmitted logic add-compare-select (ACS) 106, which selects one of the two branch metrics during each ACS calculation cycle. For each hypothesis about the input data is calculated four-bit branch metric on bus 100 in accordance with equation 1. 4-bit branch metric is also generated as a complement of the hypothesis. In this formula, the value of the code symbol is added to the Rijk metric, if the code symbol sign matches the hypothesis, otherwise zero is added to the metric. It is expected that the value of the branch metric with rate 1/2 will vary from zero to 14, and the branch metric values ​​with rate 1/3 will vary from zero to adder 15. The branch metric logic ASC overflows at 15.

Metrics bus 92 from SMT 88 to branch metric logic 90 are represented in the sign-magnitude format and erasure are determined by the symbol value according to Table 1.

If symbol metrics outside the expected range for the rate 1/3 overflow the adders, the branch metric crowded bus 100 at 15 (11112).

ACS logic 106 processes the input branch metrics on bus 100 during every calculation cycle for which it acts. Pair ASS logic blocks 108 process the 4-bit branch metric on bus 100 and the five-bit state metrics from states of RAM 110 to produce a pair of decision bits on an internal bus 112 and a new pair of state metrics on another internal bus 114. The decision bits bus 112, which are LSBs of the best previous state for each pair ASS 108 are shifted by 8-bit output latch 116. The 8-bit byte address each four pairs of decisions issued on bus 118 to the logic of making the reverse link 120.

During the first process cycle for each packet metric for the zero state is set to zero and all other metrics are set to their maximum values ​​during their states read out from the RAM 110. The decisions bus 118 and the best states in the line 122 are set zero state in batch mode for the first eight cycles each cycle. Metrics of new states, the least amount of previous state metric and linking branch metric is written back to the states of RAM 110 in place, which is calculated by shifting the current state from MSB to LSB. The decision null hypothesis chosen for equal metrics. The best state latch 124 is written a new metric for state zero at the beginning of each treatment cycle. All other new state metrics in the current processing cycle is compared with the current best state of the latch 124 and the minimum metric replaces the previous best state metric in latch 24. The best state metric of the previous process cycle is subtracted from each state metric after the reading of the state RAM 110 during the current processing cycle. ACS logic 106 continues to accumulate and normalize metrics until all four packet processing code symbols.

Yamamoto Quality Metric (YQM) or "q-bits" is attached to each state metric. YQM bit for initial state zero is set "good" or true (0), and all other YQM bits are set "bad" or incorrect (1) during the first treatment cycle IB. Bit VQM is set to true (1) for each new state metric calculated by the logic of ACS 106 if the YQM bit for the selected previous state metric was false or if the difference metrics in the ACS calculation of less than or equal to a predetermined limit value of quality (QT), described register quality limit value (see. MUX216 11).

An important element of the present invention is the set of "error metrics" produced during decoding, and comprising three types of quality information. For multiple data rate hypotheses (e.g., 9600, 4800, etc.) SVD 20 creates one or more independent quality metric elements. This includes cyclic redundancy check (CRC), the symbol error rate (SER) and the Yamamoto metric kachestva (YQM). YQM is called "q-bit." Some error metrics are omitted at lower data rates. CRC and SER, metrics are well known in the art. YQM metric can be understood upon consideration of the above work Yamamoto et al., And the following considerations referring to Figure 11. These error metrics are used to select the most likely original data transmission rate by the method described in the aforementioned patent application authors Butler et al.

Decoded symbol data is provided for each data rate hypothesis and stored in OB 54. The data cycle for each hypothesis contain three quality metric elements. CRC element is discussed below with reference to Figure 10. SER element is discussed below with reference to Figure 9, which shows SER 140. Figure 11 shows a block diagram of a portion of ACS pair 108 (Figure 9) that creates the YQM bit.

As shown in FIG. 6B, the branch metric from state x0 to state 0x is added to the x0 state metric to determine the first of two possible meter uk 0x state. The metric of a second possible 0x state is found by adding the branch metric from state x1 to the value of the state metric x1. The latter of these two possible values ​​is then assigned as the value of the new state metrics 0x. This process continues for the 1x state and for all other states in that trellis column. YQM bit is a label showing that the difference between the pair 0x state metric values ​​is less than a predetermined limit value (QT), or that there is the next state that is less than the predetermined QT. 11 LSB for ASSOh0 state is represented on the line 210 and the YQM bit for ASSOh1 state represented on line 212. The Group of boundary value QT 214 is shown for a set of 4-bit buses to a multiplexer 216. The tire MUH district size 218 selects one of the QT group 214, depending on the current transmission data rate hypothesis. An important element of the present invention is that each boundary quality value (QT) in the group 214 is programmable and can be adjusted individually or together to accommodate for different operating modes. Since different rate hypothesis data may have different QT, the MUH 216 performs switching alternative QT members of group 214.

Referring now to Figure 11, there is calculated the difference between a pair of state metric ACS and transmitted via the bus 220 to XOR, a logical branch with four branches 222. Bit solutions for line 224 is used to select the most likely of the two metrics in the multiplexer 226 to run on METODIF bus 220. Output line 228 from MUX 226 is the state metric bit selected from buses 210 and 212. Output line 228 is subjected to OR operation on the output of the comparator 230 on line 232 for receiving and transmitting the YQM bit on line 234. Comparator 230 compares selected from the group QT 214 with the difference metric state bus 220 (after taking into account the sign of the valve HOR 222). YQM bit 234 is transmitted to YQM register 93 (Figure 9).

The thus obtained YQM bit is transferred to the account of the current state in the Viterbi grid (6A). YQM procedure has the property that sets a "bad" YQM bit in any state Viterbi lattice to move forward on the decision tree. YQM bit 234 is a label that indicates that the difference between the two approaching state metrics is more or less the selected QT value. If the difference is greater than the QT value, the YQM bit is set to the YQM bit of the previous state. If the difference is less than the selected value YQM bits, then the YQM bit of the new state is set to "bad" or "1". Before starting the decoding operation of any rate hypothesis with zero state Viterbi lattice marked "good" YQM bits ("0"), and all other conditions lattice marked "bad" YQM bits. At the end of the decoding procedure rate hypothesis cycle is marked as either "good" or as "poor" depending on the YQM bit for the final zero state, which is stored in the register 93 and outputted ACS logic 106 (Figure 9). As each cycle is completed by a line from the vocoder eight zeros (00000000), the decoder knows that the correct final state of the cycle - zero state.

Logic reverse link 120 comprises a memory 126 routes, which has 64 words of 256 bits each solution. The memory 126 is read twice paths and then written once during every four calculation cycles. Thus, chainback logic 120 may write 256 bits into a single path memory word and can read the bits from each of the 64 tracks in the memory words during each processing cycle. Chainback logic 120 includes a multiplexer 128, address generator 130 and a plurality of data latches 132. Address generator 130 determines the address of the word to be written and the first chainback read cycle begins with the processing of the previous word written.

The process ends after the return link read write memory write zeros path 126 in self-determining sequence. The eight LSBs of the read address start with the best state bus 122 to the last word solutions bus 118. This address bit is zero for the last word (because the best state inputs are set to zero) for the first eight words of each block cycle (as here inputs solutions and the best states are set to zero state). This solution according to the address memorized for each bit of the read word is moved to the address read as the LSB for the address bits in the word should be considered. Eight LSB of the read address that form the bit address in the word solutions are shifted by one bit to move the MSB (eight-bit address) in the LSB position. This shift compensates for the order making a pair of ACS 108. The address generator 130 reduces the word address after each reading in the reverse link from the address of the new address to the oldest word in memory solutions tract 126. Bit solutions at 63-m reading internal bits transmitted on line 134 to output data latch 132. Each cycle 432 comprises a processing cycle, including 192 cycles for the full data rate, 96 cycles for the half data rate, 48 cycles for quaternary data rate and 24 cycles for the eighth data rate.

Working reverse link performs the same functions in both packet and continuous except for the best state control described above. The output bits of line 134 are synchronized chainback logic 120 on-line data 56 r ... (as before).

The logic of the symbol error rate (Ser) 94 performs re-encoding the output data stream through line r-data 56 and compares the newly generated code symbols with the code symbols received SVD 20 on decode input line 34. The strobe signal line 80 synchronizes SYMSTB sign bit r3 Each symbol metrics on bus 92 to a first-come-first-served basis (FIFO) 136, which compensates for the delay in the trunk and in the reverse link in VD 50. The encoder 138 and error counter 140 is reset before the beginning of each cycle to prepare clocking of each bit on line 56 to a 9-bit shift register in encoder 138. Implemented by counting the number of code symbols that do not compare to the 8-bit error counter 140, which has a limit of 255. The output of the counter 140 is transferred via a bus 96 SERROR to OB 54, where it is shifted and latched in the corresponding register.

The control logic 104 starts the clocking VD 50 upon receiving a signal on INBUFRDY line 66 and then mediates the timing of other elements of VD 50. Logic 104 starts two strobe signals (or three for rate 1/3) on SYMSTB line 80 to clock the data into the logic SMT 88 branch metric logic 90 and SER 94. During each cycle of the calculation VD 50 processes the current information bit symbol for one hypothesis on hyp bus 102 with ACS pair 108. The processing cycle includes 128 calculation cycles to process each binary character of any state of the ACS. Since the convolutional encoder has a limited length of nine to this execution, there are 29-1 = 256 states for all input information bits symbol (in each trellis column). Counter state sequence timing control logic 104, provides for a 256 count state (state 2 per cycle counting), passing the results of the count on the bus STATESEQ 142. Other elements of the timing control logic 104 encode the state register contents to generate the hypotheses on hyp bus 102. Other control signals are transferred via ACSSTATE 144 (a) to start the release ACS processing and logic 106, (b) to reset inputs metric states associated with ACS pair 108 during the first process cycle, (c) for setting a flag in the end of each processing cycle so that it was possible to maintain the best state, and (d) to trigger latch 116 solutions for each calculation cycle.

Timing control logic 104 determines the read address and write paths for the memory 126 and transmits this information via address lines 146 and 148 respectively. 11-bit counter (not shown), logic 104 is increased during each read to generate read address for each byte solutions bus 118. One of the 32 bits making recordings on the bus 118 is carried out during every four calculation cycles during a process cycle. 6 MSB created read address bus 146 by the same logic that generates the gate signals and the read address decreases between two strobe signals recording. Control signals required to load, shift and reset LSB read address bus 146 are supplied from the timing device in logic 104. The same device also determines the timing signal RSTB strobe on line RSTB 150 to harmonize the work of logic unit 120 and the inverse logic SER 94 . The logic and timing control 104 also generates clock signals for re-reset and error counter 140 in 94 SER.

The output buffer (OB) of the present invention, FIG. 10 is a functional block diagram showing the operation of the output buffer (OB) 54. Decoded data is converted on rdata bus 56 bytes in a converter logic 152 and stored in a buffer 154. Converter 152 also checks the packet CRC code in the usual manner. These packets and status bytes for the packets are available to microprocessor interface 58 via the bus DECDATA 60 for approximately 10 milliseconds from the time of sending an interrupt to microprocessor interface 58 on the INTD line 156. The results of a CRC check the packets stored in the status register (not shown). CRC polynomials, used by converter 152 depend on the packet size (see. Table 2).

CRC used are in the form g (x) = p (x) (x + 1) and used well-known simple polynomials 2118 (8916) and 53618 (AFl16) for p (x).

Used in a converter logic 152 to verify the installer is well known in science and consists of a register which is branched in accordance with the CRC polynomial, wherein the output information is stored after the branch passage XOR gate.

After treatment cycle four times in packet mode or once in continuous mode and after the data for all four rates in OB 54 interrupt line 156 is set to true (1). SVD 20 performs sequential processing 432 through the same cycles for each cycle of the batch mode, regardless of the actual data rate or packet size. Thus, the interrupt on line 156 is sent with a fixed delay with respect to the strobe signal input of a code symbol on line 64 (Figure 7). In continuous mode, the fixed delay is dependent on actual packet size. INTD interrupt on line 156 is reset automatically after seven cycles of the internal clock CHIPX8. The microprocessor (not shown) can use this interrupt signal, or the cycle timing signal to indicate when to perform readout of the output data. Buffer 154 contains the necessary space to store a complete set of packets, thereby allowing less time processing cycle, about 10 milliseconds to read the output of the microprocessor interface 58 (Figure 5). The last eight bits of each packet are zero in packet mode because SVD 20 is operated in a batch mode, with the proviso that the transmitting encoder was pretreated and set to zero. DECDATA register (not shown) in buffer 154 is automatically updated with the next byte from buffer 154 after each read. These pre-selected to minimize the waiting time the next byte microprocessor, but pre-selection still requires four internal clock cycles CHIPX8. If the microprocessor can read OB 54 faster than once every four internal CHIPX8 clock cycles, then the microprocessor must test signal BYTERDY BYTERDY bus 158 to ensure that the output word is read twice. Quality information ("error metrics") included in the output data can be used by the microprocessor to select the best packet from the four available in OB 54 in accordance with the method of the above patent application authors Vutler et al.

Converter 152 transmits the information bits to buffer 154 every 8 cycles. Data is transmitted via the internal bus 160 to buffer 154 before starting the next process cycle. Upon receipt of each data bit on the line 56 it is clocked into the CRC generator (not shown) converter 152. This CRC generator is reset to all data prior to the start of each packet. At the end of 96 and 192 bit packets remaining in the CRC information is checked and the CRC bit is set in the STATUS register (not shown) if all remaining information is zero. The read data are checked before sending an interrupt on INTD line 156 and after each reading. After sending the interrupt on INTD line 156 read address pointer is set to address zero. SYTERDY signal is set to the zero state via line 158 after each read and held there until it engages the new data byte in register DECDATA (not shown) of the buffer 154. OB 54 comprises besides the self-test logic for testing proper functioning.

The controller and processor interface elements of the present invention as shown in Figure 5, the controller 62 sends timing and control strobes for SVD 20. SVD 20 runs in accordance with the frequency of the internal oscillator clock signal and CHIRH8 controller 62 transmits a sequence of gating signals and trigger signals, in accordance with the frequency of the internal oscillator timing signal. These control signals can be triggered by a reset for testing, but during normal operation they sequentially engage a fixed set of operations, corresponding signals for DECMODE bus 68 and then return to the original state. The sequence control signal is triggered again after each decoder strobe on line 70 (Figure 7). Signal validation link that points to the correctness of the data reverse link, the job of launching RSTB strobe signal line 150, so that data can be transmitted in the OB 54. The interface controller 62 and microprocessor interface 58 contain the microprocessor control registers necessary for proper operation, including Register control and discharge line. These two elements also contains the logic and special self-control.

The actual execution of the internal modules for each of the elements described above SVD 20 can be configured suitable method known in the art, but is preferably made as a monolithic integrated circuit.

Although proposals, examples of the present description involves a sequence of processing to achieve the desired goals, but to those skilled in the art will appreciate that the logic discussed decoder may be repeated in multiple parallel decoders which operate together to provide as many outputs as there are data rates in the transmission system.

The present invention may also be modified, for example, by using cyclic redundancy coding for as many data rates as required for the system.