Method and device for controlling power in communication systems and for holding it at desired level

This invention relates to digital communication systems, particularly to a method and apparatus for adjusting transmitter power in systems designed both to minimize interference among simultaneously operating transmitters and to maximize the quality of individual transmissions.

In a cellular telephone or personal communication (PCS) a large number of "mobile stations" communicate with one another through station cell or "base stations". The transmitted signal experiences fading caused by multipath propagation, for as the mobile station moves with respect to environmental objects reflecting the signal. Adjusting the mobile station transmitter power to overcome the fading caused by multipath propagation, described in U.S. Patent No. 5056109 for the invention "Method and apparatus for adjusting transmitter power in a mobile cellular telephone system, multiple access CDMA", issued 8/10/1991.

If the mobile station transmits an excessively powerful signal, it will interfere with signals transmitted by other mobile stations. If the mobile station transmits an insufficiently powerful signal, the base station is not able to restore the transmitted information from the received signal. In the aforementioned patent, the base station measures the power of a signal received from the mobile station and transmits power adjustment commands to the mobile station over a separate channel. These commands instruct the mobile station to increase or decrease transmission power to maintain the average received signal power at a predetermined level. The base station must periodically adjust the transmission power of the mobile station to maintain an acceptable balance between interference and signal quality as the mobile station moves.

A base station processor may monitor error rates in the received signal to select an optimal power level at which is stored the average received signal. A base station processor detects errors as disclosed in copending US application "Method and apparatus for determining a data rate in a communication receiver". In the above mentioned US patent and application described embodiment the cellular telephone system, multiple access CDMA in which a mobile station transmits "cycles" comprising "symbols", represent digitized voice or other data. In more detail, this embodiment of the cellular telephone system, multiple access CDMA is described in U.S. Patent No. 5103549 on the invention "System and method for generating signal waveforms in a hundred telephone multiple access CDMA", issued 4/17/92.

The mobile station encodes cycle at one of four rates, the speed is selected depending on the needs of the subscriber. The maximum velocity which is generally preferred for high quality voice transmissions or rapid data transfer is referred to as "full rate". A rate of half, quarter and eighth of the full rate are called as "half rate", "rate 1/4" and "1/8 rate" respectively. Each symbol cycle encoded with 1/2 rate, 1/4 rate and 1/8 rate is repeated two, four and eight times, respectively for the filling cycle. The cycle is then transmitted to the base station at a constant speed regardless of the speed with which the coded symbols.

The base station has no proactive notification of the data rate at which the received encoded cycle, and this speed may differ from the speed of the previous cycle taken. The base station decodes each received series with each of the four rates and produces a number of error metrics corresponding to each rate. Error metrics are an indication of the quality of the received cycle may comprise the result of a cyclic redundancy check (CRC), Yamamoto Quality Metric, and the result of comparison with the re-encoded symbol. Formation and use of error metrics are well known in the art, and a detailed description Yamamoto quality metric is given in the article "Viterbi Decoding Algorithm for Convolutional Codes with Repeat Request" Hirosuke Yamamoto et al. IEEE Transactions on Information Theory, IT-26, including, N5, September 1980. The set of error metrics for the decoding of each frame at each rate thus includes one or more results of a cyclic redundancy check, and the Yamamoto Quality Metric comparison result from the re-encoded symbols. A base station processor analyzes the set of error metrics using a new algorithm for deciding, and determines the most probable rate at which the received cycle has been encoded. The base station then uses the rate decision to select the corresponding decoded data of a plurality of decoded data rate for transmission of data recovery cycle.

A base station processor also produces an indication "tainting" data cycle if the quality is too low, the processor can determine the rate. Similarly, the processor generates the indication "probably full speed" if the data are bit errors, but the rate is probably full rate. If there is degradation, the base station may simply discard the cycle or may replace it with interpolated data.

It would be desirable to monitor the error rate of received cycles and periodically adjust the transmission power level to maintain this ratio at an acceptable level. These problems and deficiencies clearly felt in the art and are solved by the present invention as described below.

The present invention includes a method and apparatus for adjusting the power level of a remote transmitter to provide a substantially constant error rate in the received data. The invention may be used in a base station of a cellular telephone system to create the possibility of simultaneous transmission with minimal disruption to the maximum number of mobile stations by improving power control signal transmitted by each mobile station.

In a cellular telephone system, multiple access CDMA described in the aforementioned U.S. Patent, the mobile station transmits a signal containing digitized voice data cycles or other information to the base station at the initial power level or setpoint. As described in said co-pending application, the information is encoded in cycles of full rate, half rate, quarter rate or eighth rate. The base station receives the signal and decodes each cycle for each of these speeds. Produced corresponding group error metrics for each rate, which provides an indication of the quality of the received information, if the cycle is decoded at a given speed. Then, the base station processor analyzes the error metrics group using a decision algorithm and either provides an indication of the most probable rate at which the information was encoded or provides an indication "failure data", i.e. an indication that the rate could not be determined with the required reliability.

In this invention, the base station processor counts the number of consecutive frames encoded at a rate such as full rate and the number of cycles, is the destruction. By establishing a number of consecutive full rate indications, ie without interference indicating less than full rate indication indicating data corruption or full rate likely indicates quality full rate transmission and is called "full speed mode". If the processor detects a full rate mode and then detects an additional full rate cycle, it should decrease the signal power to a level at which a small, but the allowable number of indications of data destruction or full rate likely occurs between runs at full speed. For example, one error indication 100 cycles at full speed, if each cycle comprises 567 symbols and is transmitted at a rate of 28,800 symbols per second, inaudible when transmitting conventional speech.

By establishing a number of successive indications of destruction of data, t. E. Without the intervention of other indications of speed, it indicates a low transmission quality and is called "regime of destruction of data." If the processor detects a failure mode data, it should increase the signal power. The increased signal power may overcome fading caused by multipath propagation, thereby reducing the rate of destruction of data.

The set number of consecutive indications 1/2 speed, 1/4 speed or 1/8 speed is called "variable rate mode". For further improvement of transmitter power the processor may, while in the variable rate mode, also reduce the signal power if it detects a half rate indication, one quarter rate, or 1/8 rate. Furthermore, while in the variable rate mode, the processor may increase the signal power if it detects an indication of authorization data.

Although the present invention can be used to adjust the power transmission, comprising any type of data, it is optimized for transmissions consisting of voice information. In communication systems such as cellular telephone system described in the aforementioned U.S. Patent Application and, transmitting voice messages are encoded at a variable rate, the rate is dependent on the complexity of the speech. However, continuous speech basically encoded at full rate. The speech signal occurring after a period of relative inactivity, can be encoded at lower speeds the transition to full speed as the complexity of the question. Thus, the algorithm searches for a variable rate mode, alternating with full rate regimes in those periods when the speaker pauses between words or sounds. Consequently, the processor may also increase the signal power if it detects data corruption indication or full rate likely indication following a full rate mode. The increment for which the processor increases the power upon detecting erasure indication or full rate likely indication following a full rate mode, do not necessarily have to be equal to the increment at which the processor increases the power failure mode data.

All the above and other features and advantages of the invention will become more apparent from the following description, appended claims and accompanying drawings.

The features, objects, and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the drawings that contain the same notation.

1 is a block diagram showing the present invention in the base station receiver of a cellular telephone system; Figure 2 - a generalized sequence of steps of an embodiment of the algorithm adjusting setpoint power level; 3 - 5 - detailed block diagram of an algorithm for adjusting the power level setpoint for the particular configuration of the velocity solutions.

In a cellular communication system with multiple access CDMA in which the nominal power of the system is a function of the subscriber capacity of the system in general, any reduction of mobile station power facilitates increasing nominal power of the system. The present invention provides a method and system for accurately and dynamically adjusting the mobile station transmitter power as a function of the communication link. By dynamically adjusting transmitter power of the mobile station can achieve higher nominal power system.

As shown in Figure 1, the present invention is used in the base station receiver of a cellular telephone system with multiple access CDMA. This transmitter is described in the aforementioned U.S. Patent and therefore is described here briefly. A mobile station (not shown) transmits a communication signal, typically a signal multiple access CDMA stretched with a frequency range, for example 1.25 MHz at one frequency band to the radio base station (not shown).

For a more clear understanding of the present invention provides a brief description of the coding information for the mobile station for transmission. In an exemplary embodiment, the subscriber data transmitted at different speeds, are encoded and formatted for transmission in data cycle duration, typically 20 msec. Subscriber data together with additional data cycle is preferably encoded forward error correction. The actual data rate in this example is 9.6 kbit / s (full rate), 4.8 kbit / s (half rate), 2.4 kbit / s (1/4 speed), and 1.2 kbit / s (1/2 speed). It should be noted that a constant symbol rate in cycles is preferred, but not mandatory.

This example uses razvertochnoe coding ratio of 1/3 to get the three characters for each category of user data, or additional discharge cycle. The cycle at full speed corresponding to the data rate of 9.6 kbit / s, is encoded in the amount of 192 bits of user data and further data cycle, forming 576 characters per cycle. For rate 1/2 cycle corresponding to a data rate of 4.8 kbit / s, 96 encoded bits in the amount of user data and further data cycle, forming 288 characters per cycle. Similarly, cycles with 1/4 and 1/8 speed, the respective data rates 2.4 and 1.2 kbit / s, is encoded in the amount of 48 and 24 bits of user data and further data cycle 144 and 72 form a symbol in the cycle respectively. It should be noted that groups of symbols are converted into a respective orthogonal function sequence or code group of orthogonal function codes according to the magnitude of the group of characters. In this embodiment, 6 binary symbols for the values ​​used to select one of 64 Walsh function sequences, each of length 64 chips. More details on this modulation scheme is described in the aforementioned U.S. Patent 5,103,459.

At the base station the signal is received by antenna 100 and shift to the radio receiver 102 for frequency downconversion and filtering. Analog-to-digital converter (ADC) 104 receives the analog spread spectrum signal from the radio receiver 102 and converts it into a digital signal. Correlator 106 psevdofluktuatsionnogo noise (PN) receives the digital signal and the PN code from the PN generator 108. PN correlator 106 performs a correlation process and provides an output signal to the digital processor for fast Hadamard transform or filter 110.

In the preferred embodiment, PN generator 108 for the multi-channel radio diversity generates a plurality of same PN codes with timing offset according to a particular channel signal. PN correlator 108 correlates each of the PN codes with a respective channel signal, generating respective orthogonal function symbol data. Filter 110 converts the orthogonal function symbol data into soft decision symbol data for each channel signal. Multichannel data symbols are then combined and passed as soft decision symbol data for decoding by the decoder 112 of subscriber data.

Filter 110, as part of the conversion process, it determines the amount of energy from each orthogonal function symbol of each channel signal. Taking into account the fact that each orthogonal function symbol is converted into a group of characters, the data quantity of energy from different channels are combined to obtain a corresponding symbol energy value. Filter 110, in addition to ensuring the decoder 112 soft decision data is also transmitted symbol energy value to power averager circuit 114.

Decoder 112 is typically a Viterbi decoder, receives the output data symbol soft decision from the filter and produces user data and decoder error metrics which are transmitted to the processor 116. The rate determination processor 116 may send the subscriber data to analog converter or other output circuitry (not shown) . Decoder 112 is described in more detail in copending US and only briefly described here.

Upon reception at the base station decoder 112 decodes each cycle with each possible rate and generates a corresponding group-set error metrics that characterize the quality of characters decoded from each speed. Error metric for each decoding rate include, for example, symbol error result based on re-encoding the decoded bits to produce re-encoded symbols that are compared with the received symbols and a Yamamoto Quality metric. Furthermore, for cycles at full speed and half speed control is performed on a cyclic redundancy check bits for the cyclic redundancy check bits in the additional cycle.

After decoder 112 has decoded each cycle, the processor 116 executes the rate determination is described in said US application, to determine the most probable rate at which the cycle has been encoded. This algorithm uses the error metrics provided by decoder 112 to estimate or decide the speed with which the cycle was transmitted data. Once processor 116 determines the data rate for the cycle, these data are interpreted by control bits included in each cycle, as the control or user data with the user data output for further use. Error metrics processor 116 determines whether the received data cycle data that were transmitted at full rate, 1/2 rate, 1/4 rate or eighth rate and generates a corresponding rate indication. This rate indication is transmitted to an external power control system 118, the functions of which are described in more detail below.

If the error metrics transmitted decoder 112, according to the processor 116 that the received loop was destroyed above the level at which a correction is possible via error correction techniques used in the decoder 112, the processor 116 does not decide the data rate for that cycle. Processor 116 in this case does not use or generate output for this cycle, this cycle counting cycle data destruction. The cycle of destruction, the processor 116 generates and transmits an indication of the destruction of the processor 118, indicating that it is impossible to determine the rate at which the cycle has been encoded.

If the error metrics generated by decoder 112 indicate to the processor 116 that the received cycle is disrupted cycle at full speed, which has been corrected by the decoder 112. Normally in this case the metrics indicate only that an error has occurred in the control redundancy. From this information, processor 116 determines that the most likely data rate in a given cycle is full rate and identifies the cycle as a cycle with probably full rate. Processor 116 uses or outputs the data as if it were data transmitted at full rate, provided that it may contain errors. For the cycle is probably full speed processor 116 produces a full rate likely indication, and transmits it to the processor 118.

Decisions about the speed and the detected error in the cycles can be used as an indicator of the power level at which the mobile station need transmit signals to maintain quality communications. In those cases where the number of cycles received from the speed or rate at which there is little erroneous cycles can reduce the transmitter power of the mobile station. This transmitter power reduction may continue until the error rate is not increasing to a level at which the quality may be affected link. Similarly, the capacity can be increased if the error had a negative impact on the quality of the link.

Upon receiving the rate indications from processor 116, processor 118 performs a new algorithm for adjusting the power level setpoint. This predetermined value is used, as described with reference to FIG. 1, a power generation command regulating the transmit power of the mobile station.

As mentioned previously, the filter 110 transmits the scaled symbol energy value to power averager 114. The power averager 114 sums or averages the scaled symbol energy value at an interval of 1.25 ms, i.e. in accordance with a group of six Walsh symbols or 36 data symbols, and transmits the received power level signal to comparator 120.

Processor 118 containing the appropriate internal counters, program memory and data memory, computes under program control setpoint signal power level, as will be described below, and sends it to comparator 120. Processor 118 may be located either at the base station through which the mobile station establishes communication or at a remote location, such as a mobile telephone switching office (not shown). In that situation, when a mobile station communicates through a plurality of base stations with power control, performed through this plurality of base stations, from a control point, the most convenient to place the processor 118 to the mobile telephone switching office. In those situations where processors 116 and 118 are located together, the function of these processors may be combined into a single processor.

Comparator 120 compares the received signal power level setpoint signal power level and outputs a deviation signal characterizing the deviation of the received power from the power level setpoint set by processor 118. Command Generator increase / decrease modnost 122 receives the deviation signal and generates either a power increase command, or command to reduce the power that the base station transmits to the mobile station (not shown). If the signal from power averager circuit 114 fall below the threshold level set by the setpoint signal power level deviation signal, generated by comparator results in the generation command to increase the power. And similarly, if the signal from power averager circuit signal exceed the power level setpoint, decrease power command is generated. These power commands are transmitted to the transmitter 124 where they are entered into the data transmitted to the mobile station. Spread spectrum transmitter modulates and transmits the modulated data via antenna 100 to the mobile station. Transmitter 124 typically transmits the CDMA division multiplexing on another frequency band than the mobile station transmission but is also extended frequency range, for example 1.25 MHz.

FIG. 2 shows a generalized diagram of the steps of the algorithm used to dynamically adjust the power level setpoint and thus indirectly to change mobile station transmitter power. The implementation of the algorithm seeks to implement reduction or increase of the mobile station transmitter power as a function of link quality based on the data rate different cycles. In such an implementation for changing the power level setpoint configuration is used the rate decision. Although an exemplary embodiment of the invention discloses solutions for use as an indicator of the rate configurations, nevertheless can be used and other parameters.

FIG. 2 to review the proposed group of one or more of the decisions on the frame rate (step 150). This group may consist of a set of rate decision cycle, arranged in series or in any other order, and / or may depend on the speed of the cycle. The group of rate decisions is analyzed to determine whether the configuration of this installed configuration solutions speed P1 (step 152). If a match is found the configuration change is made a predetermined power level (step 154). This measurement can be implemented in the form of increase or decrease the power level setpoint by a certain increment. Increase or decrease in the power level setpoint ultimately results in a corresponding increase or decrease in mobile station transmitter power. In those cases where the configuration solutions sovpadanie speed indicating satisfactory connection, the power level setpoint is increased, leading to the generation of commands: to reduce the power and, eventually, to a decrease in mobile station transmitter power. Similarly, in cases where the configuration solutions sovpadanie speed indicates a low quality communication link, the power level setpoint is increased, leading to the generation of commands: increase capacity and, ultimately, to an increase in mobile station transmitter power.

If a match occurs with a change in the configuration of the set value (steps 152 and 154), the decision of the rate is adjusted (step 156) and the process is repeated. A more detailed correction aspect of the present invention is discussed below.

If the determination of operation 152 configuration is not revealed sovpadanie configuration process can continue for several options. According to an embodiment can change the preset value of the power level (step 158), adjust the rate decision (step 156) and repeat the process. Preferably, the change in step 158 to distinguish from changes in step 154 ​​(increase to a decrease and vice versa), if detected sovpadanie configuration. It should also be noted that any setpoint adjustment, discussed herein can also be set to ensure that no change in the setpoint.

In a preferred embodiment, if the step of determining configuration 152 does not match the configuration is carried out for at least one additional step of determining the configuration. For example, analyzes the group of solutions of speed to determine if the configuration of the other set of configuration solutions rate P2 (step 160). If a match is found the configuration change is made a predetermined power level (step 162). This change may be an increase or decrease a given power level at a certain increment or a predetermined value is left unchanged. This increase or decrease in the power level setpoint ultimately results in a corresponding increase or decrease in mobile station transmitter power. As in step 152, where it is not detected sovpadanie configuration, if in step 160 no match configuration, the setpoint may be modified or left unchanged at step 164.

In that case, if in step 160 no match is found the configuration can generate additional configurations and determining coincidence setpoint changes. If under one of these definitions do not match the configuration of a match is found, made a final determination of a match or unspecified configuration. The group of rate decisions is analyzed to determine whether the configuration of another configuration of the solutions of fixed speed PN (step 166). If a match is found the configuration change is made a predetermined power level (step 168). This change may be in the form of increase or decrease the power level setpoint by a certain increment or a predetermined value is left unchanged. This increase or decrease in the power level setpoint ultimately results in an increase or a decrease in mobile station transmitter power. As in steps 152 or 160, where no match is found the configuration, if in step 166 no match configuration, the setpoint may be modified or left unchanged (step 170).

The process steps shown in FIGS. 2 are repeated with the corrected group of the rate decision in adjusting produced at step 156. This update can be a group of the previous group with the addition of solutions of the rate of a new cycle and removal of solutions of the speed of the old cycle using known methods of preservation. Alternatively, this group may be any desired set of rate decision.

It should be noted that the configuration chosen typically defines whether an increase or decrease in the power level setpoint. Increments increase or decrease the power level setpoint may be of different size for different coordination configurations, but they may also be of uniform size. Furthermore, the configuration of P1, as well as configuration and P2 - PN, may consist of a group of configurations to facilitate changes due to this configuration. Also, changing the set value, such as in step 154 ​​may be different depending on the configuration of the group configuration that matches the configuration of the determining step. It should also be noted that the predetermined value can be changed to a zero increment, where it remains virtually unchanged.

Using different definitions matching configuration provides more flexibility in adjusting the transmit power level of the mobile station depending on the quality of the communication link. In those cases where link quality is above the desired order to maintain reliable communications, transmission power may be reduced to the minimum required to maintain normal communication. Similarly, in cases where the line quality is lower than necessary for maintaining reliable communications, transmission power may be increased to the level necessary to maintain reliable communications.

FIG. 3 - 5 shows a detailed configuration example of solutions for speed adjustment control of the mobile station transmitter power. FIG. 3, if the cycle is the first cycle of a transmission, processor 118 (FIG. 1) initializes variables at step 200. Processor 118 sets "Setpoint," which represents the signal power level setpoint, an initial value for "starting setpoint." Processor 118 changes the setpoint signal power levels and ultimately the mobile station power level when it changes the variable "Setpoint."

Processor 118 provides counters "Full Rate Count" and "Erasure Count" representing the number of consecutive full rate indications and the number of indications of destruction of data, respectively. This counter is set to zero at step 200. The full rate mode consists of three consecutive full rate indications, failure mode data includes audio data and indicating failure mode consists of a variable speed audio indication 1/2 rate, 1/4 rate audio display or audio eighth rate indication. Processor 118 sets a logical variables "full speed mode", "failure mode data" and "Variable Rate Run," which characterize the state of the process, the value of "false" in step 200. The setting of these variables to "false" indicating the initial state of the process .

At step 202, processor 118 waits for the processor 116 will generate the rate decision. At step 204, processor 118 proceeds to step 206, if the "full speed mode" is set to "true", and to step 208 (FIG. 4) if it has the value "false".

At step 206, processor 118 branches to step 210 if the rate decision is a full rate indication and to step 212 if it is not a full rate indication. At step 210, processor 118 decreases "Setpoint" by an amount equal to the amount "delta-reducing full rate." At step 212, processor 118 branches to step 214 if the rate decision is a half rate indication, 1/4 rate or 1/8 rate, and to step 216 if the rate decision is an indication of the destruction of data or indication probably full rate.

At step 214, processor 118 sets "Full Rate Count" to "false", "Variable Rate Run" to a value "true" and "Full Rate Count" and "Erasure Count" to zero. At step 216, processor 118 increases "Setpoint" by an amount equal to a value "Delta larger full rate." After performing steps 210, 214 or 216, processor 118 returns to step 202 to wait for the next rate decision.

At step 208, processor 118 branches to step 218 if "Variable Rate Run" is set to "true", and to step 220 if it has the value "false". Proceeds to step 220 from step 208 is carried out by default if the indicator variable "failure mode data" is set to "true". At step 218, processor 118 branches to step 222 if the rate decision is a full rate indication and to step 228 if it is not a full rate indication. At step 222, processor 118 increments "Full Rate Count" and proceeds to step 224. At step 224, processor 118 branches to step 226 if "Full Rate Count" greater than three and to step 202 to wait for the next rate decision if "Account Full Rate Count "is less than or equal to three. At step 226, processor 118 sets "Full Rate Count" to a value "true" and "Variable Rate Run" to a value "false", and then proceeds to step 202 to wait for the next rate decision.

At step 228, processor 118 branches to step 230 if the rate decision is a half rate indication, one quarter rate indication, or an indication of rate 1/8 full rate likely indication, and to step 232 if the rate decision is an indication of fracture data. At step 230, processor 118 sets "Full Rate Count" and "Erasure Count" to zero and proceeds to step 202 to wait for the next rate decision. In step 230 "Setpoint" may also be reduced by an amount equal to a value "Delta variable speed reduction" in order to achieve more accurate control of the power level setpoint. In step 232, processor 118 increments "Erasure Count," sets "failure data" to "true" and "Variable Rate Run" to "false" and proceeds to step 202 to wait for the next rate decision. Furthermore, to achieve a more precise adjustment of the power level setpoint "Setpoint" may be increased by an amount equal to the "delta increase in the setpoint variable speed" at step 232. Then, processor 118 proceeds to step 202 to wait for new solutions to speed.

Proceeds to step 220 from step 208 occurs if the "variable rate mode" is set to "false" and "failure mode data" is set to "true" at step 232. While the state "failure mode data" is not used directly in step solutions to enter step 212, it is used in this example to identify the state in which the process. At step 212, processor 118 branches to step 234 if the rate decision is an indication concerning the full rate, and to step 236 if it is not a full rate indication. At step 234, processor 118 increments "Full Rate Count," sets "Variable Rate Run" to a value "true", "failure mode data" to the value "false", "Erasure Count" to zero, and then proceeds to step 202 to wait for the next rate decision. At step 236, processor 118 branches to step 238 if the rate decision is a half rate indication, one quarter rate indication, or an indication of rate 1/8 full rate likely indication, and to step 240 if the rate decision is an indication of fracture data.

At step 238, processor 118 sets "Variable Rate Run" to a value "true", "failure mode data" to the value "false", and "Full Rate Count" and "Erasure Count" to zero, and then proceeds to step 202 to wait for the next rate decision. At step 240, processor 118 increments "Erasure Count" and proceeds to step 242.

At step 242, processor 118 branches to step 244 if "Erasure Count" at least five. In step 244 "Setpoint" is increased by an amount equal to the amount "delta variable speed increase" and returns to step 202 to wait for the next rate decision. Adjusting the "Setpoint" in step 244 provides improved control of the power level setpoint after received several cycles of destruction of data.

However, if there are additional data destruction successive cycles, it is desirable to increase the setpoint by a greater amount to try to eliminate the occurrence of data destruction following cycles. At step 242, processor 118 branches to step 246 if "Erasure Count" is equal to or higher than five. At step 246, processor 118 increases "Setpoint" by an amount equal to the amount "delta-increasing destruction of data," and returns to step 202 to wait for the next rate decision. In the exemplary embodiment the value "Delta increasing destruction of data" above the value of "delta variable speed zoom."

According to an embodiment of the present invention, the adjustment "Setpoint" in step 244 may be omitted. If the "Erasure Count" is less than the value of the account at step 242, then it does not make any adjustment "Setpoint". As for the mode of data destruction cycles provided less control over the power level setpoint, it is desirable to reduce the count value to produce an earlier adjustment in step 246. For example, this value can be reduced to two or three.

In an implementation, power control algorithm, processor 118 initiates variables at step 200 and waits at step 202. The base stage receives the first transmission cycle and generates error metrics. Power averager 114 measures the power of the symbols at intervals of 1.25 ms, and adjusts its output every 1.25 milliseconds while the detector 112 decodes the cycle. Processor 116 produces a rate decision in response to the error metrics. After the processor 116 produces the rate decision, processor 118 branches via steps 204 and 208 to step 218 because the algorithm is initialized in the variable rate mode.

Cycles in the transmission of speech usually fluctuate between full rate and other rates, with continuous speech encoded at full speed. If, for example, processor 116 produces 1/8 rate indication in response to the first cycle, the processor 118 proceeds from step 218 to step 228, and then to step 230. Since this cycle is not any data destruction cycle, full speed or cycle, the processor 118 sets "Full Rate Count" and "Erasure Count" to zero. Processor 118 returns to step 202 to wait for the rate decision corresponding to the second cycle.

If, for example, processor 116 produces 1/4 rate initiated in response to the second cycle, the CPU 118 proceeds to other steps in the same manner as in the previous cycle. Similarly, if processor 116 produces 1/2 rate indication in response to the third cycle, the processor 118 also re-moves to the other stages. If processor 116 produces an indication of the 1/8 speed, 1/4 speed and 1/2 speed in response to the received cycle, the processor 118 does not change the power level.

If processor 116 produces a full rate indication in response to the fourth cycle, processor 118 branches via steps 208 and 218 to step 222 because the full rate indication follows a variable rate mode. At step 222, processor 118 increments "Full Rate Count," which will now be equal to one, and proceeds to step 224. At step 224, processor 118 returns to step 202 because there was no count three full rate indications.

If processor 116 produces a full rate indication in response to the fifth cycle, the processor 118 increments "Full Rate Count" as was described in connection with the fourth cycle. If the sixth cycle will cycle full speed again in steps 204, 208, 218 and 222, processor 118 increments "Full Rate Count". Since now the count three full rate indication, in step 224, processor 118 proceeds to step 226 and sets "Full Rate Count" to a value "true" and "Variable Rate Run" to a value "false". Next, the processor 118 returns to step 202.

If processor 116 produces a full rate indication in response to the seventh cycle, processor 118 branches via steps 204 and 206 to step 210 because the full rate indication follows a full rate mode. In step 210, the CPU 118 reduces the value "Setpoint". Next, the processor 118 returns to step 202 to wait for the next rate decision.

The comparator 120 compares the received signal power level, which is adjusted every 1.25 ms, with a setpoint signal power level, formed in accordance with the change of the value "Setpoint" and produces a deviation signal. If the received power level signal is unchanged or remains above the setpoint signal power level, comparator 120 generates a deviation signal to which the command generator 122 responds by issuing the command to reduce the power. The base station transmits this command to the mobile station, which reduces the power of the signal transmitted by it, in order to reduce the deviation signal.

If processor 116 produces an indication of corrupt data, or likely to full speed in response to the eighth cycle, the processor 118 proceeds to step 216 via steps 204, 206, 212, as follows data destruction cycle full speed. At step 216, processor 118 increases "Setpoint". Processor 118 returns to step 202 to wait for the next rate decision.

Comparator 120 again compares the received power level signal with the setpoint signal power level, formed in accordance with the value "Setpoint" and produces a deviation signal. If the received power level signal is unchanged or lower setpoint signal power level, comparator 120 generates a deviation signal to which the command generator 122 responds by issuing the command to increase the power. The base station again transmits this command to the mobile station which adjusts its transmitted power signal to reduce the deviation signal.

When the processor 118 is in the full speed mode, i.e. "Mode full speed" is set to "true", and the CPU 116 produces display full rate indication destruction of data or indication probably full rate, the processor 118 remains in the mode of full speed, and adjusts the power level as described above to optimize the power of the signal transmitted by the mobile station.

If processor 116 produces 1/2 rate indication in the ninth cycle, processor 118 branches through steps 204, 206 and 212 to step 214, in which the "full speed mode" is set to "true" and "full speed mode" is set to "False". Next, the processor 118 returns to step 202 to wait for the next rate decision. If processor 116 then issue a failure indication data in response to the tenth cycle, processor 118 branches through steps 204, 208, 218 and 228 to step 232. Processor 118 at step 232 increments "Erasure Count," which will now be equal to one, and sets "failure mode data" to "true", "variable rate mode" to "false", and optionally increases the "set point." Then, the CPU 118 proceeds to step 202 to wait for the next rate decision.

If processor 116 produces display data destruction in response to eleventh cycle, the processor 118 switches through steps 204, 208, 220 and 236 and to step 240, at step 240, increments "Erasure Count," and then proceeds to step 242. At step 242, processor 118 proceeds to step 244. At step 244, processor 118 increases the value "Setpoint". Processor 118 returns to step 202 to wait for the next rate decision.

If processor 116 produces an indication of fracture data for the twelfth and thirteenth cycles, the steps described above, in the eleventh cycle repeated. However, if the fourteenth cycle, processor 116 will give an indication of corrupt data, the processor 118 switches through steps 204, 208, 220 and 236 to step 242. In step 242, since "Erasure Count" is equal to five, processor 118 proceeds to step 246. At step 246 increases the value "Setpoint". Next, the processor 118 returns to step 202 to wait for the next rate decision.

Although the above-described processing example does not specifically describe each step of FIG. 3 - 5 can easily imagine other drawings according to these treatment options. Processor 118 continues to execute the power control algorithm as illustrated in FIG. 3 - 5, as long as it does not return to its original state at step 200.

Thus, this algorithm is initialized in state variable rate mode. The algorithm is not needed to upload the power level setpoint during full speed mode status. However, to achieve greater control over the power setpoint adjustment is made. The algorithm uses the variable rate mode state to enter either a full rate mode state if it detects three full rate indications or data failure mode if it detects a failure indication data.

After entering a full rate mode state algorithm increases the power level setpoint if it detects data corruption indication or full rate likely indication that leads to the development team to increase the power transmitted to the mobile station. Being able to full speed mode, the algorithm reduces the power level setpoint if it detects a full rate indication. If, while in the full rate mode state, the algorithm detects a half rate indication, one quarter rate or 1/8 rate is introduced condition the variable rate mode.

After entering a state of failure mode data from the mode status of the variable speed algorithm increases the power level setpoint if it detects data corruption. If, in a state of failure mode data, the algorithm detects a half rate indication, a rate 1/2 or 1/8 rate jumps to condition the variable rate mode.

In this exemplary embodiment, the relative sizes of the increments of change "Setpoint" are as follows. To increase the size change setpoint value "delta increase full rate" is the largest relative value followed by the value of "delta increase fracture data", then the value "delta variable speed increase." To reduce the size of the change "is set to" maximum relative value is the value of "delta-reducing full speed." In general, the size reduction of values ​​smaller than the predetermined setpoint increase.

It should be understood that various modifications of the example circuit in FIG. 3 - 5 which do not depart from the scope of the present invention. For example, since in an embodiment where the cycles and full-rate and half rate includes a cyclic redundancy check (CRC), the circuit in FIG. 3 - 5 do not require changes. On the other hand, since the cycles and full-rate and half rate have a CRC, half rate cycles to be regarded as a full-rate loops for the purpose of changing "Setpoint".

Although the invention has been described in the context of a cellular communication system with the CDMA channel allocation, it is equally applicable to other communication schemes and media in which digital data is transmitted in the form of loops. Consequently, the present invention is not limited to the communication scheme or secondary cellular communication system. For example, it can be used in systems such as cellular telephone, personal communications service (PCS), wireless local area network and private communication (PBX). Using the receiver specific configurations and different speeds of cycles determination cycles with errors for different configurations provides a flexible scheme for adjusting the transmission power to ensure a quality communication for the cycles of data transmitted at different speeds cycle. Furthermore, although the present invention and discussed with reference to the lack of information on the transmission cycle rate, and it is applicable to systems where the transmission rate information. In such cases, the quality of the signal can be used to assist in determining rate data for certain conditions, such as data destruction cycles or full rate likely.

DESCRIPTION OF PREFERRED EMBODIMENTS The proposed enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be apparent to, and the generic principles defined herein may be applied to other embodiments without creative efforts application. Accordingly, the present invention is not limited to the provided embodiments, and should be interpreted in the broadest scope in accordance with the disclosed principles and novel features.