Receiver for powerline carrier communication

The invention relates to systems and methods used for communications on electricity transmission lines, which require synchronization performed by a receiving device using multiple sampling rates. The system of the invention consists of a circuit-based apparatus for receiving data communications transmitted through distribution lines that carry electricity using alternating current, and includes a processing circuit configured and designed to receive an input signal that represents the data communications transmitted through the electricity distribution lines, to produce intermediate signals for each real and imaginary part of the input signal, to detect the limits of the symbol by processing the intermediate signals at a rate of: initial sampling, to reduce the initial sampling rate of the intermediate signals, according to a decimation rate, to filter the intermediate signals with a reduced sampling rate, to determine a timing mismatch between the detected limits of the symbol and the samples corresponding to the sample rate, and adjust decimation rate according to the timing delay inconsistency.

The method according to the invention uses the circuit-based apparatus for receiving data communications transmitted through distribution lines that carry electricity using alternating current.

Claims: 20

Figures: 11

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Fig. 1

Starting from the date of publication of the patent application, the application provides, provisionally; to the applicant, the protection conferred in accordance with the provisions of art.32 of Law no.64 / 1991, except in cases where the patent application has been rejected, withdrawn or considered As the scope of the protection conferred by the patent application is withdrawn it is determined by the contained claims in the application published in accordance with art. 23 aiin, (1) - (3).

<img file="RO130020A2_D0002.tif" />

RECEIVING DEVICE FOR COMMUNICATIONS ON TRANSPORT LINES

ELECTRICITY

ASSOCIATED PATENT DOCUMENT

STATE OFFICE FOR INVENTIONS IN MARK I ΓρrAfp ria hr avat Ha in van ti a

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This patent document claims the priority of US patent application 13/334538, filed on December 22, 2011, the content of which is fully included by reference.

TECHNICAL STAGE

Service providers use distributed networks in order to provide services to customers placed across large geographical areas. For example, electricity companies use electricity distribution lines to transport electricity from one or more power stations (power plants) to customers in residential or commercial complexes alike. Power stations use alternating current (AC) to transmit electricity over long distances through power distribution lines. Long distance transport can be achieved by using a relatively high voltage level. Substations placed near the locations where the customers are located lower the voltage level, more precisely the high voltage transforms it into low voltage (for example, using transformers). Electricity distribution lines carry this low alternating voltage from substations to consuming devices in locations where customers are.

Communications providers may use a distributed communications network to provide customer communications services. Similarly, energy companies use electricity distribution network networks, measuring devices, and other network elements to provide electricity to customers across the entire geographic area and to receive data from customers' locations including, but not limited to, customers. was limited to data representing the degree of utilization of the measured utility. However, data communication within a system that contains thousands of devices that represent end points of consumption, each communicating through power distribution lines, can be a particularly difficult problem. The large number of devices that represent end points of consumption contributes to a number of problems, including power processing at the end point of consumption, ^ "2014-00474

4 -12- 2012 memory size, interference and other concerns. For example, synchronization between an end point of consumption and a device transmitting downstream from the end point of consumption can be complicated by both these factors and others.

EXPOSURE OF THE INVENTION

The present invention relates to systems and methods used in conjunction with communications that require synchronization performed by a receiving device that uses multiple sampling rates. These and other aspects of the present invention are exemplified by illustrating a number of examples of implementations and applications, some of which are presented in figures and characterized in the following claims chapter.

Certain embodiments of the present invention refer to the decoding of data communications received by the devices that represent end points of consumption using reduced sampling rates for portions of the decoding process. A receiving circuit can be configured and designed to decimate an oversampled version of an input signal. A decimated version of the input signal can be used in conjunction with different signal processing functions. In accordance with the embodiments of the present invention, the over-sampled version may be used to determine the timing information that is used to provide synchronization by adjusting the decimation rate.

The embodiments of the present description are therefore directed to a device based on a circuit and to a method of using the apparatus. The device is configured together with a processing circuit to receive data communications through distribution lines that carry electricity using AC power. The processing circuit can be configured to receive an input signal that represents the data communications transmitted through the electricity distribution lines. The input signal can be represented by a modulated carrier wave operating at a given frequency. If desired, the input signal can be multiplied into the base band for signal processing. If the input signal uses quadrature modulation, then the intermediate signals can be used to separate a real part from an imaginary part of the input signal. The processor can then detect the limits of the symbol by processing the intermediate signals at a sampling rate (over-sampling).

C \ "2014-00474

4 -12- 2612 initial. Decimation is then performed to reduce the initial sampling rate of intermediate signals according to a decimation rate. Intermediate signals, now sampled at a low sampling rate, can then be filtered. As described here, decimating can be particularly useful in combination with filters to provide feedback (feedback), which may require more memory or processing for higher sampling rates. The processing circuit may then cause a timing mismatch between the detected limits of the symbol and the samples corresponding to the reduced sampling rate. The decimation rate is then adjusted according to the determined timing mismatch.

One or more embodiments of the invention are directed to a device based on a circuit used to receive data communications through distribution lines that carry electricity using AC (AC). The device has a processing circuit that is configured and designed to receive an input signal that represents the data communications transported through the power distribution lines. For a quadrature-encoded signal, the input signal is separated into intermediate signals representing a real part and an imaginary part. The processing circuit can then determine timing information from the real and the imaginary side. The intermediate signals can then be decimated according to a variable decimation rate, depending on the timing information determined. Decimal intermediate signals are also filtered.

Other embodiments are directed to devices based on circuits and to methods of using the devices for receiving data communications through distribution lines that carry electricity using AC (AC). The apparatus may include one or more processing circuits used (or co-configured and designed) to receive an input signal representing data communications transmitted through power distribution lines. Intermediate signals are obtained from a real part of the input signal and an imaginary part of the input signal. The limits of the symbol are detected by processing the intermediate signals at an initial sampling rate. The initial sampling rate of intermediate signals is reduced / decimated according to a decimation rate. The intermediate signals are then filtered at a reduced sampling rate. A timing mismatch is determined between

<img file="RO130020A2_D0004.tif" />

^ 2 0 1 4- 0 0 4 7 4 to 4 -12- 2012 the limits of symbol detected and the samples corresponding to the reduced sampling rate. The decimation rate is adjusted according to the determined timing inconsistency.

Various embodiments of the present invention are directed to a device having one or more circuits configured and designed to include or provide a first integrator configured to generate a first integration output representing the integration of the real part of the symbol. A second integrator is provided to be configured to generate a second integration output which represents the integration of the imaginary part of the symbol. Also, an indicator of signal strength is provided which is configured to determine a signal intensity from the first integration output and from the second integration output. A decimator controller is configured to generate a decimation control signal depending on the signal strength. A first decimator is configured to reduce a first sampling rate corresponding to the first integration output to a sampling rate that is controlled by a decimation control signal. A second decimator is configured to reduce a second sampling rate corresponding to the second integration output to a sampling rate that is controlled by a decimation control signal. Also included in the device is a comb-type filter configured to filter the output of the first decimator. A second comb type filter is configured to filter the output of the second integrator.

The above brief presentation of the invention is not intended to describe each embodiment or each implementation of the present invention. The following figures and detailed description, including what is presented in the claims chapter, set out in more detail some of these embodiments.

BRIEF DESCRIPTION OF THE FIGURES

Various embodiments of the present invention may be better understood by considering the detailed description which follows with the accompanying figures, which represent:

FIG. 1 shows a block diagram of one or more processing circuits, according to the embodiments of the invention set forth in the present description;

<img file="RO130020A2_D0005.tif" />

^2014-00474

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FIG. 2 shows a block diagram for a downstream receiving device (located at the end point of consumption), according to the embodiments of the invention set forth in the present description;

FIG. 3 shows a block diagram of a complex discrete Fourier transform (CDFT - complex discrete Fourier transform), in accordance with embodiments of the invention set forth in the present description;

FIG. 4A is a graph of the frequency response of a CIC (cascaded integrator comb - cascade of comb filter integrator) experimental filter for M = 1, according to the embodiments of the invention set forth in the present description;

FIG. 4B is a graph of the frequency response of a CIC (cascaded integrator comb - cascade of comb filter integrator) experimental filter for M = 3, in accordance with the embodiments of the invention set forth herein;

FIG. 5 shows a block diagram of an alternative CDFT, according to the embodiments of the invention set forth in the present description;

FIG. 6 shows an exemplary flow chart for how the implementation of processing and decoding of received symbols can be implemented, in accordance with the embodiments of the invention set forth in the present description;

FIG. 7 shows an exemplary flow chart for how a comb filter integrator cascade (CCIC) can be implemented, according to embodiments of the invention set forth in the present description;

FIG. 8 shows an exemplary flow chart for how the symbol synchronization can be implemented, in accordance with the embodiments of the invention set forth in the present description;

FIG. 9 shows an exemplary flow chart for how the degree of synchronization adjustment can be determined, in accordance with embodiments of the invention set forth in the present description;

FIG. 1OA is a graph of an over-sampled signal with a synchronization error, in accordance with the embodiments of the invention set forth in the present description;

FIG. 1OB is a graph of an over-sampled signal without synchronization error, according to the embodiments of the invention set forth in the present description; and

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FIG. 11 is a graph of an over-sampled signal, according to embodiments of the invention set forth in the present disclosure.

Although the description can be improved with various modifications and alternative forms, examples of them have been presented through the embodiments in the figures and will be described in detail. It should be understood that, however, the intention is not to limit the disclosure of the invention to the particular embodiments of the invention presented and / or described. On the contrary, the intention is to cover all the modifications, equivalences and alternatives that fall within the spirit and purpose of the disclosure of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Aspects of the present disclosure are considered to be applicable to a variety of different types of devices, systems and arrangements, including those that may be implemented for the purpose of providing synchronization correction. While this description is not necessarily limited to such applications, different aspects of the disclosure can be appreciated through discussion of different examples using this context.

Examples of embodiments of the present invention are directed to a method, device, system or device designed to facilitate the decoding of data communications received by the devices representing end-points of consumption. For example, a receiving endpoint circuit may be configured and designed to use an over-sampled version of a received signal for a first processing portion. The over-sampled version can be decimated to reduce the sampling rate for a second processing portion. Using a low sample rate can be particularly useful for reducing processing and / or storage requirements related to sample processing. For example, a component used for storage may operate with fewer operation-related requirements and a feedback component may operate with fewer storage / storage requirements. According to the embodiments of the present invention, the over-sampled version can be used to determine the timing information based on the decoding elements that operate based on the version of the reduced sampling rate of the input signals.

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4 -12- 2012

<img file="RO130020A2_D0006.tif" />

In several particular embodiments of the present invention, synchronization can be performed by adjusting the decimation rate. This allows a finer adjustment of the time at which the decoding elements of the symbol receive the samples (where the decoding elements of the symbol work using the reduced sample rate version of the signals). This is due to the fact that the decimation rate is connected to the time between the selected samples in the supersampled version.

Various embodiments of the present invention recognize that the information related to the symbol timing can be obtained from the over-sampled version without the existence of direct feedback from the symbol decoding process. Thus, the embodiments offer synchronization without the existence of a feedback loop related to the logical decoding of the symbol. More particular embodiments of the invention recognize that this timing information of the symbol can be obtained using an algorithm for detecting signal intensity following a mathematical integration of the real and imaginary parts of the over-sampled version of the signals.

The embodiments of the present description are, therefore, directed to a device based on a circuit and to the method of using the apparatus. The device is provided with a processing circuit and is configured to receive data communications through distribution lines that carry electricity using AC power. The processing circuit may be configured to receive an input signal representing the data communications transmitted through the power distribution lines. This input signal can be represented by a modulated carrier wave operating at a given frequency. If desired, the input signal can be multiplied into the base band for signal processing. If the input signal uses quadrature modulation, then the intermediate signals can be used to separate a real part from an imaginary part of the input signal. The processor can then detect the limits of the symbol by processing the intermediate signals at an initial sampling rate (over-sampling). Decimation is then performed to reduce the initial sampling rate of intermediate signals according to a decimation rate. Intermediate signals, now sampled at a low sampling rate, can then be filtered. As described here, decimation can be particularly useful in combination with filters to provide feedback (c 20 20 4 - ο Ο 474)

4 -12- 2012

<img file="RO130020A2_D0007.tif" />

feedback that may require more memory or processing for higher sample rates. The processing circuit may then cause a timing mismatch between the detected limits of the symbol and the samples corresponding to the reduced sampling rate. The decimation rate is then adjusted according to the determined timing mismatch.

For particular embodiments of the present invention, the filter is a comb type filter that uses a delay parameter. The delay parameter refers to the time when the signal information is stored and used for feedback during the filtering operation. For a given delay time, the amount of data stored is directly related to the sampling rate. Thus, if the sampling rate is low, the amount of data stored and / or processed as part of the feedback is also reduced.

Aspects of the present description acknowledge that, for a given sampling rate, decimation rate adjustments lead to a change in the time when decimated samples are selected / recorded. Thus, the timing of the decimation samples, corresponding to the input signal, can be adjusted by changing the decimation rate. The adjustment can be used to provide synchronization for subsequent decoding.

One or more particular embodiments of the present invention are directed to an apparatus which is based on a circuit for receiving data communications through the distribution lines that carry electricity using AC power. The device has a processing circuit that is configured and designed to receive an input signal that represents the data communications transported through the power distribution lines. For a quadrature-encoded signal, the input signal is separated into intermediate signals representing a real part and an imaginary part. The processing circuit can then determine timing information from the real and the imaginary side. The intermediate signals can then be decimated according to a variable decimation rate, depending on the timing information determined. Decimal intermediate signals are also filtered.

In accordance with certain embodiments of the present invention, the filter includes a feedback delay component and the timing information is determined using data obtained from the integration of the intermediate signals. in / 2 0 1 4 - 0 0 4 7 4

4 -12- 2012 some cases, the data obtained can be used to determine a received power level corresponding to a transmitted symbol.

In certain embodiments of the invention, the processing circuits may be configured and designed to be used in conjunction with a communication system that uses electricity distribution lines to communicate data between a control center and devices that represent endpoints of the invention. consumption using intermediate data collection nodes (data collection devices). This type of system can be particularly useful for metering reported consumption as well as for other functions. For example, data can be provided by power meters, gas meters and water meters, which are installed in the respective gas and water distribution networks. Moreover, while this description generally refers to endpoints of consumption as utility-related data providers (eg, power) to utility meters, and other types of data may also be communicated. The control center interface can be implemented using a variety of different communication networks that include, but are not limited to, a wide area network (WAN) using Ethernet.

In accordance with the embodiments of the present invention, each data collection device can be configured to communicate with thousands of consumer endpoints and there may be thousands of data collection devices connected to a control center. Thus, there may be millions of total final consumption points and many thousands of these final consumption points can communicate through a common power distribution line. Accordingly, embodiments, described herein, are directed to the communication, coordination and interpretation of data in relation to system restrictions. The following discussion provides an overview of different aspects of the system, being relevant to some of these restrictions.

End points of consumption can be designed to monitor and report various operating characteristics of the service network. For example, within an electricity distribution network, meters can monitor the power consumption characteristics of the network. Examples of features that define network power consumption include average or total power consumption, voltage drops, and load changes, among others. In gas and water distribution networks, meters can measure similar characteristics that are related to gas and water consumption (for example, total flow and pressure).

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<img file="RO130020A2_D0008.tif" />

The final consumption points report the operating characteristics of the network through the communication channels. In certain embodiments of the invention, the communication channels are represented by portions of the frequency spectrum. The central frequency and bandwidth of each communication channel may depend on the communications system in which it is implemented. In some implementations, the communication channels for utility meters (e.g., energy meters, gas and / or water) can be transmitted using communications networks that use electricity transmission lines that allocate the available bandwidth between endpoints according to a spectrum allocation technique based on multiple access with orthogonal division of frequency (OFDMA - orthogonal frequency division multiple access) or depending on another channel allocation technique.

When the final consumption points are implemented in connection with the energy meters in an electricity distribution network, the final consumption points report data that updates the information from the meters. Updated meter data may include total consumed power quantities, power consumption over a specific time period, peak hours power consumption, instantaneous voltage, peak voltage, minimum voltage, and other power consumption quantities. and power management (for example, charging information). Each endpoint may also transmit other types of data, such as status data (for example, operating in normal operating mode, emergency power mode, or other status such as a state of recovery following a power failure).

In some implementations, symbols (representing one or more bits representing reporting and / or status data) are transmitted through the power distribution lines over a specific symbol period. A symbol period is a period of time during which each symbol is communicated. A number of symbols are contained within a frame period, representing the time when a complete frame is transmitted, in which each frame provides synchronization for the symbols of the same data frame.

According to some embodiments of the present invention, the data collection devices are installed in substations and are used to control two-way communication with both the control center (for example, located at a distance

Ο 1 A - Ο Ο 4 7 4

4 -12- 2012 utilities office) as well as with the final consumption points (for example, located in customer monitoring locations). This exchange of messages with the end points of consumption can be sent individually only to a final point of consumption or it can be broadcast simultaneously to a group of end points of consumption connected with the data collection devices. According to certain embodiments of the invention, the data collection devices are designed in compliance with industrial specifications in order to withstand the harsh environmental conditions that are present within a substation.

Turning now to the figures, FIG. 1 shows a block diagram of one or more processing circuits, according to the embodiments of the invention set forth in the present description. According to certain embodiments of the invention, the components of FIG. 1 can be placed in a reception device, corresponding to a final point of consumption, configured to receive the communications made through the electricity transmission lines. An interface circuit 102 can provide the isolation function with respect to the high voltages present on the power distribution lines, while allowing the reception of data transmitted by one or more data collection devices. It may also include a filter to eliminate noise and harmonics generated by the AC power supplier present on the power distribution lines. Furthermore, in the case of quadrature modulation, the interface circuit 102 can separate the real part (Re) from the part (Im) of the received signal. In accordance with certain signal modulation schemes, these intermediate signals can be generated on the basis of a multiplicative (base band) version of the received signal.

The processing circuit (s) 104 and 108 provide functions associated with a high sampling rate (over-sampling) and with a low / decimated sampling rate. The over-sampled processing functions 110 and 112 can be performed both on the basis of the real and imaginary part of the intermediate signals. For example, the over-sampled processing 110 and 112 can provide an integration function based on the over-sampling rate. It produces an output signal that has an appropriate grain size / accuracy with the over-sampling rate.

The decimation elements 114 and 116 receive at the input the over-sampled output of the processing functions 110 and 112. respectively.

<img file="RO130020A2_D0009.tif" />

#-2014-00474

4 -12- 2012 sampling. The ratio between the sampled (above) input rate and the sampled (decimated) output rate represents the decimation rate for the decimation elements 114 and 116. This decimation rate can be adjusted, as set out in this description.

The sampling functions of the decimation operation 118 and 120 can then be performed at the outputs of the decimation elements 114 and 116. Aspects of the present invention are directed to the use of the sampling functions of the decimation operation 118 and 120 which reduce memory and / or processing when they use low sample rates. For example, the sampling functions of the decimation operation 118 and 120 may include, but are not limited to, a filter that uses a feedback component that stores previous samples. In certain embodiments, the filtration is represented by a comb type filter.

The decoding of the symbol 106 can be performed at the output of the sampling functions of the decimation operation 118 and 120. For example, the modulation scheme may use one of the techniques: QPSK quadrature phase shift keying, differential phase modulation (DPSK - differential phase shift keying) and frequency shift keying (FSK). The decoding of symbol 106 can be configured for demodulation accordingly. In a particular case, decoding symbol 106 may include a delta phase discriminator for detecting phase shifts.

The processing circuit (s) 108 may be configured and designed to generate synchronization information using the signal processing function 122. The signal processing function 112 receives the over-sampled signals from the processing functions 110 and 112 and uses this information to generate sync information. Synchronization information is used to determine a decimation adjustment 124. The decimation adjustment 124 is provided in the form of a decimation control to change the decimation rate of the decimation elements 114 and 116 in order to synchronize the received and processed signals specific to the circuits.

In certain embodiments of the present invention, the signal processing function 122 detects the limits of the symbol while the decimation adjustment 124 represents an adjustment made in order to align the limits of the detected symbol with the decimation sampling.

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<img file="RO130020A2_D0010.tif" />

FIG. 2 shows a block diagram for a downstream receiving device (located at the end point of consumption), according to the embodiments of the invention set forth in the present description. The receiver device is configured and designed to carry out the communication process in different multiple channels / frequency bands. As shown in the figure, a digital input signal is provided at the input floor 202 from the digital analog converter (CAD). The input floor may include several bandwidth (FTB) filters, each FTB having a frequency of passage corresponding to a particular communication channel. Frequency lowering converters 204 and 206 can be used to lower filtered signals according to an intermediate frequency (Fif). The frequency lowering converters 204 and 206 can also be configured to separate the real and the imaginary part of the input signal by mixing the cosine signal, respectively, the sinus signal.

According to certain embodiments of the invention, the sampling rate (or sampling frequency) of the digital analog converter (CAD) may be relatively high. This can be particularly useful for bandpass filtering and frequency lowering, processes that can be performed with relatively low processing and storage requirements for high sample rates. However, other types of functions may be prohibitively expensive for consumers at high sampling rates. Therefore, the frequency converters 204 and 206 can be configured to perform decimation operations in order to decrease the sampling rate. The particular example shown in FIG. 2 consists of a sampling rate of 480 Hz, although the receiving device and the relevant information displayed are not limited to this value of the sampling rate.

According to one embodiment of the present disclosure, harmonic filtering 214 may be performed in order to filter certain frequencies. These filters can be particularly useful for filtering harmonics that can be produced by the AC power provider. This AC frequency, and the resulting harmonics, can vary around a frequency of about 60 Hz in the United States and around a frequency of 50 Hz in Europe. However, these standards are relatively arbitrary and necessarily limit the various embodiments discussed here.

The processing blocks 208, 210 and 212 receive the outputs from the respective harmonic filters 214. For the PSK encoded symbols, these blocks

<img file="RO130020A2_D0011.tif" />

2014-00474

4 -12- 2012 processing provides ο delta phase discrimination, delayed recovery and symbol decoding. Several special functions include a complex discrete Fourier transform (CDFT) 216, a power determination 218, a phase detection 220, a symbol decoding 222 and a synchronization block 224. The CDFT block 216 provides signal processing and filtering used for decoding symbols. The CDFT block 216 also offers the decimation function which reduces the sampling rate. The particular example described in FIG. 2 represents a reduced sampling rate of 10 HZ, although the receiving device and the relevant information are not limited to this rate. Phase detector 220 detects modulations of the carrier wave phase corresponding to the input signal. The symbol decoder 222 decodes phase changes in order to generate the corresponding data. Determination of power 218 determines the power of the received signal measured by a combination of the real and the imaginary part of the signal.

Synchronization block 224 provides a control of the signal used to change the decimation rate of the CDFT block 216. Decimation rate adjustments lead to appropriate changes related to sample selection timing. In this way, the synchronization block 224 can adjust the timing of the working components using the reduced sampling rate.

In accordance with certain embodiments of the present disclosure, the synchronization block 224 receives the input from the CDFT block 216 prior to decimation to reduce the sampling rate. In the particular example of FIG. 2, this would correspond to a sampling frequency of 480 Hz. Accordingly, the timing block 224 can monitor the signal parameters using this higher sampling rate. Timing block 224 may use this information to detect signal boundaries. The synchronization block 224 may also receive the temporal data corresponding to the reduced sampling rate and determine the inconsistencies between the symbol limits and the reduced sampling rate. For example, the timing of the samples that are taken for the reduced sampling rate (determined by the decimator) can be synchronized with the phase detector 220 and / or with the symbol detector 222.

In more specific embodiments, the CDFT block 216 may include a filter circuit with an integration function operating at a higher sampling rate. Data from the integrator can be provided to the synchronization block

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224. Synchronization block 224 uses this data to detect symbol boundaries by, for example, monitoring signal strength.

The various additional charts and associated discussions set forth herein may refer to one or more embodiments of the present invention. These experimental embodiments may be useful in the sense that they provide different reference points and illustrative examples. However, the specifics of each experimental embodiment of the invention are not necessarily required in (or particularly relevant to) all embodiments of the present disclosure.

FIG. 3 shows a block diagram of a complex discrete Fourier transform (CDFT - complex discrete Fourier transform), according to to embodiments of the invention set forth herein. The CDFT block 302 receives the real (re) and imaginary (Im) portions of the data carrier signal. A transformation kernel transforms the real and imaginary parts. The kernel 304 works with the sampled signal with a first (over) sampling rate. The core (kernel) 304 is presented with the help of a particular combination of mixing and combining elements; however, this disclosure is not necessarily limited to this specific combination.

The output of the kernel 304 is transmitted to the filter block 306. In the embodiment of the invention shown in FIG. 3, the filter block 306 functions as a comb filter integrator cascade (CCIC). The CCIC filter includes decimation elements 310. The decimation elements 310 are configured and designed to provide a variable decimation rate depending on a value or an input / control signal. The integration function of the CCIC filter is performed before the decimation elements 310 and, therefore, operates at a higher sampling frequency. The function performed by the corresponding portion of the comb type filter of the CCIC filter is performed after the decimation elements 310 and, therefore, operates at a lower sampling rate. This can be particularly useful for simplifying / reducing the memory requirements for comb-type filtering because comb-type filtering includes a feedback component that uses previous values ​​as an integral part of the filter.

A signal value from the integration elements is sent to the synchronization and timing block of the symbol 308. The signal value ^ "2 0 1 4 - 0 0 4 7 4

4 -12- 2012 can be adjusted according to the feedback component of the comb filter, as shown by using the assembly symbol. Synchronization block 308 uses this information in order to generate a decimation element adjustment value. The decimation element adjustment value is provided to the decimation elements 310 using an input / control value / signal.

In certain embodiments of the invention, the adjustment value of the decimation element is calculated based on a mismatch between the end of the decimation section (defined according to the timings between the decimation samples) and the symbol timings (which can be determined by monitoring the received power of the signal. data carrier).

FIG. 4A is a graph of the frequency response of a CIC (cascaded integrator comb - cascade of comb filter integrator) experimental filter for M = 1, in accordance with the embodiments of the invention set forth in the present description. FIG. 4B is a graph of the frequency response of a CIC (cascaded integrator comb - cascade of comb filter integrator) experimental filter for M = 3, in accordance with the embodiments of the invention set forth herein. For each of FIGS. 4A and 4B, the data represented by the graph were generated using a sampling rate: fs = 480 Hz and a decimation rate of 48. The transfer function is represented in the following form:

<img file="RO130020A2_D0012.tif" />

<img file="RO130020A2_D0013.tif" />

As shown in the graphs, the experimental data suggest that M = 1 may provide better filtering characteristics; however, this disclosure is not limited to this. For example, different input characteristics and operating parameters may lead to other settings.

FIG. 5 shows a block diagram of an alternative CDFT, according to embodiments of the invention set forth in the present description. Similar to the CDFT example shown in FIG. 3, the example of CDFT in FIG. 5 includes a CDFT block 502, a transformation core (kernel) 504, a filter block 506, and a synchronization block 508. However, FIG. 5 also includes a low pass filter (FTJ) 510 and 512. These low-pass filters 510 and 512 can be used to filter &lt;^ • 2 0 1 4 - 0 0 4 7 4

4 -12- 2012 unwanted interference and harmonics. Unexpectedly, it has been found that filters passing down 510 and 512 cannot deliver beneficial results for certain applications. Therefore, the present disclosure deals with embodiments both with and without the use of filters passing down 510 and 512.

FIG. 6 presents an exemplary flow chart for how the implementation of processing and decoding of received symbols can be implemented, in accordance with the embodiments of the invention set forth in the present description. The flow chart can be implemented using one or more processing circuits, which can be configured and designed using, for example, software programmed instructions, hardware circuits and combinations thereof. The processing circuit (s) begin processing a particular channel in block 602. In certain embodiments, the processing circuit may be configured and designed to perform this multi-channel processing in parallel. For example, an OFDMA protocol may be used and the processing circuit may monitor several different frequencies for the OFDMA protocol.

In block 604, the processing circuit is configured and designed to perform a downward frequency conversion of the received signal. A description of the particular embodiment of the invention for a downward frequency conversion is presented in relation to the kernel in Figures 3 and 5.

In block 606, the processing circuit is configured and designed to perform a filtering function. A particular type of filtration is that of a comb filter cascade (CCIC). An example of implementing a CCIC filter processing circuit is shown in connection with FIG. 7.

The processing circuit determines, at block 608, whether or not the end of the symbol has been reached. According to the embodiments of the present invention, the end of the symbol is determined on the basis of a decimation counter. If the end of the symbol has been detected, then the processing circuit may attempt to decode the symbol in order to obtain corresponding bits of data, as shown in block 610. The processing circuit can process 612 bits appropriately and, if desired, calculate the symbol statistics in block 614. The statistics may include, but are not limited to, the average power of the symbol, average delta phase error and maximum delta phase error. If the end of a symbol is not detected, then further processing is performed before decoding the symbol. The process ends at step 616.

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FIG. 7 shows an exemplary flow chart for how a comb filter integrator cascade (CCIC) can be implemented, in accordance with embodiments of the invention set forth in the present disclosure. The processing circuit begins the filtration process at block 702 and then advances to block 704. At block 704 the processing circuit may add the following sample to an integrator. The samples at this point have a high (over) sampling rate. The processing circuit uses the oversampled output of the integrator to determine the signal power (OSPwr) at block 706. This determined power can be used to calculate the change in power that has occurred since the beginning of the current symbol. For example, to determine the power of the symbol from both the real part (ReOS) and the imaginary part (ImOS), the processing circuit may use the formula OSPwr = ReOS² + ImOS².

The processing circuit can then check, at block 708, whether or not the start of a symbol period has been reached. In certain embodiments, the symbol period is assumed to correspond to the timer sampling time of the decimator (a timing inconsistency is missing). The decimation function can be implemented by taking each N sample, where N = decimation rate ("DecimateBy"). For example, one decimation counter can be incremented for each sample received. Samples received are eliminated unless the decimation meter is equal to the decimation rate (or a multiple integer if the counter is not reset). A similar mechanism is assumed to be used in connection with flowcharts; however, different embodiments are not necessarily limited to such a specific implementation. Therefore, verification 708 can be performed by comparing the decimation counter with the decimation rate (DecimateBy).

If the beginning of a symbol is detected by the processing circuit, then the processing circuit will initialize the new symbol for the stored strings corresponding to each section per block 710. And the string index ("i") can be reset in block 712. The symbol-based sections correspond to the different sets of (above) excerpts within a symbol. For example, a decimation rate of 48 results in (over) sampling 1-48 being included in a symbol period. These samples can be divided into four sections 1-12, 13-24, 25-36 and 37-48. A string value (OSPwrMaxfi]) can be stored for each section (s).

<img file="RO130020A2_D0014.tif" />

or 2 Ο Η - Ο Ο 4 7 4

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The processing circuit checks, at block 714, the end of one of these sections. This verification can be done, for example, by comparing the decimator counter with a string value for the current section (OSPwrEnd [iJ). If the end of the current section has been reached, then the processing circuit prepares the next session (for example, by increasing the section I counter "per block 716).

In block 718, the processing circuit compares the calculated (current) power (OSPwr) with a maximum stored power value for the current section (OSPwerMax [iJ). The current value of power being higher than the previous maximum indicates that the power has increased. The current power value being lower than the previous maximum indicates that the preceding maximum is a peak / peak local value (for example, OSPwrMax [1] in FIG. 10).

When the current power value is not higher than the previous maximum, the processing circuit continues with block 728. At block 728, the processing circuit compares the current power (OSPwr) with a stored minimum power value corresponding to the current section (OSPwerMin [iJ) . The current value of power being lower than the previous minimum indicates that the power has decreased. The current value being greater than the previous minimum value indicates that the power is between the maximum and minimum current values ​​of the power.

If necessary, the processing circuit updates the minimum power (OSPwerMin [iJ) with the current power value (OSPwr) at block 730. The processing circuit also stores the decimator counter corresponding to the new minimum power value. Next, the processing circuit continues with the synchronization process 726.

When the current power value is increasing relative to the previous maximum power value, the processing circuit continues with block 720. At block 720, the processing circuit calculates a threshold value based on current power and a threshold. According to an embodiment of the present invention, OSPwrMaxLatchThreshold can be set based on a predetermined value. For example, a simulation can be used to model the transmission of test data frames and the resulting signals as well as the noise and harmonics of the power lines seen by the receiving device. The simulation results can then be used to select a value for OSPwrMaxLatchThreshold that reduces or minimizes mean delta phase error. in other situations, ^ “2014-00474

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<img file="RO130020A2_D0015.tif" />

OSPwrMaxLatchThreshold can be dynamically generated based on the current conditions of the power distribution line. Using a dynamically generated threshold can be particularly useful for adapting to changes; however, there may be a trade-off in processing resources. if the current power is considered sufficient (on the check made by block 722), the processing circuit updates the string values ​​for the current selection as shown in block 724.

FIG. 8 shows an exemplary flow chart for how the symbol synchronization can be implemented, in accordance with the embodiments of the invention set forth in the present description. The synchronization process can be entered once on each (over) sample. The processing circuit enters the synchronization flow at block 802 and then continues at block 804. At block 804 the decimation counter (DeciCount) can be decremented. For example, the counter can be initially set to the decimation rate and then decremented once with each (over) sampling until it reaches zero, indicating that a decimation rate must be provided. Consequently, the decimation counter reaches zero (determined in block 806), the processing circuit being able to assume that a new symbol period has begun. This type of method of targeting the decimation counter record is not meant to be limiting. For example, there are several different ways to keep track of decimation, including, but not limited to, counting to zero and / or detecting multiple integers of the decimation rate.

If the processing circuit determines if a new symbol period has not been reached, then it can exit the synchronization process at block 820. Otherwise, the processing circuit can reset the decimation counter to the current decimation rate (DecimateBy). , as shown by block 808.

For a CIC filter, the processing circuit may also update the comb filter in step 810. For example, the comb filter may use feedback based on the above values. These preceding values ​​may represent the decimated output of integration. As a result, the comb filter can be updated when a new decimated output is available.

Aspects of the present invention are directed to the communication protocols that use the synchronization of the symbols used by the receiving device. The receiving device may use the timing from these synchronized symbols to decode subsequent data symbols. in example # “2014-00474

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<img file="RO130020A2_D0016.tif" />

particular communication protocol shown in FIG. 8, the receiving device is configured to avoid the use of the first transmitted synchronized symbol. Thus, the first synchronization symbol is effectively omitted because it can be corrupted (for example, due to the internal adjustment of the clock of the receiving device). In addition, the second synchronization symbol is also problematic because the timing problems of the first synchronization symbol may still be present during the next decimation cycle. These omissions of synchronization symbols are represented by blocks 812 and 814. Within these blocks a synchronization counter (DoSynchCount) increases each period of the symbol and then the process exits when the counter value is less than 2.

Otherwise, the processing circuit can reset the synchronization counter (Do SynchCount) to block 816. Next, the processing circuit evaluates the values ​​of the OSPwr string to calculate the timing adjustment to block 818.

FIG. 9 shows an exemplary flowchart for how the degree of synchronization adjustment can be determined, according to embodiments of the invention set forth in the present disclosure. The processing circuit may enter process at block 902 to determine an adjustment value for the decimation rate, where the adjustment value is set to compensate for a timing mismatch. In block 904, the processing circuit initializes values ​​to be used during the process. One of these values ​​includes the value of the current section "i", which is used to index the previously stored string of values ​​for each section of the symbol current period.

In block 906, the processing circuit calculates the difference between the maximum power (OSPwrMax) and minimum power (OSPwrMin) for the current section. Block 908 is a check of whether or not the calculated difference exceeds a threshold value. If the threshold value is not reached, then the processing circuit will advance to the next section by increasing the current section value to block 914. Assuming there are multiple sections, check performed by block 916, the processing circuit will repeat the process for this section (s). Failure to comply with the threshold value will generally indicate that the maximum value is identical to the minimum (or close enough) value and therefore there is no synchronization error.

However, if the threshold value level is exceeded, then the processing circuit will check whether the power for the current section exceeds the power

0 1..4 - Ο Ο 4 7 4

4 -12- 2012 to the previous sections, as shown in block 910. If the previous sections have a higher power, then the processing circuit will advance to the next section by moving to block 914. otherwise, the processing circuit will update the maximum power and error synchronization to block 912. Thus, the processing circuit will use the synchronization error corresponding to the highest power.

Once all sections have been processed, the processing circuit uses the stored timing error to determine a decimation rate adjustment. For example, the adjustment value can be implemented as an adjustment of the start value for the decimation counter. Thus, when the decimator starts counting, it will start from a decimated rate value adjusted by the adjustment value. This changes the time at which the decimator provides a properly sampled output. A particular example of performing a decimator adjustment is shown in table 918. Table 918 includes numerator adjustments correlated with the synchronization error for a base decimation rate of 48. In this case, the synchronization error represents the value of the synchronization counter of to the largest OSPwrMax error point corresponding to the process described in FIG. 7. Once the error is determined, the process can end with block 920.

FIG. 10A is a graph of an over-sampled signal with a timing error, in accordance with the embodiments of the invention set forth herein. The dashed line represents the value of the power (for example, OSPwr = ReOS² + ImOS²). the whole graph corresponds to a complete decimation cycle. The peak power, indicated by arrow 1102, represents a likely limit point of the symbol. The end of the graph, indicated by the arrow 1104, represents the desired location of the limit point of the symbol. The location of arrow 1104 represents only 66% of the way to the end of the chart. Therefore, the graph in FIG. 10A represents 66% error.

FIG. 10B is a graph of an over-sampled signal without synchronization error, in accordance with the embodiments of the invention set forth in the present description. in FIG. 10B, the end of the graph and the peak of power coincide, as indicated by arrow 1106. This means the existence of synchronization or 0% error.

FIG. 11 is a graph of an over-sampled signal, according to embodiments of the invention set forth in the present disclosure. The dashed line represents the value of the power (for example, OSPwr = ReOS² + ImOS²). Vertical lines

Α'2014-00474

4 -12- 2012 dotted represents the separation points between the four sections 1-4. According to the various embodiments of the invention, discussed herein, a maximum (OSPwrMaxfiJ) and a minimum (OSPwrMin [i]) of power can be stored for each section "i". Decimation counter (DeciCount) can also be stored for each of the maximum and minimum power points.

Regarding section 0, the maximum and minimum powers represent the same value. Referring again to FIG. 7, the minimum value is set to the maximum value until and if the power starts to decrease after reaching the maximum power. Thus, FIG. 11 shows how the maximum and minimum powers are set to the same value, which coincides with the final section 0. Sections 2 and 3 are similar to section 0 where the values ​​for maximum and minimum are the same (although the values ​​differ for each section).

Regarding section 1, the maximum and minimum powers are not set to different values. They should also have different values ​​stored for their respective decimation counters (DeciCount [i]).

Referring again to FIG. 9, sections 2 and 3 will not be used to determine the synchronization error because DeltaOSPwr will not exceed the threshold value (for example, this would be zero). However, section 1 does not have a non-zero value for DeltaOSPwr. Assuming that this DeltaOSPwr value exceeds the threshold value, the maximum power of section 1 will cause the synchronization error. in the graph of FIG. 11, DeciCount for this maximum power is 34. The corresponding adjustment value in table 918 is 9. This adjustment value will then be added in order to change the decimator counter and thus compensate for the error.

The signals and associated logic and functionality described in relation to the figures can be implemented in several different ways. Unless stated otherwise, various systems based on processors and / or logic circuits may be used in conjunction with programs, as described in the present invention, or may prove to be more convenient to construct a more specialized apparatus to implement. applying the desired method. For example, according to the present disclosure, one or more methods may be implemented using wired circuits by programming a general-purpose processor, in another complete or semi-programmable logic circuit, and / or by a combination of such hardware elements. and a general purpose processor configured with software. In another embodiment, in certain embodiments

Λ- 2 Ο 1 4 - Ο Ο 4 7 4

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<img file="RO130020A2_D0017.tif" />

contexts, it must be recognized that a signal may be represented by one or more digital values ​​distributed between different software components or modules. Therefore, the various components and processes shown in the figures can be implemented in a variety of circuit-based forms, such as the use of data processing circuit modules.

It is recognized that aspects of the description may be implemented using computer / processor based system configurations, other than those expressly described herein. The structure required for a variety of these systems and circuits is evident depending on the applications envisaged and the above description.

People with experience in the field will use different terms and techniques above to describe communications, protocols, applications, implementations, mechanisms, etc. An example of such a technique is the description of the implementation of a technique expressed in terms of an algorithm or a mathematical expression. That is, while the technique may, for example, be implemented in the form of executable code on a computer, the expression of that technique may be succinctly transmitted and communicated, more precisely, in the form of a formula, algorithm or algorithm. mathematical expressions.

Thus, it is known that a block indicates "C = A + B" as an assembly function whose implementation in hardware and / or software involves two inputs (A and B) and returns an output (C), as in - a combinatorial logic circuit. Thus, the use of mathematical formulas, algorithms or expressions as descriptive elements must be understood as having a physical embodiment in at least one hardware (such as a processor in which the techniques of the present disclosure can be implemented and implemented. in the form of an embodiment).

In certain embodiments, the machine executable instructions may be stored for execution in a manner compatible with one or more of the methods set forth in this specification. The instructions can be used to make a general purpose processor or dedicated processor running the instructions perform the steps of the methods. Alternatively, the steps can be performed by hardware components that contain wired hardware logic dedicated to the steps or by any combination of programmed computer components and dedicated hardware components.

^-“ 2 0 1 4 - 0 0 4 7 4

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<img file="RO130020A2_D0018.tif" />

In some embodiments, aspects of the present description may be provided in the form of a computer program product, which may include a machine or computer read environment on which instructions may be used to program a computer (or other devices). electronic) for the purpose of carrying out a process, according to the present description. Accordingly, the computer-readable environment includes any type of computer-readable media / information medium suitable for storing electronic instructions.

The various embodiments of the invention described above are presented by way of example only and should not be interpreted with the purpose of limiting disclosure. Based on those discussed and presented above, persons skilled in the art will readily acknowledge that different modifications and changes may be made to this description without strictly respecting the examples of embodiments and the applications set forth and described herein. For example, such changes may include variations on how the decimator counter is updated and adjusted. Such modifications and changes do not depart from the true spirit and the scope of the present invention, set forth in the following claims.

<img file="RO130020A2_D0019.tif" />

α-2 O Η - OO 47 4

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