Loading method and apparatus for computer system

The present invention relates to personal computer systems, and in particular to a method and device for installing the BASIC input / output system (BIOS) in a personal computer system.

BACKGROUND OF THE INVENTION

Personal computers in general and

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IBM personal computers in particular have achieved widespread use to provide computer power to many segments of today's modern society. Personal computer systems can usually be defined as a desktop, laptop or desktop microcomputer consisting of a system unit having a single system processor, a display monitor, a keyboard, one or more floppy disk drives, a fixed disk memory and an optional printer. One of the distinguishing features of these systems is the use of a motherboard or planar system to electrically connect these components together. These systems are primarily designed to provide independent computing power to an individual user and are inexpensive for sale to individuals or small businesses. Examples of such personal computer systems are IBM's PERSONAL COMPUTER AT and PERSONAL SISTEM / 2 Models 25, 30, 50, 60, 70 and 80, also from IBM.

These systems can be classified into two general families. The first family, usually called Family I Models, uses a bus architecture, exemplified by IBM PERSONAL COMPUTER AT and other more IBM compatible. The second family, called Family II Models, uses IBM's MICROCHANNEL bus architecture, exemplified by IBM's PERSONAL SYSTEM / 2 Models 50 to 90.

Starting with Family I Models' oldest personal computer system, such as IBM's Personal Computer, it was recognized that software compatibility would be of the utmost importance. In order to achieve this, a code residing at the system isolation level, also called microcode, has been established between the hardware and the programming media. This code provided an operational interface between the user application system / operating system and the device to relieve the user from having to

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Concern with the characteristics of material media devices. Eventually, the code developed in the form of a BASIC input / output system (BIOS) allows new devices to be added to the system while isolating the application program from the peculiarities of the media. The importance of the BIOS has become immediately apparent because it frees a device driver from reliance on device-specific media characteristics while providing the device driver with an intermediate interface to the device. Because the BIOS was an integral part of the system and controlled the movement of data in and out of the system processor, it was resident in the planar system and was provided to the user in a fixed memory (ROM). For example, the BIOS on IBM Personal Computer had 8k of ROM residing in the planar board.

As new models of the personal computer family were introduced, the BIOS had to be updated and expanded to include new media and input / output devices. For example, with the introduction of IBM PERSONAL COMPUTER AT, the BIOS has grown to require 32 k-octets of ROM.

Today, with the development of new technology, Family II Models' computer systems have become even more sophisticated and are becoming available to consumers more often. As technology changes rapidly and new input / output devices are being added to personal computer systems, BIOS modification has become a significant problem in the personal computer system development cycle.

For example, with the introduction of IBM Personal System / 2 with MICROCHANNEL architecture, a significantly significant BIOS (ABIOS) has been developed. However, to maintain the compatibility of the software, it was necessary to include the BIOS of the

Family I Models at Family II Models. The Family I BIOS has become known as Compatibility BIOS or CBIOS. But, as explained above with respect to IBM PERSONAL COMPUTER AT, only 32 K-octets of ROM resided on the planar card. Fortunately, the system could be extended to 96 k-octets of ROM. Unfortunately, due to system limitations, this has become the maximum available capacity for the BIOS. Luckily, even with the addition of ABIOS, ABIOS and CBIOS can still be squeezed to 96 k-octets of ROM. However, only a small percentage of the 96-byte ROM area was still available for extension. With the addition of future input / output devices, CBIOS and ABIOS would exit out of ROM space. Thus new media technology 1/0 could not be easily integrated into CBIOS and ABIOS.

Due to these problems, plus the desire to make changes to the Family II BIOS as late as possible in the development cycle, it became necessary to download parts of the ROM BIOS. As marketability and consumer acceptance of the personal computer system seems to require the ability to add 1/0 devices and minimize costs, it will be understood that easy modification of the Family II Models BIOS is a substantial factor for success. according to the present invention. Thus there is a need for the development of a process and apparatus that allows portions of the BIOS to be stored in a direct access memory device, such as a fixed disk or floppy disk drive. These parts can then be easily modified and loaded into the personal computer system as needed.

Summary of the invention

The present invention has been developed with a view to solving the above problems: Accordingly, the present invention has as its object an apparatus and a process for increasing the number of device BIOS media by storing a portion of the

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BIOS on a direct access memory device.

Another object of the present invention is to provide an apparatus and method for loading the BIOS of a direct access memory device into main memory.

Still another object of the present invention is to provide an apparatus and method for confirming compatibility between the BIOS and the personal computer system.

Another object of the present invention is the ability to verify system configuration before loading the BIOS from the direct access memory device.

In broad terms, a personal computer system according to the present invention comprises a system processor, a random access main memory, a read only memory and at least one direct access memory device. Read-only memory includes a first part of the BIOS. The first part of the BIOS initializes the system processor and the direct access memory device to read a master program loader register from the direct access memory device to random access memory.

The master boot record includes a data segment and an executable code segment. The data segment includes data representing the material assets of the system and a system configuration that is supported by the main initial program loader register. The first part of the BIOS confirms that the master initial program loader register is compatible with the system's media by verifying that the data segment data in that register matches the data included in the first part of the BIOS it represents.

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system processor, flat system and configuration 1/0.

If the main program loader register is compatible with the system media, the first part of the BIOS directs the system processor to execute the executable code segment of that register. The executable code segment confirms that the system configuration has not changed and loads the rest of the BIOS from the direct access memory device to random access memory. The executable code segment then verifies the authenticity of the remaining BIOS portion and directs the processor the system to start BIOS execution now in random access memory. The BIOS, which runs in random access memory, boots the operating system to begin operation of the personal computer system. The first part of the BIOS, which is no longer addressable and was relegated by the rest of the BIOS, is abandoned.

Brief Description of Drawings

The main features and other features of the present invention are explained in the following description, made with reference to the accompanying drawings, which figures represent:

Fig. 1 is a partial cross-sectional view of a personal computer system showing a planar frame of the system connected to a number of direct access memory devices;

Fig. 2 is a block diagram of the personal computer system of FIG. 1;

Fig. 3 is a map of the ROM BIOS included in the planar board;

Fig. 4 is a flowchart describing the overall process of loading the BIOS image from a device 6.

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direct access memory memory;

Fig. 5 is the format of the registers of the main initial program loader;

Fig. A is a flowchart describing the operation of the ibl routine.

Fig. 6B is a flowchart showing the stages for loading a BIOS image from a fixed disk;

Fig. 6C is a flowchart of the phases for loading the BIOS image from a floppy disk;

Fig. 6D is a flowchart showing in more detail verification of compatibility between the master initial program loader register and the planar / processor board; and

Fig. 7 is a flow chart showing the operation of the executable code segment of the main initial program loader register.

Description of a preferred embodiment

The following description is that of the currently considered best embodiment of the present invention. This description should not be taken in a limiting sense, but only for purposes of illustration of the general principles of the present invention, since the scope thereof is better defined by the appended claims.

Referring now to the drawings and in particular to FIG. 1 shows a cross-sectional version of a personal computer system (10) with a number of direct access memory (DASD) devices (12 to 16) connected to a system board or planar board (24). through a number of output input slots (1/0) (18). A power source 22 provides electrical power to the system 10 in a well known manner. 0 The quad-plane 24 includes a system processor, which functions under the control of computer instructions, to input, process and output information.

In use, the personal computer system 10 is primarily designed to provide independent computing power to a group of users or a single user and is priced sufficiently low to be marketable to individuals or small businesses. In operation, the system processor runs on an operating system such as OS / 2 Operating System or IBM PC-DOS. This type of operating system includes a BIOS interface between DASD (12-16) and the operating system. A portion of the BIOS, divided into modules by function, is stored in ROM memory in the planar board 24, hereinafter referred to as ROM-BIOS. 0 BIOS provides an interface between the media and the operating system programming means to enable a programmer or user to program their machines without a thorough knowledge of the operation of a particular device. For example, a BIOS floppy module allows a programmer to program the floppy disk drive without a thorough knowledge of the floppy disk drive material equipment. Thus, a number of floppy disk drives designed and manufactured by different manufacturers in the system may be used. This not only reduces the cost of the system 10 but also allows a user to choose from a number of floppy disk drives.

Before referring to the structure prior to the present invention, it is worth briefly reviewing the general operation of the personal computer system (10). With reference to fig. 2 shows a block diagram of the personal computer system (10). Fig. 2 represents components of the planar board 24 and its connection to slots 1/0 (18) and other material equipment of the personal computer system. Situated in the planar board (24) is the system processor (26) consisting of a microprocessor which is connected by a local bus line (28)

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to a memory controller (30), which is further connected to a random access memory (RAM) (32). While any suitable microprocessor may be used, a suitable microprocessor is 80386, sold by INTEL.

Although hereinafter the present invention will be described with particular reference to the block diagram of the system of FIG. 2, it should be understood at the beginning of this description that the apparatus and processes according to the present invention may be used with other equipment configurations. planar framework materials. For example, the system processor could be an inter 80286 or 80486 microprocessor.

A processor planar ID number is accessible by the processor. The Planar ID is unique to the planar frame and identifies the type of planar frame being used. For example, the Planar ID may be materially cabled to be read through a system processor port 1/0 using switches.

The local bus line 28 is then connected via a bus controller 34 (CNTL BUS) to a read-only memory (ROM) (36) in the planar frame (24). An additional non-volatile memory (NNVRAM) (58) is connected to the microprocessor (26) via a serial / parallel port interface, which is further connected to the bus controller (34). Nonvolatile memory can be auxiliary battery CMOS to maintain information whenever the system power is turned off. Since ROM is normally resident in the planar frame, values ​​from the model and submodel stored in ROM are used to identify the system processor and system planar frame configuration 1/0 respectively. Thus, these values ​​will physically identify the processor and planar frame I / O configuration. NVRAM memory is used to store system configuration data, ie NVRAM will contain values ​​that describe the present system configuration. For example, NVRAM contains information that describes the capacity of a disk or floppy disk.

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determined, the type of display device, the amount of memory, the date, etc. In addition, the model and submodel values ​​stored in ROM are copied to NVRAM whenever a special configuration program such as a SET Configuration is executed. The purpose of the SET Configuration program is to store values ​​that characterize system configuration in NVRAM. Thus for a system that is properly configured, the model and submodel values ​​in NVRAM will be equal to the model and submodel values ​​stored in ROM respectively. If these values ​​are not equal, this indicates the system configuration has been modified. Referring to FIG. 6D, where this feature, in combination with the BIOS load, is explained in more detail.

Continuing our discussion with reference to fig. 2, bus controller 34 is further coupled to slots 1/0 (18), serial / parallel interface (40) and peripheral controller (42) by a planar frame bus 1/0 (43) . The peripheral controller (42) is further connected to a keyboard (44), a mouse (45), a diagnostic panel (DIAG PAN) (47) and the floppy disk controller (64). In addition to the NVRAM memory (58), the serial / parallel interface (60) is further connected to a serial port (48) and a parallel port (50) for input / output of information to a printer, device. of permanent copies, etc. As is well known in the art, local bus 28 may also be connected to a cache memory controller (CACHE CNTL) 52, a cache memory 68, a coprocessor 54 and a controller direct memory access (DMA) (56).

The system processor (26) controls its internal operation as well as the interfaces with other elements of the personal computer system (10). For example, processor system 26 is shown connected to a system interface of a small computer SCSI.

System Interface) of the planar card 1/0 (60), which is further connected to a DASD, such as a fixed disk drive (62). It should be understood that another fixed disk drive other than a SCSI may be used as a fixed disk according to the present invention. In addition to the fixed disk (62), the processor system (26) may interface with the floppy disk controller (64), which controls a floppy disk drive (66). With regard to thermonology, it is also to be understood that the term hardfile designates the fixed disk drive (62), while the floppy term refers to the floppy drive (66).

Prior to the present invention, ROM 36 could include all BIOS code that interfaces with the operating system for the peripherals of the material equipment.

According to one aspect of the present invention, however, ROM 36 is adapted to store only a portion of the BIOS. This step, when executed by the system processor 26, introduces, from either the fixed disk (62) or the floppy disk (66), a second or remaining portion of the BIOS, hereinafter also referred to as a BIOS image. . This BIOS image replaces the first part of the BIOS and, being a ί,,! integral part of the system, and resident in main memory, i! such as RAM (32). The first part of the BIOS (R0M-BI0S) as stored in ROM 36 will be explained generically with reference to FIGS. 3 and 4 and in detail with reference to FIGS. 6A to 6D. The second part of the BIOS (BIOS image) will be explained with reference to fig.5 and the loading of the BIOS image with reference to fig. 7 Another advantage of loading a BIOS image from a DASD is the ability to load the BIOS directly into system processor RAM (32). Because RAM access is faster than ROM, a significant improvement in the computer system's processing speed is achieved.

The description will now proceed with the operation of the BIOS in ROM (36) and the operation of loading the BIOS image from either the fixed disk or floppy disk. In general, ROM-BIOS pre-checks the system and loads a boot record of the main BIOS startup program into RAM. The master boot record includes a validation information data segment and a code segment that has executable code.

executable code uses data information to validate material equipment compatibility and system configuration. After testing the hardware compatibility and proper system configuration, the executable code loads the BIOS image into RAM. The BIOS image succeeds ROMBIOS and loads the operating system to start machine operation. For the sake of clarity, the executable code segment of the master boot loader registry will be referred to as MBR code, while the data segment will be referred to as MBR data.

With reference to fig. 3 shows a memory map showing the different modules of the code that make up the ROM-BIOS. The ROM-BIOS includes an Epergia Binding Stage I (Stage I POST) module (70), an initial BIOS load routine (IBL) module (72), a floppy disk module (74), a hard disk module (74), a video module (78), a diagnostic and data module (80) of material equipment compatibility. In summary, module 70 (Stage I POST) performs pre-boot and system tests. The IBL routine (72) determines whether the BIOS image should be loaded from disk or floppy disk, checks compatibility, and loads the main boot loader log.

diskette module (74) provides input / output functions for a diskette driver. The hard disk file module 76 controls the inputs / outputs for a fixed disk or the like. Video module (78) controls output functions for a video 1/0 controller that is still connected to a viewer. The diagnostics panel module (80) provides control for a system diagnostics display device. Physical equipment compatibility data 82 includes values ​​such as model and submodel values ​​which are described below with reference to FIG.

Referring now to FIG. 4 shows an overview of loading a BIOS image into the system from a fixed disk or floppy disk. When power is applied to the system, the system i processor is oriented to the entry point of Stage I POST (phase (100)). Stage I POST boots the system and tests only the system functions required to load the BIOS image from the chosen DASD, stage (102). In particular Stadium I POST initializes. processor / planar board functions, diagnostics panel, memory subsystem, interrupt controllers, time distributors, DMA subsystem, fixed-disk BlOS subroutine (module (76), hard disk file) and the BlOS-floppy routine (module (74), floppy), if necessary.

After Stage I POST boots the system, Stage I POST directs the system processor to the initial BIOS Load (IBL) included in module (72) Initial Load. The IBL routine first determines if the BIOS image is stored on a fixed disk or if it can be loaded from a floppy disk, and secondly it loads the main program loader register from the chosen media (disk or floppy disk) to RAM (phase (104)). 0 Main program loader registration includes MBR data and MBR code. MBR data is used for verification purposes and MBR code is executed to load into the BIOS image. A detailed description of the operation of the IBL routine is given with reference to FIGS. 6A to 6D.

Continuing with reference to fig. 4, after the IBL routine loads the main program loader register in RAM, the system processor is oriented to the MBR code starting address to begin execution (phase (106)). The MBR code performs a series of validity tests to determine the authenticity of the BIOS image and to verify system configuration. For a better understanding of the operation of the MBR code, fig. 7th of the drawings, in which the MBR code is described in more detail.

Based on these validity tests, the MBR code loads the BIOS image into RAM and transfers control to the newly loaded BIOS image in main memory (step 108). In particular, the BIOS image is loaded into the address space previously ROM-BIOS, ie if ROM-BIOS is addressed from EOOOOH to FFFFFH, then the BIOS image is loaded into this RAM address space, thus replacing ROM-BIOS. 0 Control is then transferred to POST Stage II, which is included in the newly loaded BIOS image, leaving ROM-BIOS. POST Stage II, now loaded into RAM, initializes the test the remaining system to load the operating system initial program loader, phase (110). After the system is initialized and tested, Stage II POST transfers control to the operating system initial program loader to load the operating system, stages (112-114). It is noted that during a hot start, the processor is oriented towards phase 108, shorting phases 100-106.

For clarity, it is appropriate at this time to illustrate a representation of the main initial program loader register format. (MBR). The MBR includes executable code segment (120) and data segments (122-138). 0 MBR code (120) includes the DASD-dependent code responsible for verifying the ROM-BIOS identity, verifying that the initial program loader IBL record is compatible with the system, verifying the system configuration and loading the BIOS image from DASD (disk or floppy) you choose. Data segments 122-138 include information used to define the media, identify and verify the registration of the main initial program loader, locate the BIOS image, and load the BIOS image.

The registration of the main initial program loader is identified by a signature of said Register (122). The main program loader register signature 122 may be a single bit pattern, such as an ABC string, in the first three octets of the register. The integrity of the main program loader register is tested by a checksum value (132), which is compared to a calculated checksum value when loading the initial program loader register. The data segments further include at least one compatible planar frame identification (ID) value (134) and compatible model and submodel values ​​(136). 0 planar frame ID value of the first main program loader register defines which planar frame the main program loader register is valid for. Similarly, the values ​​for the master boot load register model and submodel respectively define the processor and 1/0 configuration of the planar frame for which the master boot load register is valid. It has been noted that the Master Starter Charger Registration checksum signature and number identifies a valid Starter Charger Register, while Master Starter Charger Registration Card ID comparisons are used. , the registry model, and sub-model to identify a system-compatible main initial program loader record to determine if the system configuration is valid. Another value, the initial program loader register default (124), is used to determine the validity of RAM-BIOS. The MBR default (124) is compared to a corresponding value of the standard stored in ROM. If both values ​​agree, it indicates that a ROM-BIOS has started loading a BIOS image from the selected media.

The following description further describes each of the values ​​in the main program loader register and their functions:

MBR Identifier (122); _The t_rg_s The first octets of the IBM main program loader register can consist of three characters, such as ABC. This signature is used to identify a boot record ..... of the main starter program.

MBR Code Segment (120): This code verifies the compatibility of the initial program loader register with the planar frame and the processor by comparing the corresponding planar frame and model / submodel identification values. If these values ​​match, it will load the BIOS image of the chosen media into system RAM. If the system image checksum (BIOS image loaded in memory) is valid and no media load errors occur, the MBR code transfers control to the system image POST Stage II routine.

MBR Standard (124): ₀ P_ri_mei_ro main program loader register data segment field contains a pattern, such as a ROM-BIOS 1989 string This string is used to validate ROM-BIOS by comparing the value of the initial program loader register standard with the corresponding value stored in ROM (ROM boss).

MBR Version Data (126): θ _regi_sThe main starter loader includes version data for use by an update device.

System Shared Area Address Indicator (128): The data segment contains a media address indicator for the beginning of the media system sharing area for use by Stage IIPOST. On an IBL diskette, the address indicator has the track-head-sector format; On disk, the address indicator has the format RBA (Relative Block Address).

System Share Type (130): The system share type indicates the system share structure of the recording media. There are three types of full, minimal and non-present system sharing structures. The complete system share contains, in addition to precisely the BIOS image and main program loader registration, the preparation and diagnostic service. Minimal system share precisely contains the BIOS image and the boot record of the main boot program. It may happen that a system does not have access to a hard disk file with an NBL image. In this case the system share type indicates not present. Then IBL will be made from a floppy disk. These three types of system sharing allow for some flexibility in the amount of space that system sharing occupies on the media.

Checksum value (132) z The checksum value is initialized to generate a valid checksum for the register length value (.5 K-octets) of the main program loader register code .

Planar Frame ID Value MBR (134) s The data segment includes a value, such as a word string defining compatible planar frame IDs.

Each word consists of a 16-bit planar frame identifier and the sequence ends at the word value zero. If an identification of a system planar table agrees with the identification value in the main initial program loader register, such as one of the words in the sequence, the IBL media image is compatible with the system planar table. If the identification of the system planar frame does not agree with the word in sequence, the IBL media image is not compatible with the system planar frame.

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MBR Model and Submodel Values ​​(136): The data segment includes values, such as a word sequence, that define compatible processors. Each word consists of a model and submodel value and the sequence ends with a word value of zero. If a system model and submodel value (stored in ROM) agrees with the words in the sequence, the IBL media image is compatible with the system processor. If the ROM model and submodel values ​​do not agree with any word in the sequence, the IBL media image is not compatible with the system processor.

MBR map length (138); The MBR map length is initialized to the number of media image blocks.

In other words if the BIOS image is split into four blocks, the map lengths will be four, indicating four indicator / block length fields. Usually this length is set to 1 since the media image is a contiguous 128K block.

Media Sector Size MBR (138): This word value is initialized to the media sector size in octets per sector.

Media Image Block Address Indicator (138): This indicator locates a system image block in the media. Usually there is only one indicator as the media image is stored as a continuous block. On an IBL floppy disk, address indicators have the track-head-sector format; On disk the indicators have the relative address format of the block.

Media image block length (138): Media image block length indicates the size (in sectors) of the blocks located at the corresponding image block indicator. For a contiguous 128K media image that includes space for BASIC, this field is set to 256 sectors (512 octets / sector) starting at the indicator site

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of the media image block.

Referring now to FIGS. 6A to 6D, there is a detailed flow diagram of the operation of the IBL routine. Under normal conditions, the IBL routine loads the main initial program loader register from the system fixed disk to the RAL at a specific address, and then directs the system processor to start execution of the program loader register code segment. main initial. The IBL routine also contains measures to take for the malfunctioning floppy disk operating model in which the master boot record can be loaded from a floppy disk. However, the IBL routine does not allow this mode of operation if the system contains IBL media on the system fixed disk and a valid password is present in NVRAM. The user has the option to set the password in NVRAM. The purpose of preventing malfunctioning floppy disk operation is to prevent the loading of an unauthorized BIOS image from the floppy disk. In other words. Said mode of operation is used only when a fixed system disk is not operational and the user has indicated (by setting the password) the desire to be able to load from the diskette. If the IBL routine cannot load the main program loader register from either means an error message is generated and the system is stopped.

Referring now to FIG. 6A, under normal circumstances the system will contain a fixed system disk that the IBL routine initializes (phase 150). Suppose, for illustration purposes, that the fixed disk is set to Drive C of the personal computer system. Similarly, suppose Drive A is designated as a floppy disk device. The IBL routine then examines Drive C to determine if it contains IBL media, phase (152). Attention is drawn to fig. 6B, which describes this process in detail. The routine

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/!

IBL begins reading from the fixed disk in the last three sectors and continues reading by decrementing the media address indicator to 99 sectors or until a valid main program loader register is found.

If a valid record of the main initial program loader is found, it is checked for planar and processor system phase (156) compatibility. If it is not compatible with the planar frame or processor then an error, phase (158) is reported. Returning to step 152, if no valid master program loader record is found in the last 99 fixed disk sectors (primary hard disk file), an error, step 154 ​​is reported.

Returning to step 156, if a master boot loader registration has been found, a series of validity checks are performed to determine if the master boot loader registration is compatible with the computer system. Additionally, the system configuration will be checked. Attention is drawn to fig. 6D which presents this process in more detail. If the master boot loader registration is compatible with the planar frame ID, model, and submodel, and in addition the system configuration has not changed, the master boot loader registration is loaded and the code entry segment of the main initial program loader phase (160) is executed.

Returning to steps 154 and 158, if an error occurs in the loading of the main program loader register load from the fixed disk or, if a fixed disk is not available, the IBL routine determines if a word is included. pass code valid in NVRAM, phase (162). This password determines whether the BIOS image can be loaded from a floppy disk. Note that the password exists only after it has been installed by the user who passes a staging service. If you are

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If a password is installed in NVRAM, the BIOS image is prevented from loading from floppy disk, stage (164). This allows the user to ensure the integrity of system operation by having the system load only with the BIOS image on the hard disk. The password may take the form of a string stored in NVRAM.

Returning to step 162, if a valid password is not present in NVRAM, thereby allowing the BIOS image to be loaded from a floppy disk, the IBL routine initializes the floppy disk subsystem, phase 166. If Drive A does not include IBL media, an error is generated to notify the user that an invalid disk has been inserted into its drive, stage 170. The system then stops, phase (172). Attention is drawn to fig. 6C for a more detailed discussion of phase (168).

Returning to step 168, after checking Drive A for IBL means, the main initial program loader register is loaded into RAM and the code segment included in said register step 160 is executed. It is important to note that for the floppy disk the IBL routine does not include the validity checks used with the hard disk system. The reason for the lack of validity checks is for the load of an unsupported IBL image from the floppy disk. For example, if a new processor is added to the system, a new BIOS image will be included on a floppy disk. Since a new processor will cause expiration errors when loaded from a hard disk, the IBL routine provides the ability to shorten these tests by loading the BIOS image from the floppy disk.

To recap, the main program loader record is checked for system compatibility by agreeing the sis21 planar frame ID and processor model / submodel

J5L

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with the respective values ​​in the boot record of the initial program. For the disc / this check is made first IBL routine (72) and then again in the IBL initial program loader register. The first check (in the IBL routine) is done to ensure that the initial program loader registration is compatible with the system; The second check (in the initial program loader register) is done to ensure that a compatible control passed to ROM has been passed to the initial program loader register. Note that checking the initial program loader registry on disk will never fail for a compatible ROM since the IBL routine will have already checked for compatibility. By contrast, the compatibility check is not done for the floppy disk. Planar / processor compatibility is verified only during the initial program loader registration on the floppy disk. This process allows for future modifications to the loading of a new BIOS image from a reference floppy disk.

With a view to the description of the IBL routine of fig. 6A, the explanation will proceed to a comprehensive and complete understanding of the validity assays described above. With reference to fig. 6B, a flow chart of step 152 of FIG. 6A, to determine if Drive C has a valid master boot loader record. The process begins by obtaining the driver parameters to allow the IBL routine to access Drive C, phase (200). An IBL load position is set in the last three sectors of the disk (the last three sectors of the disk usually contains the master initial program loader register), step (202). Set to 1, a load count indicating the number of attempts to read a master boot record from disk, phase (204). Three sectors of the disc are read at load position IBL, stage (206). Any disk drive errors are detected, and if a disk drive read error occurs, stages (208-210) are reported. The process then returns with an error indication, phases (212-214).

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Returning to step 208, if there is no error in the driver, the hint register is scanned for the signature of the master initial program loader register, step 216. The initial program loader register signature, for example ABC characters, is compared to the first three octets of the disk register. If the disk register does not have a valid initial program loader register signature (ABC characters) and the checksum calculated from the disk register loaded in memory equals the program loader register checksum initial, the disk register is indicated as a valid error-free initial program loader registration, phase (218). The process then returns (phase 214).

Returning to step 216, if the initial program loader register signature or checksum is invalid, the load count, step 220, is incremented by 1. The charge count is then compared to a predetermined constant, for example 99, step (222).

If 99 attempts to read an initial program loader register were negative, an error is indicated and the process returns, phase (224), (212) and (214). If less than 99 attempts have been made to read an initial program loader register, the IBL load location is decremented by 1 and three new sectors are read from the new load location, phases 226 and (206). ). Thus, if a valid initial program loader register cannot be loaded from the last of the 99 sectors (equivalent to 33 copies) then an error condition is set and control returns to the IBL routine.

Referring now to FIG. 6C, a detailed flowchart is shown for loading the master boot loader register from a floppy disk in Drive A. First, the floppy drive parameters for access to the floppy drive are obtained.

<img file="PT95080A_D0015.tif" />

Drive A, phase (230). The IBL load position is adjusted for the last 3 floppy sectors (format: cylinder, head and sector), phase (232). Recall the last 3 sectors, phase (234). If an error is detected in the floppy disk drive, an error, phases (236-238) is indicated. An error condition is established and control returns to the IBL routine phases (240-242).

Referring back to base 236, if no drive error is detected, the diskette register is checked for an initial program loader register signature and the checksum, phase (244) is calculated. ). If the initial program loader register signature is missing or the checksum is invalid, an error is indicated and control returns to the IBL routine, phases (244,246,240 and 242). If a valid initial loader register signature and checksum are detected, an indication is set and control returns to the IBL routine, phase (248) and (242). Note that on a floppy disk load the IBL routine does not search through the media like the hard disk. Therefore, on a floppy disk load, the IBL media must be stored in a specific disk location.

Finally, fig. 6D shows how the IBL routine tests to verify planar frame and system processor compatibility and proper system configuration. The master initial program loader register is checked to determine system planar frame compatibility by comparing the initial program loader register planar frame ID value with the system planar frame ID read by the system processor, phase (260). If the system planar ID does not match the planar ID of the initial program loader register, this indicates that this initial program loader register is not compatible with this planar table. An error is indicated and control returns to the IBL routine, phase '(262, 264 and 266).

<img file="PT95080A_D0016.tif" />

If the master boot loader register is compatible with the planar frame, the master boot loader register is checked to verify processor compatibility, step (268). The model value and submodel value of the initial program loader register are compared to the model value and submodel value stored in ROM, respectively. A mismatch indicates that a new processor was probably introduced and this initial program loader register is not compatible with the new processor.

An error is indicated and control returns to the IBL routine, phases (270, 264 and 266). If the main program loader registration is compatible with the planar board and the processor, the process checks whether the NVRAM is reliable, step (272).

If NVRAM is unreliable, an error is indicated and control returns to the IBL routine, phases (274 and 266). If NVRAM is reliable, check the system configuration, step (276). A change in system configuration is indicated if the model and submodel values ​​stored in NVROM do not match the model and submodel values ​​stored in ROM. Note that this last comparison only indicates a configuration error. If a configuration error is indicated, an error is generated for the user. This error tells you that your system configuration has changed since you last passed SET Configuration. The user is notified of the changed configuration and control passes to the IBL routine phases (278, 264 and 266). This error is not fatal in itself, but notifies the user that SET Configuration must be run. Returning to phase (276), if the model / submodel values ​​of the system match, an indication of compatibility is established and the routine returns, phases (276, 274 and 266). Thus, compatibility between the main program loader register and the system is tested along with determining whether the system configuration has been modified.

After the IBL routine loads the registry

<img file="PT95080A_D0017.tif" />

It trans from the main program loader in RAM, checks the control for the initial address of the MBR code. Referring to FIG. 7, the main initial program loader registration executable code segment first checks the initial program loader registration standard against the standard in ROM, phase (300). If the pattern in the main program loader register does not match the default in ROM, an error is generated and the system stops, stages 302 and 305. Checking for equality in ROM standards and in the initial program loader register ensures that the main initial program loader register loaded from disk or floppy disk is compatible with the ROM in the planar frame. Returning to step 300, if the planar frame pattern matches the pattern in the initial program loader register, the MBR code compares the system planar frame ID value, the model value, and the submodel value with the corresponding values ​​in the master program loader register, phase (304). This process has been discussed in more detail with respect to fig. 6D. If the values ​​do not match, the main program loader register is not compatible with the planar board and the system processor, or the system configuration has changed and an error, phase (306) is generated. The system then stops, phase (305).

Returning to step 304, if the system planar frame ID value, model value, and submodel value match the corresponding values ​​of the main program loader register, the MBR code loads the BIOS image from means chosen for system RAM, step (308). If an error occurs in the media loading when reading the data, step 310, an error is generated and the system stops steps 313 and 305. Returning to step 310, if there is no error in the load, a checksum image of the BIOS image in step 314 is calculated.

If the checksum is invalid, an error is generated and the system stops, phases 318 and 305. Returning to step 316, if the checksum is valid, the indicators will be saved.

<img file="PT95080A_D0018.tif" />

system partition address, phase (320), and the system processor is oriented to POST Stage II to initiate system loading, phase (322).

Thus, a method and apparatus for loading the BIOS from a direct access memory device was presented. Before the BIOS is loaded, the BIOS image on the direct access memory device is checked to determine compatibility with the system. Another test includes verifying that the system configuration is appropriate. Based on these tests, the BIOS image is loaded into the RAM to be executed.

Although the present invention has been illustrated in connection with a preferred embodiment, it should be understood that many variants can occur to one of ordinary skill in the art, and that the scope of the present invention is defined by the claims only. attached and equivalent.