Method and circuit arrangement for the transmission of data signals between control devices interconnected by a loop system.

Descriptive Memory

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The present invention relates to a method and a circuit for transmitting data signals between interconnected control devices via a one-way, cadence-pulse-controlled ring-line system, which are especially comprised of devices. control of a data switching system, being transmitted through the ring line system, from control set to control set, an authorization signal to emit, which commands said device to a state of authorization to emit, before being retransmitted by the control device concerned, data signals to be emitted by that device together with a receiver address which it designates as receiver are sent to the ring-line system. desired control device and being received by a control device.

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A command which is designated as receiver by the receiver address transmitted together with the data signals, these data signals for further processing and sendD is issued a confirmation signal to be relayed through the ring line system, which has been provided for the device. which is in an acknowledgment receiving state and by which data signals have been output.

A case of the kind just mentioned is already known (German patent application DE-OS 31 36 586). In this known process, the control device which outputs the data signals remains in said acknowledgment state until the receipt of a confirmation signal generated by the control device selected as the receiver upon receipt of the data signals. It may then also be the case that a confirmation signal is missing either as a result of a malfunction of the ring line system or as a result of sporadic tampering with the information contained in the confirmation signal, so that the signaling device The command that previously issued the data signals remains in the acknowledgment reception state. This means that this control device is blocked for the transmission of other data signals. To exclude this possibility it is then possible to temporarily limit the acknowledgment status of the control devices. This requires separate supervision circuits in the control devices.

It is therefore an object of the present invention to provide a way for a process and device of the type mentioned in the introduction to be able to temporarily monitor a confirmation receiving state taken by a control device with a reduced complication command.

In a case of the type mentioned under 2 -

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In this invention the problem is solved by determining the maximum time interval during which a control device is in the acknowledgment state after the data signals are emitted by the instant the new authorization signal is received. on the control device in question, and then, upon the appearance of the acknowledgment signal received for the control device in question, within the stated maximum time interval, □ the control device in question takes a state which again makes it possible to transmit data signals, and passing, after the maximum time has elapsed, and before the acknowledgment signal in question appears for the □ control device concerned, for a fault communication and / or fault handling status.

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The invention has the advantage that no time monitoring of the acknowledgment receiving state taken by said controller any special time measuring devices is required in the control device, but is used in this case to determine the duration of the existence of a acknowledgment receiving state, the evaluation Mi of the instant of the issuing authorization signal transmitted through the ring line system. Another advantage of the present invention is that a control device that is in the acknowledgment receiving state, in the absence of an expected acknowledgment signal within the predetermined maximum time interval, is first transferred to a communication handling state. and / or malfunction treatment. In this way, it is possible to initiate measures in the shortest time to locate the fault in the respective control device or in the ring line system assembly.

For carrying out the process according to the present invention in a circuit with control devices interconnected by a ring line system, with directional operation and cadence pulsed synchronization, which respectively provide, as emitting devices, upon receipt of a signal from authorization to issue, data signals eventually to be output to the ring line system and which respectively as receiving devices receive data signals intended for them and transmitted through the ring line system and output a confirmation signal corresponding to those signals to the set of data. corresponding emission in the ring line system, It is advantageous to form the circuit such that each of the control devices presents an output command that switches the corresponding control device after the data signals are first sent to the acknowledgment reception state and thereafter when a new authorization signal appears to issue, before the expected confirmation signal appears, to a malfunction reporting and / or malfunction treatment status, and that in each control device a confirmation signal receiver is provided which, when a confirmation signal appears, emits a confirmation signal to the respective control circuit of the emission execution, based on which this control circuit executing the transmission switches the respective control device which is in a acknowledgment reception state to a state which makes it possible to send new data signals. The advantage of this circuit is that the closing devices are provided for monitoring the appearance of the authorization signals for issuing and the acknowledgment signals in each case separate devices, namely a command of execution of the emission and a receiver of the acknowledgment signals. In this way the complication of the commands of the control devices which are in an acknowledgment receiving state is reduced.

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The complication of the commands in the various control devices can be kept to a low level especially Λ4 **** by the fact that the control of the emission execution belonging to each of the control devices has a microprocessor device with a certain number of inputs. interrupt and command that with a first of the interrupt and command inputs it is switched on to receive the authorization signals for when an authorization signal appears, it gives a command signal to the interrupt and command input, and by the fact that, Another interrupt and command input is connected to the acknowledgment signal receiver already mentioned for issuing an acknowledgment signal.

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which, in order to issue to him a correspondent for the respective

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The receiver of the acknowledgment signals may be carried out with relatively uncomplicated circuits technically if the receiver of the acknowledgment signals is provided with a decoder device and a recorder connected with the microprocessor device which, upon the appearance of a confirmation signal intended for the respective acknowledgment device. the command receives it for evaluation by the microprocessor device and emits, upon receipt, a pars acknowledgment signal; a command output.

The following invention is described in more detail below by way of example, with reference to the accompanying drawings, which represent:

Figure 1 is a data switching scheme formed by a system which the present invention is employed.

blocks, a ring line system in the

Figure 2, in a block scheme, the constitution of

5 of one of the interface circuits shown only schematically in FIG. 1, as well as the constitution of one of the switching or line-connecting units, respectively;

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Fig. 3, constituting an emission buffer device in the interface circuits;

Fig. 4, constituting a device for receiving an authorization signal to emit;

Fig. 5, the constitution of an emission buffer control device; and

Fig. 6, the constitution of a receiving buffer device present in the interface circuits.

There are fig. 1 is a single-node data switching system of switching units (SUO ^ a (5Un). These switching units perform, in accordance with the principle of load sharing, the switching functions required for transmission). To this end, the switching units are connected together to a ring line system, such a ring line system may consist of a single closed loop line arrangement. But such a ring line system can also, as for example shown in FIG. 1, consisting of two ring lines (RIHGO) and (RING1) in parallel and independent of each other. With such reductance it becomes possible, for example, in the event of failure of one of the ring lines to carry out the transmission of data signals by the other ring line.

The aforesaid connection of the switching units (3UD) to (SUn) to the two ring lines is in any case via a separate interface circuit (RA) where ι®ο $ · οο.

liiliaILBMI is one of the am ring lines, a point to which reference will be made in more detail below.

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With the aforementioned ring lines (I^r1'C) and (RING1) are further connected several line link units (TliO) to (TUk) via a separate interface circuit (RA) for each of the ring lines. Together with the corresponding interface circuits, these line link units serve to transmit data signals between the switch units and the transmission lines connected to subscriber equipment that are connected to the line link units. Each of the line link units has for such a transmission line connection a number of line connections (LTC) to (LTm).

The circuit units formed by the mentioned switching units or line connection units and the corresponding interface circuits are hereinafter also referred to as control devices, where the ring line system consists of only one ring line, part of a control device only a single interface circuit.

Within the switching system shown in fig. 1, that is, between the switching units and the dial-up units, the data signals are transmitted in the form of blocks of data signals which present, during the establishment of a communication, as data signals. , signaling information and, in the case of established communication, the signals of the messages to be transmitted between the subscriber's equipment concerned. Each block of data signals to be transmitted then contains, in addition to the data signals themselves, each of them formed by a number of bits, for example δ bits, at least one receiver address, which

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means as receiver a selected control device, block start and end marks indicating the start and end of a block of data signals, and a sender address which designates as transmitter its control device, and a pre-prepared acknowledgment signal. A block of data signals thus constituted can then be issued to one of the ring lines only when an authorization signal to be transmitted from a device has been received by this control device before that. control to the control device and which controls it to an emission state.

Fig. 2 depicts in detail the constitution of a control device. As mentioned above, such a control device comprises either a switching unit or a line connection unit shown in FIG. 2 by reference (SU / TU) and a number of interface circuits corresponding to the number of ring lines. In this case, in fig. 2 Only one of these interface circuits is indicated, because all interface circuits connected with the switching or line-connecting units have the same structure internally.

The unit (switching unit or line connection unit) shown with a section in fig. 2 and designated by (SU / TU) features a microprocessor device that controls both the sending and receiving processes. From this microprocessor device are represented a microprocessor (HP) and a memory device (HEM) comprising a fixed memory (program memory) and a read / write memory connected to said microprocessor através via a bus system . The bus system consists of a data bus (D3), an address bus (AB) and a command bus (SB)₀Via data bus and address bus

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As well as via the command bus circuits designated by (V.'R) and (SA), □ interface circuit (RA) is also connected with the microprocessor (MP). In addition, two command lines of the interface circuit lead to the microprocessor (MP) interrupt inputs (INTn ~ 1) and (INTn).

The interface circuit (RA) may be subdivided into two circuit parts, namely an emission part for sending data signal blocks to the corresponding ring line and a receiving part for receiving data signal blocks from the line. in respective ring. In the following reference is first made to the receiving part.

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At the interface with the corresponding ring line a reception register (Regi) has been provided to which signals transmitted through the ring line under the command of a cadence generator, not shown, which emits the cadence pulses are transferred in parallel. (T) The rate of the cadence pulses is furthermore adjusted to the transmission speed of the ring line. Regarding the signals that have been mentioned, these are a predetermined number of data signals and an authorization signal to transmit which is transmitted on a separate line called (SBE). This signal of authorization to emit may in this case be formed by the appearance of a state of a certain binary signal of a certain duration.

On the output side, the input register (Regi) is connected with its outputs conducting the data signals, on the one hand, with a receiving buffer (EP) and, on the other hand, with the receiving signal receiver. confirmation. This is formed by an address decoder (DEC) and a confirmation register (Reg2). On the input side, both are connected with said input register (Regi) outputs. The address decoder output is connected to a confirmation register cadence input. This acknowledgment register in turn displays outputs of the data signals that are connected with the aforementioned data bus (DB). In addition, a confirmation register (Reg2) command line leads to the microprocessor (MP) interrupt input (I.NTn-1).

As will be explained further below, said race buffer (EP) serves to receive the data signal blocks for the respective control device and for the retransmission of the data signal blocks for other control devices. connected to the ring line. On the output side, this receiving buffer is connected, on the one hand, with the aforementioned data bus (DB) and, on the other hand, with the first inputs of a DW1 data needle, as well as via a line device with inputs from a register (Reg3).

The emitting part of the interface circuit (RA) has an emitting buffer (5P) which from the aforementioned microprocessor device receives signals via the data bus (DB), the address bus (AB) and via lines (UR) and (5A) of the command bus line (SB). In addition, one input of the output buffer device is connected to the output that drives the authorization signal to emit from the input register (Regi) through a line called (5EE *). Finally, another input □ buffer device a broadcast (SP) receives the cadence signals (T).

Through the outputs of data signals, the emission buffer (SP) is connected via a line device (SD) with other data needle inputs (D'tl) already mentioned. This data needling is controlled, inter alia, by a warning signal appearing on a line designated (5L1) by the emission buffer. The data needle is connected with a control input via an OR (GO) circuit with line (5L1).

The last mentioned data needle inputs (DW1) are furthermore still connected to the register (Reg3) with its outputs of the data signals, connected on the input side with the line device (QS). A command output of this recorder is connected via a line (3L2) and circuit OR (GO) with the data needle control input (DW1).

On the output side, the data needle (D'dl) is connected with data signals inputs from an output register (Reg4) at the interface with the corresponding ring line and controlled by the cadence pulses (T). · This recorder It is connected by another input, via a line (SBA *) to an output of the transmit buffer (SP) which carries an authorization signal to transmit to relay. On the output side, the output register (Reg4) is connected with the corresponding ring line. Incidentally, the line (SBA *) is also connected with the microprocessor interrupt input (INTn) (MP). Through a line (5A¹), finally, the sending buffer device is still connected with the command bus line (SB).

Regarding the receiving buffer (EP) and the acknowledgment register (Reg2) it is further noted that these, to be controlled by the microprocessor (HP), are connected in addition to the data bus (D3), also with the address bus line (AB) and the command bus line (SB). However, their links are not represented

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to simplify fig. 2.

The following describes firstly the cooperation of the circuit components shown in FIG. 2, in the case of data signal transmission before entering into the details of the constitution of the receiving buffer (EP) and the sending buffer (SP).

First, it is assumed that data signals are to be transmitted from the control device shown in FIG. 2 for another control device. To this end, firstly the microprocessor device associates the data signals consisting of a predetermined number of bits to form at least one block of data signals, adding to the actual data signals a block start mark indicating the beginning of a block of data signals and a receiver address which designates as receiver and the selected control device. A block of data signals thus constituted is then driven by write pulses transmitted by line (uR), transferring word for word to the sending buffer (SP). By word is meant a predetermined number of simultaneously transmitted bits transmitted in the form of a parallel signal to the sending buffer. For example, a word may consist of 16 bits, that is, two data signals if each data signal consists of E bits.

Following word-to-word transmission of a data signal block, the microprocessor device then outputs via the line (5A) a broadcast request signal to the broadcast buffer (SP). However, this signal remains first in the broadcast buffer without being considered until a signal of authorization to emit appears, which through the

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In (Reg) s of the line (S13E *) reaches the emission buffer device. Following the appearance of an authorization signal to emit, the data signal block that has just been stored in the emission buffer device is, however, sent word by word through the output register (Reg4) to the corresponding ring line. A block end mark indicating the end of a data block is then added to the data signal block, as well as a Sender Address designating as the sender the control device that issues the data signal block, as well as a confirmation signal previously prepared for the recipient. The output buffer (SP) then relays the previously received send signal over the line (SilA *) to the output register (Reg4), which outputs this send signal for the incoming line. ring.

Upon issuance of the authorization signal to emit that is indicated to the microprocessor (4P) by a signal on the line (SA '), the corresponding control device first goes to a acknowledgment state in which it only requests receive operations are processed and in which the interrupt input (INTn) of the microprocessor is activated.

The acknowledgment receiving state normally remains until a confirmation signal is issued upon receipt of the newly transmitted finger signal block by the control device considered as the receiver. This acknowledgment signal is the previously prepared acknowledgment signal already transmitted in the data signal block, which is modified in the control device considered as the receiver. By means of this modification, information regarding the reception of the transmitted data signal block is brought to the transmitter. For example, through a

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acknowledgment signal modified in a particular manner may indicate error-free transmission of a block of data signals.

To a modified acknowledgment signal is added the transmitter address of the newly received data signal block and the end mark of the corresponding data signal block. The address and block end mark are then taken from the received data signal block.

The appearance of a confirmation signal is then monitored with the aid of the receiver of the confirmation signal already mentioned. The address decoder (DEC) belonging thereto permanently compares the signals appearing at the output of the input register Regi (Fig. 2) with a signal consisting of the address assigned to the control device in question and the end of combined block. Then when the address decoder checks for a match, it outputs a command signal on its output. With the appearance of this command signal the acknowledgment signal transmitted following the address and the end of block mark is then transferred to the acknowledgment register (Reg2).

Upon receipt of the acknowledgment signal, the acknowledgment register outputs through its command output a confirming confirmation signal to the micraprocessdar (MP). It accepts the confirmation signal that has just been stored in the confirmation register for further evaluation. In the course of this evaluation, the microprocessor then switches the corresponding command device from the acknowledgment receiving state to a state in which a new finger signal block is possible. Whether the acknowledgment signal is evaluated depends on whether it transmits another block of data signals that may be waiting to be issued, or if, βο $ οο lliuuim

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firstly, in the event of a transmission error detection, measures are taken for error handling such as, for example, measures for a new transmission of the previously issued data signal block. On the other hand, in this state the interrupt input (INTn) is blocked.

In addition, the control devices are continuously monitored for the authorization signal to be emitted, namely the respective emission buffer (SP). This, upon the appearance of the allow signal to send, outputs a command signal to the interrupt input (INTn) of the microprocessor (MP). If, until the output of this control signal, in a control device that is precisely in an acknowledgment state the acknowledgment signal it expects does not appear, then the microprocessor (MP) switches the corresponding control device to a state of acknowledgment. malfunction communication and / or malfunction treatment. In this state, possibly in addition to a malfunction report, measures are also initiated for the treatment of the malfunction. These lead, for example, to which all switching system devices involved in transmitting the unconfirmed data signal block, that is, the two considered and the used ring line checked step by step. If this example, that the concerned ring interface (RA) line connected with it does not function of the malfunction may consist of a ring that does not then link the data signal block transmission line

5e, control devices operate for transmission, check reveals, □ u circuits correctly, then the transfer service treatment was being used to the contrary, command positives participating in the transmission that did not correctly handle the transmission. failure may result in the respective control device being excluded from other data signal transmission.

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The following describes the control operations performed upon receipt of a block of data signals in a control device. As mentioned above, for receiving data signal blocks the receiving buffer (EP) is provided. This device, upon the appearance of the block start mark indicating the start of a data signal block, compares the receiver address transmitted at the beginning of the data signal block with an address assigned to the control device in question. coincidence of addresses compared with each other, signals belonging to the data signal block will be transferred to a memory device until a block end mark indicating the end of the data signal block appears. These remain in that memory first until they are transferred by the unit's microprocessor device (SU / TU) (fig. 2 \ The transfer can then be performed, for example, by means of a command signal emitted when the block end mark appears. by the receiving time device. For this purpose the signal can be fed to the microprocessor at another interrupt input, for example at the input (FIG. 1).

Prior to the transfer of a block of data signals, the receiving buffer still has a check for its error-free transmission, for example in the form of a parity control. The receiving buffer then modifies the acknowledgment signal transmitted in the data signal block prepared by the transmitter of the data signal block according to the verification result and transmits this modified acknowledgment signal together with the address assigning the signal. sender of the newly received data signal block and with the block end mark for the register (Reg3). The end mark and □ address are then taken from the received data signal block. The register (Reg3) then relays the transferred signals

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through the data apparatus (DW1) and the ds output register (Reg4) to the line sm ring. For this, the data needle (DW1) is properly controlled by the register (Reg3) via line (SL2).

If, on the contrary, the receiving buffer device (EP), when a start mark of a block of data signals appears, check. not matching the addresses compared to each other, then that device relays the data signal block without changes to the data needle (DW1). Through this data needle and the next output register (Reg4), the data signal block will then again reach the ring line and thus the next control device on the ring line.

In the following further reference is made to the constitution of the emission buffer device (SP) and the reception buffer device (EP). ha fig. 3 a block scheme of the emission buffer is shown. Among other things, this device has a temporary memory (FIFQ1) connected with its data signal inputs to the data line (DB). This temporary mammary, which is also referred to as first-in-first-out memory, serves for the aforementioned reception word for word of a block of data signals prepared by the unit's microprocessor device (5U / TU), and for its retransmission to the sm ring line upon the emergence of an authorization signal to emit. The necessary read and write operations are controlled by a buffer circuit controller P5 shown in FIG. 5, which is connected to the buffer through lines (V.'R1), (RD) and (FE). The lines (URI) and (RD) serve, in this case, for the transmission of writing or reading pulses, respectively. Through the line (FE), the buffer emits a command signal indicating its status.

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With its data signal outputs, the buffer (PHYFO1) is linked with data signals inputs from a jumper (Reg5). These register which on the output side is connected to the line device designated in fig. 2 by (SD), is connected with a cadence input via the aforementioned line (RD) and an input for activating its data signal outputs via the line (Eiul) of the buffer circuit controller ( P3).

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In addition, □ voFJ buffer and emission device has two other registers (Reg6) and (Reg7). These registers are connected with their data signal outputs to the aforementioned (SD) line. For the activation of these data signal outputs, each register also has an input d command which can be controlled via a line (EN2) or (EN3), respectively, by the buffer circuit controller (PS). The register (Reg6) in this case stops the preparation of the sender address and the end-of-block mark to be output in a signal block. This information is taken to this entry-side register via the

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Transfer of the sender address and the end-of-block mark is done with the aid of a write pulse &lt;* w the stored buffer □ which is provided by the line controller (1R2). In the register (Reg7) is a confirmation signal prepared previously mentioned.

For the control of buffer write operations (FIFC1), the buffer circuit controller (PS) is connected with the address line (Ad) and the line (h'R) through which they are transmitted. address signals or writing pulses respectively '

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THE

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In order to control the read operations in the buffer and registers (Reg5), (Reg6) and (Reg7), the buffer control device is, on the other hand, connected, on one side, for the transfer of cadence pulses with the line (T) already shown in FIG. 2 and, on the other hand, with a line (RF). Along this line the buffer circuit controller (PS) receives from a device shown in more detail in FIG. 4, for receiving an authorization to send (SBS) signal, an enable signal for reading output from a buffer of data signals stored in the buffer (FIFD1). This device (SUS) is connected with lines 53E *, (SL1) and (S3A *) shown in FIG. 2. In addition, via a line (3A *), it is connected to the output of a bistable multivibrator (FF1) which receives at its cadence input from the microprocessor (RP) through line (3A), □ broadcast request signal already mentioned. A reset input of this bistable multivibrator is finally connected via line (RS) with the buffer circuit controller (PS). In addition, line 3A 'is also connected to command bus line SB.

The emission buffer (SP) shown in FIG. 3 the following command operations are performed. For word-by-word transfer of a block of data signals to buffered memory (FIFCl), writing pulses are issued by the microprocessor (HP) in connection with address signals which designate buffering memory to the device. circuit control switch (PS). It relays the writing impulses to temporary memory. 0 The block of transferred data signals, word for word, with the aid of these writing pulses, remains first stored in temporary memory. Following this transfer of the data signal block, finally, the microprocessor further provides, via line 5A, an emission request signal which

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switches the bistable multivibrator (FF1) to active state &lt;&gt;

By this active state of the bistable multivibrator (FF1), the device for receiving an authorization signal to emit (535) indicates the presence of a block of data signals to be emitted. When this device then receives an authorization signal to emit, it outputs a corresponding signal through the line (RF) to the buffer circuit controller (PS) which then applies to the buffer (FIF01) and to the register. (Rsg5) the reading pulses appearing in the cadence pulse frame (T). In addition, the buffer circuit controller further emits a signal activating the outputs of the register (Reg5) data signals. Thus, the block of data signals precisely stored in the buffer (FIFQ1) is read, word for word, and relayed through the register (Reg5) and the data needle (DW1) to the line sm ring. Data needling is therefore appropriately controlled by the device (S3S).

state

The output reading is then performed until, when reading the current signal block trend (FIF01), it outputs a signal indicating its line (FE) stop to the buffer device (PS). This signal causes the buffer circuit controller to block said data signals from the register (Reg5), and then first the outputs from the data signals from the register (Rego) and then the outputs from the data. (Reg7), are activated by each cadence pulse (T). Thus, as already added to the signal block of the circuit signal us

In the end of the transmitted data, the sender address, including the block mark and the previously prepared acknowledgment signal, acknowledged by the buffer F5, the multivibrate inactive state. This authorization to issue receΐ)

After the device is issued, the bistable circuit command (FF1) will be reset and the □ device signal (SBS) will be relayed over the line (S3A to the ring line, and a command signal which indicates this reset is issued to the microprocessor (HP) through the line (SA ').

In fig. 4 shows the constitution of the device for receiving an issuing authorization signal (SBS). This device features a bistable RS-type multivibrator (FF2) whose adjustment input (S) is connected with an output that negates the output signal of an E (Gl) circuit. This circuit E is connected with a line input (SBE *) which drives the smitter signal and, with another input, the line (5A '), the latter also leading to the bistable multivibrator reset input (FF2). . Both lines are also connected to the input of an E (G2) circuit, negating the input connected to the line (SA¹) the input signal led to it. On the output side, this circuit E is connected to an input of an OR circuit (G3). Another input of this circuit CU is connected to the output of a monostable multivibrator (MV) which, in turn, is connected on the input side to the output of the aforementioned bistable multivibrator R3 (FF2). To this output of the bistable multivibrator are also connected the lines SL1 and RF (Fig. 3).

The device shown in fig. 4 then always immediately relays an allow signal to emit which appears on line SBE 'through circuit E (G2) and circuit CU (G3) to the output register (Reg4) shown in FIG. 2, when the bistable multivibrator (FF1) is in an idle state, that is, when no microprocessor request signal has been emitted before. 5b, by contrast, the bistable vibrator (FF1) is in the active state, so the newly transmitted transmission path for the broadcast authorization signal is blocked. When an authorization signal for arithmetic appears, the bistable multivibrator (FF2) is changed to its active state, in which the activation signal, already mentioned, for reading a block of control signals appears on the line (RF). data stored in the temporary menary (FIFDl). Furthermore, in this state, a command signal for the data needle (DW1) is output via line SL1 (fig. 2).

Replacing the Bistable Multivibrator (FF1)

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data also causes the bistable multivibrator (FF2) to be changed to its inactive state. In this change, □ monostable multivibrator (MV) connected following the bistable multivibrator (FF2) outputs a predetermined duration output signal which is relayed as an authorization signal to emit via circuit OR (52).

Fig. 5 shows the constitution of the buffer circuit controller (PS). The buffer circuit control device has, according to said figure, a decoder (DEC2) which, on the input side, is connected to the address bus line (A3) and the line (UR). According to the address signals applied to the address line, the decoder relays the writing pulses transmitted by line (WR) or line (WR1) cu to line (WR2).

In addition, the buffer control device (PS) has a cadence activation signal (T) such as a mentioned circuit, pulses of

54) which, in the presence of the line (RF) emits read pulses, to the line (RD). The at the output of this circuit E is further connected to the cadence inputs of two bistable multivibrators (FF3) and (FF4) connected one after the other. The non-denied input of the bistable multivibrator (FF3) is then directly linked to the input of the bistable multivibrator (FF4) data signal. The input of the bistable multivibrator data signal (FF3) is connected to the output of an E (G6) circuit. On the input side, this circuit E is connected on the one hand to the line FE shown in FIG. 3 and, on the other hand, to the input denied output signal of the bistable multivibrator (FF3). This output also connects the line (EN2). The bistable multivibrator (FF4) is connected, with its non-negating output signal output, to line (RS) and, with its output signal negating output, line (EN3). The line (FE) just mentioned, is also connected an inverter (G5), connected on the output side to the line (EN1).

The circuit just described consists of the circuit E (G6), the two bistable multivibrators (FF3) and (FF4) and the inverter (G5), emits when a signal indicating □ empty state of the temporary memory appears. (FIFD1), first a lock signal to block the outputs of the register data signals (Reg5) and then an activation signal respectively of the registers data signals outputs (Reg6) and (Reg7). In addition, the bistable multivibrator (FF4) also prepares a signal that produces replacement of the bistable multivibrator (FF1).

Fig. 6 represents the constitution of the receiving buffer device (EP) already mentioned. For comparing the above addresses, this device has a comparator device (Vgl) connected to the outputs of the input register (Regi) data signals (Fig. 2) which, in case of the matching of the comparing addresses, outputs an adjustment signal to a bistable multivibrator (FF5). On the exit side, this

<img file="PT83339B_D0032.tif" />

Bistable multivibrator is connected with an input of an E (GT) circuit. In another input this circuit E receives, as writing pulses, the cadence pulses (T). At the output of this circuit E (G7) is an input of the write pulses of a memory (FIF02). This memory is, for example, a temporary memory that is connected with its data signal outputs to that of the data bus. (DB). In the presence of an adjustment signal just mentioned, the data block is transferred to this temporary memory, word by word, with the aid of the cadence pulses (T) transmitted through the circuit E (G7). Data signal word transfer is performed until the bistable multivibrator (FF5) is reset to idle by the end of block mark indicating □ end of data signal block. · For this reset, the multivibrator Bistable (FF5) is connected to the buffer input by the line (EK) leading the block end mark. This line is also connected to another bistable multivibrator (FF6) which, upon the appearance of the block end mark, outputs the command signal already mentioned, which indicates to the microprocessor (MP) the presence of a signal block of data. We do not refer here in detail to the reader of a block of data signals from buffer (FIFD2). This output is read in a manner known as by feeding appropriate command signals through command line (SB) channels. The output reading then ends with the appearance of a signal indicating the empty state of the buffer. The microprocessor (MP) receives this buffer signal (FIF02), for example as a command signal, via the command bus (SB) or as an interrupt signal at an interrupt input,

The buffer memory input (FIFQ2) is connected with a device (SB) for checking the memory blocks.

<img file="PT83339B_D0033.tif" />

data signals received. This device checks the received data signal blocks for their error-free transmission, for example by performing a parity control. Then the device modifies the acknowledgment signal previously prepared by the sender contained in a received data signal block according to the result of the verification and then outputs this modified acknowledgment signal together with the address designating the sender of the signal block. just received and the block end mark to the register (Reg3).

Before the buffer (FIF02) a data needle (DW2) is still connected. This data needling is controlled by the aforementioned comparator device (Vgl). It then ONLY relays data signal words belonging to a data signal block to temporary memory if the comparator device has verified a matching of the addresses compared to each other. Otherwise, the entire received data signal block is relayed through the data needle (DW1) of FIG. 2 and the output register (Reg4) to the corresponding ring line.

It has been explained earlier with reference to FIGS. 2 is that for receiving acknowledgment signals and data signal blocks, two separate address decoders are provided in the control devices, namely the address decoder (DEC) and the comparator device (Vgl). Instead of these two address decoders, however, only a single address decoder can also be used, which receives, for detection of acknowledgment signals and data signal blocks, in addition to the lines that transmit the addresses, as well as the lines. that convey the start mark and the end mark of the block.

<img file="PT83339B_D0034.tif" />

_ ie _

Process for transmitting data signals between command devices (SUO, RA; ...; 5Un, RA; TUO, RA; ... TUk, RA) connected to each other by a ring line system (RlNGO, RING1 which functions by commanding cadence pulses and depending on the direction of transmission, the control devices being formed in particular by devices control of a data switching system by transmitting to via the anal line system, from control device to control device an emission permit signal which controls this control device to an emission permit state, prior to being retransmitted by the respective control device the data signals to be transmitted by it, together with a receiver's address designating the command slide desired by the system with a ring line and receiving a control device, which is designated by the receiver's address transmitted together with the data signals, these data signals are for further processing and a confirmation signal is being transmitted to the ring-line system which is provided for the control device to be transmitted. is in a state of receipt of the acknowledgment by which the data signals have been emitted, characterized in that the maximum period of time during which, after the issuance of the data signals, a control device remains in the acknowledgment state determined by the moment when the new broadcast authorization signal appears on the respective control

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In the case of confirmation that it is of interest to the control device to arrive within said maximum time lapse, the control device in question assumes a state which permits the re-emission of data signals and, in the event of □ maximum time lapse before Upon reaching the acknowledgment signal of interest to the control device in question, this control device shall be brought into a fault indication state and / or to a fault treatment state.

dispose

2S agreement