Inverse transport processor with memory address circuitry

DESCRIPTION “Reverse Transport Processor with Memory Addressing Circuits”

This invention relates to apparatus for processing program component data packets from a packet video signal and extracting corresponding loads of different program signal components. It encompasses an apparatus for addressing a separator memory and the concept of using a common transport separator memory.

BACKGROUND OF THE INVENTION

It is known, for example, from US-A-5 168 356 and US-A-5 289 276, that it is advantageous to transmit packet compressed video signals, allowing the respective packets a measure of protection / correction of mistake. The systems in the above patents transmit and process a single television program, albeit with a plurality of program components, from the respective transmission channels. These systems use reverse transport processors to extract the video signal component from their programs for further processing to condition the video component for playback. US-A-5 289 276 only explains the processing of the video signal component. USA-5 168 356 describes a reverse transport processor which separates the other program components with a simple demultiplexer that responds to packet header data to distinguish the respective signal components. The separate video component is coupled to a separator memory, while the remaining signal components are shown coupled directly to their respective processing circuits.

It is known from US-A-5,233,654 that a code with television signals can be transmitted to provide interactive programming. This code will typically be operated on or executed by a computer associated with a television receiver. It is also known from WO94 / 14284 how to utilize various deferred time memory structures for dissemination of television programming in formation.

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In applications where most program components are compressed, some separation between the transmission channel and most of the respective component processing (decompression) apparatus is required, so it is desirable to couple most, if not all, components to the separator memory. . The data rates of different program components may vary widely between their components as well as within their components. Thus, it is advantageous to separate each component separately. In general, separator memory is not insignificant for separating data from compressed program components and processing interactive programs. In fact it can contribute significantly to the cost of a receiving system.

If the reverse transport processor resides, for example, in an overhead box, the memory size and administration circuits should be kept to a minimum to keep consumer costs as low as possible. Thus, it is economically desirable to use the same memory and memory management circuits for program component separation, processor maintenance, and interactive functions.

SUMMARY OF THE INVENTION

The present invention is a reverse transport processor system for a TDM packet signal receiver. The system includes an apparatus for selectively extracting the desired loads of program component data and coupling this data to a common separator memory data entry access. A microprocessor generates the data, which is also applied to the data entry access of the common separator memory. The respective data and component loads generated by the microprocessor are stored in the respective blocks of common separator memory in response to the associated memory addresses which are applied to a memory address input access via an address multiplexer.

In a particular embodiment, the program component packet loads of the respective program components are multiplexed for a memory data entry access and directed to select random access memory (RAM) areas according to a plurality of memory indicators. beginning and end. The start and end indicators are stored in a first

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679 028 / ΡΤ plurality of registers, one for each program component. Addresses are generated in part through a plurality of multiplexed read indicator registers with an adder to successively increment the indicators for the respective program components. Start indicators are associated with read indicators for memory addresses that pass through indicated memory blocks selectively assigned to their respective program components.

In a further embodiment, a decoding device is included to decrypt payload data according to packet-specific decryption keys.

In a still further embodiment, a detector for detecting charges including designation data is included. Loads containing designation data are directed through common separator memory to a smart card, which generates packet-specific decoding keys.

A data output from memory is coupled to a channel interconnected with the respective program component processors. Responding to data requests from the respective program component processors, and requests to write data from the component load source, memory access to the read and write functions is arbitrated so that no data is lost from entering program, and all component processors are served.

BRIEF DESCRIPTION OF DRAWINGS

The invention will be described with reference to the drawings, in which:

FIG. 1 is a pictorial representation of a time division multiplexed packet television signal, FIG. 2 is a pictorial representation of the respective signal packets;

FIG. 3 is a block diagram of a receiver for packet selection and processing of multiplexed component signals embodying the present invention;

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679 028 / FIG. 4 is a block diagram of exemplary memory management circuits which may be implemented for element 17 of FIG. 3;

FIG. 5 is a pictorial representation showing the formation of memory addresses for the service channel data;

FIG. 6 is a pictorial representation showing the formation of memory addresses for auxiliary packet data;

FIG. 7 is a block diagram for exemplary circuits for generating auxiliary packet memory addresses;

FIG. 8 is a block diagram of alternative register circuitry for incrementing memory addresses;

FIG. 9 is a flow chart of the memory address control operation;

FIG. 10 is a block diagram of a conditional access filter / start code detector.

DETAILED DESCRIPTION

FIG. 1 shows a signal stream consisting of a sequence of boxes representing signal packets which are components of a plurality of different television or interactive television programs. These program components are assumed to be comprised of compressed data and as such the amount of video data for the respective images is variable. Packages have a fixed length. Packets with letters having similar indices represent the components of a single program. For example, V ,, A ,, Dj represent video, audio, and data packets and the packages designated V_no THE_no D! represent the video, audio and data components for program 1, and V₃, A₃₁, A₃₂, D₃, represent the video, audio 1, audio 2, and data components of program 3. The data packets Dj may contain, for example, control data for initiating certain action within a receiver, or they may include executable codes, which form an application to be executed, for example, by a microprocessor, located

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79 79 679 028 / ΡΤ within or associated with a receiver.

At the top line of the package sequence, the respective components of a particular program are shown grouped. However, there is no need for packages of the same program to be bundled as indicated by the complete sequence of packages. Nor is there any special order for the sequence of occurrence of the respective components.

The respective packets are arranged to include a prefix and a payload as shown in FIG. 2. The prefix of this example includes two 8-bit bytes comprising five fields, four (P, BB, CF, CS) of which are 1-bit fields, and one (SCID) of which is a 12-bit field. The SCID field is the signal component identifier. The CF field contains a mark to indicate whether the packet load is scrambled, and the CS field contains a flag indicating which of the two alternative unscramble keys is to be used to unscramble the scrambled packets. The prefix of all packages is aligned in the package, so the location of the respective fields is easily identifiable.

Within all loads is a header, which contains a continuity count, CC, module 16, and a TOGGLE mark bit, which are specific program components. Continuity counting is simply a successive numbering of successive packages of the same program component. The TOGGLE flag bit is a bit signal which, for the video component, changes the logic level or changes the state in packets that define the start of a new image (frame), that is, packets, which contain an image layer header.

FIG. 3 illustrates in block form a portion of a digital television signal receiver that includes elements of a reverse transport processor. The signal is detected by an antenna 10 and applied to a tuning detector 11 which extracts a particular frequency band from the received signals and provides a baseband compressed signal in a binary format. The frequency band is selected by the user through a microprocessor 19 by conventional methods. Nominally the transmitting digital signals will have been error coded using, for example, Reed-Solomon direct error correction (FEC) coding. Baseband signals will be like this

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679 028 / ΡΤ applied to an FEC decoder 12. The FEC decoder 12 synchronizes the received video and provides a signal packet stream of the type illustrated in FIG. 1. FEC 12 may provide packets at regular intervals, or on demand, for example, via memory controller 17. In either case a packet or synchronization signal frame is provided by the FEC circuit which indicates the times in that their package information is transferred from the FEC

12.

The detected frequency band may contain a plurality of time division multiplexed programs in the form of packets. To be useful, only packets from a single program should be passed to additional circuit elements. In this example it is assumed that the user is not aware of which package to select. This information is contained in a program guide, which has a program consisting of data, which interrelates the program signal components via SCIDs, and may include information regarding, for example, subscriber designations. The program guide is a listing for each program, from SCIDs to the audio, video, and data components of the respective programs. The program guide (packets D4 in FIG. 1) is assigned a fixed SCID. When power is applied to the receiver, microprocessor 19 is programmed to load the SCID associated with the program guide into one of a similar programmable SCID register bank 13. The prefix portion SCID fields of the respective detected packets of FEC 12 signals are successively loaded into an additional SCID register 14. Programmable registers and the received SCID register are coupled to the respective input accesses of a comparator circuit 15, and the received SCID is compared to the SCID program guide. If the SCID for a packet matches the SCID program guide, comparator 15 conditions a memory controller 17 to route that packet to a predetermined location in memory 18 for use by the microprocessor. If the received SCID does not match the SCID program guide, the corresponding packet is simply thrown into the trash.

The microprocessor waits for a user programming command via an interface 20, which is shown as a computer keyboard, but may be a conventional remote control, or the receiver front panel switches. You may be asked to view a program provided in the

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79 79 679 028 / ΡΤ channel 4 (in the language of analog TV systems). Microprocessor 19 is programmed to scan the program guide list that has been loaded into memory 18 for its respective channel 4 program component SCIDs, and to load these SCIDs into the other respective programmable registers of register bank 13, which are associated with the corresponding component signal processing circuit.

Packets received from the audio, video or data program components to a desired program should finally be routed to the respective audio 23, video 22, or auxiliary data 21 (24) signal processors, respectively. . Data is received at a relatively constant rate, but signal processors nominally require sudden pulse input data (e.g., according to their respective decompression types). The exemplary system of FIG. 3 first routes its packets to predetermined memory locations in memory 18. Next, respective processors 21 through 24 require component packets from memory 18. Routing the components through memory provides a measure of the speed of desired separation or choke signal data.

Audio, video and data packets are loaded at their predetermined memory locations to allow signal processors convenient convenient access to component data. In order for the loads of the respective component packages to be loaded into the appropriate memory areas, the respective SCID comparators are associated with those memory areas. This association can be done by wires in memory controller 17, or the association can be programmable. If the former, audio, video and audio SCIDs will always be assigned to programmable recorders 13 respectively. Whether the latter of the audio, video or data SCIDs can be loaded into any of the programmable registers 13, and the appropriate association will be programmed into memory controllers 17 when their respective SCIDs are loaded into the programmable registers.

In the steady state, after program SCIDs have been stored in programmable registers 13, the received signal packet SCIDs are compared with all SCIDs in the SCID registers

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79 79 679 028 / ΡΤ programmable. If a match is made to each stored audio, video or data SCID, the corresponding packet load will be stored in the audio, video or data memory area or block respectively.

The respective signal packets are coupled from FEC 12 to memory controller 17 via a signal decoder 16. Only the signal loads are shuffled and the packet headers are passed through the unchanged decoder. Whether or not a package to be unscrambled is determined by the CF mark in the package prefix, and how it is to be unscrambled is determined by the CS mark. If SCID is not matched for a respective packet, the decoder can simply be prevented from passing any data. Alternatively, if there is no SCID match for a packet, the decoder may be allowed to decipher according to its latest settings and the memory write control may be prevented to discard the respective packet.

The decoder is programmed with decryption keys provided by the smart card apparatus 31. The smart card responds to designation information contained in particular program guide packages to generate appropriate decryption keys. The system of the present example incorporates two levels of cipher or program access, ECM designation control messages, and EMM designation management messages. Program designation control and administration information are regularly transmitted in specific SCID-identifiable packets included in the packet stream comprising the program guide. The ECM information contained in these packets is used by the smart card to generate the decoding keys used by the decoder. The EMM information included in these packages is used by the smart card to generate the decryption keys used by the decoder. The designation information included in these packages is used by the subscriber-specific smart card to determine the program material to which the subscriber is assigned. EMM designation information within these packages may be geographically specific, group specific, or subscriber specific. For example, the present system will include a modem (modulator / demodulator) (not shown) for communicating billing information from the smart card to the program provider, for example a satellite transmitter. The smart card can be programmed, for example, with the area code and telephone exchange of the receiver's location. O

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ΕΜΜ may include data, which when processed by the smart card will designate or deny receipt of particular programs in particular area codes.

The program provider may want the ability to darken particular areas or groups with very short driving time. For example, a transmitter may be required to darken a football game in the local stadium area if tickets for the game have not been sold. This information is not available until immediately prior to the start of the game. With such a short driving time it may not be possible to program the EMM to darken the local area. Additional encoding of designation information is included within the designation data loads to allow for the darkening in question.

Packets containing the designation data include a 128-bit payload header arranged in 4 specially encoded 32-bit groups. An E 30 matching filter or code decoder is arranged to detect certain combinations of bit patterns within the 128-bit header. If a match is detected the decoder communicates with the memory controller 17 and the smart card 31 to make the remainder of the designation load available to the smart card (via memory 18). If no match is detected, the charge is not accepted by the specific receiver. Special codes may be periodically changed if the match filter 30 is made programmable. These codes may be periodically provided by the smart card. For more specifics on smart card operation, when related to the viewer's designations, the reader is invited to review section 25 of “THE SATELLITE BOOK, THE COMPLETE GUIDE TO SATELLITE TV THEORY AND PRACTICE”, Swift Television Publications, 17 Pittsfield, Cricklade, Wilts, England.

Matching filter or code decoder E is arranged to perform a second function, which is to detect particular MPEG video headers. These headers or start codes have a length of 32 bits, (which is why the designation payload headers are encoded in 32-bit groups). If video data is lost, an MPEG video decoder can only resume decompression video data at particular data entry points. These points of

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79 79 679 028 / ΡΤ input match the MPEG start codes. The decoder may be arranged to communicate with the memory controller 17 to inhibit the flow of video data to memory upon loss of video packets and to summarize write video loads to memory only after following MPEG start code will be detected by decoder 30.

FIG. 4 illustrates exemplary apparatuses for memory controller 17 shown in FIG. 3. Each program component is stored in a different contiguous block of memory 18. In addition, other data, such as data generated by microprocessor 19 or a smart card (not shown) may be stored in memory 18.

Addresses are applied to memory 18 by a multiplexer 105, and input data is applied to memory 18 via a multiplexer 99. Output data from memory management circuits are provided to signal processors by an additional multiplexer 104. output data provided by multiplexer 104 is derived from microprocessor 19, memory 18 or directly from multiplexer 99. Program data is presumed to have a standard resolution and image quality and to occur at a particular data rate. On the other hand, high definition television signals, HDTV, which may be provided by this receiver, occur at a significantly higher data rate. In practice all data provided by the FEC will be routed through memory 18, through multiplexer 99 and memory I / O circuit 102, except for higher speed HDTV signals, which can be routed directly from multiplexer 99 for multiplexer 104. Data for multiplexer 99 is provided from decoder 16, smart card circuitry, microprocessor 19, and a mean error code source 100. The term "averaging error codes" as used herein means special codewords to be inserted into a data stream to condition the respective signal processor (decompressor) to suspend processing until a predetermined codeword is detected. , such as a start code, and then summarize the processing according to, for example, the start code.

Memory addresses are provided to multiplexer 105 from program addressing circuits 79 to 97 from microprocessor 19,

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679 028 / ΡΤ from smart card apparatus 31 and auxiliary packet address counter 78. Selection of particular addresses at any particular time period is controlled by a direct memory access DMA, circuit 98 Comparator 15 SCID control signals and required data signals from respective signal processors are applied to and responsive to DMA 98, memory access contention is arbitrated. The DMA 98 cooperates with a service indicator controller 93 to provide the read or write addresses to the respective program signal components.

Their addresses for the various signal component memory blocks are generated by four groups of program component registers or service indicators 83, 87, 88, and 92. The start indicators for their respective memory blocks, in which the respective signal components are stored, they are contained in registers 87 for the respective signal components. The start indicators may have fixed values, or they may be calculated by conventional memory management processes in the microprocessor 19.

The latest address indicators for the respective blocks are stored in the service register 88, one for each potential program component. Similar to start addresses, end addresses may have fixed values, or they may have calculated values, provided by microprocessor 19. The use of calculated values ​​for start and end indicators is preferred because a more advanced system is provided. versatile with less memory.

Memory write indicators or top indicators are generated by adder 80 and service top registers 83. There is a service top register for each potential program component. A write or top indicator value is stored in a register 83 and supplied to address multiplexer 105 during a memory write cycle. The top indicator is also coupled to adder 80, wherein it is incremented by one unit, and the increment indicator is stored in the appropriate register 83 for the next write cycle. Registers 83 are selected by the service indicator driver 93 for the appropriate program component that is currently in service.

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In this example it is assumed that the start and end indicators are 16-bit indicators. Registers 83 provide 16 bit write and top indicators. The 16-bit indicators have been selected to facilitate the use of 16-bit and 8-bit power lines for loading start and stop indicators in registers 87 and 88. Memory 18, on the other hand, has 18-bit addresses. . 18-bit write addresses are formed by chaining the two most significant bits from the start indicators to the 16-bit top indicators, with the start indicator bits at the most significant bit positions of the 18-bit write address. Combined. Start indicators are provided by the respective registers 87 to the service indicator controller 93. The service indicator controller analyzes the most significant start indicator bits from the start indicators stored in registers 87, and associates these bits with the 16-bit top indicator bus. This is illustrated by bus 96, shown to be combined with the top indicator bus exiting multiplexer 85, and FIG. 5 with reference to the solid arrows.

In FIG. 5, the middle and top rows of the boxes represent the bits of a start indicator, an address, and a header or end indicator, respectively. The highest numbered boxes represent the most significant bit positions. Arrows indicate which bit positions of the start or top / end indicators originate the respective bits of an address. In this lead the solid arrows represent a steady state operation .

Similarly, memory read indicators or end indicators are generated by adder 79 and end of service registers 92. There is an end of service register for each potential program component. A read or end indicator value is stored in a register 92, and provided to address multiplexer 105 during a memory read cycle. The end indicator is also coupled to the adder 79, in which it is incremented by one unit, and the incremented indicator is stored in the appropriate register 92 for the next read cycle. Registers 92 are selected by the service indicator driver 93 for the appropriate program component that is currently in service.

Registers 92 provide 16-bit end indicators. 18-bit read addresses are formed by chaining the upper two bits

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<img file="PT679028E_D0005.tif" />

start indicators on the 16-bit end indicators, with the start indicator bits at the most significant bit positions of the combined 18-bit write address. The service indicator controller analyzes the most significant start indicator bits of the start indicators stored in registers 87, and associates these bits with the 16-bit end indicator bus. This is illustrated by bus 94 shown to be combined with the end indicator bus exiting multiplexer 90.

The data is stored in memory 18 at the calculated address. After storing one byte of data, the top indicator is incremented by one and compared to the final indicator for this program component, and if they are equal the most significant bits of the top indicator are replaced by the lowest 14 bits of the indicator. and zeroes are placed at the two lower positions of the top indicator portion of the address. This is illustrated in FIG. 4 with reference to the arrows, with parallel thin strokes, between the start indicators and the address. This operation is illustrated by arrow 97, which points from the service indicator controller 93 to the top indicator power line from the multiplexer 85. The application of the lowest start indicator bits 14 is presumed to exceed the top indicator bits. Replacing the top indicator bits with the lowest start indicator bits in the address for this one write cycle causes memory to flow through the memory block designated by the two start indicator top bits, thus obviating the reprogramming write addresses at the beginning of each packet to a single memory location within a block.

If the top indicator ever equals the end indicator (used to indicate where to read data from memory 18) a signal is sent to the microprocessor interrupt section to indicate that the end-end destruction has occurred. . Further writing to memory 18 of this program channel is prevented until the microprocessor allows the channel again. This case is very rare and should not occur in normal operation.

Data is retrieved from memory 18, at the request of the respective signal processors, at addresses calculated by adder 79 and registers 92. After reading one byte of stored data, the end indicator is incremented by one unit and compared end indicator for this logic channel on the service indicator controller 93. If the

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79 79 679 028 / são end and end are equal so the most significant bits of the end indicator are replaced with the lowest 14 bits of the start indicator and zeroes are placed at the two lower bit positions of the end indicator portion. from the address. This is illustrated by the arrow 95 exiting controller 93 and pointing to the end indicator bus from multiplexer 90. If the end indicator is now equal to the top indicator, then its memory block is set to empty and no more bytes will be sent to the associated signal processor until more FEC data is received for this program channel. Effective replacement of the top or end indicator portions of their write or read addresses with the lowest 14 bits of the start indicator may be accomplished by appropriate multiplexing, or by using three status interconnects.

Data transmitted in auxiliary packets is typically directory, header, or control information and is thus processed slightly differently from program component data. The data in the auxiliary packages includes the information needed to establish the indispensable memory storage areas for the respective program components and any included applications. As such preference is given to helper packages. Two service blocks are provided for each component. Each block has an eight-bit sequential address or storage locations for 256 bytes of data. Each block has an eighteen-bit total address, which is illustrated in FIG. 6. The eight address LSBs are provided by a sequential counter. The ninth bit is provided by the CS or scramble key bit from the transport prefix. The tenth to twelfth bits are generated by responding to SCIDs assigned for program detection. This example assumes that the system has the ability to process and detect five program or service components (including the program guide). There are thus five programmed SCIDs in the respective programmable SCID registers 13 and five SCID comparators 15. The five comparators each have an output terminal, and each terminal is assigned a program component. The five possible programs that are associated with the five comparator output terminals are assigned their respective three-bit codes, with three bits being the smallest number of bits that can represent five states. The three-bit codes are entered as the tenth through twelfth bits of the auxiliary packet addresses. SCIDs for the five respective program components are assumed to be assigned to registrars

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679 028 / ΡΤ programmable, arbitrarily numbered 1 through 5. The three-bit codes assigned to the components assigned to programmable registers 1 through 5 are, 000, 001, 010, 011, and 100, respectively. Depending on whether each program component is currently being detected, the three bit code associated with the programmable register containing the current SCID program component will be inserted in the twelfth to twelfth bit positions at the write address of. memory.

The six most significant bits of the 18 auxiliary bit addresses are provided by the microprocessor according to conventional memory management techniques.

FIG. 7 illustrates exemplary auxiliary memory address generation circuits. FIG. 7 includes a prefix register 125 used to pick up the prefix bit CS which is applied to microprocessor 19. The five control lines of the SCID detector 15 are applied to a three bit converter 126 to five control lines. which can be a simple Boolean logical operator. The three bits generated by converter 126 are applied to microprocessor 19 which makes up the respective 10 most significant bit (MSB) portions of the auxiliary addresses. Upon detecting an auxiliary packet, the address portion 10 MSB is applied to the MSB portion of a register of a register bank 128. The 8 LSB portion of the respective register 128 is set to a predetermined value, typically zero, at the beginning. of each auxiliary package. The 8 LSB portion is joined to the 10 MSB portion and applied to an input access of a 10 to 1139 multiplexer. The 8 LSB portion of the respective addresses provided by the multiplexer 129 are coupled to an adder 130, wherein the address value 8 LSB is incremented by one unit and coupled back to the 8 LSB portion of register 128 via an additional multiplexer 127. The incremented LSB portion (with its MSB portion) serves as the next successive address for the respective auxiliary packet. Multiplexers 127 and 129 are controlled by DMA controller 98 to select the current memory block to be addressed. Note that in an alternative embodiment ο μΡΟ 19 may be arranged to establish at least a portion of the auxiliary addresses.

Auxiliary packets are typically processed independently and an entire ancillary packet load is typically loaded into memory prior to

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79 79 679 028 / poder can be used. As such, the memory block to be addressed for writing from a current auxiliary packet will not normally be addressed at the same time for reading and writing purposes. Therefore, the same registers can be used for read and write addressing. Since an auxiliary packet is stored in a respective memory block, portion 8 LSB are repositioned to the predetermined start address in preparation for reading the data. In an alternative arrangement, a parallel bank of registers, multiplexers and an adder, similar to elements 127 to 130, may be configured to generate read addresses. These read addresses may be time division multiplexed with an additional multiplexer in cascade connection with multiplexer 129.

Memory read / write control is performed by the direct memory access and service indicator controllers, DMA, and elements 93 and 94. The DMA is programmed to plan the read and write cycles. Planning is dependent on whether FEC 12 is providing data to be written to memory or not. FEC data write operations take precedence, so that no input signal component data is lost. In the exemplary apparatus illustrated in FIG. 4, there are four types of devices which can access the memory. These are the smart card (not shown), the FEC 12 (more precisely the decoder 16), the microprocessor 19 and application devices such as audio and video processors. Memory contention is handled as follows. The DMA, which responds to data requests from the various processing elements listed above, allocates blocks of memory to the respective program components. Memory access is provided at time intervals of 95 ns, during which one byte of data is read from or written to memory 18. There are two major modes of access assignment, defined by FEC Provisioning Data, or FEC Non-Provisioning Data respectively. Each of these modes is assigned and prioritized as follows, assuming a maximum FEC data rate of 5 Mbytes / second, or one byte for every 200 ns. These are:

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FEC supply data

1) FEC data writing;

2) Microprocessor application read / write device read

3) FEC data writing;

4) microprocessor read / write;

and for

FEC non-delivery data

1) smart card reading / writing;

2) microprocessor application / read / write device read;

3) smart card reading / writing;

4) Microprocessor read / write.

Because FEC data writing cannot be deferred, the FEC (or more correctly the decoder), when the data provision must be guaranteed memory access during each 200 ns interval. The alternating time slots are shared between the application devices and the microprocessor. When no data is available for the devices that request it, the microprocessor is enabled to use application time intervals.

Controller 93 communicates with the SCID detector to determine which of its start, top and end indicator registers to access memory write operations. Controller 93 communicates with the DMA to determine which of the start, end and end registers to access memory read operations. DMA 98 controls the selection of the corresponding addresses and data by multiplexers 99, 104 and 105.

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Preferred alternate circuits for incrementing memory addresses are shown in FIG. 8, circuits that may be used in the apparatus of either FIG. 4 or FIG. 7. FIG. 8 illustrates its implementation as for the implementation of the end indicator according to FIG. 4. At the beginning of a packet, the indicator in the associated register 92A is coupled to adder 79A, in which it is incremented by 1. Instead of storing the intermediate incremental end indicators in registers 92A of FIG. 8 (92 of FIG. 4), intermediate incremental indicator values ​​are successively stored in a working register 107. After the last indicator value for a signal packet is generated, the updated indicator in register 107 is transferred to the register. 92A associated with the SCID packet.

It is not uncommon for data in a memory tab to need to be omitted. For example, a partial package may have been stored when a system error or data interruption occurred. To conserve memory space, data omission is performed simply by overwriting the partial data packet. Overwriting this data is done by resetting the appropriate indicator to the value it displayed at the beginning of the packet. Such a reset is accomplished by not transferring the value in register 107 to the indicator register, which is nothing to do.

It is advantageous to insert averaging error codes in the signal stream of video components when packets are lost to condition the video signal decompressor to suspend decompression until the particular signal entry point occurs in the data stream. It is not practical to predict where and in which video package a next entry point might occur. In order to find the next entry point as quickly as possible, you need to include an averaging error code at the beginning of the first video packet after detecting that a packet has been lost. The circuits of FIG. 4 place an averaging error code at the beginning of all video packets and then strip the averaging error code from their respective packets if there is no loss from a previous packet. The averaging error code is entered at the first M memory address locations reserved for the load of current video packets by writing to memory 18 for M write cycles before the video load arrives from the decoder. At the same time, multiplexer 99 is conditioned by DMA 98 to apply the source average error code 100 to the

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79 679 Ο28 / ΡΤ memory 18 Ε / Ο. Simplesmente is simply ο integer of the memory locations required to store the averaging error code. Assuming that memory stores 8-bit bytes and the average error code is 32 bits, M will be 4.

Addresses for loading the media error code into memory are provided by the respective component video service register 83 via multiplexer 82 and multiplexer 85. It will be appreciated that the first M addresses provided from the indicator register 83, for loading the averaging error code at memory locations that would otherwise be loaded with component video data, will simply be the M sequential addresses that would normally be produced by video top indicator. These same addresses are in a floor delay element M 84, so that immediately after the last byte of the averaging error code is stored in memory 18, the first of the M addresses is available at the output of the delay element 84.

The timing of loading the average error code into memory coincides with determining a lost packet. Loading the averaging error code while determining packet loss does not place timing constraints on signal flow processing.

If a packet loss is detected, the current packet video component is stored in memory 18, starting at the next address or M + 1 address location of the memory block established for that component. This is achieved by conditioning the multiplexer 85 to continue passing the delayed top indicators of the appropriate register 83. Alternatively, if no packet loss is detected, the first M bytes of the video component in the current packet are stored in memory locations where the averaging error code was immediately stored previously. This is accomplished by the service indicator controller conditioning the multiplexer 85 to pass the delayed top indicators of the delay element 84 to the write cycles. At the end of the M write cycles the service indicator controller 93 will condition the multiplexer to pass back top indicators without delay. When the multiplexer switches back to the delayed top indicators, the next delayed indicator will correspond to the order address M + 1.

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Packet error or loss detection is performed by an error detector 101 which responds to the current packet's DC and HD data. Detector 101 examines the DC continuity count in the current packet to determine if it differs from the DC of a previous packet of a unit. In addition, the TOGGLE bit in the current packet is examined to determine if it has changed from the previous packet. If the CC value is incorrect, the status of the TOGGLE bit is examined. Depending on whether one or both CC and TOGGLE bits are in error or changed respectively, a first or second error correction mode is instituted. In the second mode, initiated by CC is in error and having changed the TOGGLE bit, the system is conditioned to reposition to a packet containing an image layer header. In the first mode, where only CC is erroneous, the system is conditioned to reposition to a packet containing a slice start code. (A slice layer is a subset of the compressed data within a frame.) In both the first and second modes, the media error code written to memory is retained in its load to alert the decompressor to take remedial action.

Depending on the particular designs of a given receiver, it may or may not be conducive to including averaging error codes in different components of the signal components when the respective component transport packets are lost. In addition, it may be advantageous to use different averaging error codes for different signal component formats or compression processes. Thus one or more sources of averaging error codes may be required.

FIG. 9 illustrates an exemplary flowchart of the DMA 98 memory access process. The DMA responds (200) to the detection or non-detection of a packet received by SCID detection. If an SCID has been detected indicating the presence of decoder 16 data to be written to memory, one byte of program data from the decoder is written (201) to separator memory 18. The memory block in which it is written is determined. by processor 93, which responds to the current SCID. The DMA then determines (202) whether any of the program component processors, including the smart card and pPC, are requesting data or read / write (R / W) access to memory 18. If not When data requests are made in the DMA, the process returns to step 200. If a data R / W request is made, DMA

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79 79 679 028 / ΡΤ determines (203) the priority of the request. This will be accomplished by a conventional interrupt routine or alternatively by a sequential one-byte service, in an arbitrary order of such data requesting program processors. For example, assume that an arbitrary order of access priority is video, audio I, audio II, smart card, and μΡΟ. Also assume that video, audio II and ο μΡΟ are requesting memory access. During the current operation of step 203 a video byte will be read from memory. During the next operation of step (203) an audio byte II will be read from memory and during the next subsequent occurrence of step (203) one byte of the μΡΟ data will be written to memory 18 or read from it and so on. . Note that the smart card and μ acesso access addresses are provided by the smart card and μΡΟ respectively, but the addresses for video, audio and program guides are available from the address indicator layout (80 to 93).

Once priority access has been established (203), the required program processor (204) is served with a data byte written to memory 18 or read from it. Next, a data byte of decoder 16 is written (205) in memory. A check (206) is made to determine if ο μΡΟ is requesting access. If ο μΡΟ is requesting access, it is served (207) with one data byte. If ο μΡΟ is not requesting access, the process skips to step 202 to determine if any of the program processors are requesting access. In this way the input data is always guaranteed access to another memory access period, and intervening memory access periods are spread between the program processors.

If data is not currently available from the decoder 16, i.e. an SCID is not currently detected, then the process (208 to 216) is followed. Firstly (208) the smart card is examined to determine if a memory access is required. If so, it is given one byte memory access 209, otherwise a check 210 is made to determine if any of the program processors are requesting memory access. If an R / W data request has been made, the DMA determines (211) the priority of the request. The appropriate processor is served (212) with read-write access to one-byte memory. If an R / W data request is not made by the

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79 679 028 / ΡΤ program processors, ο process skips to step (213) where a test is performed to determine if the smart card is requesting memory access. If so, it is served (216) with one-byte memory access, otherwise the process skips to step (200).

It should be recognized that, in the present preferred example, when in FEC Non-Delivery Data mode, the smart card is provided with two to one access precedence over all other program processors. This priority is programmed on a programmable state machine within a DMA device and is subject to change by μΡΟ. As mentioned above, the system is intended to provide interactive services, and ο μΡΟ 19 will respond to interactive data to at least partially perform the interactive operation. Thus, ο μΡΟ 19 will use memory 18 for both application storage and working memory. In these cases, the system operator may change the memory access priority to give μΡΟ 19 the most frequent memory access. Memory access priority reprogramming may be included as a subset of the interactive application instructions.

FIG. 10 illustrates an exemplary packet detection apparatus which includes conditional access information or MPEG start codes (decoder 30 of FIG. 3). Either decoder 30 is conditioned to detect designation loads or MPEG start codes is a function of the SCID being currently received. In FIG. 10, it is assumed that the data provided from the decoder 16 is aligned in 8-bit bytes and in packets. That is, the first byte of a designation payload or the first byte of an MPEG start code is precisely aligned with the start of a packet load, such that for detection of the specific header or start code words. , its position in the bit / byte stream is precisely known. Data from decoder 16 is applied to an 8-bit register 250, which has an 8-bit parallel output access coupled to the respective first input links of a comparator 254 which can be configured, for example, by a bank. eight exclusive NOU (XNOU) circuits with their respective output connections coupled to an E-port and a latch. The latch may be a data latch arranged to lock the results of port E at each byte range.

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A 32-bit MPEG start code is stored as four bytes in an 8-bit register bank 265. Designation header codes are stored as 8-bit bytes in an 8-bit register bank 257. Loading of register banks 251 and 265 are controlled by microprocessor 19 and / or the smart card. Start code registers 265 are coupled to a four to one multiplexer 266, and the designation header registers are coupled to the sixteen to one 257 multiplexer. The output access points of multiplexers 257 and 266 are coupled to a two to one 249. The respective output connections of multiplexer 249 are coupled to the respective corresponding second input terminals of comparator 254. Note that the input and output connections of multiplexers 249, 257 and 266 are 8-bit buses. If the respective values ​​displayed on respective output links of register 250 are correspondingly the same as the output values ​​displayed by respective output links of multiplexer 249, a true signal is generated by comparator circuit 254 for the corresponding data byte.

For start code detection, multiplexer 266 is exploited by counter 258 to sequentially couple the four different registers 265 to the XNOU in sync with the occurrence of the first four data bytes coming from the decoder 16. Alternatively, for designation load header detection, multiplexer 257 is exploited by counter 258 to sequentially couple registers different from registers 265 in the comparator circuit.

The comparator circuit output is applied to an accumulation and test circuit 255. Circuit 255 determines if any of a predetermined number of byte matching conditions have occurred, and if so, generates a write enable signal for the designation data on a portion of the particular load under examination. In the present system the designation payload header contains 128 bits arranged in four 32-bit segments. Different subscribers will be willing to look at different combinations of 128-bit bytes. For example, a subscriber apparatus may be arranged to match the first four bytes of the designation payload header. Another subscriber apparatus may be arranged to match the second four bytes of the designation payload header and so on. In either of these exemplary situations the circuitry 255

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79 679 028 / ão will determine if a match has occurred for the appropriate four consecutive bytes.

The apparatus of FIG. 10 also includes circuits (elements 261 to 263) for detecting an all zero designation load header condition. The bits of the respective bytes arriving from the data are coupled to the respective 8-bit OR port 263 terminals. If either bit is a logical bit, the OR 263 port generates a logical output of one. The output of OR port 263 is coupled to an input of a two-port OR port 262, which has one output and a second input coupled, respectively, to the data input and output terminals Q of a D-type latch 261. The type D latch is timed by synchronization circuit 259, synchronized with the arrival of input data bytes. If any bit in any of the data bytes which occurs after the latch is repositioned is a logical one, latch 261 will show a logical one at its output Q until the next repositioning pulse. Output Q of latch 261 is coupled to an inverter which shows a zero output level whenever the latch shows an output level one. Thus, if after the 128 bits (16 bytes) of the header pass through register 250, the inverter output is high, then the 128 bits are evaluated as zero. Responding to the detection of a high drive output level after the assignment load header has passed, circuits 255 will generate a data write enable signal.

The system partition has been found to be particularly effective such that the SCID detector, decoder, addressing circuits, conditional access filter, and smart card interface are all included in a single integrated circuit. This limits the number of external circuits which can lead to critical timing constraints.