Computer control

<td>POLAND REPUBLIC ICE</td><td>PATEINT DESCRIPTION</td><td> 81689</td>

<td></td><td>Additional patent to patent</td><td>MKP G06f 15/16</td>

<td></td><td>Reported: November 19, 1971 (P. 151661)</td><td></td>

<td></td><td>Priority: November 20, 1970 for 1 and 2</td><td>Intt CI² G06F 15/16</td>

<td>OFFICE PATENT PRL</td><td>Sweden The application was announced on 20.04.1973 Patent description published: 20.04.1976</td><td>READING ROOM '^officeę^dat Patent Γ »!» ϊ · ί lamwnr.'f</td>

Inventor: --— Patent holder: Telefonaktiebolaget LM Ericsson, Stockholm (Sweden)

A system for synchronizing meters in a system composed of many computers

The subject of the invention is a synchronization system of computer counters in a data processing system consisting of a number of cooperating computers, in which system the length of the primary interval is determined by the meter reaching a certain state.

More precisely - the problem is the mutual synchronization of counters in individual computers, with synchronization being understood as storing a numerical value in a specific number of digital positions in the counters in all computers.

In particular, the invention relates to a system for synchronizing counters, each of which belongs to one computer of a data processing system consisting of many computers and each receives counting pulses from its own synchronization oscillator, whereby these counters by reaching a specific numerical position determine the duration of the processing period and then with the help of the synchronization signal they are moved to the initial numerical position, and when they reach this initial numerical position, they themselves produce a synchronization signal. In a data processing system composed of many cooperating computers, they must be mutually synchronized so that, for example, common memory assemblies can be used and information can be exchanged between computers. It is known to control several computers by means of a common clock synchronization generator. - However, this has the major disadvantage that when this clock generator is damaged, such damage affects the entire data processing system. From the description of RFN DT — OS 1952926, a system of computers with two operating parallel assemblies is known, one of which is an active unit and the other is a backup unit, with the backup unit synchronization generator being synchronously controlled by the active unit synchronization generator to enable takeover without any interruption data processing by the backup team when the active team is damaged.

The disadvantage of this type of synchronization is that it is not suitable for such a computer system that is composed of many cooperating and simultaneously active computers, and the ratio of the active team to the reserve team is not clearly defined as a result. , '

The object of the invention is to overcome this disadvantage, and the object of the invention is to provide a multi-computer system with such a system of mutual synchronization between computers that if any computer is damaged, the other computers will continue to maintain mutual synchronization.

689

This task was solved according to the invention by the fact that synchronizing signals are fed to a common cable for all computers connected to each computer with a logic circuit, which on the one hand contains a trigger circuit triggered by a signal and on the other hand contains a pulse generating system which after triggering the flip-flop system produces a pulse of a specific duration, and, furthermore, the output of this pulse generating circuit is connected to the counter control input and to the trigger input of the trigger and shifting system, as a result of which the trigger system is blocked during the synchronization signal. . .

According to the invention, each computer contained in the system is controlled, firstly, by its own synchronization generator, and secondly, mutual synchronization occurs by the fact that each computer periodically gives a synchronization pulse to a common cable for all computers.

The system according to the invention is so advantageously made that a delay system is used which prevents the meter reading from changing at the same time by the next switching pulse and by the signal from the trigger system which replaces the pulse generating system and includes a logic circuit whose inputs are connected to a synchronization generator and a flip-flop system, and the output is connected to 'the first monostable flip-flop system, and furthermore, the delay circuit includes a logic circuit I with an inverting input to which the output of the second monostable flip-flop system is connected, controlled by a synchronization generator, while the output of the first monostable flip-flop circuit is connected to the second input of the logic circuit I.

The subject of the invention is presented on the basis of the attached drawing, in which Fig. 1 shows an example of a block diagram according to the invention, consisting of three computers, Fig. 2 - construction details of one of the blocks of Fig. 1, and Figs. 3-5 explaining time charts . Referring to Fig. 1, three computers D1, D2, D3 are interconnected by a PIB line, showing only those fragments that are necessary to demonstrate the invention. All computers are built in the same way. The CLO clock of each computer increases the state of the CLR binary counter, for example having twelve positions, which in Fig. 1 are numbered from 0 to 11, with position 0 being the least significant.

The synchronization system can be briefly described as follows. Clocks in individual computers increase the state of the respective counters, with the assumption that the counter in D3 increases the fastest. This counter will therefore be the first in a situation where, for example, the flip-flop at position 7 changes its state from I to 0, so that its eight least significant positions will contain zeros. Switching this flip-flop sends a synchronization signal to the E3 line. The synchronization signal is fed to a common PIB line, and then to all computers via lines F1, F2, F3. The conditions triggered by the incoming synchronization signal are identically the same in computers D1 and D2 and therefore · they will be described in detail only in computer D1.

The synchronization signal comes to computer D1 through the F1 line and through the C system, which blocks the signals coming out of the computer, to input 1 of the FF flip-flop, which, as will be presented below, causes all synchronization signals coming within a specified time after the first synchronization signal to be overlooked. All computers send synchronization signals when their counters, as a result of counting clock pulses or synchronization, are in the previously presented state. However, when the FF flip state changes, only the first synchronization signal will cause synchronization. In a simpler solution, which corresponds to the position a of switch B, the change of the FF flip-flop condition activates the monostable system G, which generates a pulse, which on the one hand is fed back to the reset input of the FF flip-flop, zeroing it and keeping it in this state for the duration of the pulse, and the other side to the CLR counter control input. In this way, the eight least significant positions, i.e. positions 0-7, are set to zero, and thus the counter reaches the same status as the counter in computer D3 that sent the synchronization signal.

In some cases, however, it is inconvenient for the synchronization pulse to be fed to the meter at any time, in particular simultaneously with the clock adding pulse, because at the same time the appearance of these two switching pulses may cause the occurrence of undesirable transient states in the meter, which entail ambiguity of the meter operation .

By placing delay system A between the output of the FF flip-flop and the control input of the CLR counter, this can be avoided, i.e. it is achieved that synchronization does not occur when the counter level increases. Position B of switch B corresponds to this solution. Synchronization signal sent from the meter when the position 7 changes? 1 to 0, it is converted into a pulse either by the · C system on the output line in the sending computer or by the C system on the input line in the receiving computer.

Referring to Fig. 2, which shows the structure of Delay A in Fig. 1, input 24 is connected to the output of the FF flip-flop in Fig. 1, and clock input from the clock CLO is fed to input 25. Clock pulses are fed to one input of the dual-input AND-21 element, and the signal from the output of the positive flip-flop to the other 'its input.

The first circuit I-21 delays the clock signal before feeding it to the first SS1 forming circuit, which is for example a monostable flip-flop. The SS1 system generates a pulse, the duration of which is divided into two periods t1 and t2, where t1 is the maximum transfer propagation period through the eight least significant positions of the CLR counter, and t2 the period in which the FF flip-flop blocks the other incoming synchronization pulses, i.e. sometimes necessary for counter synchronization. The pulse generated by the 'first forming system SS1 is fed to one input of the second input, the second system 23. The clock pulse from the clock is simultaneously used to stimulate the second forming system SS2, built for example with a monostable flip-flop. The pulse generated by the SS2 system, whose duration is equal to t1, is given to the second input of the second system 23, which is the negated input. At the output of system I 23, therefore, a pulse of duration t2 is obtained, the front edge of which is shifted by the time t1 in relation to the front edge of the clock pulse. The pulse generated by the second system I 23 is applied. from output 26 on the one hand to the FF flip-flop, which after blocking the pulse stops blocking the incoming synchronization pulses, and on the other hand is fed to the control input of the CLR counter to zero the eight least significant positions, i.e. positions 0-7. The CLR counter has the property that the 8 'position is switched by one pulse.

The synchronization process is more illustrated by the graph in Fig. 3, in which the vertical arrows indicate the cause and effect of the pulses, the horizontal axis is the time axis. Fig shows the synchronization pulse which computer D3 is fed to the FF flip-flop in computer D1. The FF flip-flop is set up with a synchronizing signal, as indicated by the vertical arrow in the drawing from Fig. 3a to Fig. 3b, which shows the state of the FF flip-flop at the input 24 shown in Fig. 2. As long as no computer clock pulse appears at the input 25 of Fig. 2, nothing happens in the system, Fig. 3c shows the clock pulse, and Fig. 3d pulse at the output of the second circuit I 21. The graph shows that the pulse of Fig. 3d is generated by the pulse of Fig. 3c, which is correct provided that the FF flip-flop is in one state, i.e. the signal in Fig. 3b is high . Impulse with fig. 3d energizes the SS1 monostable flip-flop, which generates a pulse of duration t1 + t2, shown in Fig. 3e. The clock pulse of Fig. 3c further stimulates the monostable flip-flop SS2, which generates a pulse of duration t1, shown in Fig. 3f. When the pulse of Fig. 3f is negated at the input of the second circuit I 23, an impulse will appear at the output of this system when the pulse from the SS2 monostable flip-flop ends, as shown in Fig. 3g. Impulse with f 3G has a duration, which is the difference in the duration of pulses generated by SS1 and SS2. This pulse also sets stand up zero, for the duration of the pulse, the FF flip-flop keeps it in this state until the counter is synchronized.

Two basic possibilities can be distinguished in the synchronization system. Assuming for simplicity a system consisting of only two computers, the first possibility is a situation in which the meter reading in the first computer at the moment. synchronization is greater than the counter on the other computer. The second option is a situation in which the state of the first meter is equal to the state of the second meter.

The graph of synchronization in a two-computer system is shown in Fig. 4 in a situation where the state of the first counter is greater than the state of the second counter. If the synchronization signal appears, for example, from computer D1 on line E1 (Fig. 1), then it is sent to both other system computers and line F1 to computer D1 itself. This last signal is hereinafter referred to as its own synchronization signal.

Fig. 4a ', b # ........ f show signals in the D1 communication, and Fig. 4a °, b ......... f' signals in the computer

D2, whose counter is less than the computer's D1.

Figs. 4a 'and a show the meter readings at positions 0-7 of the respective computers, Figs. 4b' and b clock pulses, Figs. C 'and c. Outgoing synchronization signals and Figs. 4d'. and d. incoming signals. synchronizing. In Fig. 4e, the high level depicts the time at which the FF flip-flop is zero, and Fig. 4f and f shows a signal that resets the 0-7 counter positions and resets the FF flip-flop.

Assuming that the counter in the faster computer D1 contains ones at eight minor positions (Fig. 4a '), there is a guarantee that after the next clock pulse a' synchronizing 'signal will be sent (Figs. 4b' and c '). This signal is transmitted on one side to computer D2, as shown in Fig. 4d, and on the other hand as its own synchronization signal to computer D1 (Fig. 4d '). In both computers, the FF flip-flops are set to state one, fig. 4e ', and the synchronizers are waiting for the next clock pulse. According to the example, the computer counter D2 is 7 by less than the computer counter D1 and when both clock pulses appear in both computers, one will be added to both counters. Then both counters are synchronized with waiting ^^ n ^^ and ^^ ni ^ ^ me, so that positions 0-7 will contain zeros.

689

Synchronizing signals as mentioned previously are only produced when the state of position 7 changes from one to zero, hence as a result of synchronization of the D2 computer, a synchronization signal will be sent to the D1 computer (the second pulse in Fig. 4d) and the synchronization operation will be repeated after for the second time on both computers. This time, however, there will be no change in position 7 from one to zero in any meter, and therefore no further synchronization signals will be generated. So in the described synchronization system the younger positions of each counter were set twice to 'zero state'.

Referring to Fig. 5 showing the course of synchronization in a two-computer system, when the states of both counters are equal, Fig. 5a ', b' ........ f shows the signals in the computer Dl, and Fig. 5a, b .. ...... f in computer D2, with the clock pulse appearing earlier in computer D1.

According to Figs. 5a 'and a, the counters of both computers contain ones in eight least significant positions. The clock pulse in computer D1 (Fig. 5b ') appears slightly earlier than the clock pulse in computer D2 (Fig. 5b). The clock pulse adds one to the meter in computer D1, so that the meter will contain zeros at positions 0-7 simultaneously with the synchronization signal being sent (Fig. 5c '). This signal will not cause any changes in the D2 computer, because in the meantime its counter reached the state of all zeros at positions 0-7 (Fig. 5a) under the influence of a clock pulse (Fig. 5b). On the other hand, computer 01 has adopted its own synchronization pulse (Fig. 5d), which causes the meter to synchronize after the next clock impulse, i.e. when the meter was increased by one (Fig. 5a ',. The above solutions lead to the statement that if the computer counter is equal, the faster counter will wait for a slower. .

As can be seen from these two examples, the effects of the exchange of synchronizing signals between cooperating system computers depend largely on the tolerance of clocks. The narrower the tolerances, the less likely there will be the double synchronization process shown in Figure 4.

Thus, the most common condition of a synchronization system is that a faster computer is waiting for a slower time^s. No^kmy computer controls all^s time passed by synchromization^ęchange ^komputer^aboutin those initiating this process. This results from Fig. 5, where computer D1 is delayed so much during synchronization with respect to computer D2 that the next synchronization signal is likely to be sent from computer D2.

In the system, they will increase the number of computers, synchronization control will be exchanged irregularly between computers, but computers whose counters are increased the fastest will control synchronization, on average, more often than other computers.