Modifying run-time-instrumentation controls from a lesser-privileged state

TECHNICAL FIELD [0001] The present invention relates generally to processing in a computer environment, and more particularly, to varying control of performance instrumentation from a less-favored state.

BACKGROUND OF THE INVENTION [0002] Computer processors execute programs or instruction streams using increasingly complex branch prediction and logic circuits that buffer instructions. These processes have been introduced to increase the throughput of instructions and therefore processing efficiency. The introduction of logic circuits to improve performance makes it difficult to predict for sure how specific software will be performed on a computer processor. During the software development process, there is usually a balance between functionality and performance. The software is executed on one or more levels of abstraction from the basic hardware that executes the software. If the hardware is virtualized, an additional layer of abstraction is introduced. With the introduction of logic to increase efficiency, and different levels of abstraction, it is difficult to maintain a thorough understanding of what is currently happening at the hardware level when the program is being executed. Without this information, software developers use more abstract methods, such as duration of operation, memory usage, number of threads, and the like for optimizing software. US Patent Publication No. 2010/0088771 A1 (Heller, LC et al. "Virtualization of a Central Measurement Unit Measure"), April 8, 2010) discloses the ability to measure the main computing unit, virtualized in to maintain the simultaneous use of this ability by a number of slave machines guest) within a virtual environment. Each slave machine of this environment has an independent control of enabling / disabling this capability for such a slave machine.

[0003] US 2005/0034107 A1 (Airaud, C. et al. "CrossTriggering of Processing Devices"), February 10, 2005) discloses a data processing device for mutual-triggering processes diagnostic devices on numerous processing devices. This data processing device comprises a routing module having a plurality of transmission channels, wherein one or more of these transmission channels is capable of indicating the occurrence of a diagnostic event on one or more processing devices.

SUMMARY OF THE INVENTION

TECHNICAL PROBLEM [0004] If information specific to hardware is available, it is usually provided to the designer after the event, and is provided as a whole, at a high level, and / or interwoven with the activity of other programs and the operating system, making it difficult to recognize problems that may affect the performance and accuracy of the software.

TROUBLESHOOTING [0005] Embodiments include a method, system and product in the form of a computer program to vary modulated run-time-instrumentation controls (MRIC) from a less-privileged state. The MRIC instruction is downloaded. This MRIC instruction contains the address of the run-time control instrumentation block (RICCB), the RICCB is taken based on the address contained in the MRIC instruction.The RICCB contains values ​​for changing the subset belonging to the actuator instrumentation processor. Performing instrumentation includes the current buffer address (RCA) of the buffer position instrumentation (RIB) program of the performance instrumentation program. RIB stores information about the performance instrumentation of these events identified by the processor during program execution. These RICCB values ​​are loaded for the control of the performance instrumentation. Information about the event is delivered to the RIB based on the values ​​that have been loaded for the control of the performance instrumentation. Considered from the standpoint of the first aspect, the present invention provides a computer-implemented method for performing changing actuator controls, MRIC, instructions from a program operating in a less-privileged processor state, MRIC instruction for setting only a subset of actuator controls located in the register, wherein all these said actuator controls can be loaded by the privileged LRIC actuator controls, the instruction being executed in a preferred processor state, the method comprising: downloading the MRIC instruction, the MRIC instruction containing the address of the instrumentation control block, RICCB; downloading, by the processor, this RICCB, where RICCB contains a number of execution instrumentation control values ​​for changing said member belonging to the actuator control instrumentation, a subset of executory instrumentation controls containing the current buffer address of the performance instrumentation program, RCA, from the RIB buffer position of the a_runtime instrumentation program, where the RIB is used to store information on performance instrumentation for events identified by the processor during program execution; loading, numerous values ​​for controlling the performance instrumentation; using these loaded numerous values ​​to provide information about the event of performance instrumentation to the RIB; obtaining a value dependent on the model for at least one of the plurality of RICCB values; and loading of this model-dependent value for controlling the performance instrumentation. Considered from the viewpoint of the next aspect, the present invention provides a computer system for performing changing actuator controls, MRIC, instructions from a program operating in a less-privileged state of the processor, where the RICCB contains a number of execution instrumentation control values ​​for changing the said subset of control inputs of the computer processor execution instrumentation, a subset of executory instrumentation controls containing the current address of the performance instrumentation control buffer, RCA, buffer position of the riffing program, RIB, where the RIB is used to store information on performance instrumentation events recognized by the computer processor during program execution; loading of these numerous values ​​to control the performance instrumentation; using these loaded numerous information about the RIB implementation event to obtain a value-dependent model for at least one of these multiple RICCB values;

[0006] Additional features and advantages are realized by these techniques of the present invention. Other embodiments and aspects of the present invention are described in detail herein and are considered as part of the invention as claimed. For a better understanding of the present invention with its advantages and properties, reference should be made to the description and figures of the drawing.

[0007] The essence of the invention is specifically indicated and separately claimed in the claims at the end of the present description. These and other features and advantages of the present invention result from the following detailed description taken into account in connection with the accompanying drawing figures, in which:

BRIEF DESCRIPTION OF THE DRAWINGS [0008] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIG. 1A is a diagram illustrating an example of a host computer system in an embodiment;

FIG. 1B is a diagram illustrating an exemplary emulation computer system in an embodiment;

FIG. 1C is a diagram illustrating an exemplary computer system in an embodiment;

FIG. 2 is a diagram illustrating an exemplary computer network in an embodiment;

FIG. 3 is a diagram illustrating elements of a computer system in an embodiment;

FIG. 4A shows the components of the computer system in an embodiment;

FIG. 4B shows the detailed elements of the computer system in an embodiment;

FIG. 4C shows the specified elements of the computer system in an embodiment;

FIG. 5 is a schematic diagram of a system for processor performance instrumentation according to an embodiment;

FIG. 6 shows an instruction to change the performance instrumentation (MRIC) in an embodiment;

FIG. 7 is a flowchart for initiating an MRIC instruction from a less-preferred state program in an embodiment;

FIG. 8 is a flowchart for initiating an MRIC instruction from a less-preferred program state in an additional embodiment;

FIG. 9 shows a part of a rationing control actuation block (RICCB) comprising controls, which may be set by a preferential state in an embodiment;

FIG. 10 shows a portion of the RICCB control block if the semi-privileged bit (K) is set to 1 in an embodiment;

FIG. 11 depicts a portion of the RICCB controls if the semi-privileged bit (K) is set to 0 in an embodiment;

FIG. 12 shows the reporting group according to an embodiment; and FIG. 13 illustrates a product in the form of computer software in the form of an implementation.

DESCRIPTION OF EMBODIMENT [0009] An embodiment of the present invention is a system, method and product in the form of a computer program for updating a subset of actuator control inputs from a less-privileged state. In an embodiment, a program with a less-privileged state has the ability to change most or all of the actuator controls based on the correctness of current actuator controls, the current state of actuator controls, and based on the marker (K) indicating that the configuration in the less-favored state is allowed. The less-privileged state program performs a change control instruction (MRIC) of the performance instrumentation to update the control of the performance instrumentation. Despite this,

[0010] FIG. 1A shows representative components of the superior computer system 50 in an embodiment. A different combination of components can also be used in a computer system. This representative superior computer system 50 includes one or more processors 1 connected to the storage space (computer memory) 2 as well as to the I / O interfaces to the storage devices 11 and networks 10 for connecting to other computers or SAN devices and the like. Processor 1 is compatible with architecture having a designed set of instructions and designed functionality. Processor 1 can have dynamic address translation (DAT) 3 to convert program addresses (virtual addresses) to real addresses in memory. DAT 3 typically includes a translation lookaside buffer (TLB) 7 for buffering translation so that subsequent access to this computer memory block 2 does not require a delay associated with address translation. Typically, the cache 9 is applied between the computer memory 2 and the processor 1. The cache 9 can be hierarchical and have a large cache available for more than one CPU, and smaller, faster (lower level) caches between this large cache and each cache CPU. In some embodiments, these lower-level caches are separated to provide low-level caches for retrieving instructions and accessing data. In the embodiment, the instruction is retrieved from the computer memory 2 by the instruction retrieval unit 4 via cache 9. This instruction is decoded in the instruction decoding unit 6 and provided (along with other instructions in some embodiments) to the instruction execution units 8. Typically, several instruction execution units 8 are used, e.g. an arithmetic execution unit, a floating-point execution unit, and a branch instruction execution unit. The instruction is performed by the instruction execution unit 8, accessing the arguments from the registers specified by the instruction or from the computer memory 2, as needed. If access to the argument (to be downloaded or saved) from computer memory 2 is to be obtained, then access is dealt with, under the supervision of the instruction being performed, the read-write unit 5. The instructions can be performed in hardware circuits or in the internal microcode (firmware) or in combination of the two.

[0011] In FIG. 1B, is an image of an emulated computer system 21 that emulates a superior computer system with a superior architecture, such as the superior computer system 50 of FIG. 1. In this emulated master computer system 21, the host processor 1 is the emulated master processor (or virtual master processor) 29, and comprises a native processor 27 having a native instruction set architecture different from that for the processor 1 of the computer system 50. The emulated computer system 21 has a memory 22 available to the native processor 27. In an embodiment, the memory 22 is divided into a part of the computer memory 2, and a portion of the memory 23 of the emulation procedures. Computer memory 2 is available for programs of this emulated computer system 21 in accordance with the architecture of the host computer. Native processor 27 executes native instructions of a structured instruction set for an architecture other than that of emulated processor 29, whereby native instructions are obtained from memory 23 emulation procedures, and can access host computer instructions for execution from a program in computer memory 2 by applying one or more instructions obtained in the next & access / decode procedure, which can decode those parent computer instructions accessed to determine the procedure to execute the native instruction to emulate the function of the host computer to which access has been granted. Other functionalities, which are defined for the architecture of the superior computer system 50 may be emulated by the designed functional procedures, including functionalities such as general purpose registers, control registers, dynamic address translation, and input / output subsystem (I / O) and memory subsystem support a handheld processor. These emulation routines may also use functions available in the native processor 27 (such as general-purpose registers and dynamic translation of virtual addresses) to enhance the performance of these emulated procedures. Special accessories and unloading mechanisms may also be provided to assist the native processor 27 in emulating the functions of a superior computer system 50.

[0012] In a mainframe computer, designed machine instructions are used by programmers, in the present times typically "C" programmers through a compiler application. These instructions stored on the storage medium can be used natively on the IBM z / Architecture server, or alternatively on machines that support other architectures. They can be emulated in existing and in future IBM mainframe servers and in other IBM machines (for example in pSeries (R) servers and xSeries (R) servers). They can be performed in machines operating under the Linux operating system or in various machines using accessories manufactured by IBM (R), Intel (R), AMD^TM, Sun Microsystems and others. In addition to working on hardware under the Z / Architecture (R) architecture, Linux can also be used as machines that use Hercules, UMX, Fundamental Software, Inc. emulation. (FSI) or Platform Solutions, Inc. (PSI), generally work in emulation mode. In emulation mode, the emulation software is executed by a native processor to emulate the architecture of the emulated processor.

[0013] One or more components of the emulated computer system 21 are further described in "IBM (R) z / Architecture Principles of Operation" ("Principles of operation of the IBM / R) z / Architecture"), publication No. SA22- 7932-08, 9th edition, August, 2010. IBM is a registered trademark of International Business Machines Corporation, Armonk, New York, United States of America. Other names used herein may be registered trademarks or product names of International Business Machines Corporation or other companies.

[0014] The native processor 27 typically runs emulation software stored in a memory of 23 emulation procedures comprising either firmware or a native operating system to emulate the emulated processor. The emulation software is responsible for downloading and executing the emulated processor architecture instructions. The emulation software keeps the emulated program counter to control the instruction boundaries on an ongoing basis. The emulation software may retrieve one or more emulated machine instructions at once and convert this one or more emulated machine instructions into a suitable group of native machine instructions for execution by the native processor 27. These transformed instructions can be buffered so that faster conversion can be achieved. Emulation software maintains the architecture of the emulated processor to ensure proper operation of the operating system and software written for the emulated processor. In addition, the emulation software provides resources recognizable by the emulated processor architecture including, but not limited to, control registers, general-purpose registers, floating point registers, dynamic address translation functions including, for example, segment arrays and page arrays, interrupt mechanisms, thread switch mechanisms , time of day (TOD) clocks and designed interfaces for I / O subsystems,

[0015] The specific instruction that is emulated is decoded, and a subroutine is called to perform the function of that particular instruction. The software emulation function emulating the function of the emulated processor 29 is implemented, for example, in a subprogram "C" or in a controller, or some other way of providing a controller for a specific hardware, which will be within the knowledge of the person skilled in the art after understanding the preferred description. implementation form.

[0016] In an embodiment, the present invention may be implemented programmatically (sometimes referred to as a licensed internal code, firmware, micro-code, milli-code, pico-code and the like, each of which will be in accordance with the present invention) . Referring to FIG. 1A, the processor also known as the CPU (master computing unit) 1 of the master computer system 50 gains access to software program code that includes the present invention from a storage device 11 such as a long-term storage medium, a CD-ROM, a tape drive, or a hard disk. The software program code may be included on any of a number of known media used in a data processing system, such as a floppy disk, hard disk, or CD-ROM. This code can be distributed on such a medium,

[0017] Alternatively, the program code may be included in the computer memory 2, and access to it via processor 1 may be obtained there- by using a processor bus (which is not shown). Such a program code includes an operating system that controls the function and interaction of various computer components and one or more application programs. The program code is typically paged from a compact medium such as a storage device 11 to the computer memory 2, where it is available for processing by the processor 1. These techniques and methods for entering software program code into memory or physical media, and / or providing this software code through the network are well known and will not be discussed further here. Program code,

[0018] FIG. 1C represents a representative hardware system such as a workstation or server in which the present invention may be embodied. The system 100 of FIG. 1C comprises a representative basic computer system 101, such as a personal computer, workstation or server, including an optional peripheral device. The basic computer system 101 includes one or more processors 106 and a bus (not shown) used to connect and allow communications between this one or more processors 106 and other components of the basic computer system 101 according to known techniques. The bus connects a processor 106 to a memory 105 and a long-term storage space 107, which may include, for example, a hard disk (including, for example, any magnetic medium, CD, DVD and flash memory) or tape drive. The basic computer system 101 may also include a user interface adapter that connects the one or more processors 106 via a bus with one or more interface devices such as a keyboard 104, a mouse 103, a printer / scanner 110 and / or other interface devices, which may be any user interface device, such as a touch screen, a table with input buttons and the like. The bus also combines this one or more processors in a display device 102 such as an LCD or a monitor via a graphics card. which connects one or more processors 106 via a bus with one or more interface devices, such as a keyboard 104, a mouse 103, a printer / scanner 110 and / or other interface devices, which may be any user interface device, such as a screen touchscreen, a table with input buttons and the like. The bus also combines this one or more processors in a display device 102 such as an LCD or a monitor via a graphics card. which connects one or more processors 106 via a bus with one or more interface devices, such as a keyboard 104, a mouse 103, a printer / scanner 110 and / or other interface devices, which may be any user interface device, such as a screen touchscreen, a table with input buttons and the like. The bus also combines this one or more processors in a display device 102 such as an LCD or a monitor via a graphics card. a table with data entry buttons and the like. The bus also combines this one or more processors in a display device 102 such as an LCD or a monitor via a graphics card. a table with data entry buttons and the like. The bus also combines this one or more processors in a display device 102 such as an LCD or a monitor via a graphics card.

[0019] The basic computer system 101 may connect to other computers or networks via a network adapter having the ability to connect 108 to the network 109. Examples of network adapters are communication channels, token rings, Ethernet or modems. Alternatively, the primary computer system 101 may connect using a wireless interface such as a cellular digital packet data (CDPD). The basic computer system 101 may be associated with some other computers in the local area network (LAN) or in a wide area network (WAN), or the primary computer system 101 may be a client in the client system / another computer's server and the like.

[0020] FIG. 2 shows a data processing network 200 in which the present invention may be embodied. The data processing network 200 may include a plurality of separate networks, such as a wireless network, and a wired network, each of which may include individual workstations 201, 202, 203, 204, and or the primary computer system 101 of FIG. 1C. In addition, as will be appreciated by those skilled in the art, it may comprise one or more LANs, where the LAN may consist of a plurality of intelligent workstations coupled to a master processor.

[0021] The program code 111 may be included in the memory 105, and it may be accessed through the processor 106 using a processor bus. Such a program code includes an operating system that controls the function and interaction of various computer components and one or more application programs 112. The program code is typically paged from the long term storage medium 107 to the fast memory 105, where it is available for processing by the processor 106. These techniques and methods for inserting software program code into memory, into a physical medium, and / or providing this software code via a network are well known and will not be further discussed herein. Program code when it is created and saved on a physical medium (including, but not limited to, electronic memory modules (RAM), flash memory, compact discs (CDs), DVDs, magnetic tape, and the like are often referred to as a "computer program product". The product carrier in the form of a computer program can usually be read by the processing system, preferably in a computer system, to be performed by the processing system.

The cache that is most available to the processor (usually faster and smaller than other processor caches) is the lowest (level L1 or first) cache, and the main storage space (main storage) is the top-level cache (L3, if there are 3 levels). The lowest-level cache memory is often split into an instruction cache (I-Cache) that stores the machine instructions to be executed, and a data cache (D-Cache) that stores data arguments.

[0023] Still referring to FIG. 2, these networks may also include mainframe computers or servers, such as a gateway computer 206 (client server), or application server 208 (remote server), which may access a data repository and to which one may obtain access directly from workstation 205. Gateway computer 206 serves as the entry point for each network 207. An input gateway is needed when combining one network protocol with another. The gateway computer 206 may preferably be connected to another network (e.g. to the internet 207) via communication link means. The gateway computer 206 may also be directly connected to one or more workstations 101, 201, 202, 203 and 204 using a communication link.

[0024] In an embodiment, access to the software program code that implements the present invention is accessed by the processor 106 of the primary computer system.

101 from a long-term storage medium, such as a long-term storage medium 107 in FIG. 1C. The software program code may be included on any of numerous known carriers for use by a data processing system, such as a floppy disk, hard disk, or CD-ROM. The code may be provided on such a medium, or may be provided to users 210 and 211 from a storage or storage space of a computer system via a network to other computer systems for use by users of such other systems.

[0025] Referring to FIG. 3, exemplary processor application is illustrated for processor 106. One or more cache levels 303 have been used to buffer memory blocks to increase processor performance 106. Cache 303 is a high-speed buffer storing memory data cache lines that most likely they will be used. Typically, the cache lines are 64, 128, or 256 bytes of memory data. In an embodiment, separate caches are used for caching instructions and for caching data. Consistency of the cache (synchronization of copies of lines in memory and caches) is often provided by various snoop-like viewing algorithms well known in the art. The main storage space, such as the processor system memory 105 is often referred to as a cache memory. In a processor system having 4 levels of cache 303, memory 105 is sometimes referred to as level 5 cache (L5) because it is usually faster, and stores only a portion of the nonvolatile storage space (DASD, tape, etc.) that is available to the system. computer. The memory 105 "buffers" the pages of data paged to and from the memory 105 by the operating system. which is available for the computer system. The memory 105 "buffers" the pages of data paged to and from the memory 105 by the operating system. which is available for the computer system. The memory 105 "buffers" the pages of data paged to and from the memory 105 by the operating system.

[0026] The program counter (instruction counter) 311 controls the address of the current instruction to be executed. The program counter in a z / Architecture processor is 64-bit and can be reduced to 31 or 24 bits to handle previous addressing restrictions. The program counter is usually implemented in the program status word (PSW) of the computer, so that it can survive the switching of the thread. Thus, a running program having a program counter value may be interrupted by, for example, an operating system (i.e., the current thread is switched from the program environment to the operating system environment). The PSW of this program preserves the value of the program counter when the program is not active, and while the operating system is being executed, the program counter (in the word PSW) of the operating system is used. In an exemplary embodiment of the present invention, the program counter is incremented by an amount equal to the number of bytes of the current instruction. Instructions in limited order processing (RISC) usually have a fixed length, while processing instructions with a complex number of instructions (CISC) are usually variable length. The z / Architecture Architecture instructions from IBM are CISC instructions that have a length of 2, 4, or 6 bytes. The program counter 311 is changed by, for example, either a thread switch operation or an operation including a branch instruction branch. In the thread switch operation, the current program counter value is stored in the PSW along with other status information regarding the program being executed (such as status codes), and a new program counter value is downloaded indicating the instruction of the new program module to be executed. The branch-taking operation is performed to allow the program to make a decision or to loop within the program by downloading the result of the branch instruction to the program counter 311.

[0027] In an exemplary embodiment of the present invention, instruction retrieval unit 305 is used to retrieve instructions on behalf of processor 106. An instruction downloading unit 305 either retrieves a "next succeeding instruction" of those target instructions for a branch instruction, or a first program instruction following a thread switch. . In an embodiment, instruction downloading unit 305 uses prefetch techniques based on the probability that these pre-extracted instructions can be used. For example, the instruction downloading unit 305 can download 16 bytes of instructions that contain the next subsequent instruction and additional bytes of further instructions.

[0028] These downloaded instructions are then executed by the processor 106. In an embodiment, the downloaded instruction (these downloaded instructions) is transmitted to the instruction decoding / spreading unit 306 belonging to the instruction pick-up unit 305. The instruction decoding / spreading unit 306 decodes this instruction (these instructions) and sends information about this decoded instruction (these decoded instructions) to the corresponding execution units 307, 308 and / or 310. The execution unit 307 receives information about the decoded arithmetic instructions from the downloading unit 305. instructions and will perform arithmetic operations on the arguments in accordance with the operating code (code of the case) of this instruction. Arguments are provided to the execution unit 307 or from the memory 105, designed registers 309, or from the direct field of this instruction. The results of this exercise, when saved, are stored either in the memory 105, the designed registers 309, or in other machine equipment (such as control registers, PSW registers and the like).

[0029] The processor 106 typically has one or more execution units 307, 308 and 310 for executing instruction functions. Referring to FIG. 4A, the execution unit 307 can connect to the designed registers 309, the decode / spreading unit 306, the read / write unit 310 and other processor units 401 via the logic circuit boards 407. The execution unit 307 can use several 403, 403 and 405 registers for storing information on which the ALU 402 will operate. ALU 402 performs arithmetic operations, such as addition, subtraction, multiplication and division, as well as logical operations such as OR and EXCLUSIVE-OR (XOR), as well as rotation and offset. In the exemplary embodiment of the present invention, The ALU 402 supports specialized operations that depend on the construction solution. Other circuits may provide other designed features 408 including, e.g., status codes and recovery support systems. Typically, the result of the ALU operation is stored in the output register system 406, which is able to convey this result to various other processing functions. In other exemplary embodiments of the present invention, there are a plurality of processor unit systems, while the present description is only intended to provide a representative understanding of one embodiment. Typically, the result of the ALU operation is stored in the output register system 406, which is able to convey this result to various other processing functions. In other exemplary embodiments of the present invention, there are a plurality of processor unit systems, while the present description is only intended to provide a representative understanding of one embodiment. Typically, the result of the ALU operation is stored in the output register system 406, which is able to convey this result to various other processing functions. In other exemplary embodiments of the present invention, there are a plurality of processor unit systems, while the present description is only intended to provide a representative understanding of one embodiment.

The ADD instruction will, for example, be executed in an execution unit 307 having arithmetic and logic functionality, while, for example, a floating point instruction will be executed in a floating point execution unit (not shown) having specialized floating point capabilities. Preferably, the execution unit operates on the arguments recognized by the instruction by executing the functions specified by the command code on these arguments. For example, the ADD instruction may be executed by the execution unit 307 on the operands found in the two designed registers 309 recognized by the register fields of the instruction.

[0031] The execution unit 307 performs an arithmetic addition on two operands and stores the result in a third argument, where the third operand can be a third register, or one of the two source registers. The execution unit 307 preferably uses an arithmetic logic (ALU) 402 that has the ability to perform various logic functions, such as offset, rotation, AND, OR and XOR, as well as many algebraic functions, including addition, subtraction, multiplication, division. . Some ALU 402 units are designed for scalar operations and some for floating-point operations. In the exemplary embodiments of the present invention, data can be in the form of Big Endian (where the least significant byte is at the highest byte address) or Little Endian (where the least significant byte is at the lowest byte address) depending on the architecture. The architecture of IBM-owska z / Architecture is

Big Endian. The fields with the sign can be a sign or size, stored in addition to 1 or in addition to 2, depending on the architecture. A number written in addition to 2 is advantageous in that the ALU does not have to realize the subtraction ability, since either a negative value or a positive value in addition to 2 only requires addition within the ALU. The numbers are usually described briefly, where, for example, a 12-bit field defines the address of a 4096 byte block and is usually described as a 4Kbyte (kilobyte) block. [0032] Referring to FIG. 4B, branch instruction information for executing branch instructions is typically sent to a branch unit 308 that uses a branch prediction algorithm such as branch history table 432 to predict the branching result, before other dependent operations are completed. The target order of the current branch instruction will be retrieved and speculatively executed before the dependent operations are completed. When dependent operations are completed, the speculatively executed branched instructions will either be completed or abandoned based on the states of the dependent operations and the speculated result. Ordinary branch instructions can check status codes and branching to a destination address, if the status codes meet branch branch instruction requirements, the destination address can be calculated, for example, based on a number of numbers, including those in the register fields or in the direct field of the instruction . In the example for the present invention, the branch unit 308 may use an ALU 426 having a plurality of 427 chips, 428 and 429 of the input registers and the 430 register of the output register. Branch unit 308 may communicate, for example, with general purpose registers, decode / spreading unit 306, and other layouts 425.

Executing a group of instructions may be interrupted for a variety of reasons, including, for example, a context switch initiated by, for example, an operating system, exception or program error causing context switching, I / O break signal causing context switching, or multithreaded multi-threading activity programs (in a multi-threaded environment). In the example for the present invention, the context switch operation maintains information about the status of the currently executing program, and then retrieves information about the status of another program that has been called. Status information can be recorded, for example, in hardware registers or in memory. The status information contains the value of the program counter indicating the next instruction to be executed, status codes, information on memory translation and content of designed registers. The operation of the context switch can be checked by hardware circuits, execution programs, operating system programs, or the firmware code (microcode, pico code, or internal licensed code (LIC)) separately or in combination.

[0034] The processor accesses the arguments according to the methods defined by the instruction. The instruction may provide a direct argument using the value of a part of the instruction, it may provide one or more register fields indicating explicitly either general purpose registers or special purpose registers (e.g. floating point registers). As arguments, the statement can use implicit registers specified by the command code field. The statement can use places in memory for arguments. The location of the argument in memory can be provided through the register, direct field, connection of registers and direct field as presented by the ability of far-displacement in the z / Architecture, in which the instruction specifies the basic register, an indicator register and a direct field (displacement field) that are added to each other to provide an argument address in memory. Here, the place is usually a place in the main memory (main storage space), unless indicated otherwise.

[0035] Referring to FIG. 4C, the processor accesses the storage space using the read / write unit 310. The read / write unit 310 may perform a read operation by obtaining the target address of the operand in memory via the cache / memory interface and retrieve the argument to the designed register 309 or other storage location, or perform a write operation by obtaining the target address of the operand in memory and write an argument obtained from the designed register 309 or other memory location at the destination of the argument in memory. The read / write unit 310 may be speculative, and may access memory in a sequence that is not a sequence in the order of instructions, however, the read / write unit 310 is intended to give the programs the impression that the instructions were executed sequentially. The read / write unit 310 may communicate with the designed registers 309, decoding / spreading unit 306, memory / cache / memory interface or other elements 455 and consists of different register arrangements, ALU 458, and logic control 463 for address calculation storage space and to provide a streamline order to keep operations in order. Some operations may be out of order, but the read / write unit provides functionality that causes out-of-order operations to be executed sequentially, as is well known in the art. The read / write unit 310 may communicate with the designed registers 309, decoding / spreading unit 306, memory / cache / memory interface or other elements 455 and consists of different register arrangements, ALU 458, and logic control 463 for address calculation storage space and to provide a streamline order to keep operations in order. Some operations may be out of order, but the read / write unit provides functionality that causes out-of-order operations to be executed sequentially, as is well known in the art. The read / write unit 310 may communicate with the designed registers 309, decoding / spreading unit 306, memory / cache / memory interface or other elements 455 and consists of different register arrangements, ALU 458, and logic control 463 for address calculation storage space and to provide a streamline order to keep operations in order. Some operations may be out of order, but the read / write unit provides functionality that causes out-of-order operations to be executed sequentially, as is well known in the art. the cache-memory / memory interface or other elements 455 and consists of different register arrangements, ALU 458, and logic control 463 to calculate the addresses of the storage space and to provide the stream sequence to keep the operations in order. Some operations may be out of order, but the read / write unit provides functionality that causes out-of-order operations to be executed sequentially, as is well known in the art. the cache-memory / memory interface or other elements 455 and consists of different register arrangements, ALU 458, and logic control 463 to calculate the addresses of the storage space and to provide the stream sequence to keep the operations in order. Some operations may be out of order, but the read / write unit provides functionality that causes out-of-order operations to be executed sequentially, as is well known in the art.

[0036] Preferably, the addresses that the execution program "sees" are often referred to as virtual addresses. Virtual addresses are sometimes referred to as "logical addresses" and "effective addresses". These virtual addresses are virtual because they are redirected to places in physical memory using one of various DAT technologies, such as DAT 312 in FIG. 3, including, but not limited to, placing the offset value in front of the virtual address, translating the virtual address via one or more translation tables, translation tables composed of at least the same segment table and table table or from their combination, preferably, an array segment having an entry pointing to the page table. In the z / Architecture, a translation hierarchy is provided covering the first array of the area, the second area table, the third area table, the segment table, and the optional page table. Address translation efficiency is often increased by the use of a translation lookaside buffer (TLB) that contains entries that map a virtual address to a corresponding location in physical memory. These entries are created when DAT 312 translates the virtual address using translation tables. The subsequent use of this virtual address may use this entry from the fast TLB buffer instead of the slow sequential access to the translation table. TLB content can be managed using various swapping algorithms, including LRU (Least Recently Used). Address translation efficiency is often increased by the use of a translation lookaside buffer (TLB) that contains entries that map a virtual address to a corresponding location in physical memory. These entries are created when DAT 312 translates the virtual address using translation tables. The subsequent use of this virtual address may use this entry from the fast TLB buffer instead of the slow sequential access to the translation table. TLB content can be managed using various swapping algorithms, including LRU (Least Recently Used). Address translation efficiency is often increased by the use of a translation lookaside buffer (TLB) that contains entries that map a virtual address to a corresponding location in physical memory. These entries are created when DAT 312 translates the virtual address using translation tables. The subsequent use of this virtual address may use this entry from the fast TLB buffer instead of the slow sequential access to the translation table. TLB content can be managed using various swapping algorithms, including LRU (Least Recently Used). These entries are created when DAT 312 translates the virtual address using translation tables. The subsequent use of this virtual address may use this entry from the fast TLB buffer instead of the slow sequential access to the translation table. TLB content can be managed using various swapping algorithms, including LRU (Least Recently Used). These entries are created when DAT 312 translates the virtual address using translation tables. The subsequent use of this virtual address may use this entry from the fast TLB buffer instead of the slow sequential access to the translation table. TLB content can be managed using various swapping algorithms, including LRU (Least Recently Used).

[0037] In the case where processor 106 is a multiprocessor system processor, each processor is responsible for maintaining common resources such as I / Os, caches, TLB buffers, and memory, in a mutually locked state for consistency. In an embodiment, "snoop" technologies will be used to maintain cache coherence. In a snoop view environment, each cache line can be marked as being in any state among shared, exclusive, changed or abnormal states, and the like, to facilitate sharing.

[0038] The I / O units 304 of FIG. 3 provide the processor 106 with means for connecting peripheral devices including, for example, a tape drive, disk, printers, displays, and networks. I / O units 304 are usually presented to the computer program via software drivers. On mainframe computers, such as the z / Series z / Series system, channel adapters and open system adapters are mainframe I / O units that provide connectivity between the operating system and peripherals.

[0039] The instrumentation data is data related to the operation of the processor 106. In an embodiment, access to instrumentation data and units of another system level may be restricted or not available. The computer processor operates in a privileged state (i.e. in the supervisor state), and in a less-privileged state (i.e. a problematic state). In a privileged state, the program can have access to all system resources through privileged operations (for example, access to all control registers and supervisor memory space). This privileged state is also referred to as the privileged mode or supervisor mode. An operating system running on a computer processor can operate in a privileged state. A less-privileged state is a non-privileged state, in which access to system resources is limited. For example, application programs operating in a less-privileged state may have limited or no access to control registers and may only access the user memory space allocated by the operating system to this application program. The less-privileged state is usually assigned to application programs under the control of the operating system, and in the unprivileged state no privileged operations can be performed. This underprivileged state is also known as a problematic state, problem mode, or user mode. to control registers and can only access the user memory space allocated by the operating system to this application program. The less-privileged state is usually assigned to application programs under the control of the operating system, and in the unprivileged state no privileged operations can be performed. This underprivileged state is also known as a problematic state, problem mode, or user mode. to control registers and can only access the user memory space allocated by the operating system to this application program. The less-privileged state is usually assigned to application programs under the control of the operating system, and in the unprivileged state no privileged operations can be performed. This underprivileged state is also known as a problematic state, problem mode, or user mode.

[0040] One such proprietary resource that is not available to write for a program running in a less-privileged state is the word (PSW) of the program state. The PSW may include a program counter for the next instruction to be executed, a status code field, which can be used by branch instructions, an instrumentation control field to indicate whether instrumentation is enabled or disabled, and other information used to control instruction queuing and condition determination a computer processor, including the privileged state assigned to the program. In a multithreaded computing environment, multiple programs share or receive time slices, available computing power of a computer processor. Each processor has thread information containing the related PSW, primary address of the address translation table for accessing the main storage space allocated to that program, a set of current values ​​of general-purpose registers, control registers, floating point registers, and the like. Actively active or controlling PSW is called the current PSW. It manages the program being executed. The computer processor has the ability to interrupt, which allows the computer processor to rapidly switch the thread to another program in response to the exception and external stimulus conditions. If an interrupt occurs, then the computer processor places the current PSW in the assigned space of the storage space, called the old-PSW location, for a specific interrupt class. The computer processor downloads a new PSW from the second allocated space of the storage space. This new content specifies the next program to be executed. In an embodiment, these locations in the storage space are located in the memory location available to the computer processor. If the computer processor has finished processing this interrupt, then the program handling this interrupt may reload the old content containing the old-PSW, causing it to be the current PSW again, in such a way that the interrupted program may resume operation.

[0041] The PSW fields can be referenced or explicitly (e.g., if the instructions read some of the PSW bits), or implicitly (e.g., when downloading instructions, retrieving arguments, address generation calculations, address generation sources, and the like) . An open reference is usually performed at runtime, whereas an implicit reference is usually performed at different stages of pipelining during the execution of the instruction (i.e., instruction retrieval, instruction decoding, execution time, and completion time). Individual fields in PSW can be referenced or updated independently of each other.

[0042] In an embodiment, by manipulating a thread, the operating system controls the computer processing resources, including the inclusion of the instrumentation-performance by the computer processor. Instrumentation-executive can be turned on or off during the operation of the operating system, as well as by any software applications launched by the operating system. The instrumentation on / off status is turned on as information about the thread in the PSW associated with the program.

[0043] The run-time-instrumentation (RI) property can be used on models that use the z / Architecture type architecture. If ownership

RI is installed and enabled, then the data is collected during program execution to one or more cache pools within the CPU, and then they are reported to the software buffer. Each stored unit of information is called a reporting group. The content of the reporting group consists of numerous entries, the content of which represents events recognized by the CPU during program execution.

[0044] If the ownership of the performance instrumentation is placed in the configuration, then the PSW field (bit RI) enables the performance instrumentation. The importance of executory instrumentation determines the ability to enable the RI bit, but if the RI is one, then the CPU actuations are important, and the performance instrumentation is enabled. The ownership of performance instrumentation may include the following instructions: download actuator controls, change actuator controls, send executive instrumentation, perform further performance instrumentation, disable performance instrumentation, enable performance instrumentation, record actuation of instrumentation, and check actuator controls.

[0045] The instruction on how to load the run-time instrumentation controls (LRIC) initiates the control of the performance instrumentation that manages the performance instrumentation. The change run-time-instrumentation controls (MRIC) instruction alters all or a subset of the actuator controls that were originally established by LRIC. The instruction, run-time-instrumentation emmission (RIEMIT), collects the value of the general-purpose register by storing it in a bulk buffer. The next run-time-instrumentation next (RINEXT) instruction performs direct sampling of the next, in order, instruction (NSI) after RINEXT. The manual disable performance instrumentation. run-time-instrumentation off) (RIOFF) turns off the performance instrumentation. The instruction enable run-time-instrumentation on (RION) turns on the performance instrumentation. The instruction runtime-instrumentation controls (STRIC) instruction inserts the current values ​​of actuator controls into a specific place in the storage space. The instruction check the test run-time-instrumentation controls (TRIC) checks those controls If they are valid, then the drive indicator is changed.

[0046] The ownership of the performance instrumentation includes the ability to cause an external warning-measurement to be processed. Some of this information collected by the performance instrumentation and reported to the program's buffer depends on the model and therefore is not specified. The data samples provided by the performance instrumentation functionality are aimed at statistical estimation of performance characteristics, are relatively accurate, and can not be reproducible. For example, regardless of the sampling mode, it is not possible to predict whether a given sample statement that caused an exception or is associated with specific internal actions of the system will cause the reporting group to be saved and, if they are saved,

[0047] A cache pool is used to intercept a set of entries whose contents report events recognized by the processor during program execution. Examples are: execution of one or more executed branches, transaction abandonment events, and argument of the RIEMIT statement. Execution of the RIEMIT instruction collects the value of the general-purpose register by writing it to the collective buffer. Additional data can be collected and / or saved in other buffers, such as instruction data buffer.

[0048] Reporting is subject to reporting controls. If the sample instruction is recognized, then each reporting control turns on the checking of the corresponding status. If there is a corresponding state, then the reporting group is created and saved. Reporting group is not saved if no reporting control is enabled or there is no corresponding status for enabled reporting control. Reported data about the sample instruction are retrieved from the data-instruction buffer and other sources dependent on the model, and are then used to create these contents of one or more entries of the reporting group, where each one of such entries is a statement entry.

[0049] Types of entries that can be captured in the reporting group include: fill, excess, start, timestamp, instruction, send, drop TX, call, return, and move. The filler entry is used in the reporting group if the number of valid entries in the cache buffer is insufficient to fill the reporting group with the current size of the reporting group. The excess entry can be used in the additional section of the reporting group. The begin entry is the first entry of the first reporting group. The timestamp entry is saved as the 0 entry for each reporting group other than the first reporting group. The instruction entry is created, if the reporting group is saved for the given statement as the last entry of the reporting group. The send entry is created by successfully executing RIEMIT. The entry to abandon the transaction-execution mode (TX) is created by either implicit abandonment or by executing a transaction dropout statement. A call entry is created by executing a branch statement that is classified as a branch call type statement. The return entry is created by executing the return statement, which is classified as a return statement. The transfer entry is created by executing a branch statement that meets specific state code criteria. The entry to abandon the transaction-execution mode (TX) is created by either implicit abandonment or by executing a transaction dropout statement. A call entry is created by executing a branch statement that is classified as a branch call type statement. The return entry is created by executing the return statement, which is classified as a return statement. The transfer entry is created by executing a branch statement that meets specific state code criteria. The entry to abandon the transaction-execution mode (TX) is created by either implicit abandonment or by executing a transaction dropout statement. A call entry is created by executing a branch statement that is classified as a branch call type statement. The return entry is created by executing the return statement, which is classified as a return statement. The transfer entry is created by executing a branch statement that meets specific state code criteria. which is classified as a branch call type statement. The return entry is created by executing the return statement, which is classified as a return statement. The transfer entry is created by executing a branch statement that meets specific state code criteria. which is classified as a branch call type statement. The return entry is created by executing the return statement, which is classified as a return statement. The transfer entry is created by executing a branch statement that meets specific state code criteria.

[0050] FIG. 5 is a pictorial schematic of a system for processor execution instrumentation that can be used in an embodiment. In an embodiment, the system 500 includes a main processing unit (CPU) such as the processor 106 of FIG. 1. In an embodiment, the processor 106 is a single processor. Alternatively, the processor 106 is a single processing core of a multi-core processor. In an embodiment, the processor 106 is capable of operating at varying rates.

[0051] In an exemplary embodiment of the present invention, the processor 106 further comprises a register 510. The register 510 is a hardware register having the capacity to store data words for use by the processor 106. The register 510 includes one or more latches for storing data bits that are available for processor 106. For example, register 510 may include general-purpose registers and control registers. Processor 106 further includes an instrumentation module 506 that communicates with register 510. Instrumentation module 506 is configured to collect instrumentation data, such as a one or more branching execution path, transaction execution abandon events, various execution arguments, timestamp information, and the like, directly from the processor 106.

[0052] The processor 106 executes one or more operating systems 516, and one or more applications 518. This one or more operating systems 516 and one or more applications 518 are stored in the storage space 520, such as a hard disk, CD-ROM, flash memory, and the like, and are loaded into main memory 514 in an executable memory area 504 reserved for storing one or more active portions of an operating system and / or application currently being run, called pages that are they are retrieved from storage space 520 to execution memory 504 as needed. In the exemplary embodiment of the present invention, each of the operating systems operates as a virtual machine managed by a supervisor.a hypervisor) (which is not shown) and is executed by the processor 106.

In an exemplary embodiment of the present invention, the processor 106 loads the PSW into the register 510 from the PSW 512 data in main memory 514 for the currently operating system or application from the main memory 514 and sets the settings of one or more processors in, e.g. 510. In an exemplary embodiment of the present invention, the PSW in register 510 includes one or more bits for activating and controlling instrumentation module 506.

[0054] This one or more applications 518 include software applications compiled to perform on a particular operating system, an interpreter code running on the interpreter (e.g. Java^TM), or threads supporting the operating system (for example, process management, "daemon" processes, and the like). Each of these operating systems 516 and or one or more applications 518 may execute instructions to trigger or stop the collection of instrumentation data by the instrumentation module 506.

In an exemplary embodiment of the present invention, one or more applications 518 execute an instruction that has been specified as a sample instruction, thereby creating a test point on completion of this sample instruction, and this then causes the instrumentation module 506 to carry the collected data. this application from the cache 508 to the program buffer 522 in main memory 514, which is available for this application. The main memory 514 may be any addressable memory known in the art. In an embodiment, the main memory 514 may include a fast-access buffer storage space, sometimes called a cache memory. Each CPU may have a cache associated with it. In an additional example embodiment of the present invention, main memory 514 is a dynamic random access memory (DRAM). In yet another exemplary form of the invention, the main memory is a storage device, such as a computer hard disk, or flash memory available for application.

[0056] The executive instrumentation function is a new functionality that can be used not only in a laboratory environment, or for separate analysis, but also in real software environments, within processing programs, and under program supervision. The privileged state may set the processor's controls 106 to manage the performance instrumentation. The flexibility of the performance instrumentation functionality is enhanced by providing the capability to vary, from the less-favored state, most of the controls. A less-favored state will most likely benefit from performance instrumentation. The less-favored status is protected by changing specific settings to ensure that that (1) the privileged state maintains the integrity and control over all programs with a less-privileged status, which it activates, and (2) the less-privileged status may or may not carry out performance instrumentation, if the operating system itself performs instrumentation. Both can perform performance instrumentation if the supervisor temporarily turns off the performance instrumentation, writes down his executive instrumentation thread, plays the thread of the performance instrumentation of the less-favored program, and then launches the program in the less-privileged state with the executive instrumentation switched on again. If the change of the thread does not include the appropriate recording / reproduction of the performance instrumentation controls,

[0057] In an embodiment, in order to better handle a program with a less-privileged state, the instruction is defined to change the execution instruction (MRIC). The MRIC instruction is a semi-privileged instruction that is used to vary the particular CPU controls 106 regarding the performance instrumentation, those controls that are currently active in the register 510. These controls are initially loaded by successfully executing the instructions, download the instruction control (LRIC) by privileged status.

[0058] The ability of the MRIC instruction to interact with the actuator controls is described in detail below. If the execution of the MRIC statement is successful, then all the controls that are specified by the MRIC instruction are set when the MRIC instruction is successfully executed, otherwise, if the execution of the MRIC statement is unsuccessful, then none of the controls are changed.

[0059] FIG. 6 shows an MRIC instruction in an embodiment. In an embodiment, the MRIC 600 instruction includes operating code 602 and 604 (also referred to as "command code" or "split instruction code" in this particular case). Command code 602 and 604 indicates to a processor, such as processor 106 in FIG. 5, the MRIC 600 instruction. The MRIC 600 instruction also contains the address of the argument, which is determined from field 606 (B2) of the basic register, by the set of displacement fields 608 and 610 taken together. The sum of the contents of the basic register plus the displacement indicates the location of the executive instrumentation control block (RICCB), which contains the instrumentation control settings that will be updated by this MRIC instruction. Movement boxes 608 and 610 indicate the displacement from the address contained in the base register indicated by field 606 of the base register, the sum of which matches RICCB. FIG. 6 shows an embodiment of the MRIC instruction for explanation purposes. It will be understood by those skilled in the art that the MRIC instruction in other embodiments may be formatted differently and / or may contain other arguments and command codes.

[0060] The MRIC 600 instruction is used to update only a subset of the controls that can be updated by the LRIC instruction. These controls set by the MRIC 600 instruction are limited to a subset of the controls that have been successfully set by the LRIC instruction. The performances of the performance instrumentation contain a series of bits that control the operation of the MRIC instruction, including the ability to update various actuator controls. In an embodiment, these bits are arranged in a subset of all actuator controls, which can only be set by the LRIC instruction.

[0061] FIG. 7 is a flowchart of initiating an MRIC instruction from a less-privileged state program in an embodiment. In block 702, the MRIC instruction is taken by the processor. In block 704, the MRIC instruction is executed by this processor. In block 706, control execution instrumentation values ​​in the RICCB are loaded for actuator controls. At block 708, actuator control inputs provide information to the program buffer 522 of FIG. 5 based on the loaded settings.

[0062] FIG. 8 is a flowchart for initiating an MRIC instruction from a less-privileged program in an additional embodiment. In an embodiment, the flow chart of FIG. 8 is performed by the instrumentation module 506 of FIG. 5. In block 802, the MRIC instruction is issued by the program with the less-privileged status. The MRIC instruction contains a command code and an argument. The argument of the MRIC instruction is RICCB, which contains the control values ​​of the performance instrumentation that will be used to update the control of the performance instrumentation. These values ​​include, for example, a control value for managing the details of the sample collection of the performance instrumentation; the value of control to manage the details of instrumentation data collection, the value of control to manage the details of executive instrumentation data reporting to the program buffer; current address within the software buffer location, and the like.

[0063] In block 804, it is determined whether the execution of the MRIC is allowed. The execution instrumentation bit S (controlled only by LRIC) determines whether it is allowed that the less-privileged program executes the MRIC instruction. If the execution instrumentation bit S is set to 1, then the processing goes to block 806.

[0064] In block 806, it is determined whether the validity bit (also referred to as bit V) of the current actuator controls is set to 1. The validity bit indicates the validity of the set of actuator controls in the processor, as previously set by the LRIC instruction. If current execution instrumentation controls are not valid (that is, the previous LRIC instruction was invalid), then in block 818, the MRIC statement can not be executed successfully. In an exemplary embodiment of the present invention, the failed execution of the MRIC instruction does not change the previous settings and the actuation controls remain at their previous values. The validity bit can not be updated by the MRIC statement. In block 808, the RICCB is downloaded, which is indicated by the MRIC instruction.

[0065] If the validity bit is set to 1 (i.e., the actuator controls are valid), then the processing goes to block 810. In block 810, if the bit K is zero (i.e., the less-privileged program does not operate in the semi-privileged state with reference to executory instrumentation controls), then, in block 814, neither the primary address nor the limiting address is updated, but all other controls updated by MRIC are updated. If the K bit is one (ie the program with the less-privileged status operates in the semi-privileged state with respect to the performance instrumentation), then in block 812 all the controls that are updated by the MRIC are updated,

[0066] FIG. 9 illustrates a portion of an actuation control actuation control block (RICCB) comprising actuations that can be set by the preferential state in an embodiment. The control block portion 900 may include additional values ​​other than those described with reference to FIG. 9. The change of part 900 of the control block can be performed by the LRIC instruction.

[0067] The portion of the control block includes valid bit 902 (bit V). The validity bit 902 indicates the validity of the set of executory instrumentation controls in the processor, as they were set by the LRIC instruction.

[0068] The control block also includes bit S 904, which is used to determine whether the less-privileged program is allowed to execute the MRIC instruction. Bit K 906 indicates whether the less-privileged program is allowed to perform in semi-privileged mode with respect to executory instrumentation controls, such as the primary address, and the address limiting actuation of the performance instrumentation. The H 908 bit determines whether the address controls (i.e. the primary address, the restricting address, and the current address) refer to the primary virtual address space or the home virtual address space. Bit o 910 is ignored, and treated as 0.

[0069] The control bit of a less-privileged status sample (bit Ps) is used in conjunction with programs with a less-privileged state. Being in a less-favored state and using Ps 912 in execution instrumentation controls of zero, the control of the reporting of the performance instrumentation is ignored if the performance instrumentation is turned on, and thus does not cause the reporting group to be recorded. Being in a less-favored state and when Ps 912 is busted in the control of the performance instrumentation of one, the reporting controls are checked and used in accordance with the function specified for them.

[0070] The control supervisory-state sample control bit 914 (Qs bit) is used in conjunction with supervisory-state programs. Being in the supervisory and beating Qs 914 in executory instrumentation controls of zero, the control inputs of the performance instrumentation are ignored if the performance instrumentation is turned on and thus do not cause the reporting group to be recorded. Being in the supervisory state and with the beating of Qs 914 in the control of the performance instrumentation of one, the reporting controls are checked and used in accordance with the function specified for them.

[0071] The control bit of the less-privileged status cache 916 (bit Pc) controls the updates of the cache buffer 508 of FIG. 5. Being in a less-favored state and using Pc 916 in execution instrumentation controls, zero control of the cumulative buffer of the performance instrumentation is ignored if the runtime instrumentation is turned on, preventing the cumulative buffer 508 from being updated. Being in a less-favored and beat mode Pc 916 in actuation instrumentation controls of one, the collective buffer actuators are checked and used in accordance with the function specified for them.

[0072] The control-91 control buffer bit 918 (bit Qc) controls the bulk buffer updates 508. Being in the supervisory status and with the Qc918 bit in execution instrumentation controls of zero, the control of the collective control instrumentation of the actuator controls is ignored if the performance instrumentation is enabled, which prevents the bulk buffer 508 from being updated. Being in the supervisory and QCA918 status in the actuator instrumentation of one, the indicated cumulative buffer actuators are checked and used according to the function specified for them. [0073] Bit G 920 is the control of an ongoing interruption held by the performance instrumentation, also referred to as a stopped interrupt. If the G 920 bit is zero, the paused interrupt is not terminated. If the G920 bit is one, then the paused interrupt continues. If the first reporting group in the program buffer 522 is written, the bit G 920 is set to zero. This means that if the original address of the program buffer is equal to the address limiting the program buffer, the bit G 920 is set to zero. If an attempt is made to write other than the first reporting group to the program buffer 522, the G 920 bit is set to zero if no execution instrumentation stop state is present, and the reporting group is recorded. If an attempt is made to write other than the first reporting group to the program buffer 522, the bit G 920 is set to one if the execution instrumentation stop state is present, and the reporting group is not recorded. then the interrupted interrupt continues. If the first reporting group in the program buffer 522 is written, the bit G 920 is set to zero. This means that if the original address of the program buffer is equal to the address limiting the program buffer, the bit G 920 is set to zero. If an attempt is made to write other than the first reporting group to the program buffer 522, the G 920 bit is set to zero if no execution instrumentation stop state is present, and the reporting group is recorded. If an attempt is made to write other than the first reporting group to the program buffer 522, the bit G 920 is set to one if the execution instrumentation stop state is present, and the reporting group is not recorded. then the interrupted interrupt continues. If the first reporting group in the program buffer 522 is written, the bit G 920 is set to zero. This means that if the original address of the program buffer is equal to the address limiting the program buffer, the bit G 920 is set to zero. If an attempt is made to write other than the first reporting group to the program buffer 522, the G 920 bit is set to zero if no execution instrumentation stop state is present, and the reporting group is recorded. If an attempt is made to write other than the first reporting group to the program buffer 522, the bit G 920 is set to one if the execution instrumentation stop state is present, and the reporting group is not recorded. If the first reporting group in the program buffer 522 is written, the bit G 920 is set to zero. This means that if the original address of the program buffer is equal to the address limiting the program buffer, the bit G 920 is set to zero. If an attempt is made to write other than the first reporting group to the program buffer 522, the G 920 bit is set to zero if no execution instrumentation stop state is present, and the reporting group is recorded. If an attempt is made to write other than the first reporting group to the program buffer 522, the bit G 920 is set to one if the execution instrumentation stop state is present, and the reporting group is not recorded. If the first reporting group in the program buffer 522 is written, the bit G 920 is set to zero. This means that if the original address of the program buffer is equal to the address limiting the program buffer, the bit G 920 is set to zero. If an attempt is made to write other than the first reporting group to the program buffer 522, the G 920 bit is set to zero if no execution instrumentation stop state is present, and the reporting group is recorded. If an attempt is made to write other than the first reporting group to the program buffer 522, the bit G 920 is set to one if the execution instrumentation stop state is present, and the reporting group is not recorded. then the G 920 bit is set to zero. This means that if the original address of the program buffer is equal to the address limiting the program buffer, the bit G 920 is set to zero. If an attempt is made to write other than the first reporting group to the program buffer 522, the G 920 bit is set to zero if no execution instrumentation stop state is present, and the reporting group is recorded. If an attempt is made to write other than the first reporting group to the program buffer 522, the bit G 920 is set to one if the execution instrumentation stop state is present, and the reporting group is not recorded. then the G 920 bit is set to zero. This means that if the original address of the program buffer is equal to the address limiting the program buffer, the bit G 920 is set to zero. If an attempt is made to write other than the first reporting group to the program buffer 522, the G 920 bit is set to zero if no execution instrumentation stop state is present, and the reporting group is recorded. If an attempt is made to write other than the first reporting group to the program buffer 522, the bit G 920 is set to one if the execution instrumentation stop state is present, and the reporting group is not recorded. this bit G 920 is set to zero. If an attempt is made to write other than the first reporting group to the program buffer 522, the G 920 bit is set to zero if no execution instrumentation stop state is present, and the reporting group is recorded. If an attempt is made to write other than the first reporting group to the program buffer 522, the bit G 920 is set to one if the execution instrumentation stop state is present, and the reporting group is not recorded. this bit G 920 is set to zero. If an attempt is made to write other than the first reporting group to the program buffer 522, the G 920 bit is set to zero if no execution instrumentation stop state is present, and the reporting group is recorded. If an attempt is made to write other than the first reporting group to the program buffer 522, the bit G 920 is set to one if the execution instrumentation stop state is present, and the reporting group is not recorded.

[0074] Bit U 922 is activation control for interrupting buffer overflow and hold interruption. If the bit U 922 is zero, then the generation of the interrupt request is turned off, and if it remains, it remains in the waiting state.

[0075] Bit L 924 is a control of the duration of the buffer overflow interrupt. If the L 924 bit is zero, then the buffer overflow interruption is not in the waiting state. If the L 924 bit is one, then the buffer overflow interruption is not completed.

[0076] The key field 926 is a 4-bit unsigned integer whose value is used as a security-space-storage key for storing the reporting group. Storage of the reporting group is only allowed when the storage space key matches the access key associated with the request to access the storage space, and downloading is allowed if this storage space key matches the access key or when the storage space key security-retrieving bit is zero. These keys match if the four bits of the storage key access control are equal to the access key, or when the access key is zero.

[0077] FIG. 10 shows a portion of the RICCB control block when the MRIC is allowed to perform in half-privileged mode (i.e., the K bit is one). The control block 1000 may include additional values ​​other than those described with reference to FIG. 10. In an embodiment, any grayed-out MRIC instruction section is not available to a less-privileged program. If the semi-privileged mode is allowed, then the primary address (ROA) 1002 and the limit address 1004 are set by the program in the less-privileged state by the MRIC instruction.

[0078] In an embodiment, the field (RCA) 1006 of the current address may be updated by the MRIC instruction. Field 1006 of the current address checks the reporting group size field 1044 (RGS field) and affects the number of positions of the significant bits so as to create the address of the program buffer. The 64-bit current address of the execution instrumentation buffer is word 0, bit positions 0 through 26 - RGS word 1, and RGS + 5 binary zeros added on the right. This is the starting position in the program buffer 522 of FIG. 5 the next reporting group that will be stored in the program buffer 522. The reporting group is the information unit that is formed by the instrumentation module 506, and subsequently stored in the program buffer 522. In an exemplary embodiment of the present invention,

[0079] The remaining sample interval count field (RSIC field) can be updated by the less-privileged program using the MRIC instruction. The RSIC 1042 field contains an unsigned 64-bit integer that indicates the timer interval of the remaining sample. If the value of the RSIC 1042 field in the actuator controls is zero, or is equal to the value of field 1040 of the scaling factor (SF field), and the performance instrumentation is enabled, then the time interval of the next sample is the full time interval based on the values sampling field 1008 (field M) and field SF 1040. If the RSIC field 1042 is non-zero and smaller than the field SF 1040, and the implementation instrumentation is enabled, then the time interval of the next sample is a partial time interval. If the RSIC 1042 field is non-zero and larger than the SF 1040 field value and the performance instrumentation is enabled, then the time interval of the next sample is the extended time interval. If the extended time interval expires, then the next time interval is based on the value of field SF 1040. If the RSIC field 1042 is set to a non-zero value, it is subject to the same model dependent maximum limitation, which also applies to field SF 1040. If the original value field RSIC 1042 is zero, then the sampling mode dictates whether the RSIC 1042 field is set to the value in the field SF 1040 while executing the LRIC and MRIC instructions, or whether it still represents zero until the runtime instrumentation is turned on.

[0080] The SF field 1040 includes an unsigned 64-bit integer whose value is the result of the unit scaling factor count. The size of these units is determined from sampling field 1008 (field M). If the value of the RSIC field is zero, then the field SF 1040 provides the initial value of the RSIC field 1042, which is reduced to zero, at which point the current statement is recognized as a sample instruction and the internal count is refreshed from the value of field SF 1040. Correct field value SF 1040 is in the range of one to two⁶⁴ - 1. If zero is specified, then one is assumed. However, each model may have both a minimum and a maximum value of the field SF 1040. These minimum and maximum values ​​may also be different based on the sampling field 1008. If a value smaller than the minimum is specified, then the minimum value depends on the model. If a value greater than the maximum value is specified, then the maximum value depends on the model.

[0081] DC control field 1036 is a 4-bit unsigned integer whose value indicates a cache delay level associated with a miss cache when retrieving or writing data. This means that the sample instruction encountered a miss in accessing the cache data. If this is not prohibited by other control of the execution instrument, then an attempt is made to write a reporting group representing a sample instruction whose access to the data recognized a miss at a cache delay level numerically greater than or equal to the level determined by the DC control field 1036. The cache structure and the cache delay level for accessing the data depend on the model. For instructions with many or with long arguments, the model depends on which, if any, access to the argument is used to control reporting. The behavior dependent on the model may ignore the DC control field value 1036, and therefore not use it, which is the reason for writing the reporting group.

[0082] IC field 1034 is an unsigned 4-bit integer whose value indicates a cache delay level associated with a miss cache miss when retrieving or writing data. This means that the download of the sample instruction has failed to access the cache data. For both the IC 1034 field and the DC control field 1036, the cache delay level is an abstraction of how far access to a specific cache is from the processor's point of view. The delay level depends on the combination of the number of nested cache levels between the processor and the main storage space, and how these levels of cache are shared among multiple processors. A higher level of delay generally translates into access requiring the use of more time. The values ​​in field IC 1034 and in field 1036 of the DC control can be considered as the zero identification of the cache delay level. For example, the zero value corresponds to the L1 cache (i.e. the cache memory that is closest to the processor). The value of one is therefore the cache of the next level, which can be known as the L2 cache, or, on some machines, as the L1,5 cache. Values ​​2-15 indicate the logical progress of additional cache delay levels until main memory is reached, but not including main memory itself. In general, cache structures do not go as deep as fifteen levels. For this reason, a value of 15 in field IC 1034 and in field 1036 of DC control is interpreted as a special case, meaning that miss caching when downloading instructions or accessing data, and regardless of the level of cache delay, is not recognized for the purpose of generating write report group. Unless it is prohibited by other executive instrumentation control, an attempt is made to write a reporting group representing a sample instruction, the download of which identified a failure at the level of cache latency numerically higher than or equal to the level indicated by IC field value 1034. Cache structure and level cache delay for instruction retrieval depends on the model.

[0083] The cache-latency-level-override reporting bypass bit 1032 (bit F) exists for non-branching instructions and for branching prediction controls. If the F 1032 bit in the execution instrumentation controls is zero, then the control of the cache reporting (field IC 1034 and field 1036 of the DC control) of the actuation instrumentation are checked and used in accordance with the function specified for them. Branch prediction actuations (bits BPxn 1022, BPxt 1024, BPti 1026, and BPni 1028) belonging to the actuator controls are checked and used in accordance with the function specified for them. If bit F 1032 is one, then the same controls are ignored,

[0084] The data-cache miss control bit 1030 (bit D) indicates whether or not to write the reporting group. If bit D 1030 is one, then an additional type entry may or may not be placed in the additional section of the reporting group that contains the model-specific data for the sample instruction.

[0085] The MRIC instruction contains controls (BPxn 1022, BPxt 1024, Bpti 1026, and BPni 1028) branch prediction reporting (BP). If the BP reporting control bit in the actuator controls is zero, then the corresponding state is not checked. If the BP reporting control bit is one and there is a corresponding branch prediction state, the reporting group is recorded.

[0086] Bit BPxn 1022, when it is one, enables checking branch prediction information. Thus, if the sample branch to be performed is the result of an incorrect prediction but has not been executed, the reporting group is saved.

[0087] The BPxt 1024 bit, when it is one, enables checking branch prediction information. Thus, if the sample branch that was not supposed to be executed is the result of an incorrect prediction and has been executed, then the reporting group is saved.

[0088] Bit BPti 1026, when it is one, turns on the branch prediction information. Thus, if the sample branch to be performed is the result of the correct prediction, and was performed, but the branching goal is the result of incorrect prediction, then the reporting group is saved.

[0089] Bit BPni 1028, when it is one, turns on the branch prediction information. Thus, if the sample branch that was not supposed to be executed is the result of correct prediction, and it was not executed, and the branching goal is the result of incorrect prediction, then the reporting group is saved.

[0090] Control of the inclusion of bit 10 of transaction execution mode (bit X) entries controls the collection of entries for abandoning the transaction execution mode. If the X1020 bit in the execution instrumentation controls is zero, then the transaction execution abandonment entries are not collected. If the X1020 bit in the actuator controls is one, then the transaction execution abandon entries are collected and placed in the collective buffer 508 of FIG. 5. If the model does not have the transaction execution functionality installed, bit X1020 is ignored.

[0091] The RIEMIT instruction bit bit 1018 (bit E) controls the execution of the RIEMIT instruction. If the bit E 1018 in the control of the performance instrumentation is zero or is ignored and treated as zero, when the performance instrumentation is enabled, then RIEMIT performs the empty operation. If bit E 1018 is one and is therefore not ignored, then RIEMIT is enabled to perform the function specified for it.

[0092] Bit J 1046, if zero, specifies that the branch on conditional statement (BC) is in a category of branches of a different kind, regardless of the value of the mask. If the bit J 1046 is one, then the BC instruction that specifies the mask of 15 is a category of a kind of return branch (retern-type). If the BC instruction specifies a mask of 1-14, bit J 1046 does not affect it, and it is always in the category of other types of branches. If jin the category of return branches, then the bit R 1016 controls the attachment to the buffer 508 of FIG. 5. If it is in the category of other types of branches, then bit B 1048 controls the inclusion of 508 into the cumulative buffer. A category of other types of branching can also be indicated as a category of transfer-type branches.

[0093] The code bit 1014 of the instruction address (bit C) controls the inclusion of branching in the type of call. If the C 1014 bit in the actuator controls is one, and the instruction is a branch of the call type, the cache pool is updated. If a combination of a branch-type branching type and a return type is detected, then the C 1014 bit works on both, and the R 1016 bit has no effect.

[0094] Bit R 1016 is a control for the inclusion of return type branches. If the bit R 1016 in these actuator controls is one and the instruction is a return branch, then the cumulative buffer 508 is updated.

[0095] Bit B 1048 is control of the inclusion of branches other than branches of the type of call and return type. If the bit B 1048 in these actuator controls is one, and the instruction is a branch of another type recognized by the performance instrumentation, then the cumulative buffer 508 is updated.

[0096] The maximum-address exceeded bit 1012 (MAE bit), if set to 1, means that one or more reporting groups having an instruction address code (field C) set at number one. When the MAE 1012 bit is set to one, further execution of the performance instrumentation does not set it back to zero. Executing LRIC instructions or MRIC statements that specify the MAE bit as zero sets the MAE bit to zero.

[0097] The run-timeinstrumentation next (RINEXT) bit 1010 (bit N) controls the inclusion of the next execution instrumentation instruction that controls the execution of the sample instruction. If the N 1010 bit in these actuator controls is zero, or is ignored and treated as zero, then RINEXT performs an empty operation. If the N 1010 bit is one and is therefore not ignored, RINEXT is enabled to perform the function specified for it.

[0098] Sample mode field 1008 (field M) is a 4-bit unsigned integer whose value in the actuation instrumentation controls is determined by the sampling mode for those actuator controls.

[0099] The reporting group size (RGS) field 1044 is an unsigned 3-digit number, the value of which is the number of entries of the reporting group (RGS). The number of entries in the reporting group can vary from two entries containing the start / timestamp entry and the entry of the last instruction, up to two hundred and fifty-six entries. In an embodiment, the upper limit may depend on the model. The number of 16-byte entries placed in the reporting group is 2^{(RGS + 1)}.

[0100] The basic-CPU limitation control bit 1038 (bit Y) and the minor CPU-control limiting control bit 1039 (bit Z) are collectively referred to as limiting control. Limiting the logging of the reporting group means that no attempt is made to write. Limitation control does not work and there is no limitation if the capabilities of a given CPU among all CPUs in a given configuration are the same. In configuration, if the capabilities of the CPU are different from the capabilities of another CPU, the limiting control works, and at least one CPU has commanded operation with the capabilities of the primary CPU, while at least one other CPU has commanded operation with the capabilities of the secondary CPU. Primary and secondary CPU capabilities vary in speed. If both the Y 1038 and the Z 1039 bits are zeros, the restriction does not occur. If the bit Y 1038 is zero and the bit Z 1039 is one, then the limitation occurs if the CPU, e.g. processor 106, operates with the capabilities of the secondary-CPU. If the bit Y 1038 is one and the bit Z 1039 is zero, limitation occurs if the CPU, e.g. processor 106, operates with the capabilities of the primary-CPU. If both the bit Y 1038 and the bit Z 1039 are one, then there is a restriction. works with the basic-CPU capabilities. If both the bit Y 1038 and the bit Z 1039 are one, then there is a restriction. works with the basic-CPU capabilities. If both the bit Y 1038 and the bit Z 1039 are one, then there is a restriction.

[0101] The above fields and bits of FIG. 10 are examples of the placement and naming of these fields and are here only for the purpose of explanation. It will be understood that in other embodiments only a subset of these fields may be used, the fields may be in any order or position and / or may be described by other names.

[0102] As described before, if the performance instrumentation is enabled during program execution, the runtime data 508 is stored in the processor 106 in processor 508. In an exemplary embodiment of the present invention, the collection buffer 508 is an internal processor buffer 106 that is used for saving the latest accumulated entries. If a sample trigger point is detected, then these entries are copied from the bulk buffer 508 to the program buffer 522 as part of the reporting group which is written to the program buffer 522. In an exemplary embodiment of the present invention, these entries are copied from the bulk buffer 508 in a manner non-destructive.

[0103] The cache 508 may be referred to as a "hardware cache pool" because the cache buffer 508 is located in the processor and in the implemented embodiment as a matrix of register pairs for storing the instruction address and event metadata for the given event. An example of an event is a downloaded branch for which a pair of registers can store the address of the branch instruction, and the metadata can contain the purpose of the branching, as well as information about the previous behavior of such branching. In an embodiment, these register pairs are arranged and updated successively as the events in the instruction stream occur. The counter is kept to indicate the indicator of a freshly updated entry in this matrix. In an exemplary embodiment of the present invention, the cache 508 is a looped buffer, and when the cache 508 is full, the next event overwrites the first entry in the matrix, and the subsequent update of the register pairs of the matrix again starts on subsequent events. For this reason, assuming that the CB [0] matrix to CB [N-1], and the counter and indicating the most recent updated indicator, the trace of captured events will be represented by the sequence CB [i], CB [i-1] ... CB [1], CB [0], CB [N-1], CB [N-2] ... CB [i + 1]. In another embodiment, two indicators are used: a header indicator indicating the oldest entry in the buffer, and a final / current indicator indicating the latest entry in the buffer. and subsequent updating of the register pairs of this matrix again starts on subsequent events. For this reason, assuming that the CB [0] matrix to CB [N-1], and the counter and indicating the most recent updated indicator, the trace of captured events will be represented by the sequence CB [i], CB [i-1] ... CB [1], CB [0], CB [N-1], CB [N-2] ... CB [i + 1]. In another embodiment, two indicators are used: a header indicator indicating the oldest entry in the buffer, and a final / current indicator indicating the latest entry in the buffer. and subsequent updating of the register pairs of this matrix again starts on subsequent events. For this reason, assuming that the CB [0] matrix to CB [N-1], and the counter and indicating the most recent updated indicator, the trace of captured events will be represented by the sequence CB [i], CB [i-1] ... CB [1], CB [0], CB [N-1], CB [N-2] ... CB [i + 1]. In another embodiment, two indicators are used: a header indicator indicating the oldest entry in the buffer, and a final / current indicator indicating the latest entry in the buffer.

[0104] Events that represent processor state 106 at any given runtime point are sequentially captured into bulk buffer 508. Bulk buffer 508 is used to intercept a set of entries whose contents report events recognized by the processor 106 during program execution (e.g., performing one , or more downloaded branches, abandonment events, the RIEMIT instruction, and the like). In an embodiment, these recognized events depend on the RICCB content shown in FIG. 10. The entries in the form of the presented implementation of the cache buffer 508 contain the address of the event instruction, and other relevant event metadata. Examples of event metadata include, but are not limited to: the address of the instruction of the downloaded branch and its purpose, including some information on the earlier behavior of this branch; the instruction address for the RIEMIT instruction and the corresponding registry value; and the address of the transaction dropout instruction and the corresponding transaction restore entry location.

[0105] An exemplary embodiment of the population buffer 508 stores up to thirty-two entries (i.e., information about thirty-two events), with the address of each instruction defined by sixty-four bits (e.g., bits 0:63), and event metadata defined by sixty - four bits (e.g., bits 64: 127). The size of the bulk buffer (RCB) is the size dependent on the model, showing the number of entries. In an embodiment, the size of the byte buffer cache 508 is a multiple of the 16-bit entry size. The size of the cumulative buffer (RCB) is the number of entries greater than or equal to the difference between the size of the largest reporting group (RRG) of this model and the number of entries in the reporting group that were not obtained from the cumulative buffer (RNC). Therefore, in the embodiment,

In an exemplary embodiment of the present invention, the content of the bulk buffer 508 and the data buffer of the instruction (if any) is emptied or otherwise influenced by the following events: (1) interrupt; (2) a PSW bit that turns on and off the execution instrumentation functionality (e.g. bit 24) changes from one to zero; and (3) if the sample instruction is recognized when the execution instrumentation functionality is in the transaction-execution mode (in this case, further updating of the data bulk buffer 508 and instruction data buffer is stopped and then resumed when the transaction is completed, when it is recording reporting group, and the 508 cache and the instruction-data buffer are emptied).

[0107] In an exemplary embodiment of the present invention, such as the emulated host computer system shown in FIG. 1B, the collective buffer 508 is implemented using registers and / or memory. In such an embodiment, the optional instruction-data buffer, if any, is also implemented using registers and / or memories.

[0108] In the exemplary embodiments of the present invention, additional possibilities may affect data collection and may be perceived as providing additional collection-data points, while not significantly interfering with the normal counting of counting instructions or counting cycles as previously described. This includes executing the RIEMIT instruction that collects the general register value by storing it in the bulk buffer 508. In addition, the data collection control bits in the executive instrumentation controls described earlier can be used to match those types of collected data (e.g., control bits E, C, R, and B). In this way, the type of data collected is programmable.

[0109] In an embodiment, the instruction-data buffer is used to collect data-dependent sample instructions that are used to create an entry of an instruction in performing instrumentation. The instruction-data buffer collects data from the instruction pending that it will be available when the instruction is recognized as a sample instruction. In an exemplary embodiment of the invention, the instruction-data buffer is a hardware buffer / storage space in the processor where information about the instruction that becomes triggered as a test point is written so that during the logout process, it could be saved with data from the buffer 508 Similarly to the 508 cache, it contains the address of the instruction, and the metadata associated with this instruction.

[0110] In accordance with exemplary embodiments of the present invention, other collected data may not come from a bulk buffer 508 or from a data buffer-instruction. Examples include data used to create the following parts: (1) the first entry of the reporting group: timestamp or entry entry; and (2) additional types of entries can be created for each reporting group, so not stored in the 508 cache, such entries, if they exist, can be placed in an additional, machine-specific, reporting group section. These entries are referred to herein as "system information entries".

[0111] FIG. 11 depicts a portion of the RICCB control block when the MRIC is not allowed to perform in half-privileged mode (i.e., the K bit is zero). The control block 1100 may include additional values ​​other than those described with reference to FIG.

11. If the semi-privileged mode is not allowed, the primary address section 1102 and the limiting address section 1104 are not used, and the current values ​​are not changed by the less-privileged program state.

[0112] In an embodiment, only a subset of all actuation controls are updated by successfully executing the MRIC instruction by the less-privileged state program.

[0113] If RICCB is captured, a number of errors can be encountered. In addition, if the RICCB address in the MRIC instruction is not correctly arranged, then an exception occurs. Similarly, if the address in the MRIC statement is not available, either because of an error state or an invalid address, then an exception occurs. If, during the execution of an MRIC instruction, it is determined that the RICCB values ​​conflict in any particular way (for example, they are internally inconsistent), then an exception is also present.

[0114] In an exemplary embodiment of the present invention, the exception of a special operation is recognized for any of the following reasons: the MRIC instruction is issued and the performance instrumentation is enabled, the current actuation controls are incorrect; and / or the processor is in a less-privileged state and the execution bit of the performance instrumentation in current actuator controls is zero.

[0115] In an embodiment, a specification exception is recognized for any of the following reasons: the storage space argument belonging to the MRIC is not arranged at the two-word boundary; the processor is in the supervisor state or the K bit in the current actuator controls is one and any of the following states are recognized: the specified limiting address is smaller than the specified primary address; the specified current address is smaller than the specified primary address; and the specified current address is greater than the sum of unity plus the specified generated restriction address; and the processor is in a less-privileged state, the bit kw of the current RI controls is zero and any of the following states are recognized: the specified current address is smaller than the current primary address; the specified current address is greater than the sum of unity plus the specified limiting address; an invalid mode is specified.

[0116] In an embodiment, the MRIC instruction that is defined for a particular processor of some architecture may be executed by a subordinate processor with a different architecture. In an embodiment, the minor processor recognizes the software-based emulation routine, and executes the MRIC instruction using this software-based emulation routine.

[0117] FIG. 12 shows an example of a high-level reporting group 1200 stored in the program buffer 522 at the test point. The size of the reporting group is represented by RRG, equal to 2^{(RGS + 1)}, where RGS is the size of the reporting group as an exponent. The model-dependent number of entries (RNC) copied from a location other than the cache 508 may or may not be copied non-destructively when used as a reporting group. In the example of FIG. 12, RRG = 8, RGS = 2, and RNC =

4. An example of reporting group 1200 shown in FIG. 12 includes a header section 1202, a content section 1204, a section 1206 additional entries, and a footer section 1208.

[0118] The header section 1202 may include a start entry or time stamp entry for storing status information, tracking information and / or time dependencies. The start entry is recorded in the header section 1202 for the first reporting group stored in the program buffer (that is, if the RCA 1006 is equal to ROA 1002). In an embodiment, the start entry contains an entry type field of "02", a field of number of reporting groups (NRGs) to indicate how many reporting groups are currently stored in the program buffer, the RGS field for indicating the size those reporting groups, the stopped field (S) to indicate whether the program buffer 522 is full or not, the halted field (H) to indicate whether the performance instrumentation is stopped, and a time of day (TOD) field to indicate when the start entry was saved. In an exemplary embodiment of the present invention, at least a subset of these fields in the start entry is taken from an RI control block (e.g. from RICCB). An example of the timestamp entry character has an entry type of "03" and contains the TOD clock field to indicate when this entry was saved. In an exemplary embodiment of the present invention, the time stamp entry is recorded in the header section 1202 for each reporting group other than the first reporting group. An example of the timestamp entry character has an entry type of "03" and contains the TOD clock field to indicate when this entry was saved. In an exemplary embodiment of the present invention, the time stamp entry is recorded in the header section 1202 for each reporting group other than the first reporting group. An example of the timestamp entry character has an entry type of "03" and contains the TOD clock field to indicate when this entry was saved. In an exemplary embodiment of the present invention, the time stamp entry is recorded in the header section 1202 for each reporting group other than the first reporting group.

[0119] The report group content section 1204 may include various entries for events and information sampled from the data buffer 508. Events and information may represent, for example, state information captured by the send instruction, abandon transaction execution, call, return, branching and filling.

[0120] In an exemplary embodiment of the present invention, the send entry is created and stored in the bulk buffer 508 after the RIEMIT instruction has been successfully executed.

An example of the entry form send contains an entry type field of "10", the instruction address field code for indicating how the bits of the address address for the current PSW are shown in the send entry, the address field of the instruction, which varies depending on the addressing mode ( for example, 64, 31 or 24-bit) and contains the instruction address for the RIEMIT statement or the runtime instruction if RIEMIT was the purpose of the runtime instruction and the send data field for storing the data from the general register specified by the RIEMIT instruction.

[0121] In an exemplary embodiment of the present invention, an abstraction of the transaction-execution mode is created and stored in the bulk buffer 508 by either unconditional abandonment, or by executing a transaction abandon statement. The execution form of the abandon entry contains the entry type field with the value "11", the field of the address code of the instruction for indicating how the position of the current service PSW address bits is entered in the transaction-specific abandon entry, the instruction address field, which varies depending on the mode addressing (for example, 64, 31 or 24-bit) and includes the address of the instruction of the dropped statement or the runtime instruction if the instruction dropped was the purpose of the runtime instruction and the field for any model-related data associated with the abandon.

[0122] In an exemplary embodiment of the present invention, a call entry is created by executing a branching instruction in a call type, such as BRANCH AND SAVE (BASR) when the R2 field is non-zero, BRANCH AND SAVE (BAS), BRANCH RELATIVE AND SAVE LONG, BRANCH RELATIVE AND SAVE, BRANCH AND LINK (BALR) when R2 is non-zero, BRANCH AND LINK (BAL), and BRANCH AND SAVE AND SET MODE when R2 is non-zero. An example of a call entry contains an entry type field with the value "12", an instruction address code field for indicating how the position of the current service PSW address bits in the transaction-specific abandon entry is presented, the address field of the instruction, which varies depending on the addressing mode (e.g. 64,

[0123] Return entries and transfer entries may have the same format as call entries. In an exemplary embodiment of the present invention, the return entry has an entry type field with a value of "13" and is created by executing a return type branch instruction such as BRANCH ON CONDITION (BCR) when the R2 field is nonzero and the mask is 15. For the return entry, the instruction address field contains the address of the branch instruction or the execution type instruction if the branch is the target of the execution type instruction and the destination address field contains the return position.

In an exemplary embodiment of the present invention, the transfer entry has an entry type field of value "14" and is created by executing a branch return instruction such as a. BRANCH ON CONDITION (BCR) when the R2 field is nonzero and the mask is in from 1-14; b. BRANCH ON CONDITION (BC) when bit J is zero or when the mask is in the range 1-14; c. BRANCH ON COUNT (BCT, BCTR, BCTG, BCTGR); d. BRANCH ON INDEX HIGH (BXH, BXHG); e. BRANCH ON INDEX LOW OR EQUAL (BXLE, BXLEG); f. BRANCH RELATIVE ON CONDITION (BRC); g. BRANCH RELATIVE ON CONDITION LONG (BRCL); h. BRANCH RELATIVE ON COUNT (BRCT, BRCTG); i. BRANCH RELATIVE ON COUNT HIGH (BRCTH); j. BRANCH RELATIVE ON INDEX HIGH (BRXH, BRXHG); k. BRANCH RELATIVE ON INDEX LOW OR EQUAL (BRXLE, BRXLG); l. COMPARE AND BRANCH (CRB, CGRB); m. COMPARE AND BRANCH RELATIVE (CRJ, CGRJ); n. COMPARE IMMEDIATE AND BRANCH (CIB, CGIB); o. COMPARE IMMEDIATE AND BRANCH

RELATIVE (CIJ, CGIJ); p. COMPARE LOGICAL AND BRANCH (CLRB, CLGRB); q. COMPARE LOGICAL AND BRANCH RELATIVE (CLRJ, CLGRJ); r. COMPARE LOGICAL IMMEDIATE AND BRANCH (CLIB, CLGIB); and p. COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (CLIJ, CLGIJ). A forwarding entry is created when a branch is taken. For the forwarding entry, the instruction address field contains the address of the branch instruction or type instruction instruction if the branch is the target of the execution type instruction and the destination address field contains the return position.

[0125] A fill entry is used in the reporting group when the number of valid entries in bulk buffer 508 is not enough to populate the reporting group of the current RGS. The execution form of the entry includes the field of the entry type with the value "00" to indicate that this entry is an entry in the entry, and the remaining bytes are undefined. [0126] Section 1206 of additional entries, if any exists, may contain entries depending on the model. In the embodiment, the additional entry format is similar to the entry entry except that the entry type is set to "01" to indicate that this entry is an additional entry, and the remaining bytes of this additional entry may contain data depending on the model.

[0127] The footer section 1208 may include an instruction entry including information about the execution of the sample instruction. The statement entry is created when the reporting group is saved for the sample instruction. The entry form of the instruction entry contains the entry type field with the value "04", the instruction address field code for indicating how the bits of address addresses for the current PSW are presented in the instruction entry, the address field of the instruction, which varies depending on the addressing mode (for example, 64, 31 or 24 bit) and contains the instruction address for a sample instruction or execution type instruction if the sample instruction was the purpose of the execution type instruction, and an instruction-data buffer (IDB) field containing any Model-based data collected from IDB.

[0128] As described above, the embodiments may be implemented in the form of computer-implemented processes and devices to apply these processes. The embodiment may include a product 1300 in the form of a computer program as shown in FIG. 13 on a carrier 1302 read / appropriate for a computer with logical dependencies 1304 of a computer program code containing instructions placed on a tangible medium as a factory product. Examples of factory products for computer-readable / computer-readable media 1302 may include floppy disks, CD-ROMs, hard disks, flash memory (USB) drivers, or any other readable computer storage medium, where, if the logical dependencies 1304 of a computer program code they will be loaded onto it and made by a computer, this computer becomes a device for applying the present invention. Embodiments include logical dependencies 1304 of a computer program code, e.g. stored on a storage medium, whether loaded into and / or running by a computer, or transmitted via a transmission medium, such as wires or electrical wiring, through a fiber optic cable, or electromagnetic radiation. , where, if the logical code 1304 dependencies of the computer program code are loaded onto it and executed by the computer, this computer becomes a device for applying the present invention. When it is applied to a general-purpose microprocessor, the logical dependency segments 1304 of the computer program code configure the microprocessor to create specific logic circuits.

[0129] Technical effects and advantages include an MRIC instruction that can be performed by a less-privileged program to change the settings of the performance instrumentation when performing from a less-privileged state.

[0130] The terminology used herein is only intended to describe specific embodiments and its intended purpose is not to limit the present invention. As used herein, the singular forms are also intended to include plural forms unless otherwise expressly indicated. Furthermore, it is understood that the terms "includes" and / or "comprising", if used in this specification, define the presence of said functionalities, integers, steps, operations, elements, and / or subassemblies, but do not exclude the existence or addition of one , or more other functionalities, integers, steps, operations, elements, sub-assemblies and / or groups thereof.

[0131] Suitable constructions, materials, operations, or equivalents of any measure or function of the plus or function step, in the claims that follow, are intended to cover any structure, material, or operation for performing functions in conjunction with other claimed elements as separately claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the present invention in the disclosed form. Many changes and variations will be apparent to those skilled in the art without departing from the scope of the present invention. The present embodiment has been selected and described in order to best explain the principles of the present invention and its practical application,

[0132] As will be appreciated by one skilled in the art, the aspects of the present invention can be used as a system, method or product in the form of a computer program. Accordingly, aspects of the present invention may take the form of a completely hardware embodiment, a fully programmatic embodiment (including firmware, resident software, micro-code, and the like) or embodiments combining the software and hardware aspects of the present invention, which may to be here all generally referred to as "layout", "module", or "system". Furthermore, aspects of the present invention may take the form of a product in the form of a computer program comprised of one or more computer readable media having a computer-readable program code contained therein. [0133] Any combination of one or more computer-readable media may be used. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, e.g., but is not limited to, an electronic, optical, electromagnetic, infrared or semiconductor system, apparatus, or device, or any useful combination thereof. More specific examples (the inventory is not exhaustive) of computer-readable storage media include the following: an electrical connection having one or more wires, a computer diskette, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), optical fiber, portable read-only disk (CD-ROM), optical storage device, magnetic storage device, or any useful combination of the above. In the context of this document, a computer-readable storage medium may be any material medium that it may contain, or save the program for use by or in combination with a system, apparatus or instruction execution device.

[0134] A computer readable medium may include a transmitted digital signal with a computer-readable program code included therein, e.g. in the baseband, or as part of a carrier wave. Such transmitted signal may take on one of many different forms, including, but not limited to, electromagnetic, optical, or any useful combination thereof. The computer-readable medium may be any computer-readable medium that is not a storage medium readable to the computer and which may connect, transmit, or transfer the program for use by or in conjunction with a system, apparatus or instruction execution device.

The program code included on a computer-readable medium may be transmitted using any suitable medium, including, but not limited to, a wireless, wire, fiber optic, radio (RF) carrier, and the like, or any combination of the above.

[0136] A computer program code for performing operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object-oriented programming language such as Java, Smalltalk, C ++, or similar, and traditional procedural programming languages, such as like the programming language "C" or similar programming languages. The program code can be executed completely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or completely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN),

[0137] Aspects of the present invention have been described above with reference to illustrations of flow diagrams and / or pictorial diagrams of methods, apparatuses (s) and products in the form of a computer program, according to an embodiment of the present invention. It is understood that each block of illustration of the flow chart and / or block diagram, and combinations of blocks of illustrations of the flow chart and / or block diagram may be implemented by the instructions of the computer program. These computer program instructions may be provided to a general purpose computer processor, a specialized computer, or other programmable data processing device to create a device, so that instructions that are executed by a computer processor or other programmable data processing device,

[0138] These computer program instructions can also be stored on a computer-readable medium that can guide a computer, other programmable data processing device, or other device to function in a specific manner so that the instructions stored on a computer-readable medium form a factory product containing instructions that implement the function / actions specified in the flowchart and / or block or blocks of the flowchart.

[0139] These computer program instructions may also be input to a computer, other programmable data processing device or other devices to cause a series of working steps to be performed by the computer, other programmable data processing device, or other devices to creating a process implemented by the computer in such a way that the instructions that operate on the computer or other programmable device provide a process performing the functions / operations defined in the flowchart and / or block or blocks of the flowchart.

[0140] As described above, the embodiments may be implemented in the form of computer-implemented processes or devices for using these processes. In an embodiment, the present invention is implemented in a computer program code run on one or more network elements. Embodiments include a product in the form of a computer program on a computer-usable medium with logical dependencies of a computer program code containing instructions contained on a material carrier as a factory product. Exemplary factory products for computer-readable media may include floppy disks, CD-ROMs, hard disks, flash memories (USB) flash, or any other computer-readable medium where, if the logical dependencies of the computer program code are entered and executed by the computer, then the computer will become a device for applying the present invention. Embodiments include logical dependencies of a computer program code, e.g., contained on a storage medium inserted into or made by the computer, or transmitted via a transmission medium such as electrical wires or cabling through a fiber optic or electromagnetic radiation, where, if the logical dependencies of the computer program code will be entered into, and executed by the computer, then the computer will become a device for applying the present invention. When it is used on a general purpose microprocessor,

[0141] The flow diagram and block diagrams in these figures illustrate the architecture, functionality and operation of possible implementations of systems, methods and products in the form of a computer program according to various embodiments of the present invention. For this reason, each block in the flowchart or block diagrams may represent a module, segment, or portion of code that includes one or more executable instructions to perform specific (logic) functions. It should also be noted that in some alternative embodiments, these functions selected in such a block may appear in a different order in these figures. For example, two blocks shown as sequential may in fact be substantially simultaneous, or these blocks may sometimes be executed in reverse order, depending on the functionality being implemented. It should also be noted that each block of block diagrams and / or illustrations of flow charts, and combinations of block diagrams and / or schematic illustrations may be implemented by systems based on special-purpose equipment that performs specific functions or actions, or combinations of special attachments. applications and computer instructions.