Method, apparatus, and system for time synchronization

[0001] The invention relates to communication technologies, in particular a method, apparatus and time synchronization system.

Background of the invention [0002] With the advent of third generation mobile communications technology (3G) and more modern digital mobile technologies, the requirements for time synchronization are constantly increasing. Time synchronization is becoming more and more important considering the costs, security and service requirements. At present, the time synchronization accuracy required by mobile services is in the order of microseconds. However, it is difficult to achieve high-precision time synchronization.

[0003] The IEEE1588 (PTP) exact time protocol provides the basic mechanism for accurate time synchronization between a master clock and a slave clock. This mechanism requires the collection of a sufficient amount of time stamp information transmitted between the master clock and the slave clock, and the adjustment of time synchronization between the master clock and the slave clock according to the collected time stamp information.

[0004] The prior art has at least the following disadvantages: for most optical and Ethernet installations, a synchronization pulse signal may be used to trigger the acquisition of the necessary time stamp information. Time stamps are for example obtained on the signal edge of the transmitted frame and on the signal edge of the received frame. However, in bandwidth transmission systems that transmit signals continuously in symbol sets, such as systems based on discrete multi-tone modulation (DMT) and orthogonal frequency multiplication (OFDM), there is no obvious boundary between symbols and the receiving side has difficulties in obtaining information about time stamps, which makes it difficult to implement precise time synchronization between the master clock and the slave clock.

[0005] Document of Hyuntae Cho et al. "Implementation of a precision time protocol over low rate wireless personal area networks", Computer Systems Architecture Conference, 2008, ACSAC 2008, 13th Asia-Pacific, IEEE, Piscataway, NJ, USA, August 4, 2008 (August 8, 2008), pages 1-8, ΧΡ031321187; ISBN: 978-1-4244-2682-9, describes the design and implementation of an accurate time protocol in low-speed wireless personal networks (LR-WPAN). In order to achieve high accuracy in LR-WPAN networks, it analyzes delay and fluctuation factors in wireless environments and aims to minimize these factors.

[0006] US 6,243,369 B1 describes a two-way data transmission system. "There is an algorithm that can be executed in the MAC or TC layer process or inline logic 340 of Fig. 8 to determine the beginning of the insertion point for the time stamp. This algorithm is based on the observation that the FEC frame in 64-QAM contains 34 MPEG 13-byte packets, in 256-QAM the FEC frame contains 50 6-byte MPEG packets. Using this information, the algorithm accurately determines the place in the MPEG packet where the synchronization message will be placed to insert the synchronization message so that it is completely surrounded within the MPEG packet ".

Summary of the Invention [0007] Embodiments of the invention show a method, apparatus and time synchronization system for performing time synchronization between a master clock and a slave clock in communications systems that transmit signals continuously in sets of symbols.

[0008] A method of time synchronization in a system based on discrete multi-tone modulation (DMT) according to any one of claims 1 to 8.

[0009] A time synchronization device in a system based on discrete multi-tone modulation (DMT) according to any one of claims 9 to 14.

[0010] Time synchronization system in a system based on discrete multi-tone modulation (DMT) according to any one of claims 15 to 16.

[0011] In embodiments of the invention in communication systems that transmit signals in sets of symbols, a predetermined specific position of a specific symbol is used as a switching edge to obtain time stamp information, and time synchronization is performed between the master clock and the slave clock according to the obtained information. about the time stamp. Thus, time synchronization is performed between the master clock and the slave clock in communication systems that transmit signals continuously in symbol sets.

Brief Description of the Drawings [0012] For a better understanding of the technical solution in the invention or in the state of the art, the accompanying drawings are shown below to illustrate embodiments of the invention or the state of the art. In fact, the accompanying drawings are merely exemplary, and those skilled in the art can obtain other drawings from such accompanying drawings without creative effort.

Fig. 1a shows the basic mechanism of time synchronization in an application scenario in an embodiment of the invention;

Fig. 1b is a flowchart of a method of time synchronization in an embodiment of the invention;

Fig. 2 is a flowchart of another method of time synchronization in an embodiment of the invention;

Fig. 3 is a flowchart of another method of time synchronization in the example

- 3 embodiments of the invention;

Fig. 4a is a flowchart of another method of time synchronization in an embodiment of the invention;

Fig. 4b shows a first example of using the average time offset determination in an embodiment of the invention;

Fig. 4c shows a second example of using the average time offset determination in an embodiment of the invention;

Fig. 5 is a first schematic diagram showing a digital subscriber line (DSL) transmission bandwidth transmission in an application scenario in an embodiment of the invention;

Fig. 6 is a second schematic diagram showing a DSL system of bandwidth transmission in an application scenario in an embodiment of the invention; Figure 7 shows the structure of a time synchronization device in an embodiment of the invention;

Figure 8 shows the structure of another time synchronization device in an embodiment of the invention;

Fig. 9 shows the structure of a time synchronization system in an embodiment of the invention;

Detailed Description of Embodiments [0013] The technical solution within the scope of the invention is described below with reference to the accompanying drawings. In fact, the embodiments described below are merely exemplary without including all embodiments of the invention. Skilled artisans may derive other embodiments from the embodiments set forth herein without making any creative effort, and all such embodiments will be within the scope of protection of the invention.

[0014] Fig. 1a shows the basic mechanism of time synchronization in an application scenario in an embodiment of the invention. As shown in Fig. 1a, the basic time synchronization mechanism can be briefly described as follows:

The master clock periodically sends a piece of synchronization information (Sync). After the Sync information is sent, the master clock sends a Follow_UP piece of information, which includes a time stamp, where the time stamp records the actual time (hereinafter referred to as the master device transmission time stamp Tm1) of the master clock when the master clock sends the Sync information. The slave clock records the time (hereinafter referred to as receiving the Ts1 time stamp by the slave) of the slave clock when the slave clock receives the Sync information.

[0015] After receiving the Sync information, the slave clock sends a delay request (DelayReq), which includes a time stamp to the master clock, where the time stamp registers the time (hereinafter referred to as sending the Ts2 time stamp by the slave) of the slave clock when the slave clock transmits DelayReq. 4. After receiving Delay_Req, the master clock sends the delay response (Delay_Resp) it contains

- a 4 time stamp to the slave clock, where the time stamp registers the time (referred to here as receiving the Tm2 time stamp by the master device) of the master clock when the master clock receives the Delay Req.

[0016] In this way, when the slave clock receives the DelayResp, four time stamps are obtained, i.e. Tm1, Ts1, Ts2, and Tm2. The slave clock may calculate the offset between the master clock and the slave clock and the transmission link delay according to Tm1, Ts1, Ts2, and Tm2. The forward link delay includes the download forward link delay (Delay 1) and the loading forward link delay (Delay2). The transmission link delay from the master clock to the slave clock is Delay 1, and the transmission link delay from the master clock to the master clock is Delay2. Time shift, Delay 1 and Delay2 meet the following relationship:

Offset = Ts1 - Tm1 - Delay 1 (1)

Shift = Ts2 - Tm2 + Delay2 (2) [0017] Assuming that Delay 1 is equal to Delay2, that is, Delay 1 = Delay2, the following formula can be obtained:

Offset = (Ts1 + Ts2 - Tm1 - Tm2) / 2 (3) [0018] The clock time of the slave clock can be synchronized with the clock time of the master clock according to the offset calculated by applying formula (3).

[0019] In this embodiment, the previous mechanism is used in communication systems that transmit signals in DMT system symbol sets. The boundary between symbols is difficult to determine because symbols in DMT systems are transmitted continuously. Therefore, in order to apply the previous mechanism to DMT systems, the triggering edge for receiving time stamp information should be specified in these communication systems. In this embodiment, the specific position of the specific symbol is first determined on the master clock and the slave clock, i.e. the preset position of the preset symbol is used as the trigger edge to receive the time stamp information.

[0020] Fig. 1 is a flowchart of a time synchronization method in an embodiment of the invention. In this embodiment, the method of time synchronization is performed by slave clock devices. As shown in Figs. 1a and 1b, the method of time synchronization in this embodiment includes the following steps:

Stage 11: Obtaining a timestamp of sending by the master device, timestamp of receiving by the slave device, timestamp of sending by the slave device and receiving timestamp by the master device, where the timestamp of sending by the master device is the clock time of the master clock that is received by the slave clock and read by the master clock at the time of transmission of the preset specific position of the first specific symbol, the time stamp of the slave receiving is the clock time of the slave clock, which is read by the slave clock when receiving

- 5 specific position of the first specific symbol, the slave sending time stamp is the clock time of the slave clock that is read by the slave clock about the sending time of the specific position of the second specific symbol, and the main device receiving time stamp is the clock time of the master clock, which is read by the master clock about the time of receiving the specific position of the second specific symbol.

[0021] In systems that continuously transmit signals in sets of symbols, a specific position of a specific symbol may be pre-set to trigger a local clock time reading. This position can be the starting position of the symbol. The start position of the symbol can be the position after the cyclic prefix of that symbol. During actual implementation, the position after interference protection (ISI) is the start position of the symbol. In addition, the end of the symbol or any position in the center of the symbol can be used as a specific position to trigger the timestamp acquisition.

[0022] In order to perform time synchronization between the master clock and the slave clock, reading of the master device sending time stamp, slave receiving time stamp, slave sending time stamp and master device receiving time stamp is triggered at the corresponding symbol positions. This means that Tm1, Ts1, Ts2 and Tm2 as shown in Fig. La are obtained. Tm1 and Tm2 that read the master clock at specific positions of the first specific symbol and the second specific symbol may be transmitted in the associated messages shown in Fig. 1a, and the messages shall be sent to an equal device. In this way, the slave clock may receive Tm1, Ts1, Ts2 and Tm2 according to the specific positions of the slave clock in the first specific symbol and in the second specific symbol, i.e. Ts1 and Ts2.

Step 12: Adjusting the slave clock time according to the obtained time stamps to synchronize with the clock time of the master clock.

[0023] According to Tm1, Ts1, Ts2 and Tm2, ​​the offset between the clock time of the master clock and the clock time of the slave clock can be calculated using formula (3). The clock time of the slave clock is adjusted according to the calculated offset, so that the clock time of the slave clock is synchronized with the clock time of the master clock.

[0024] In this embodiment, in communications systems that transmit signals in sets of symbols, a predetermined specific position of a particular symbol is used as a trigger edge to obtain time stamp information; when the specified symbol position is reached, the action of acquiring the master timing of the slave, slave receiving timestamp, slave receiving timestamp or master receiving of the timestamp is triggered, and the time is synchronized between the master clock and the slave clock according to the timestamp information obtained. Yes

Thus, time synchronization is implemented between the master clock and the slave clock in systems that transmit signals continuously in sets of symbols.

[0025] Fig. 2 is a flowchart of another method of time synchronization in an embodiment of the invention. In this embodiment, the method of time synchronization is performed by master clock devices. As shown in Fig. 2, the method of time synchronization in this embodiment includes the following steps:

Stage 21: Obtaining a timestamp of sending by the master device and the timestamp of receiving by the master device, where the timestamp of sending by the master device is the clock time of the master clock, which is read by the master clock about the time of sending the predefined position of the first specific symbol and the timestamp of receiving by the master device is the clock time of the master clock, which is read by the master clock about the time of receiving the preset specific position of the second specific symbol.

[0026] The specific positions of the first specific symbol and the second specific symbol are preset to trigger the master clock or slave clock to read the local clock time. For example, the specific position of the first specific symbol is used to trigger the master clock to read the local clock time (i.e., Tm1) at the time of sending the specific position of the first specific symbol; and the specific position of the second specific symbol is used to trigger the master clock to read the local clock time (i.e., Tm2) at the time of receiving the specific position of the second specific symbol. The first specific symbol is different from the second specific symbol, but the specific positions of these two specific symbols may be the same. For example, the start position of the first specific symbol and the start position of the second specific symbol may be predefined at the specific positions of the first specific symbol and respectively the second specific symbol.

Step 22: Forwarding the master device sending time stamp and master device receiving time stamp to the slave clock so that the slave clock adjusts the clock time of the slave clock to synchronize the clock time with the master clock.

[0027] The specific position of the first specific symbol is also used to trigger the slave clock to read the local clock time (i.e. Ts1) at the time of receiving the specific position of the first specific symbol. The specific position of the second specific symbol is also used to trigger the slave clock to read the local clock time (i.e., Ts2) at the time of transmitting the specific position of the second specific symbol.

[0028] The slave clock may adjust the clock time of the slave clock according to Tm1, Ts1, Ts2 and Tm2 to synchronize with the clock time of the master clock. Details are given in step 12 shown in Fig. 1b.

[0029] In this embodiment, in communications systems that transmit signals in

- 7 sets of symbols, a pre-set specific position of a specific symbol is used as a trigger edge to obtain time stamp information when a specific position of a specific symbol is reached, the action of reading a time stamp is triggered, and the master clock sends a read time stamp to the slave clock, thanks to which the slave clock synchronizes with the main clock time. Thus, in communication systems that transmit signals continuously in symbol sets, time synchronization is performed between the master clock and the slave clock.

[0030] Fig. 3 is a flowchart of another method of time synchronization in an embodiment of the invention. In this embodiment, the symbol of the obtained time stamp is corrected according to the phase information of the subcarriers that make up the specific symbol, e.g., single carrier phase information. As shown in Fig. 3, the method of time synchronization in this embodiment includes the following steps:

Step 31: The master clock reads the local clock time (i.e. Tm1) of the master clock at the time of sending the specific position of the first specific symbol, and sends Tm1 to the slave clock.

Step 32: The slave clock reads the local clock time (i.e., the slave receiving time stamp Ts1 ') of the slave clock at the time the specific position of the first specific symbol is received.

[0031] In this embodiment, the specific position of the first specific symbol or the second specific symbol may be the start position of the specific symbol. When the master clock or slave clock is the receiving side receiving synchronization information, the previous algorithm for determining the start position of the symbol (i.e., the symbol synchronization algorithm) can be used to calculate the start position of a specific symbol, the main device receiving time stamp or the slave receiving time stamp is obtained at the starting position of the specified symbol.

[0032] However, due to factors such as interference, channel nonlinearity and the sampling rate limit, the start position of the specific symbol obtained by using the symbol synchronization algorithm may differ slightly from the actual start position of the specific symbol. In particular in low frequency charging bands, the linearity of the channel frequency response in these bands is very poor due to the low sampling rate, causing a large error in calculating the start position. If the symbol synchronization algorithm is used to calculate the symbol's start position, Ts1 'or Tm2' is obtained. The offset error based on Ts1 'or Tm2' can be increased, thus limiting the accuracy of time synchronization between the slave clock and the master clock. In order to increase the accuracy of time synchronization between the slave clock and the master clock, a symbol correction can be performed at a specific position of the specific symbol. In this embodiment, the symbol of the obtained time stamp is corrected according to the phase information of the subcarriers that make up the specific symbol, e.g., single carrier phase information.

- 8 Step 33: The slave clock obtains the phase difference Δφ of any subcarriers that form the first specific symbol relative to the specific position of the particular symbol on the master clock and the slave clock.

[0033] The specific symbol generally consists of many subcarriers. At this stage, the phase difference is the phase difference of any of the subcarriers relative to the start position of the specific symbol on the master clock and the slave clock. The initialization information or frequency domain equalizer information (FEQ) of the receiving device on the master clock or slave clock transfers the subcarrier phase difference on the master clock and slave clock. Hence, the phase difference of any subcarrier relative to the start position of the specific symbol on the master clock and the slave clock may be pre-derived according to the initialization information or FEQ information of the receiving device on the master clock or the slave clock.

[0034] Otherwise, a phase difference may be obtained according to the subcarrier signal phase relative to the symbol start position on one side and the subcarrier signal phase relative to the calculated symbol start position on the other side. In particular, the phase of the subcarrier signal relative to the start position of the symbol is already known when the master clock device or the slave clock device sends some specific signals during initialization. For example, if the subcarrier signal phase relative to the start position of a specific symbol is zero degrees, the subcarrier signal phase relative to the calculated start position of the specific symbol on the slave clock may be a non-zero number of degrees, e.g., 45 degrees, because there are some errors between the calculated start position of the specific symbol and the actual start position of the specified symbol. In this case, the phase difference of the subcarrier signal can be obtained relative to the start position of the specific symbol on the master clock and the slave clock, for example φφ = 45 °.

[0035] To increase the reliability and accuracy of the correction process and reduce the negative impacts caused by factors such as selective frequency noise, a subcarrier signal with a better signal-to-noise ratio can be selected to perform symbol correction.

Step 34: The slave clock determines the time offset At corresponding to φφ [0036] For example, the obtained phase difference (φφ = 45 °) is converted to At. Optionally, At is equal to the phase difference divided by angular velocity.

Step 35: The slave clock corrects Ts1 'according to t, and obtains Ts1.

[0037] The time offset calculated by the slave clock according to the subcarriers that make up the first specific symbol is used to correct Ts1 '. The time offset calculated by the master clock according to the subcarriers that make up the second specific symbol is used to correct Tm2 '. The step of performing the symbol correction on Ts1 'or Tm2' may include: subtracting Δ1 from Ts1 'or Tm2', and obtaining Ts1 or Tm2.

[0038] In those steps, Ts1 'and Tm2', which are obtained at the specific position of the specific symbol with a large error, are corrected to Ts1 and Tm2, ​​which are obtained at the actual specific position of the specific symbol.

Step 36: The slave clock reads the local clock time (i.e., Ts2) of the slave clock at the time of sending the specific position of the second specific symbol, and sends the second specific symbol to the master clock.

Step 37: The master clock reads the local clock time (i.e. Tm2 ') of the master clock at the time of receiving the specific position of the second specific symbol.

Step 38: The master clock determines the time offset corresponding to the phase difference of any of the subcarriers that make up the second specific symbol, relative to the specific position of the specific symbol on the master clock and the slave clock, corrects Tm2 'according to the time offset and obtains Tm2.

[0039] At this stage, the method of correcting Tm2 'by the master clock is similar to the method of correcting Ts1' by the slave clock in steps 33 to 35, and is not further described.

Step 39: The master clock sends Tm2 to the slave clock.

Step 310: The slave clock adjusts the clock time of the slave clock according to Tm1, Ts2, Ts1 and Tm2 to synchronize with the clock time of the master clock.

[0040] If Tm1, Ts2, Ts1 and Tm2 are substituted in formula (3), an offset between the master clock and the slave clock is obtained. The clock time of the slave clock is adjusted in accordance with the offset to synchronize with the clock time of the master clock.

[0041] In this embodiment, Tm2 'and Ts1' are corrected according to the time offset corresponding to the phase difference of the single carrier on the master clock and the slave clock, so that Tm2 and Ts1 are closest to the time stamps that are obtained by the receiving side in the actual determined the position of the specified symbol. Therefore, the time offset error between the master clock and the slave clock is reduced and the time synchronization accuracy between the slave clock and the master clock is improved.

[0042] Fig. 4a is a flowchart of another method of time synchronization in an embodiment of the invention. In this embodiment, the symbols of the obtained time stamps are corrected according to the phase information of the subcarriers that make up the specific symbol, e.g. the phase information with at least two carriers. As shown in Fig. 4a, the method of time synchronization in this embodiment includes the following steps:

Steps 41 to 42 are similar to steps 31 to 32, but are not further described.

Step 43: The slave clock obtains phase differences of at least two subcarriers that make up the first specific symbol relative to the specific position of the specific symbol on the master clock and the slave clock.

[0043] If the error between the calculated specific position of a specific symbol and the actual specific position of a specific symbol is greater than the subcarrier period, the symbol can

- correct according to the phase information of the subcarrier group (e.g. two or more subcarriers). The method for obtaining the phase difference of any of the subcarriers in this step is similar to step 33, but is not further described.

Step 44: The slave clock determines the average time shift of each phase difference, corrects Ts1 'according to the average time shift and obtains Ts1.

[0044] Fig. 4b illustrates a first example of the use of determining the average time offset in an embodiment of the invention. The horizontal coordinate of the sub chart in the upper left corner of Fig. 4b refers to the subcarrier serial number, and the vertical coordinate refers to the phase. To increase the time synchronization accuracy of all symbol subcarriers, two or more subcarriers with a better signal-to-noise ratio and linear frequency response can be selected. This means that each carrier carrying this group of subcarriers has approximately the same time offset. The sub chart in the upper right corner of Fig. 4b shows that a number processing algorithm is used to fit the curve in the sub chart in the upper left corner of Fig. 4b to a straight line. For example, a minimum mean square error algorithm may be used to match the sub-graph in the upper left corner of Fig. 4b with the straight line shown in the sub-graph in the upper right corner of Fig. 4b. The sub-graph in the lower right corner of Fig. 4b refers to the slope of the curve in the upper corner of Fig. 4b. The sub-graph in the lower left corner of Fig. 4b refers to the time offset of each subcarrier that is transformed from the slope shown in the sub-graph in the lower right corner of Fig. 4b. If the selected subcarrier group has good frequency response linearity, the time offset corresponding to the phase difference of each subcarrier is approximately equal, which is represented by a straight line on the subchart in the lower left corner of Fig. 4b. The average time offset At is calculated according to all time offsets; symbol correction is performed on the calculated specific position of the specific symbol and the corrected specific position of the specific symbol is obtained.

[0045] Fig. 4c illustrates a second example of the use of determining the average time offset in an embodiment of the invention. If each subcarrier in the subcarrier group has a weak linear frequency response, then the method shown in Fig. 4c can be used to determine the average time offset corresponding to the phase information of each subcarrier to reduce the symbol correction error. The difference between the method of Fig. 4b and the method of Fig. 4c is as follows: In Fig. 4c the sub chart in the upper left corner is converted into a slope graph in the lower right corner; the time offset of each subcarrier in the lower left corner of Fig. 4c is obtained according to the slope diagram.

[0046] After obtaining the time offset of each carrier, the average value of all time shifts is calculated and the average time offset At is obtained. For example, the average value of the five time shifts shown in the sub-graph in the lower left corner of Fig. 4c is calculated and the average time shift At is obtained. Symbol correction is performed on the slave device receiving the time stamp or the master device receiving the time stamp according to At. For example, At

- 11 is subtracted from the obtained Ts1 'or Tm2' and the resulting Ts1 or Tm2 is obtained.

[0047] At this stage, the slave clock corrects Ts1 ', which is obtained by the slave clock at the calculated specific position of the specific symbol with a large error relative to Ts1, which is obtained at the actual specific position of the specific symbol.

[0048] Steps 45 to 46 are similar to steps 36 to 37, but are not further described.

Step 47: The master clock determines the average time offset corresponding to the phase difference of at least two subcarriers that make up the second specific symbol, relative to the specific position of the specific symbol on the master clock and the slave clock, corrects Tm2 'according to the average time offset and obtains Tm2.

[0049] At this stage, the method of correcting Tm2 'by the master clock is similar to the method of correcting Ts1' by the slave clock in steps 43 to 44, but is not further described.

[0050] In this method, the master clock corrects Tm2 ', which is obtained at the calculated specific position of the specific symbol with a large error relative to Tm2, ​​which is obtained at the actual specific position of the specific symbol.

[0051] Steps 48 to 49 are similar to steps 39 to 310, but are not further described.

[0052] In this embodiment, Tm2 'and Ts1' are corrected according to the average time shift corresponding to the phase difference of each carrier in the group of at least two subcarriers that form the first or second specific symbol, relative to the master clock and the slave clock, such that Tm2 and Ts1 are closest to the time stamp obtained in the actual specific position of the specific symbol. In this way, the time offset error between the master clock and the slave clock is reduced and the accuracy of time synchronization between the slave clock and the master clock is improved. In this embodiment, the symbol may be corrected when the error between the calculated specific position of the specific symbol and the actual specific position of the specific symbol is greater than the subcarrier period, thus improving time synchronization accuracy.

[0053] The previous embodiments shown in Figures 1a to 4c are described assuming that Delay1 is equal to Delay2. If Delay 1 is not equal to Delay2, then the mapping of the relationship between Delay1 and Delay2 should be determined to calculate the offset according to the basic mechanism shown in Fig. 1a and formula (1) and formula (2). This means that the offset should be calculated according to Tm1, Ts1, Ts2, and Tm2 and the mapping relationship between Delay 1 and Delay2. The slave clock then adjusts the local clock time using the offset to synchronize the local clock time with the master clock.

[0054] The mapping relationship between Delay1 and Delay2 in relation to digital subscriber line (DSL) bandwidth transmission is described below.

[0055] DSL technology is a high speed transmission technology that transmits data through a twisted pair cable. DSL bandwidth transmission technology includes an asymmetrical digital subscriber line (ADSL) and a very digital subscriber line

- 12 high speed (VDSL). Various DSL with bandwidth transmission perform modulation and demodulation using DMT modulation technology.

[0056] Fig. 5 is a first schematic diagram showing a DSL bandwidth transmission system in an application scenario in an embodiment of the invention. As shown in Figure 5, the DSL bandwidth transmission system includes a central office complex (CO) and a client room device (CPE). CO and CPE send data through a twisted pair cable. WHAT is on the master clock and CPE is on the slave clock. The CPE clock time needs to be synchronized with the CO clock time.

[0057] CO or CPE may be divided into three sub-layers in a physical medium, namely a transport protocol-dependent convergence sub-layer, a physical-media-dependent TC-sublayer (PMD-TC), and a physical-media-dependent sublayer (PMD). Since the track delay caused by the twisted pair between CO and CPE is small, the two ends of the twisted pair can be used as reference points to read local clock information in ideal circumstances, i.e. to obtain time stamps. However, both ends of the twisted pair cable and the hybrid circuit that is adapted to convert an analog signal into two telephone line signals generally do not support the read and write functions. Thus, in this embodiment, time stamps are obtained on the sublayer near the twisted pair (i.e. the PMD sublayer) so as to reduce the offset error caused by the device delay and improve the accuracy of time synchronization.

[0058] Fig. 6 is a second schematic diagram showing a DSL bandwidth transmission system in an application scenario in an embodiment of the invention. In Fig. 6, for CO and CPE in the DSL system only the PMD sublayer device is illustrated. The PMD CO sublayer device includes the CO digital signal transmitting circuit, the CO analog signal transmitting circuit, the CO digital signal receiving circuit and the CO analog signal receiving circuit. The PMD sublayer device on the CPE includes a CPE digital signal sending circuit, a CPE analog signal sending circuit, a CPE digital signal receiving circuit, and a CPE analog signal receiving circuit. The delay generated by the CO digital signal transmitting circuit, the CO digital signal receiving circuit, the CPE digital signal sending circuit and the CPE digital signal receiving circuit can be obtained directly using existing circuit design information, test method or emulation method. The delays generated by these circuits are called device delay information.

[0059] On the downlink from CO to CPE, the delays generated include the At 1 delay of the CO digital signal transmission circuit, At2 delay of the CO analog signal transmission circuit, At3 delay of the downlink path, At2 'delay of the CPE analog signal receiving circuit and At1' delay of the circuit the digital CPE signal .. At1 and At2 refer to the main unit delay information. At2 'and At1' refer to the slave device delay information, and At3 refers to

- 13 downlink track delay information. In this way, Delay1 meets the following equation:

Delayl = At1 + At2 + At3 + At2 '+ At1' (4) [0060] In the charging link from CPE to CO, the generated delays include the delay AT4 of the digital CO signal receiving circuit, At5 delay of the analog CO signal receiving circuit, delay Δt6 of the link path charging, At5 'delay of the CPE analog signal transmission circuit and At4' delay of the CPE digital signal transmission circuit. At4 and At5 refer to the master device delay information.

At5 'and At4' refer to the slave delay information, and At6 refers to the uplink path delay information. In this way, Delay2 meets the following equation:

Delay2 = At4 + At5 + At6 + At5 '+ At4' (5) [0061] Generally speaking, Delay1 is not equal to Delay2. The difference between Delay1 and Delay2 is usually greater than ^ s, thus significantly affecting the accuracy of time synchronization. In applications, the mapping relationship between Delay1 and Delay2 can be roughly processed, and the functional relationship between Delay1 and Delay2 is determined. E.g,

Delay2 = f (Delay1) (6) [0062] In formula (6), the function f can be a linear or non-linear function. Later, f is changed to a linear function to simplify the calculation of the shift.

[0063] In the course of implementing the invention, the inventor measures and analyzes delays (shown in formula (4)) in Fig. 6 by using a circuit measurement or emulation method. The inventor states the following result: At2 and At5 delays occurring when the CO analog signal transmission circuit and the CO analog signal receiving circuit processing different subcarriers are close to the set value; At2 'and At5' delays occurring when the CPE analog signal transmission circuit and the CPE analog signal receiving circuit processing different subcarriers are close to the set value. By checking the characteristics of the twisted pair cable, the creator finds that the At3 downlink path delay and the At6 downlink path delay of the twisted pair cable have specific relationships at each frequency point. E.g,

Delay (48 ± 16 x 4.3125 kHz) = 1.07 x Delay (96 ± 16 x 4.3125 kHz) (7) [0064] This formula means that the time for sending a neighbor signal 48 x 4.3125 kHz link charging with a twisted pair cable is 1.07 times longer than the time required to send a neighboring signal 96 x 4.3125 kHz.

[0065] Based on the previous analysis, formula (6) can be simplified as follows:

Delay2 = a * Delay1 + b (8) [0066] In formula (8), Delay1 may be the downlink signal delay in a twisted pair cable, and Delay2 may be the uplink signal delay in a twisted pair cable

- 14 two-wire; a and b refer to constant factors whose specific values ​​can be obtained in accordance with the uplink and uplink device delays and the uplink and uplink delay time characteristics.

[0067] If formulas (1), (2) and (8) are combined, the delay can be calculated.

[0068] Alternatively, each time stamp may be pre-adjusted according to the device delay so as to perform time synchronization according to each corrected time stamp. Tm1, Ts1, Ts2, and Tm2 shown in Fig. 6 refer to the time stamps obtained at the accession of the PMD sublayer. In this embodiment, the obtained time stamps can be corrected according to the delay information of the PMD sublayer device so as to obtain corrected time stamps on both sides of the twisted pair cable. For example, the time stamps after taking into account the device delay are as follows:

<td>Tm1 "= Tm1 + AtMt2</td><td> (9)</td>

<td>Ts1 "= Ts1- ^ t1 '+ Δ12')</td><td> (10)</td>

<td>Tm2 "= Tm2 - (Δ14 + Δ15)</td><td> (11)</td>

<td>Ts2 "= Ts2 + (At4 '+ Δ15')</td><td> (12)</td>

[0069] In this case, Delay2 and Delay 1 are equivalent to Delay2 'and Delay 1' at both ends of the twisted pair cable, where Delay2 'and Delay 1' refer to the uplink path delay and the twisted pair download path delay. According to formulas 1, 2, 4, 5 and 9 to 12, the following formulas can be obtained:

Delay2 '= a * Delay 1' (13)

Shift = Ts1 Delay 1 '(14)

Offset = Ts2 "- Tm2" + Delay2 '(15) [0070] In formula (13) a refers to a constant factor whose specific value can be obtained according to the delay time characteristics of the uplink and twisted pair twisted pair. Preferably a can be any value meeting the condition 1 □ a &lt;1.1. The offset can be calculated according to formulas (13) to (15). The CPE clock time can be adjusted according to the offset to synchronize with the CO clock time. In this embodiment, the obtained time stamps are corrected according to the PMD device delay information of the sublayer so that the mapping relationship between the uplink delay and the downlink delay can be simplified as well as the mapping relationship between the uplink track delay and the downlink track delay. In this way, corrected time stamps are obtained at both ends of the twisted pair cable. Thus, the offset error between CO and CPE is reduced, and the time synchronization accuracy is improved.

[0071] Based on the DSL system shown in Fig. 6, the process of correcting time stamps on the download link from CO to CPE and on the loading link from CPE to CO is described below, referring to the method of correcting the symbol and the method of determining

- mapping relationships between the uplink delay and the downlink delay.

1. CO to CPE download link: The CO digital signal transmission circuit reads the CO local time (i.e. acquires Tm1) at the specific position of the symbol; when a specific symbol is sent to the CPE digital signal receiving circuit via a downlink, the CPE digital signal receiving circuit reads the local time CPE (i.e. acquires Ts1 ') at the predetermined specific position of the specific symbol. Then Tm1 and Ts1 'are corrected. This correction process consists of three parts:

(1) Correction of Ts1 'by CPE: CPE corrects Ts1' using the method shown in Fig. 3 or Fig. 4a according to the time offset corresponding to the subcarrier phase difference. In this way, Ts1 is read in the actual specific position of the specific symbol.

(2) Correction of Ts1 by CPE: CPE corrects Ts1 by using the pre-obtained 1111 'and Δ12' according to formula (10). In this way, Ts1 "is obtained on the twisted pair side close to CPE.

(3) Correction of Tm1 by CO: CO corrects Tm1 by using the pre-obtained. \ T1 and Δ £ according to formula (9). In this way, Tm1 "is obtained on the side where the twisted pair cable is close to CO.

Based on the previous description, the following formula can be obtained:

Offset = Ts1 "- Tm1" - Delay 1 * = (Ts1 - (Δ1Γ + Δ12 ')) - (Tm1 + ΔΠ + Δβ) - Delay 1' (16)

2. Charging link from CPE to CO: The digital signal transmission circuit CPE reads the local time CPE (i.e. acquires Ts2) at the specific position of the specified symbol; when a specific symbol is sent to the CO digital signal receiving circuit via the charging link, the CO digital signal receiving circuit reads the CO local time (i.e. acquires Tm2 ') at the pre-calculated specific position of the specific symbol. Then, Ts2 and Tm2 'are corrected. This correction process also includes three parts:

(1) Correction of Tm2 'by CO: CO corrects Tm2' using the method shown in Figure 3 or Figure 4a, according to the time offset corresponding to the subcarrier phase difference. In this way, Tm2 is obtained at the actual specific position of the specific symbol.

(2) Correction of Tm2 by CO: CO corrects Tm2 by using the pre-obtained Δΐ4 and Δΐ: 5 according to formula (11). In this way, Tm2 "is obtained on the twisted pair side close to CO.

(3) Correction of Ts2 by CPE: CPE corrects Ts2 by using the pre-obtained Δ14 'and Δΐ: 5' according to formula (12). In this way, Ts2 "is obtained on the side where the twisted pair cable is close to CPE.

Based on the previous description, the following formula can be obtained:

- 16 Offset = Ts2 "- Tm2" + Delay2 '= (Ts2 + (At4' + At5 ')) - (Tm2 - (At4 + At5)) + Delay2' (17) [0072] Because Delay2 '= a * Delay1 ', you can get offset, Delay1', and Delay2 '. The CPE clock time is adjusted according to the offset to synchronize with the CO clock time.

[0073] In this embodiment, the time stamp is obtained when the PMD sublayer device receives / sends the specific position of the specific symbol; the timestamps obtained by the receiving side are corrected according to the difference of the subcarrier phases on CO and CPE; the mapping relationship between the uplink delay and the downlink delay is simplified; an auxiliary correction is made on the time stamp according to the information about the delay of the PMD sublayer equipment for CO and CPE. In this way, the offset error between CO and CPE is significantly reduced, and the time synchronization accuracy is improved.

[0074] Fig. 7 shows the construction of a time synchronization device in an embodiment of the invention. As shown in Fig. 7, the time synchronization device includes a time stamp receiving module 71 and a time adjustment module 72.

[0075] The timestamp obtaining module 71 is adapted to obtain the master device transmitting time stamp, the slave receiving time stamp, the slave sending time stamp and the master device receiving time stamp. The master transmission time stamp is the clock time of the master clock, which is received by the slave clock and read by the master clock about the transmission time of the predetermined position of the first specific symbol; the time stamp of receiving the slave is the clock time of the slave clock, which is read by the slave clock at the time of receiving the specific position of the first specific symbol; the slave sending time stamp is the clock time of the slave clock, which is read by the slave clock about the transmission time of the specific position of the second specific symbol; and the time stamp of receiving the master device is the clock time of the master clock, which is read by the master clock at the time of receiving the specific position of the second specific symbol.

[0076] Clock time adjustment module 72 is adapted to adjust the clock time of the slave clock according to the obtained time stamps for synchronization with the clock time of the master clock.

[0077] Based on the previous technical solution, optionally the master timestamp for receiving may be corrected by the master clock according to the phase information of the subcarriers that make up the second specific symbol. The time adjustment module 72 may further include a correction time correction unit 721 of the slave receiving time stamp and a first time adjustment assembly 722. The slave receiving time stamp adjustment assembly 721 is adapted to correct the slave receiving time stamp according to the phase information of the subcarriers that make up the first specific symbol. The first time adjustment assembly 722 is adapted

For adjusting the slave clock clock time according to the master device transmission time stamp, slave transmission time stamp, the slave receiving time stamp corrected and the master device receiving corrected time stamp to synchronize with the master clock time.

[0078] Optionally, the correction timing assembly 721 of the slave receiving time stamp is further adapted to: obtaining a phase difference of any of the subcarriers that form the first specific symbol, relative to the specific position of the first specific symbol on the master clock and the slave clock; determining a time offset corresponding to the phase difference; and correcting the slave receiving time stamp according to the time offset. Alternatively, the slave receiving time correction flag correction device 721 is further adapted to: obtain a phase difference of at least two subcarriers that form the first specific symbol, wherein the phase difference is the phase difference of each subcarrier relative to the specific position of the first specific symbol on the master clock and the slave clock; determining the time offsets corresponding to each phase difference; determining the average time offset of all time offsets; and correcting the time stamp [0070] receiving the slave according to the average time offset.

[0079] Optionally, in the previous technical solution, the master device transmission time stamp is the clock time of the master clock that is received by the master PMD device on the master clock with the predefined transmission time of the predetermined position of the first specific symbol; the time stamp of receiving the slave device is the clock time of the slave clock that is read by the PMD device on the slave clock at the time of receiving the specific position of the first specific symbol; the slave sending time stamp is the clock time of the slave clock that is read by the PMD device on the slave clock about the transmission time of the specific position of the second specific symbol; and the time stamp of receiving the master device is the clock time of the master clock, which is read by the PMD device on the master clock at the time of receiving the specific position of the second specific symbol.

[0080] Furthermore, the master device transmitting time stamp and the master device receiving time stamp may be time stamps corresponding to the master clock clock time which is corrected by the master clock according to the pre-obtained PMD master delay information. The time adjustment module 72 may include a track delay determination assembly 723, a slave delay correction assembly 724, and a second time adjustment assembly 725. The track delay determination assembly 723 is adapted to determine the mapping relationship between the master clock and the slave clock and between the uplink track delay and the downlink track delay. The slave delay correction device 724 is adapted to correct the slave sending time stamp and the slave receiving time stamp according to the pre-acquired information about

- 18 delay of slave device PMD slave device on slave clock. The second time adjustment assembly 725 is adapted to adjust the slave clock clock time according to the corrected time stamps and mapping relationship between the uplink path delay and the downlink path delay.

In embodiments of the invention, in communication systems that transmit signals in sets of symbols, a predetermined specific position of a specific symbol is used as a switching edge to obtain time stamp information, and time synchronization is performed between the master clock and the slave clock according to the obtained timestamp information. Thus, time synchronization is performed between the master clock and the slave clock in communication systems that transmit signals continuously in symbol sets. In this embodiment, the specific form of representation of the time synchronization device is not limited. It can be a slave clock device, for example CPE. The mechanism for implementing time synchronization between the master clock and the slave clock has already been illustrated in Figures 1a to 6.

[0082] Fig. 8 shows the structure of another time synchronization device in an embodiment of the invention. As shown in Figure 8, the time synchronization device includes a time stamp receiving module 81 and a time stamp transmitting module 82.

[0083] The time stamp receiving module 81 is adapted to obtain a time stamp of transmitting the master device and a time stamp of receiving the master device. The master device transmission time stamp is the clock time of the master clock, which is read by the master clock about the time of preset transmission of a specific position of the first specific symbol. The master device receiving time stamp is the clock time of the master clock, which is read by the master clock at the time of receiving the predetermined position of the second specific symbol.

[0084] The timestamp sending module 82 is adapted to send the master time broadcast timestamp and the master time receive timestamp to the slave clock, whereby the slave clock adjusts the slave clock clock time to synchronize it with the master clock time.

[0085] Based on the previous technical solution, the timestamp sending module 82 may further include a timestamp receiving correction unit 821 and a timestamp sending assembly 822. Thus, timestamp sending assembly 822 is adapted to transmit the master device transmission time stamp and the master device corrected timestamp.

[0086] Optionally, the master receiving time correction marker 821 is further adapted to: obtain a phase difference of any of the subcarriers relative to a specific position of the second specific symbol on the master clock and the slave clock; determining a time offset corresponding to the phase difference; and correcting the receiving time stamp of the main unit according to the time offset. Alternatively, the master unit timestamp correction unit 821 is

19 further adapted to: obtaining a phase difference of at least two subcarriers, wherein the phase differences are the phase differences of each subcarrier relative to a specific position of the second specific symbol on the master clock and the slave clock; determining the time offsets corresponding to each phase difference; determining the average time offset of all time offsets; and correcting the receiving time stamp of the main unit according to the average time offset.

[0087] Optionally, the master device transmission time stamp is the clock time of the master clock, which is read by the master device PMD on the master clock at the time of transmitting the specific position of the first specific symbol. The master device receiving time stamp is the clock time of the master clock that is read by the PMD device on the master clock at the time of receiving the specific position of the second specific symbol.

[0088] Furthermore, the time stamp transmitting module 82 may include a main device delay correction assembly 823. The master device delay correction assembly 823 may be adapted to correct the master device transmitting time stamp and the master device receiving time stamp according to the pre-acquired PMD master device information about the master device delay. Thus, the timestamp sending assembly 822 is further adapted to transmit the master device transmission timestamp and the master device receiving timestamp corrected by the master device delay correction unit 823.

[0089] In this embodiment, in communications systems that transmit signals in symbol sets, a predetermined specific position of a specific symbol is used as a trigger edge to obtain time stamp information, when a specific position of a specific symbol is reached, the action of reading the time stamp is triggered, and the read time stamp is sent to the slave clock, so that the slave clock synchronizes with the time of the master clock. Thus, in communication systems that transmit signals continuously in symbol sets, time synchronization is performed between the master clock and the slave clock. In this embodiment, the specific form of representation of the time synchronization device is not limited. It can be a master clock device, for example CO. The mechanism for implementing time synchronization between the master clock and the slave clock has already been illustrated in Figures 1a to 6.

[0090] Fig. 9 shows the structure of a time synchronization system in an embodiment of the invention. As shown in Fig. 9, the time synchronization system includes a master clock device 91 and a slave clock device 92.

[0091] The master clock device 91 is adapted to: obtain a master device transmit time stamp and a master device receive time stamp, and send a master device transmit time stamp and a master device receive time stamp to the slave clock device 92.

[0092] The slave clock device 92 is adapted to: obtain the mark

- master device transmission time, slave receiving time stamp, slave sending time stamp and master device receiving time stamp, and controlling the slave clock time according to the obtained time stamps to synchronize with the master clock time.

[0093] In the previous technical solution, the master time broadcasting stamp is the clock time of the master clock, which is read by the master clock device at the time of transmitting the predetermined position of the first specific symbol; the time stamp of receiving the slave device is the clock time of the slave clock, which is read by the slave clock device at the time of receiving the specific position of the first specific symbol; the slave sending time stamp is the clock time of the slave clock, which is read by the slave clock device about the transmission time of the specific position of the second specific symbol; and the time stamp of receiving the master device is the clock time of the master clock, which is read by the master clock device at the time of receiving the specific position of the second specific symbol.

[0094] In the time synchronization system in this embodiment, the predetermined specific symbol position is used as the trigger edge for obtaining timestamp information, when the specified symbol position is reached, the act of reading the timestamp is triggered, and the read timestamp is sent to the slave clock, thanks to which the slave clock synchronizes with the time of the master clock. Thus, in systems that transmit signals continuously in symbol sets, time synchronization is performed between the master clock and the slave clock. Fig. 8 shows a detailed structure of the master clock device in an embodiment of the invention. Fig. 7 shows a detailed structure of a slave clock device in an embodiment of the invention. The mechanism for implementing synchronization between the master clock and the slave clock through the interactions between the master clock device and the slave clock device has already been illustrated in Figures 1a to Fig. 6 [0095] Those skilled in the art should understand that the accompanying drawings are merely schematic views of preferred embodiments , and the modules or processes in the accompanying drawings are not mandatory in carrying out the invention.

[0096] Furthermore, the modules in the device in embodiments of the invention may be distributed in the manner described herein, or distributed in other ways, for example in one or more apparatus of other embodiments. The modules in the previous embodiments can be combined into one or divided into several component modules.

[0097] The serial number of the embodiments given above is for the sake of clarity only, but is not the preferred order.

[0098] It will be understood by those skilled in the art that all or part of the steps of the method according to embodiments of the invention may be implemented by a program issuing instructions to the relevant equipment. This program can be stored in readable by

- 21 computer storage medium. When the program is running, steps of the method according to embodiments of the invention are performed. The storage medium can be in the form of read-only memory (ROM), random access memory (RAM), magnetic disk, or read-only compact disk (CD-ROM).

[0099] It should be noted that the above embodiments are provided only for developing the technical solution of the invention, but are not intended to limit the invention. Although the invention has been described in detail with respect to previous embodiments, it is obvious that those skilled in the art may make modifications to the technical solutions described in the above embodiments, or may make equivalent exchanges of certain technical functions without causing the nature of the corresponding technical solutions to deviate from the scope embodiments of the invention.

Prepared and verified

Grażyna Palka

Patent Attorney