Device and the method for generating scrambling code in the UMTS mobile communication system

Description of the invention

Field of the Invention

The present invention relates generally to a device for generating encryption codes in a mobile communication system, and in particular to a device for generating multiple encryption codes using masking codes.

Background of the invention

A multiple-access mobile communications system with code distribution (hereinafter referred to as the "CDMA system") uses encryption codes to separate base stations. The European W-CDMA, UMTS (Universal Mobile Telecommunications System) system generates multiple encryption codes classified as a group of encryption codes with a predetermined length. A method of increasing capacity in addition to separating base stations, which is the purpose of using encryption codes in the CDMA system, is to use orthogonal encryption codes for many groups of encryption codes to separate channels. This means that if all orthogonal codes are used to separate channels for a given group of scrambling codes, the mobile communication system may use a second group of scrambling codes to increase the number of available communication links. The UTMS mobile communication system uses the Gold string 218-1 as encryption codes to receive multiple encryption codes (one primary encryption code and multiple secondary encryption codes in one base station) consisting of multiple groups of encryption codes. The 218-1 Gold string contains a group of 218-1 separate Gold codes. Gold sequences of the same group are characterized by good mutual correlation. Here, the Gold string with a length of 218-1 is divided into 38400 bits (chips) and is repeatedly used for encryption.

Each base station in the UMTS mobile communication system has a unique encryption code called the "main encryption code", which is used to allow terminals to distinguish one base station from others operating in the system. Also, each unique encryption code used to spread (encrypt) the downlink signals of each base station is called the "master encryption code," and one of the groups of encryption codes used to scatter downlink data channels when orthogonal codes are unavailable is called "secondary encryption code". The base station uses its unique main encryption codes to scatter (encrypt) common control channel signals sent to all mobile stations with the appropriate orthogonal code, to scatter (encrypt) data channel signals sent to currently communicating mobile stations with the appropriate orthogonal codes, which are assigned each data channel signal for separating downlink channels. The base station has its unique main encryption codes so that the mobile station can distinguish it from neighboring base stations. The number of main encryption codes must be sufficiently large, e.g. at least 512, that the mobile station can simultaneously detect signals from base stations sharing the same encryption codes. In this way, the individual neighbor base stations use different primary encryption codes among the 512 primary encryption codes. When there are no more orthogonal codes with the main scrambling code allocated to channel separation, then the individual base stations use the secondary scrambling code selected from its many groups of secondary scrambling codes corresponding to the used primary scrambling codes.

An example of a system using multiple encryption codes is a downlink in a UTMS system. It should be noted that for purposes of illustration, the term "encryption code" is interchangeable with the term "Gold code" or "Gold string" indicating the same encryption code.

Figure 1 is a block diagram of a downlink transmitter structure in a UTMS mobile communication system.

As shown in Figure 1, after receiving the DPCCH dedicated physical control channel and the DPDCH1, ... and DPDCHn dedicated physical data channels, which have previously been channel coded and interlaced, 100-104 demultiplexers (whose number corresponds to the number of physical data channels N plus one for DPCCH) divide the DPCCH dedicated physical control channel and the DPDCH1, ... and DPDCHN dedicated physical data channels into I (co-phase) and Q (trench square). Channels I and Q derived separately from demultiplexer 101 are fed to multipliers 110 and 111. Multipliers 110 and 111 multiply channels I and Q with orthogonal code 1 for channel separation and send the output signal to scrambler 120. Similarly, channels I and Q derived separately from 102-104 demultiplexers are subjected to the same operation

As above and N to the scrambler systems 124-128 are supplied. Then, the scramble code group generator 100 generates secondary scrambling codes corresponding to the scramblers 120, 124-128 and outputs them to the appropriate scramblers. Here, the scramblers 120, 124-128 multiply the output signals of the respective multipliers with the output signals of the generator 100 of the group of scrambling codes in the combined mode to output the real parts of the encrypted signals to the adder 130 and the imaginary parts of the encrypted signals to the adder 135. The adder 130 sums the real parts of the encrypted signals from scramblers 120, 124-128, while adder 135 sums up imaginary parts.

Fig. 2 shows a block diagram of a cipher code group generator 100 of Fig. 1, which simultaneously generates a plurality of cipher code groups.

Although the fact is that only the main encryption codes are to be used for the common control channel and data channels, secondary encryption codes can be used instead of the main encryption codes to increase the number of available communication links. If e.g. base station A uses the main encryption code with available orthogonal CH codes, and all the other orthogonal CH codes have been allocated to different channels, then there are no more codes available that could be assigned to new channels if the new terminal wants to communicate with base station A . In this case, instead of using the main encryption code A, the secondary Z encryption code can be used for new channels and the orthogonal CH codes can then be assigned to new channels, because the new channels use the secondary Z encryption code instead of the main A encryption code. the channels can be distinguished from the initial channels using orthogonal CH codes, because the new channels use the secondary Z encryption code instead of the main A encryption code. Therefore, the base station must be able to generate multiple groups of encryption codes.

The normal group 100 of encryption codes shown in FIG. 2 includes a plurality of Gold string generators 201 and a plurality of delay elements 203 corresponding to the Gold string generators 201. After receiving control information about the encryption codes for multiple channels from the upper layer, the Gold string generator 201 generates encryption codes, i.e. Golda code sequences based on control information, and outputs the generated encryption codes in such a way that they contain the I channel component. Delay elements 203 delay the encryption codes with the I component by a predetermined number of bits (chips) and generate the delayed encryption codes with the Q channel component.

Figure 3 is a block diagram of a downlink receiver structure in a UMTS communication system. In the case of common downlink control channels, the receiver is designed to decrypt common downlink control signals that have been encrypted with the main encryption codes. At the same time, for downlink data channels, the receiver is also intended to decrypt signals encrypted with secondary encryption codes when the downlink data channels use the secondary encryption code. Therefore, the receiver must be able to generate multiple encryption codes.

As shown in Fig. 3, after receiving signals from the transmitter, as shown in Figs. 1 and 2, the components of channels I and Q are fed to deskramblers 310 and 315, respectively. The group 300 encryption code generator simultaneously generates encryption codes corresponding to the given channels and outputs them on 310 and 315 deskramblers. Then, deskramblers 310 and 315 multiply the received I + jQ signals by the signals of the coupled scramble codes received from the generator of 300 groups of scramble codes to decrypt the received signals, and then derive the channel components I and Q of the decrypted signals on the respective multipliers 320, 322, 324 and 326. Here, the orthogonal codes allocated to the respective channels are concentrated in multipliers 320, 322, 324 and 326 and output to the appropriate demultiplexers 330 and 350. The demultiplexers 330 and 350 demultiplex the concentrated components of channel I and Q.

Fig. 4 is a block diagram of the scramble code group generator 300 of Fig. 3, which simultaneously generates multiple scramble code groups. Although the encryption group generator 300 is actually intended to primarily use primary encryption codes for common control channels, it can also use secondary encryption codes for channels depending on users, such as data channels, in the absence of orthogonal codes available. Thus, the mobile station must be able to generate multiple groups of encryption codes.

In the situation shown in Fig. 4, the scramble code group generator 300 in the receiver includes a plurality of Gold string generators 401 and a plurality of delay elements corresponding to the Gold string generators 401. After receiving control information about the encryption codes for many

In the upper layer channels, Golda generator 401 generates encryption codes corresponding to control information and outputs the generated encryption codes in such a way as to contain the I channel component. The delay elements 403 delay the encryption codes with the I component by a predetermined number of bits ( chips) and generate delayed encryption codes with a Q channel component.

Fig. 5 is a block diagram of the structure of Gold's string generators in Figs. 2 and 4.

Figure 5 shows that the Gold string is usually generated by binary addition of two separate m-strings. The shift register generating the upper m-string is implemented in the form of a polynomial generator defined as f (x) = x¹⁸x +⁷+1, and the shift register generating the lower m-string is implemented in the form of a polynomial generator defined as f (x) = x¹⁸x +¹⁰x +⁷x +⁵+1.

In the current description of the UMTS standard there is no description of the numbering of encryption codes and their generation. Therefore, in light of the UMTS standard description, the transmitter and receiver require multiple encryption code generators as described above, used to generate multiple encryption codes and thus use many separate generators for individual encryption codes, which leads to greater complexity of the systems. Also, when using Gold strings as encryption codes, the complexity of the systems may depend on how the encryption codes are divided into primary and secondary encryption codes, and how the encryption codes are numbered.

Brief description of the invention

Therefore, the object of this invention is to provide a device for generating encryption codes grouped into units of a predetermined length using masking functions, which allows the complexity of the systems to be minimized.

Another object of the present invention is to provide a device for generating encryption codes including the primary encryption code and the associated secondary encryption code to be used instead of the primary encryption code to increase the number of available communication links. Encryption codes are generated using masking functions. Yet another object of the present invention is to provide a device for generating the primary encryption code and associated secondary encryption codes. In an embodiment of the present invention, the first shift register is used to generate the first m-train and the second shift register is used to generate the second m-train. The first m-string is added to the second m-string to generate the main encryption code. In order to generate the associated secondary encryption codes, the bits of the first shift register are introduced into N masking sections, which use masking functions to cyclically shift the first m-string. The outputs of each masking section are added to the second m-string to generate N secondary encryption codes.

To achieve the above-mentioned objectives of the present invention, there is provided a data transmission device in a mobile communication system that includes a splitter in the form of a multiplier configured to split a data signal with at least one orthogonal code, an encryption code generator configured to generate the K-th main encryption code or conditionally to generate a secondary encryption code of the Kth primary encryption code; and a scrambler configured to encrypt the split data signal using one of the primary encryption code and the secondary encryption code, which data transmission device in the mobile communication system is distinguished by the fact that the encryption code generator has been configured to generate ((K-1) * M + K) -th Gold code as the K-th main encryption code by adding (((K-1) * M + K) -1) -shifted shifted first m-string and second m-string, or conditionally to generate at least one of ((K-1) * M + K + 1) -th to (K * -M + K) -th Gold code as the secondary encryption code of the K-th main encryption code. K is a natural number and M is the total number of secondary scrambling codes per one primary scrambling code. K is the number of the main encryption code and satisfies the relationship 1 <K <512. The data transmission device further includes means for shifting at least one of the primary scrambling code or secondary scrambling code by a fixed number of bits to form a Q channel component. The encryption code generator includes: a first m-string generator for generating the first m-string by using a series of first registers with the values ​​of a and the first shift register, where i = 0 to c-1, ac is the total number of first registers; a second m-train generator for generating the second m-train by using a series of second registers with the bj values ​​of the second shift register, where j = 0 to c-1, ac is the total number of second registers; at least one masking section for masking the value of ai of the first shift register by means of a first set of mask values ​​of Ki for generating a third m-string, where i = 0 to c-1; and at least one adder

For adding the first m-string and the second m-string to generate the main scrambling code, or for summing the third m-string and the second m-string to generate the secondary scrambling code. The masking section shifts the first m-string L times to generate the L-th secondary scramble code associated with the primary scramble code. L satisfies the relationship 1 <L <M, where M is the total number of secondary scrambling codes per primary scrambling code. The masking section is described by the expression Σ (Κϊ x ai). The apparatus for receiving data in a mobile communication system includes an encryption code generator configured to generate the Kth main code or conditionally to generate a secondary encryption code of the Kth main encryption code; and a deskrambler configured to decrypt the received data signal with one of the primary encryption code or at least one secondary encryption code; and a connector in the form of a multiplier for combining the decrypted data signal with at least one orthogonal code, where K is a natural number and M is the total number of secondary scrambling codes per one primary scrambling code. K is the number of the main encryption code and 1 <K <512. The data receiving device further includes means for shifting at least one of the primary scrambling code and the secondary scrambling code by a fixed number of bits to form a Q channel component. The encryption code generator includes a first m-string generator for generating the first m-string by using a series of first registers with the values ​​of a and the first shift register, where i = 0 to c-1, ac is the total number of first registers; a second m-train generator for generating the second m-train by using a series of second registers with the bj values ​​of the second shift register, where j = 0 to c-1, ac is the total number of second registers; at least one masking section for masking the value of ai of the first shift register by means of a first set of mask values ​​of Ki for generating a third m-string, where i = 0 to c-1; and at least one adder to sum the first m-string and the second m-string to generate the main scrambling code or to add the third m-string and the second m-string to generate the secondary scrambling code, wherein the masking section shifts the first m-string L times to generate the L-th secondary encryption code associated with the primary encryption code. L satisfies the relationship that 1 <L <M, where M is the total number of secondary scrambling codes for each primary scrambling code. The masking section is described by the expression Σ (Κ x ai).

Brief description of the figures

The above-mentioned and other purposes as well as the features and advantages of the present invention will become more apparent upon reading the following detailed description in connection with the accompanying drawings, of which:

Fig. 1 is a block diagram illustrating the structure of a known downlink transmitter in a general UTMS mobile communication system;

Fig. 2 is a block diagram illustrating the known cipher code group generator of Fig. 1;

Fig. 3 is a block diagram illustrating the structure of a known downlink receiver in a general UMTS mobile communication system;

Fig. 4 is a block diagram illustrating the structure of the known cipher code group generator of Fig. 3;

Fig. 5 is a detailed block diagram showing the structure of the known Golda string group generator in the general UMTS mobile communication system;

Fig. 6 is a block diagram illustrating the structure of the encryption code according to the first aspect of the present invention;

Fig. 7 is a detailed block diagram showing the structure of a cipher code group generator in a downlink transmitter in a UMTS mobile communication system in accordance with the first embodiment of the present invention;

Fig. 8 is a detailed block diagram showing the structure of a cipher code group generator in a downlink receiver in a UMTS mobile communication system in accordance with the first embodiment of the present invention;

Fig. 9 is a diagram showing the structure of the encryption code according to the second aspect of the present invention;

Fig. 10 is a detailed block diagram showing the structure of a cipher code group generator in a downlink transmitter in a UMTS mobile communication system in accordance with a second embodiment of the present invention; and

PL 234 297 B1

Fig. 11 is a detailed block diagram showing the structure of an encryption group generator in a downlink receiver in a UMTS mobile communication system in accordance with a second embodiment of the present invention.

A detailed description of the preferred embodiments

A preferred embodiment of the present invention will be described below with reference to the attached figures. In the following description, well-known functions and constructions will not be described in detail, as they would unnecessarily obscure the picture of the invention.

The Gold string used here as the encryption code is generated by binary adding two different m-strings. Assuming that the strings, both with length L, are defined as m 1 (t) and m2 (t), the set of Gold strings may contain L different Gold strings with good mutual correlation characteristics. The set of Gold strings can be expressed by equation 1.

[Equation 1]

G = <mi (t + T) + m2 (t) I 0 <t <L-1>, where t is the number of the time variable and τ the offset value. As follows from Equation 1, the set of Gold strings is the set of all strings containing the sum of m-string m1 (t) cyclically shifted τ times and m-string m2 (t). Thus, for the purposes of the present invention, the sum of m-string m1 (t) cyclically shifted τ times and m-string m2 (t) will be called the Gold string g- This means that g ^ t) = m1 (t + ^ + m2 (t) If the Gold period is 2¹⁸-1, then individual m-sequences constituting Gold's sequence also have a period equal to 2¹⁸-1. Thus, m-string m1 (t) can be shifted cyclically a maximum of 2¹⁸-1 times and the number of elements in the Gold string set is equal to 2¹⁸-1, which is the maximum value of cyclic shifts.

The set of Gold strings used in the embodiment of the present invention comprises 2¹⁸-1 Gold strings, each containing m-string m1 (t) with a generating polynomial defined as f (x) = x¹⁸x +⁷+1 and m-string m2 (t) with a generating polynomial defined as f (x) = x¹⁸x +¹⁰x +⁷x +⁵+1.

The second m-string m1 (t) cyclically shifted τ can be obtained by applying masking functions to the stored values ​​of the shift register generating the initial m-string.

An embodiment of the present invention provides a generator for the simultaneous generation of multiple Gold strings using masking functions and a method for effectively dividing a set of Gold strings into a set of main encryption strings and a set of secondary encryption strings to reduce the number of masking functions stored in memory.

The first embodiment

Fig. 6 is a diagram showing the structure of the primary and secondary encryption code according to the first embodiment of the invention.

First, after choosing Gold from among 2¹⁸-1 Gold strings, the first 38400 bits (chips) are used as the main encryption string, the second 38400 bits (chips) as the first secondary encryption code corresponding to the main encryption code, the third 38400 bits (chips) as the second secondary encryption code corresponding to the main encryption code, fourth 38400 bits (chips) as the third secondary encryption code corresponding to the main encryption code, fifth 38400 bits (chips) as the fourth secondary encryption code corresponding to the main encryption code, sixth 38400 bits (chips) as the fifth secondary encryption code corresponding to the main encryption code. In this case, when 512 primary encryption codes are used, there are 5 groups of secondary encryption codes corresponding to the 512 primary encryption codes. In particular 2¹⁸-1 (the length of the encryption codes) divided by 38400 is equal to six (groups of encryption codes). Of these six groups of scrambling codes, the first group of scrambling codes is used as the main scrambling codes, and the other five groups of scrambling codes are used as secondary scrambling codes. In this structure, if the cell (base station) uses its own primary encryption code and secondary encryption codes selected from its own group of secondary encryption codes, then the selected secondary encryption codes belonging to the group of secondary encryption codes corresponding to the main encryption code will be used for the channel encryption codes downlinks when orthogonal codes with the main encryption code are missing. As shown in fig. 6, after selecting the primary encryption code, the secondary encryption codes corresponding to the primary encryption code are also part of the Gold string, which also contains the primary encryption code. Here, secondary encryption codes are generated by applying masking functions to the primary encryption code. This method was used in the transmitter group encryption code generator shown in Fig. 7, which simultaneously generates one primary encryption code and multiple secondary encryption codes.

In the situation shown in Figure 7, the scramble code group generator 701 includes a first m-string generator 750 comprising: an upper shift register memory (hereinafter referred to as "memory

First shift register ") 700 (with registers from 0 to 17), and adder 730, and a second m-string generator 760, including the lower shift register memory (hereinafter referred to as" second shift register memory ") 705 (with registers from 0 to 17) and adder 735, set of masking sections 710 to 712, 714 to 716, set of adders 742 to 744 and 740, and delay elements 722 to 724 and 720. Memory 700 of the first shift register stores the determined initial register value "a0" and memory 705 of the second shift register stores the determined initial register value "b0". The values ​​stored in each of the registers in memory 700 and memory 705 may change in each period of the input clock (not shown in the figure). The register memory 700 and 705 stores the binary values ​​(or symbol) respectively "ai" and "bi" in the form of 18 bits (i = 0 to c-1, where c = the total number of registers in the register memories 700 and 705).

Generator 750 of the first m-string generates the first m-string using register memory 700 and adder 730, which is a binary adder that adds binary values ​​from registers 0 and 7 of register memory 700 and outputs the sum to register 17. Register 0 of register memory 700 sequentially outputs values binary forming the first m-string during each period of the input clock. Masking sections 710 to 712 store values ​​(k1 and k^Ni) mask codes for generating cyclic shifts of the first m-string with a predetermined number of bits (chips). Cyclic shifts are obtained by multiplying the values ​​of masking codes with the values ​​"ai" of the memory register 700 of the first shift register, as expressed in the following equation: Z (k^Land χ ai) (L = 1 to N). The calculated values ​​are given on adders 742 to 744.

The second m-generator 760 generates the second m-string using register memory 705 and adder 735, which is a binary adder that adds binary values ​​from registers 0, 5, 7 and 10 of register memory 705 and outputs the sum to register 17. Register 0 register memory 705 sequentially outputs binary values ​​forming a second m-string during each input clock period. Masking sections 714 to 716 store values ​​(pp¹and to p^Ni) mask codes for generating cyclic shifts of the second m-string with a predetermined number of bits (chips). Cyclic shifts are obtained by multiplying the values ​​of the masking codes with the "bi" values ​​of the memory register 705 of the second shift register. The calculated values ​​are given on adders 742 to 744. Each of the 750 and 760 m-string generators generates a m-string according to the generating polynomial.

Adder 740 sums the values ​​of the zero register (i.e. last bits) of the first and second shift registers 700 and 705 to generate an encryption code, which becomes the main encryption code. Adders 742 to 744 add one bit generated by each of the masking sections 710 to 712 connected to memory 700 of the first shift register to one bit generated by the masking sections 714 to 716 corresponding to the masking sections 710 to 712 respectively. In other words, the output from the first masking section 710 from the first group is added together with the output from the first masking section 714 of the second group etc. until the output from the Nth masking section 712 from the first group is added to the output from the Nth masking section 716 from the second group. Thus, each of the masking sections 710-712 in the first group has a corresponding masking section in sections 714-716 of the second group. The outputs from the respective masking sections are added together in adders 742-744. This means that the individual masking sections have their one-to-one couplings relative to the 700 and 705 memories of the first and second shift registers. For example, the first masking section 710 of the first shift register memory 700 corresponds to the first masking section 714 of the second shift register memory 705, the Nth masking section 712 corresponding to the Nth masking section 716 etc. Between two coupled masking sections (i.e. first masking sections 710 and 714 or Nth masking sections 712 and 716), combiner 742 to 744 is included, which sums both output bits from the masking sections in response to the input clock signal. Here, the output signals of adders 742 to 744 have an I channel component.

Delay elements 722 to 724 and 720 are delayed by channel I signals with a predetermined number of bits (chips) to generate the corresponding Q channel signals.

A description of the operation of the invention constructed according to the above description will now be given.

After entering the initial value for the main encryption code into the 700 and 705 memories of the first and second shift registers, each of which has 18 registers for cyclically shifting the "ai" or "bi" values ​​of the register, values ​​of zero memory registers 700 and 705 of the first and second shift registers are fed to the adder 740 and 18 values ​​of "ai" of memory register 700 of the first shift register are fed to the first to the Nth masking section 710 to 712 to generate cyclically shifted sequences of the first registers sliding. Including

During the 18 values ​​of the "bi" register value of memory 705 of the second shift register, it is brought to the first to the Nth masking section 714 to 716 to generate cyclically shifted sequences of the first shift registers. Then the first masking section 710 masks the input values ​​from memory 700 (upper) of the first shift register (all 18 bits from 18 registers in the shift register memory 700) by masking function k¹ (i.e. Z (k1i x ai)) and outputs the masked values ​​to the combiner 744 to generate the first secondary encryption code. Masking is simultaneously processed in all masking sections 710-712. The Nth masking section 712 masks the input values ​​from the first (upper) shift registers using the masking function k^Nand (i.e. Z (k^Nix ai)) and outputs masked values ​​to the combiner 742 to generate the Nth secondary encryption code. The Nth masking section 716 masks the input values ​​from the second (lower) shift registers using the masking function s^Nand (i.e. Z (p^Nix ai)) and outputs masked values ​​to the combiner 744 to generate the Nth secondary encryption code. The first masking section 714 masks the input values ​​from register memory 705 using the masking function s¹and (i.e. Σ (β¹ί x ai)) and outputs the obtained values ​​to the adder 742 to generate the first secondary encryption code. Each of the masking sections 710-712 masks the input values ​​from the memory 700 of the first shift register and outputs the masked values ​​to the respective combiners 742-744. Then, adder 740 sums the output bits of the zero registers of the first and second shift registers 700 and 705. These generated output signals are immediately delayed at delay element 720. Adder 744 sums the output bits from the Nth masking sections 712 and 716 to generate channel I signals that are immediately fed to delay element 724. Delay element 722 delays channel signals I output from the 744 adder with a predetermined number of bits (chips) to generate the Q channel scrambling signals. Adder 742 sums the output bits from the first masking sections 710 and 714 to generate channel I signals. These channel I signals are immediately delayed by a predetermined number of bits (chips) in delay element 722. Next, the values ​​of the zero register and the 7th memory 700 of the first shift register in adder 730 are added and the sum values ​​are brought to the seventeenth register input, while the values ​​on the left shift to the right by one, and the leftmost register fills up again with the value derived from adder 730. The values ​​of the zero, fifth, seventh and tenth memories of the 705 second shift register are added together in the 735 adder and the sum value is brought to the seventeenth register input, while the values ​​on the left shift to the right by one position and the extreme left register (i.e. register seventeenth) is filled with a value derived from adder 735. This procedure is repeated to generate multiple cipher codes.

Fig. 8 shows a receiver encryption code generator for simultaneously generating one primary encryption code and one secondary encryption code. The receiver is only to use the encryption codes for the common control channel and the data channel and therefore needs one primary encryption code and one secondary encryption code.

As shown in Fig. 8, after providing the initial value for the main encryption code to memory 840 of the first shift register having 18 upper shift registers and memory 845 of the second shift register with 18 lower shift registers, values ​​of the zero register of memory 840 and 845 of the first and second shift registers is fed to adder 810. At the output of adder 810 is the main encryption code. 18 register values ​​"ai" of memory 840 of the first shift register are fed to the masking section 820. During this time, 18 values ​​of "bi" of memory register 845 of the second shift register are fed to the masking section 825. Then masking section 820 masks the input values ​​of the first shift register with a masking function ki (i.e. Σ (Κ x ai)) and outputs the masked values ​​to adder 815 to generate the first secondary encryption code. The masking section 825 masks the input values ​​from the second (lower) shift register using the masking function si (i.e. tzn (βί x ai)) and outputs the masked values ​​to adder 815 to generate a secondary encryption code. Then, adder 810 sums the output bits of the zero memory registers 800 and 805 of the first and second shift registers to generate the main I scramble code signals. These generated I-channel master scramble signals are immediately delayed with a predetermined number of bits (chips) in delay element 830 to generate the Q-channel master scramble signals. Adder 815 sums the output bits from masking sections 820 and 825 to generate master-code signals encryptor for channel I, which is immediately delayed in delay element 835. Next, zero register values ​​are added

And the first 7 shift registers in adder 800 and the sum values ​​are brought to the seventeenth register input, while the values ​​on the left are shifted to the right by one. The values ​​of the zero, fifth, seventh and tenth register of the second shift registers are added together in the 805 adder and the sum value is given to the seventeenth register input, while the values ​​on the left are shifted to the right by one position. This procedure is repeated to generate multiple encryption codes.

The encryption code generator according to the first embodiment requires a number of separate masking functions stored in the masking sections to generate each secondary encryption code, i.e. it uses 2N masking functions to generate N encryption codes. Accordingly, the structure of the primary and secondary encryption codes shown in Fig. 6 allows the use of the encryption code generator of the transceiver structures shown in Fig. 7 or 8, which furthermore contains only 2N masking functions with a relatively low complexity of circuits and generates many encryption codes.

Second embodiment

Figure 9 shows the structure of the primary and secondary encryption codes according to the second embodiment of the present invention. While the first form masks both m-string m1 (t) and m-string m2 (t) to generate scrambling codes, the second embodiment includes only m-string other than m1 (1) cyclical shifting of m-string m2 ( t) for generating encryption strings. That is, this embodiment is well expressed in Equation 1.

Fig. 9 shows that when M secondary scrambling codes correspond to one primary scrambling code, then the first, (M + 2) -th, (2M + 3) -th, ((K-1) * M + K )-you,...

and (511M + 512) -th Gold strings are used as the main encryption codes. Secondary encryption codes corresponding to ((K-1) * M + K) -th Gold string used as (K) -th main encryption string consists of M Gold strings, i.e. ((K-1) * M + (K + 1 )), ((K-1) * M + (K + 2)), ... and (K * M + K) -th Gold sequence. In this case, using the 512 primary encryption strings, each of the collections of secondary encryption codes corresponding to the 512 primary encryption codes consists of M secondary encryption codes. With this structure, if the cell uses one of the primary scrambling codes, then the secondary scrambling codes belonging to the group of secondary scrambling codes corresponding to the primary scrambling code will be used when it is necessary to use secondary scrambling codes. As shown in fig. 9, after selecting the main scrambling code, secondary scrambling codes corresponding to the main scrambling code are generated by adding cyclically shifted first m-strings and the second m-string. Here, secondary encryption codes are generated by applying masking functions to strings in the memory of the first shift register. This method is used in the encoder code generator of the transmitter shown in Fig. 10, which simultaneously generates one primary encryption code and multiple secondary encryption codes.

In the situation shown in Fig. 10, the first m-string generator 1050 includes memory 1040 of the first shift register (with registers from 0 to 17) and the totalizer 1010 for summing the outputs of registers 0 and 7. The second m-string generator 1060 contains memory of the second register shift (with registers from 0 to 17) and adder 1015 to sum the outputs of registers 0, 5, 7 and 10. The encryption code generator shown in Fig. 10 contains two generators 1050 and 1060 m-strings, masking sections 1000 to 1005, adders 1032 to 1034 and 1030, delay elements 1022 to 1024 and 1020. Memory 1040 of the first shift register stores a predefined initial value "a0", while memory 1045 the shift register stores the predetermined initial value "b0". The 1040 and 1045 shift register memories can store 18 binary values ​​(bits or symbols) "ai" and "bi" (0 <and <17). Both m-string generators 1050 and 1060 generate in series in each clock pulse clock (which is not shown in the drawing) the corresponding output bits according to their generating polynomials. In a second embodiment of the present invention, a Gold string of 38 400 symbols is used to generate encryption codes. In this way, the 1040 and 1045 shift registers memories can be reset to their initial value when each of the 1040 and 1045 shift registers outputs a 38400 symbol string. The first m-string generator 1050 generates the first m-string using register memory 1040 and adder 1010, which is a binary adder that adds binary values ​​from registers 0 and 7 of register memory 1040 and outputs the sum to register 17. Register 0 of register memory 1040 sequentially outputs binary values ​​forming the first m-string during each period of the input clock. Masking sections 1000 to 1005 store mask code values ​​(k1 and k^Ni) to generate cyclic shifts of the first m-string with a predetermined number of bits (chips). Switchable

Cyclic glides are obtained by multiplying the values ​​of the masking codes with the values ​​"ai" of the memory register 1040 of the first register, as expressed in the following equation: Z (k^Land χ ai). The calculated values ​​are fed to adders 1032 to 1034. In a preferred embodiment of the present invention, each of the mask code values ​​(k¹ to k^Ni) creates a new string, which is the first m-string cyclically shifted from 1 to N times. In this way, each mask code value is determined by the desired number of cyclic shifts.

Adder 1030 sums the values ​​of the zero register (i.e., last bits) of memory 1040 and 1045 of the first and second shift registers to generate an encryption code, which becomes the main encryption code. Adders 1032 to 1034 add one bit generated by each of the masking sections 1000 to 1005 to one bit generated by memory 1045 of the second shift register to generate the channel I encryption code signals. The output of adder 1030 is used here as the primary encryption code, and the output of the encryption codes from adders 1032 to 1034 can be used as secondary encryption codes corresponding to the main encryption code. An example of possible mask values ​​(k1i to kⁿi): k¹ = (000000000000000010), k²i = (000000000000000100), k³i = (0000000000000001000), ... By controlling the mask values, other main and secondary codes can be generated. The following example shows how to get the mask code needed to cyclically shift the m-string "n" times. In general, x should be dividedⁿ by the generator polynomial for m-series (i.e. xⁿ/ f (x) and use the rest of the division to create the mask code. For example, if a 31-digit mask code is desired, take x³¹ and divide them by the polynomial that generates f (x) = x¹⁸x +⁷+1, calculate the remainder that cannot be further divided. The final rest is x¹³x +⁹x +²as shown below:

x³¹ = x¹³x¹⁸ = x¹³(x⁷+1) = x²⁰x +¹³ = x²x¹⁸x +¹³ = x²(x⁷+1) + x¹³ = x¹³x +⁹x +²

Binary string corresponding to x¹³x +⁹x +² has the form 000010001000000100, which is the mask code needed to cyclically move the m-string 31 times.

Delay elements 1022 to 1024 and 1020 delay channel I signals with a predetermined number of bits (chips) to generate the scramble code signals for channel Q.

As explained above, the second embodiment of the present invention generates the groups of scrambling codes shown in Fig. 9 and uses only the Gold thrust generator, masking sections 1000 to 1005 and adders 1022 to 1034.

There will now be a description of the operation of the present invention carried out as described above.

After entering the initial value for the main encryption code into memory 1040 and 1045 of the first and second shift registers, each of which has 18 registers, zero values ​​of memory registers 1040 and 1045 of the first and second shift registers are fed to the sumer 1030 and 18 values ​​of "ai" memory register 1040 of the first shift register are fed to the first Nth masking section 1000 to 1005 to generate from 1 to N cyclically shifted strings of the first m-string. Then the first masking section 1000 masks the input values ​​(ai) from the memory 1040 of the first (upper) shift register by the masking function k¹ to generate the first secondary encryption code (i.e. Z (k¹and χ ai)) and outputs masked values ​​to the adder 1032. The nth masking section 1005 masks the input values ​​(ai) from the first (upper) shift registers 1040 using the masking function k^Nand (i.e. Z (k^N χ ai)) and outputs masked values ​​to the adder 1034 to generate the Nth secondary encryption code. At the same time, adder 1030 sums the output bits of the zero memory registers 1040 and 1045 of the first and second shift registers. These generated output signals are immediately delayed at delay element 1022. Adder 1032 sums the output bits from the first masking section 1000 and the zero register of memory 1045 of the second shift register. The output signals are immediately fed to the delay element 1022. Then the values ​​of the zero register and the 7th memory register 1040 of the first shift register in adder 1010 are added and the summed values ​​are brought to the seventeenth register input, while the values ​​on the left shift to the right by one and the leftmost register is filled up again with the value derived from adder 1010. The values ​​of the zero, fifth, seventh and tenth memories of the second shift register 1045 are added together in adder 1015 and the sum of values ​​is brought to the seventeenth register of memory register 1045, while the values ​​on the left shift to the right by one position and the extreme left register ( ie register seventeenth) are filled in with the value derived from adder 1015. This procedure is repeated to generate multiple cipher codes.

PL 234 297 B1

Fig. 11 is a block diagram of an encryption code generator in a receiver serving to simultaneously generate one primary encryption code and one secondary encryption code. The embodiments shown in Figs. 10 and 11 can be used in a transmitter or receiver.

The receiver according to the second embodiment of this invention must use only one encryption code and therefore requires only one masking section 1100.

In the situation shown in Fig. 11, after providing the initial value for the main scrambling code to the memories 1140 and 1145 of the first and second shift registers, each of which has 18 registers, the values ​​of zero memory registers 1140 and 1145 of the first and second shift registers are fed to the adder 1120. 18 "ai" values ​​of memory register 1140 of the first shift register are applied to mask section 1100 to generate cyclically shifted m-strings. Then the first masking section 1100 masks the input (ai) values ​​from the register memory 1140 with the masking values ​​ki to generate the first secondary encryption code (i.e. T (kx ai)) and outputs the masked values ​​to the adder 1125. Adder 1120 sums the output bits of the zero memory registers 1140 and 1145 first and second shift registers. These generated output signals from adder 1120 are immediately delayed at delay element 1130. At this time, adder 1125 sums the output bits from masking section 1100 and zero memory register 1145 of the second shift register and outputs the result signal immediately to delay element 1135. Then, the values ​​of zero register and 7th memory of the first shift register 1140 in the adder 1110 are added, while when the values ​​on the left shift to the right by one, and the leftmost register fills up again with the value derived from adder 1110. The values ​​of the zero, fifth, seventh and tenth memories of the second shift register 1145 are added together in adder 1115, while the values ​​on the left are shifted to the right by one position, and the leftmost register is filled with the value derived from adder 1115. Mask values ​​can be controlled controller (not shown in the figure) when the receiver must generate other encryption codes.

The encryption code generator according to the second embodiment requires a mask value stored in the masking section to generate a secondary encryption code, i.e. it uses N mask value to generate N encryption codes. Accordingly, the structure of the primary and secondary encryption codes shown in Fig. 9 allows the use of an encryption code generator in the transceiver with the structure shown in Fig. 10 and 11, which further includes only N masking functions with low system complexity and can generate multiple encryption codes.

Although the invention has been shown and described with reference to certain preferred embodiments, it is obvious to those skilled in the art that various changes may be made in the form and details of this invention without departing from the spirit and scope of the invention as defined in the accompanying patent claims.