Dynamic address translation with translation exception qualifier

The present invention relates in general to systems and methods for translating a virtual address in a computer system, in particular systems and methods for translating a virtual address into a real address or absolute address of a data block in a computer system having dynamic address translation functionality in which virtual address translation occurs via the hierarchy of translation tables.

BACKGROUND OF THE INVENTION [0002] Dynamic Address Translation (DAT) provides the ability to interrupt program execution at any time, save it with its data in auxiliary memory, such as a direct access memory device, and then return the program and data to other places at a later time. in main memory to resume execution. The transfer of the program and its data between the main memory and the auxiliary memory can be carried out gradually, and the return of the information to the main memory can take place in response to the attempt made by the CPU to access it when it is needed to execute the program. These functions can be performed without changing or inspecting the program and its data,

[0003] With appropriate support by the operating system, the dynamic address translation function may be used to provide the user with a system in which the memory appears to be larger than the main memory that is available in the configuration. This apparent main memory is often referred to as virtual memory, and the addresses used to mark places in virtual memory are often referred to as virtual addresses. The user's virtual memory may significantly exceed the size of the main memory that is available in a given configuration and is normally maintained in the post-memory memory. It is believed that virtual memory is built of data blocks, commonly referred to as data blocks (also referred to as segments and areas). Only recently referenced virtual memory pages are assigned to occupied blocks of the physical main memory. When a user refers to virtual memory pages that do not appear in the main memory, they are inserted to replace places in the main memory for which the probability that they will be needed is smaller. In some cases, virtual memory is assigned to the main memory for a long period of time (or permanently), regardless of whether the memory is referenced. Exchange of memory pages can be performed by the operating system without the user's knowledge. it is smaller. In some cases, virtual memory is assigned to the main memory for a long period of time (or permanently), regardless of whether the memory is referenced. Exchange of memory pages can be performed by the operating system without the user's knowledge. it is smaller. In some cases, virtual memory is assigned to the main memory for a long period of time (or permanently), regardless of whether the memory is referenced. Exchange of memory pages can be performed by the operating system without the user's knowledge.

[0004] Programs use addresses (or virtual addresses) to access virtual memory. The program can download instructions from virtual memory or load data or store data from virtual memory using virtual addresses. Virtual addresses associated with the scope of virtual memory define the address space. With the appropriate support by the operating system, the dynamic address translation functionality can be used to provide a number of address spaces. These address spaces can be used to give degrees of isolation between users. This type of support can consist of a completely different address space for each user, thus providing complete isolation or the shared area may be present by mapping parts of each address space into a single common memory region. There are also instructions that allow access to a semi-privileged program to more than one of this kind of address space.

[0005] Dynamic address translation allows translation of virtual addresses from a wide variety of address spaces. For example, on the IBM system processor^® The system with these address spaces is called the main address space, the secondary address space and the address spaces defined by the Access Register. The privileged program can also provide home address space. Dynamic address translation can be specified for instruction addresses and data generated by the CPU.

[0006] As is known, the DAT mechanism is implemented by using consecutive portions of a virtual address as indexes to select entries in a series of translation tables (e.g., a first area table, a second area table, a third area table, a segment table, and a page table). Each intermediate table entry, if it is marked as valid, contains the beginning, offset and length of the next lower level table, which is then indexed by the next part of the virtual address, until the "leaf" entry containing the actual or absolute frame address is reached. The remaining part of the virtual address is then used as a byte index to this frame in order to complete the translation result.

[0007] Virtualization is used to improve the performance and flexibility of computing environments. Before virtualization, a single operating system usually worked on the machine. In a virtualized environment, the supervisor or host program has control over the machine's resources. This host creates numerous virtual machines, bins, in which separate, independent operating system cases, called guests, can work, sharing resources such as, for example, a processor and memory under the control of the host. [0008] In a paged guest environment (virtual machine), for example on an IBM® System z processor, the dynamic address translation occurs on two levels: the virtual guest page is stored by the actual guest frame, and these guest frames are in turn represented as memory virtual host, divided into virtual host pages that are stored by the actual host frames. Because address translation is managed independently by the guest and the host, the guest frame of any size can be mapped to a virtual host area consisting of pages of any size. Thus, the guest frame can consist of one side of the host, many host pages (large guest frame on many small sides of the host) or parts of the host page (small guest frame on the large host page). The memory can be managed more efficiently and you can use the handheld translation buffer (TLB) in the machine more efficiently when the host uses a page of the same size as the guest frame he stores. For example, a 1 megabyte guest frame is treated as a guest unit and should be returned through a 1 megabyte host frame instead of 256 separately paged 4K bytes frames. This allows the single TLB translate TLB buffer to map the entire megabyte of guest virtual addresses to the appropriate absolute host addresses.

[0009] In order for the host page size to match the size of the guest frame. the host must be able to determine what frame size the guest intends to use in different areas of the guest's memory. In some cases, a guest may use a frame management instruction that indicates the intended size of the guest frame and the handling of the instruction by the host or firmware may then give a host frame matching size for storing the guest frame. However, if the guest does not use this instruction at the time of use or if he later changes the size of the frame, then the host and guest sizes may no longer match. In particular, if the host has paged part of the guest memory and then the guest refers to it, there is a host translation exception, so that the host has the ability to store the memory storing the beneficial contents of the guest frame. This interruption gives the host an additional option of assigning a frame matching the size of the guest frame.

[0010] There is a need for improved dynamic address translation functionality that provides additional functionality that is hitherto unknown in the field that effectively and efficiently informs the host processor to allocate a suitably sized frame by which it is to store a guest frame in response to it. whether the interrupt caused by execution in the host or guest configuration, and if in guest configuration, whether this interrupt refers to a large or small guest frame identified by a leaf entry of the guest DAT table or to a guest frame defined in some other way.

[0011] US 2004 / 024953A1 describes a method of using multiple virtual memory spaces to achieve efficient binary compatibility between multiple source architectures and a single target architecture.

SUMMARY OF THE INVENTION [0012] A method according to claim 1 and a corresponding system and product in the form of a computer program offering a translation exception qualifier for dynamic address translation functionality that translates a virtual address into a real address or an absolute data block address in the main computer system memory are provided. having machine architecture.

[0013] In one embodiment, a virtual address to be translated is obtained. The beginning address of the first translation table in the hierarchy of translation tables used in translation is obtained. The hierarchy of translation tables consists of one or more of the first area table, the second area table, the third area table, the segment table, and, optionally, the page table. Dynamic translation of the virtual address to the actual address or absolute address of the block of data in the main memory is performed. If the translation can not be completed, for example, if one of the array entries needed for translation is marked as invalid, then the translation exception is aborted. In response to the interruption event of the host translation exception during translation of the virtual address, bits are written in the translation exception qualifier to indicate that the translation exception was one of the following: the exception of the host DAT that occurred during host program execution or the exception of the host DAT that occurred during the execution of the guest program. The TXQ field may also indicate that the translation exception was an exception to the guest DAT that occurred during the execution of the host program; that the translation exception was the exception of the host DAT relating to the address received from the leaf entry of the guest table; that the host DAT exception concerned the address received from the real address of the guest page frame; and that the host DAT exception applied to the address obtained from the absolute guest frame address. The TXQ field may also indicate the size of the guest frame, where the host DAT exception applies, and that a larger or smaller frame size is needed so that the host or firmware can provide the correct size of the host frame for storing the guest frame. Other embodiments are provided.

[0014] The invention will now be described with reference to specific illustrated embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS [0015] The attached figures, on which like reference numbers refer to identical or functionally similar elements in different views and which together with the following detailed description are attached and form part of the description, serve to further illustrate various embodiments and explain various principles and advantages of the present invention.

FIG. 1 shows one embodiment of a host computer system according to the prior art in which enhanced dynamic translation of a guest and host address will be performed;

Figure 2 illustrates an exemplary emulated host computer system according to the prior art that emulates a host computer system with a host architecture; FIG. 3 depicts one prior art embodiment of how the program status word is used to determine an effective ASCE for dynamic translation of a virtual address;

FIG. 4 depicts one prior art example in which the effective ASCE determined in FIG. 3 is used to determine the highest translation table in the hierarchy of translation tables used for virtual address translation;

Figure 5A illustrates one embodiment of a dynamic translation process of a virtual address using a hierarchy of translation tables to the level of the segment table;

Figure 5B illustrates the continuation of the dynamic address translation of Figure 5A, wherein the format control (FC) segment table entry (STE) format check is zero;

Figure 5C illustrates the continuation of the dynamic address translation of Figure 5A, wherein the format control (FC) segment table entry (STE) checksum is one; Figure 6 is a flowchart of one embodiment of an enriched dynamic address translation (EDAT) at guest level to obtain a format control field in a segment table entry;

figure 7 shows the continuation of the flow of activities from node 630 of figure 6 when the guest STE checksum is zero; Figure 8 shows the continuation of the flow of activities from node 632 of Figure 6, when the guest STE control bit is one; FIG. 9 is a flowchart of one host implementation EDAT example that can be invoked from a guest EDAT process to obtain a format control field in a host segment table entry;

Figure 10 shows a continuation of the flow of activities from node 928 of Figure 9, when the host STE format checksum is zero;

Figure 11 shows a continuation of the flow of activities from node 930 of Figure 9, when the STE host format control bit is one;

figure 12 shows the contents of control register 1;

figure 13 shows the contents of control register 7;

figure 14 shows the content of control register 13;

figure 15 shows the content of the program status word;

figure 16 shows the contents of the prefix register;

figure 17 shows the relationship between a real address and an absolute address;

figure 18 shows the virtual address format;

figure 19 shows the virtual address format;

Figure 20 shows the formats of the region table entries;

figure 21 shows the format of the entry taken from the table of the segment;

Figure 22 shows the format of the segment table entry; and figure 23 shows the format of the entry taken from the page table.

DETAILED DESCRIPTION [0016] It should be understood that the statements used in the description of the present application do not necessarily limit any of the various claimed inventions. In addition, probably statements may refer to certain innovative properties, but not to others. Unless otherwise stated, individual elements may appear in the plural and vice versa, without losing generality.

[0017] A person skilled in the art will be familiar with the issues of memory addressing in a computing environment and the use of bits in a register or an address field to denote different states and operate on those states. In addition, an expert with an average knowledge of the field will have knowledge of computer software and the operation and relationships between components of computer systems, sufficient to implement this description in their own computing environments without unnecessary testing.

OVERVIEW [0018] An example of functionality of enriched Dynamic Address Translation (DAT) is provided. When the Enhanced DAT Translation functionality is installed and enabled, the DAT translation can be generated either by the actual page frame address or the absolute segment frame address, as determined by the Segment Table Entry Format (STE) control bit in the segment table entry. As used herein, the term "enriched DAT applies" means that all the following statements are true: 1) EDAT functionality is installed; 2) the EDAT functionality is enabled via bit 40 of control register 0 (CR0); and 3) the address is translated via DAT table entries.

[0019] When the enriched DAT translation is applicable, then the following additional function is available in the DAT translation process:

- A DAT protection bit is added to the area table entries, having a similar function to the DAT protection bits in the segment table and page table entries.

- An STE format control bit is added to the segment table entry. When the STE format control bit is zero, the DAT translation proceeds according to the current definition, except that the change recording override in the page table entry indicates whether the change bit setting can be omitted for the page.

- When the STE format control bit is one, the segment table entry also includes the following:

- Absolute address of the segment frame (not the beginning of the page table) specifying the absolute location in the block memory of 1 megabyte.

- Access control bits and a download protection bit, which can optionally be used instead of the corresponding bits in the individual segment memory keys.

- A bit that specifies the validity of the access control bits and the download protection bit in the segment table entry.

- A cancel change registration bit, which indicates whether the change bit setting can be omitted from the individual segment memory keys.

- The translation exclusion qualifier (TXQ) is stored when the DAT exception is aborted to provide details about the execution environment (host or guest) in which the exception occurred, as well as the source of the address that has been translated.

Host Computer System [0020] The emulated system includes an emulator program that emulates a computer system that can offer both the host architecture and the ability to perform interpretation. The memory of the emulated system can contain both host and paged guests. The host program working in the emulated host architecture can run the instruction. Start Interpretive Execution of the guest program, which then works under the emulation of the interpretive function. One example of the functionality of the interpretive exercise and the instructions Start Interpretation Performing (SIE) for the execution of the paged guest is described in "IBM® System / 370 Extended Architecture", IBM® Pub. Well. SA22-7095 (1985). [0021] Reference is now made to Figure 1, which illustrates one embodiment of a host computer system 100 in which enhanced dynamic translation of a guest and host address will be performed. The host 100 computing environment is preferably based on the z / Architecture® system offered by International Business Machines Corporation (IBM), Armonk, New York. The z / Architecture® system is more fully described in: "z / Architecture® Principles of Operation, IBM® Pub. Well. SA22-7832-05, 6th Edition, (April 2007). The z / Architecture®-based computing environments include, for example, eServer and zSeries New York. The z / Architecture® system is more fully described in: "z / Architecture® Principles of Operation, IBM® Pub. Well. SA22-7832-05, 6th Edition, (April 2007). The z / Architecture®-based computing environments include, for example, eServer and zSeries New York. The z / Architecture® system is more fully described in: "z / Architecture® Principles of Operation, IBM® Pub. Well. SA22-7832-05, 6th Edition, (April 2007). The z / Architecture®-based computing environments include, for example, eServer and zSeries^®, both produced by IBM^®.

[0022] The computing environment 100 includes a central processor complex (CPC)

102 creating virtual machine support. The CPC 102 includes, for example, one or more virtual machines 104, one or more processors 106, at least one host 108 (e.g. a control program, such as a supervisor), and an input / output subsystem 110. The virtual machine support CPC gives the ability to work large numbers of virtual machines, each of which is capable of adopting a guest operating system, such as Linux, for example.

[0023] Each virtual machine has the ability to function as a separate system. That is, each virtual machine can be independently reset, the host contains the guest operating system and work with various programs. An operating system or application program running on a virtual machine seems to have access to a full and complete system, but in reality only part of it is available.

In this particular example, the virtual machine model is a V = V model in which the virtual machine memory is stored by virtual memory, not real memory. Each virtual machine has a virtual linear memory space. Physical resources are the property of the host and shared physical resources are hosted by the host to guest operating systems, as needed to meet their processing needs. This V = V virtual machine model assumes that interactions between guest operating systems and physical shared machine resources are controlled by the host because a large number of guests usually prevents the host from simply dividing and assigning hardware resources to configured guests. One or more aspects of the V = V model are described more fully in "z / VM: Running Guest Operating Systems", IBM® Pub. Well. SC24-5997-02, (2001).

[0025] Central processors 106 are physical processor resources that can be assigned to a virtual machine. For example, a virtual machine 104 includes one or more virtual processors, each of which represents a whole or share in a physical processor resource that can be dynamically allocated to a virtual machine. Virtual machines are managed by the host. The host can be implemented in the form of a microcode running on one or more processors or it can be part of the operating system of the host working on the machine. In one embodiment, the host is a VM supervisor such as z / VM® offered by IBM®. One embodiment of z / VM® is more fully described in "z / VM: General Information Manual", IBM® Pub. Well. GC24-5991-04, (2001).

[0026] The I / O system 110 directs the information stream between the devices and the main memory. It is connected to the central processing complex. It may be part of the central processing complex or may be separate from it. The I / O subsystem releases central processors from the task of direct communication with I / O devices connected to CPC and allows simultaneous data processing along with I / O processing.

Central Processors 106 may have Dynamic Address Translation (DAT) functionality (function or unit) for converting program addresses (virtual addresses) to actual memory addresses. The DAT functionality usually includes a hand-held translation buffer for storing translating translations so that later access to a computer memory block does not require a delay in address translation. Typically, a cache between the computer memory and the processor is used. The cache can be hierarchical with a large cache available for more than one CPU and smaller, faster (lower level) caches between the large cache and each CPU. In some implementations, lower-level caches are split to obtain separate low-level caches for instruction retrieval and data access. In an embodiment, the instruction is retrieved from the memory by the instruction retrieval unit via the cache. The instruction is decoded in the instruction decoding unit and sent (along with other instructions in some embodiments) to the execution units of the instructions. Typically, several execution units of the instructions are used, e.g. an arithmetic execution unit, a floating-point executive unit, and an executive branch instruction unit. The instruction is executed by the execution unit, retrieving arguments from the registers or memory specified for the instructions, if necessary.

[0028] In an embodiment, the invention may be implemented by software (sometimes referred to as Licensed Internal Code (LIC), firmware, microcode, milikod, picokod and the like, each of which will be consistent with the present invention). The software code that realizes the present invention is typically retrieved by a processor, also known as a CPU (central unit) of a computer system from a long-term storage medium, such as a CD-ROM drive, a tape drive, or a hard disk drive. The software code may be implemented on any of a variety of known carriers intended for use with a data processing system, such as a floppy disk, hard disk or CD-ROM.

[0029] Alternatively, the program code may be implemented in memory and downloaded by the processor using the processor bus. This kind of program code includes an operating system that controls the operation and interaction of various computer components and one or more application programs. The program code is usually paged from the dense storage medium to the high speed memory where it is available for processing by the processor. Techniques and methods for executing software code in memory, on a physical medium, and / or distributing software code over a network, are well known and will not be described further here. Program code, after being created and saved on a physical medium (including, but not limited to, electronic memory modules (RAM), flash memory, compact discs (CDs), DVDs, magnetic tape and other, is referred to as the "computer program product". The product carrier of a computer program can usually be read by the processing system preferably in a computer system for execution by the processing system.

[0030] Another example of a computing environment for including one or more aspects of the present invention is illustrated in Figure 2. In this example, an emulated host computer system 200 that emulates a host computer system 202 having a host architecture is depicted. The emulated host processor 204 (or the virtual host processor) is implemented via a emulation processor 206 having a different architecture of a set of native instructions than that used by the host computer processors. The emulated host computer system has a memory 208 available to the emulation processor 206. In an exemplary embodiment, the memory 208 is divided into a portion of the host computer's memory 210 and a portion of emulation procedures 212. Host computer memory 210 is available to emulated host computer programs 202 and may include both host and supervisor 214 and one or more virtual machines 216 executing guest operating systems 218, analogously to similarly named items in Figure 1. Emulation processor 206 performs native instructions a constructed set of architecture instructions other than the emulated processor; native instructions are obtained, for example, from the memory of 212 emulation procedures. The emulation processor 206 may reach the host instruction to execute from the program in the host computer 210 by applying one or more instructions received in the Sequence & Access / Decode procedure, which can decode the downloaded host's instructions to determine the procedure to execute the native instruction to emulate the function of the host instruction retrieved. One such host statement can be, for example, the Start Interpretation Execution (SIE) instruction, with which the host attempts to execute a program in a virtual machine. Emulation procedures 212 may include support for this instruction and also for executing a sequence of guest instructions in a virtual machine as defined in this SIE instruction.

[0031] Other functionalities that are defined for the host computer system architecture can be emulated by constructed functionalities that include functionalities such as general-purpose registers, control registers, dynamic address translation, and, for example, I / O subsystem support and memory a handheld processor. Emulation routines may also use the functions available in emulation processor 206 (e.g., general registers and dynamic translation of virtual addresses) to improve the operation of emulation procedures. Special instrumentation and unloading motors can also be used to support the processor when emulating the host computer's functions. The host computer, in one embodiment, is connected to various types of storage media 220, such as a floppy disk, hard drive or CD-ROM. The software code can be distributed on such media or it can be distributed to users via the network 222.

Computer processor and registers [0032] In an exemplary embodiment, the functionality of the CPU instruction instructions communicate with a plurality of registers over the communication bus. The communication bus may be internal or external to the central processing unit. Some registers can be read-only. Other hardware and / or software components may also read / write to one or more registers available to the CPU. The instruction operation code (opcode) specifies which type of register to use in each specific operation of a machine instruction.

General Registers [0023] The instructions may mean information in one or more of the 16 general registers. General registers can be used as base address registers and index registers in address arithmetic as well as accumulators for general arithmetic and logic operations. Each register contains 64 bit positions. General registers are identified by numbers 0 - 15 and are indicated by a 4-bit R field in the instruction. Some instructions provide addressing of many general registers through the presence of several R fields. For some instructions, the use of a specific general register is rather suggested than directly designated by the R field of the instruction.

[0034] For some operations, either bits 32-63 or bits 0-63, two adjacent general registers are combined, yielding a 64 bit or 128 bit format, respectively. For these operations, the program must determine an even numbered register, which contains the leftmost (higher order) 32 or 64 bits. The next above-numbered register contains the extreme right (lower order) 32 or 64 bits. Apart from their use as accumulators in the case of general arithmetic and logic operations, 15 out of 16 general registers are also used as base address registers and index registers when generating the address. In these cases, the registers are indicated by a four-bit field B or X in the instruction. A value of zero in field B or X means that the base or index is not used,

Control Registers [0035] Control registers are used to maintain and manipulate control information outside of the program status word. The CPU 16 has 16 control registers, each of which has 64 bit positions. The bit positions in the registers are assigned to individual functionalities in the system, such as recording program events and are used either to determine that the operation may take place or to provide special information required by the functionality. The control registers are identified by numbers 0 - 15 and are indicated by four-bit R fields in the LOAD CONTROL and STORE CONTROL instructions. These instructions can address numerous control registers.

Control register 1 [0036] Control register 1 contains a primary address space control element Primary Address Space Control Element (PASCE). In one embodiment, the control register 1 has one of two formats, as illustrated in figure 12, depending on the real space control bit (R) in the register:

[0037] Selected fields in the main address space control element (PASCE) are allocated as follows:

[0038] Beginning of the main table of the segment or segment table (Primary Region Table or

Table Origin segment): Bits 0-51 of the main area table or segment table designation in control register 1, with 12 zeros appended to the right, form a 64-bit address, which is the beginning of the main segment table or segment table. It is not possible to predict whether the address is real or absolute. This table is called the main area table or segment table, because it is used to translate virtual addresses in the main address space.

[0039] Primary Real Space Control (R) Bit: If bit 58 of control register 1 is zero, the register includes a region table or segment table designation. If bit 58 is one, then the register contains the real space designation.

When bit 58 is one, one value of the common segment bit in the trunk translation representation of the segment table entry buffer protects this entry and a copy of the translation buffer page it represents before using the main address space for translating, even when matching between the beginning of the mark in control register 1 and the beginning of the table in the translation buffer popup entry.

[0040] Main Control Bit Type Designation (DT): When bit R is zero, the type of array designation in control register 1 is determined by bits 60 and 61 in the register as follows:

<td>Bits 60 and 61</td><td>Type of sign</td>

<td>11</td><td>The first array of the area</td>

<td>10</td><td>The second array of the area</td>

<td>01</td><td>The third array of the area</td>

<td>00</td><td>Segment table</td>

Major designation (DT) control bits When the R bit is zero, bits 60 and 61 must be binary when attempting to use the PASCE to translate the virtual address in which the leftmost one-bit is located in bit positions 0-10 address. Similarly, bits 60 and 61 must be binary 11 or 10, when the leftmost one located bit is in the bit positions 11 -21 of the address, and they must be binary 11, 10 or 01 when the leftmost one located bit is in bit positions 22 - 32 of the address. Otherwise, the exception of ASCE type is considered.

[0042] The length of the Main Area Table or the Segment Table (TL): Bits 62 and 63 of the main area table designation or segment table designation in the control register 1 determine the length of the main region table or segment table in units of 4096 bytes, thereby forming the length of the area array or segment table variable in multiples of 512 entries. The length of the main table of a region or segment table in units of 4096 bytes is one more than the TL value. The length field contents are used to determine whether a part of the virtual address (RFX, RSX, RTX, or SX) to be translated via the table means an entry that lies within the array. [0043] Beginning of the Main Mark of the Real Space: Bits 0 - 51 of the primary real space designation in the control register 1, with 12 zeros attached on the right, they form a 64-bit address that can be used to create and use the translation buffer popup entries that give a virtual translation equal to the actual references to the main address space. Although this address is used only as a birthmark and is not used to make references to memory, it still has to be an important address; otherwise, an incorrect entry of the popup translation buffer may be used when the content of control register 1 is used. that this address is used only as a birthmark and is not used to make references to memory, it still has to be an important address; otherwise, an incorrect entry of the popup translation buffer may be used when the content of control register 1 is used. that this address is used only as a birthmark and is not used to make references to memory, it still has to be an important address; otherwise, an incorrect entry of the popup translation buffer may be used when the content of control register 1 is used.

[0044] The following bits of control register 1 are not assigned and are ignored: bits 52, 53 and 59 if the register includes the area table designation or segment table designation, and bits 52, 53 and 59 - 63 if the register contains a real space designation .

Control Register 7 [0045] Control register 7 contains a Secondary Address Space Control Element (SASCE). In one embodiment, control register 7 has one of two formats, as illustrated in Figure 13, depending on the real-time control bit (R) in the register.

Control register 13 [0046] Control register 13 includes a Home Address Space Control Element (HASCE). In one embodiment, control register 13 has one of two formats, as illustrated in Figure 14, depending on the real-time control bit (R) in the register.

Access Registers The CPU has 16 access registers numbered from 0 to 15. The access register consists of 32 bit positions including an intermediate ASCE specification. ASCE is a parameter used by the Dynamic Address Translation (DAT) mechanism to translate references to the appropriate address space. When the CPU is in a mode called access register mode (controlled by bits in the program status word), the B field of the instruction used to determine the logical address for the memory argument is the access register, and the ASCE parameter specified by the access register is used by the DAT mechanism for a reference. For some instructions, the R field field is used instead of the B field.

[0048] Each of the access registers 1-15 may mean any address space, including the current instruction space (primary address space). Access register 0 means the main space of the instruction. When one of the access registers 1 - 15 is used to designate the address space, the CPU determines which address space is determined by translating the access register content. When the access register 0 is used to designate the address space, the central processing unit treats the access register as the main instruction space and does not examine the actual content of the access register. Therefore, 16 access registers can mean at the moment the main instruction space and up to 15 other spaces.

Program status word (PSW) [0049] The program status word includes the instruction address, condition code and other information used to control instruction sequencing and determine the state of the central processing unit. The active or controlling word of the program status is called the current program status word. It manages the program being executed. [0050] The CPU has an interrupt ability that allows the CPU to quickly switch to another program in response to exceptions and external stimuli. When an interruption occurs, the CPU places the current program status word in the assigned memory location, called the old location of the program status word, for the specified interrupt class. The CPU CPU gets a new program status word from the second memory location assigned. This new program status word defines the next program to be executed. After the interrupt processing is complete, the interrupt handler may re-load the old program status word, causing it to be the current program status word again, so that the interrupted program can be continued.

[0051] There are six interrupt categories: external, I / O, machine test, software, restart and call supervisor. Each class has a different pair of locations of the old program status word and a new program status word permanently assigned in real memory.

Current Program Status Word [0052] The current program status word in the CPU has the information required to execute the current active program. The program status word is 128 bits long and contains the instruction address, condition code and other control fields. In general, the program status word is used to control instruction sequencing and to hold and indicate the status of the CPU in relation to the program being executed. Additional control and status information is included in control registers and permanently assigned memory locations. The status of the CPU may be changed by loading a new program status word or part of the program status word.

[0053] The control is switched during the interruption of the central processing unit by storing the current program status word so as to maintain the status of the central processing unit and then loading a new program status word. Execution of LOAD PSW or LOAD PSW EXTENDED or successful completion of the initial loading sequence of the program introduces a new program status word. The address of the instruction is updated by sequential execution of instructions and replaced by successful branching. Other instructions are provided that work on part of the program status word.

The new or modified program status word becomes active (i.e. information entered into the new program status word takes control of the CPU) when the interrupt or execution of the instruction that changes the program status word is terminated. Interruption for Program Event Recording (PER) associated with a statement that changes the program's status word, is under the control of the PER mask, which is effective at the beginning of the operation. Bits 0 - 7 program status words are collectively referred to as a system mask. In one embodiment, the program status word has the format illustrated in Figure 15.

[0055] A brief summary of the functions of selected program status word fields is given below. [0056] DAT (T) mode: Bit 5 controls whether there is allegedly dynamic translation of the address of logical addresses and instructions used for accessing the memory. When bit 5 is zero, the DAT mechanism is disabled and logical addresses and instructions are treated as real addresses. When bit 5 is one, the DAT mechanism is turned on and dynamic translation of the address is called.

[0057] PSW key: Bits 8-11 define an access key for memory references by the CPU. If the reference is subject to key-controlled protection, then the PSW Key is matched to the memory key when information is stored or when information is retrieved from a location that is protected from download. However, for one of the arguments of each statement among MOVE TO PRIMARY, MOVE TO SECONDARY, MOVE WITH KEY, MOVE WITH SOURCE KEY, and MOVE WITH DESTINATION KEY, the access key specified as an argument is used instead of the PSW Key.

[0058] Address Space Control (AS): Bits 16 and 17, in combination with bit 5 of the Program Status Word, control the mode of translation.

[0059] Condition Code (CC): Bits 18 and 19 are two bits of the condition code. The condition code is set to 0, 1, 2 or 3, depending on the result obtained when executing certain instructions. Most of the arithmetic and logic operations, as well as some other operations, set the condition code. The BRANCH ON CONDITION statement can specify any choice of condition code value as a branch criterion.

[0060] Address of the Instruction: Bits 64 - 127 of the program status word are the address of the instruction. This address is the location of the leftmost byte of the next instruction to be executed, unless the CPU is in a standby state (bit 14 of the program status word is one).

Types and address formats [0061] For addressing main memory address, three main address types are recognized:

absolute, real and virtual. The addresses are distinguished on the basis of transformations that are performed on the address during access to the memory. Address translation converts a virtual address to a real address. The prefix converts the real address to the absolute address. In addition to these three basic address types, additional types are defined, which are treated as one of the three basic types, depending on the instructions and the current mode.

Absolute address [0062] An absolute address is an address assigned to a location in the main memory. The absolute address is used to access the memory without performing any transformations on it. The channel subsystem and all CPUs in a given configuration reference the shared primary memory location by using the same absolute address. The available main memory is usually allocated adjacent absolute addresses beginning at 0 and these addresses are allocated in full blocks of 4 kilobytes at integral limits. An exception is recognized when an attempt is made to use an absolute address in a block that has not been assigned to physical locations. In some models, memory reconfiguration controls may be present, which allow the operator to change the correspondence between absolute addresses and physical locations. However, at any time, the physical location is not associated with more than one absolute address. The memory consisting of the location of the bytes sequenced according to their absolute addresses is referred to as absolute memory.

Real Address [0063] The real address identifies the location in the real memory. When the actual address is used to access the main memory, it is converted, via prefixing, to create the absolute address. In each case, one real address is assigned to the absolute address for each CPU in the given configuration. When the actual address is used by the CPU for access to the main memory, it can be converted to the absolute address by performing the prefixing. The specified transformation is defined by the value in the prefix register for the CPU. The memory consisting of byte locations sequenced according to their real addresses is referred to as real memory.

Virtual address [0064] The virtual address identifies the location in the virtual memory. When a virtual address is used to access the main memory, it is translated via a dynamic address translation, or to a real address that can be prefixed to create an absolute address or directly to an absolute address.

Primary virtual address [0065] The primary virtual address is a virtual address to be translated via the Main Address Space Control Element (PASCE). Logical addresses are treated as the main virtual addresses in the main space mode. Address statements are treated as major virtual addresses in primary space mode, secondary space mode, or access register mode. The address of the first argument of the MOVE TO PRIMARY statement and the address of the second MOVE TO SECONDARY argument are treated as the main virtual addresses. Furthermore, when a paged guest is executed, the main memory (memory) that the guest sees as absolute memory is represented in the host's main address space; that is, the guest's absolute addresses are treated as the main virtual addresses of the host.

Secondary virtual address [0066] The secondary virtual address is a virtual address that is translated via a secondary address space control element (SASCE). Logical addresses are treated as secondary virtual addresses in secondary space mode. The address of the second argument of the MOVE TO PRIMARY statement and the address of the first MOVE TO SECONDARY argument are treated as secondary virtual addresses.

Virtual address specified by the access register (AR) [0067] The virtual address specified by the access register (AR) is the virtual address to be translated via the address space control element determined by the Access Register Specified Address Space Control Element. Logical addresses are treated as virtual addresses specified by the access register in the access register mode.

Home virtual address [0068] The home virtual address is a virtual address that is translated via a home address space control element (HASCE). Logical addresses and instruction addresses are treated as home virtual addresses in the home address space mode.

Address of the instruction [0069] The addresses used to retrieve instructions from the memory are called instruction addresses. Address addresses are treated as real addresses in real mode, as major virtual addresses in main space mode, secondary space mode or access register mode, as well as home virtual addresses in home space mode. The instruction address in the current program status word and the destination address of the EXECUTE statement are instruction addresses.

Effective address [0070] In some situations it is convenient to use the term "effective address". An effective address is an address that exists before performing any transformation by dynamic address translation or prefixing. The effective address can be specified directly in the register or it can result from address arithmetic. Address arithmetic is the addition of the base and displacement or base, index and displacement.

Prefixing [0071] The prefixing gives the ability to assign a real address range 0 8191 to another block in absolute memory for each CPU, thus allowing more than one CPU to share the main memory for concurrent work with minimal interference, especially when processing interrupts. The prefix causes real addresses in the range 0 - 8191 to correspond to one block of 8 kilobytes absolute addresses (prefix area) identified by the value in bit positions 0-50 prefix222 for the CPU, and the real address block identified by this value in The prefix register matches one to one absolute addresses 08191. The other real addresses are the same as the corresponding absolute addresses. This transformation allows each central CPU to access all of the main memory, including the first 8 kilobytes and locations marked by prefix registers of other CPUs.

[0072] The prefix is ​​the 51-bit size included in the bit positions 0-50 of the prefix register. In one embodiment, the prefix register has the format illustrated in Figure 16.

Prefix register format [0073] When using prefix, the real address is converted to an absolute address by using one of the following rules, depending on the real address bit 0 50:

1. Bits 0 - 50 address, if all have a value of zero, are replaced with bits 0 50 prefix.

2. Bits 0 - 50 of the address, if they are equal to bits 0 - 50 of the prefix, are replaced with zeros.

3. Bits 0 - 50 of the address, if not all have the value zero and do not equal to bits 0 50 of the prefix, remain unchanged.

[0074] Only the address shown in memory is translated via prefixing. The content of the address source remains unchanged.

[0075] The distinction between real addresses and absolute addresses is made even when the prefix register contains only zero, in which case the real address and its corresponding absolute address are identical.

Relationship between real address and absolute address [0076] The relationship between real addresses and absolute addresses is graphically illustrated in figure 17.

Address spaces [0077] The address space is the next sequence of integers (virtual addresses); along with specific transformation parameters that allow each number to be associated with the byte location in memory. This sequence starts from zero and progresses from left to right.

[0078] When the CPU uses a virtual address to access the main memory, it is first converted, via dynamic address translation (DAT), to the real address or the absolute address. The actual address can also be prefixed to form an absolute address. The DAT mechanism may use the first area table, the second area table, the third area table, the segment table, and the page table as transformation parameters. The designation (origin and length) of the top-level table for the specific address space is called the address space control element (ASCE) and is intended for use by the DAT mechanism in the control register or as defined by the access register.

[0079] The DAT mechanism uses, at various times, ASCE in different control registers or determined by access registers. The selection is determined by the translation mode specified in the current program status word. Four translation modes are available: main space mode, secondary space mode, access register mode and home space mode. Different address spaces can be addressed depending on the translation mode.

[0080] In any case, when the CPU is in major space or secondary space mode, it can translate virtual addresses belonging to two address spaces - the main address space and the secondary address space. In any case, when the CPU is in access register mode, it can translate virtual addresses from up to 16 address spaces - the main address space and up to 15 address spaces defined by the access register. Whenever the CPU has a home address space, it can translate virtual addresses from the home address space.

[0081] The primary address space is identified as such, because it consists of major virtual addresses that are translated via the Main Address Space Control Element (PASCE). Similarly, the secondary address space consists of secondary virtual addresses translated via the secondary address space control element (SASCE). The address space defined by the access register (AR) consists of the virtual addresses specified by the access register, translated via the address space control element determined by the access register (AR), and the home address space consists of the home virtual addresses translated via the element control home address space (HASCE). The ASCE control elements of the main address space and secondary address space are located in control registers 1 and 7 respectively. The ASCE control elements of the address space defined by the access register (AR) can be located in control registers 1 and 7 or in table entries called secondary tables ASN. The HASCE control element is located in control register 13.

Dynamic address translation [0082] Dynamic address translation is a translation process of a virtual address (e.g., during a memory reference) to a corresponding address in the main memory (real address or absolute address in the embodiment). The virtual address can be the main virtual address, the secondary virtual address, the virtual address specified by the access register or the home virtual address. These addresses are translated via control elements respectively PASCE, SASCE, SASCE specified by AR or HASCE. After selecting the appropriate ASCE control element, the translation process is the same for all four types of virtual address.

Address Translation Mode [0083] An effective address is an address (virtual address) that exists before any transformation is performed by dynamic address translation or prefixing.

The three bits in the program status word that control the dynamic address translation are bit 5, the DAT bit, and bits 16 and 17, which are control bits of the address space. When the DAT mode bit is zero, the DAT mechanism is disabled and the CPU is in real mode. When the DAT mode bit is one, then the DAT mechanism is enabled and the CPU is in the translation mode marked by the address space control bits: binary value 00 means master space mode, binary value 01 means re 5 access mode, binary value 10 means secondary space mode, while binary value 11 means home space mode. These different types of modes are presented below along with the treatment of addresses in each mode.

<td colspan="3">Bit PSW</td><td></td><td></td><td colspan="2">Treatment of addresses</td>

<td>5</td><td>16</td><td>17</td><td>DAT</td><td>Mode</td><td>Addresses of instructions</td><td>Logical addresses</td>

<td>0</td><td>0</td><td>0</td><td>off</td><td>Real mode</td><td>Actual</td><td>Actual</td>

<td>0</td><td>0</td><td>1</td><td>off</td><td>Real mode</td><td>Actual</td><td>Actual</td>

<td>0</td><td>1</td><td>0</td><td>off</td><td>Real mode</td><td>Actual</td><td>Actual</td>

<td>0</td><td>1</td><td>1</td><td>off</td><td>Real mode</td><td>Actual</td><td>Actual</td>

<td>1</td><td>0</td><td>0</td><td>On</td><td>Main space mode</td><td>The main virtual</td><td>The main virtual</td>

<td>1</td><td>0</td><td>1</td><td>On</td><td>Access register mode</td><td>The main virtual</td><td>Virtual AR</td>

<td>1</td><td>1</td><td>0</td><td>On</td><td>Space mode secondary</td><td>The main virtual</td><td>Secondary virtual</td>

<td>1</td><td>1</td><td>1</td><td>On</td><td>Space mode home</td><td>Virtual home</td><td>Virtual home</td>

Translational modes [0084] The program status word is a 128 bit word that, in part, offers two bits that indicate the addressing mode. In one embodiment, bit 31 is the Extended Addressing Mode (EA) bit, and bit 32 is

Base Addressing Mode (BA). These two bits indicate the size of the addresses. The state of each of these two bits is a binary value (1 or 0). If the EA bit is 0 and the BA bit is 0, then 24-bit addressing indicates this. If 24-bit addressing is indicated then the bits of the 40-63 64-bit word (64-bit unit is commonly referred to as the double-length word) are the location where the address is located. If the address of the instruction occupies the second bits of the 128-bit unit (quadruple), then the positions of the bits in the pro-gram word are as follows. In 24-bit mode, the instruction address is in bits 104 127 of the program status word. In the 31-bit mode, the instruction address is in bits 97 - 127 of the program status word. In 64-bit mode, the instruction address is in bits 64 - 127 of the program status word. If the EA bit is 0 and the BA bit is 1, then 31-bit addressing is indicated. The corresponding 64-bit word contains a 31-bit address located in bit positions 33-63. If the EA bit is 1 and the BA bit is 1, then bits 0-63, which constitute the whole 64 bits of the 64-bit word, contain the address. Otherwise, the exception status is indicated. After receiving the addressing mode, the ASCE element must be designated. which constitute the whole 64 bits of the 64-bit word, contain the address. Otherwise, the exception status is indicated. After receiving the addressing mode, the ASCE element must be designated. which constitute the whole 64 bits of the 64-bit word, contain the address. Otherwise, the exception status is indicated. After receiving the addressing mode, the ASCE element must be designated.

Address Space Control (ASCE) [0085] Reference is now made to Figure 3, which illustrates one embodiment of how a program status word is used to determine an effective address space control element (ASCE) for dynamic translation of virtual addresses. The ASCE element can, for example, specify a 2 gigabyte address space (Giga = 2). Alternatively, it may specify, for example, an address space of 4 terabytes (Tera = 2⁴⁰), 8 petabytes (Pera = 2⁵⁰) or 16 exabyte (Eksa = 2⁶⁰). Or it can also determine the real space designation. The real space designation means that the virtual address is treated as an actual address in memory without reference to one or more address translation tables.

[0086] The program status word 300 includes a translation bit (T) 302 and address space bits 304 (AS). In block 306, if the translation bit (T) is zero, then the address is real address 326. If, at 308, the address space (AS) is zero (binary 00), then the effective ASCE control element for that virtual address is the control element of the main address space (PASCE) 310. If, in 312, the address space is one (binary 01), then the effective control element ASCE is a control element determined by the access register 314. If, in 316, the address space (AS ) has the value of two (binary 10), then the effective control element ASCE is the control element of the secondary address space (SASCE) 318.

[0087] After selecting an effective ASCE control element, the dynamic address translation process is preferably the same for all four types of virtual addresses.

[0088] The segment table designation or the area table designation causes the translation to be performed via tables established by the operating system in real or absolute memory. The real space designation means that the virtual address is simply treated as a real address, without using tables in memory.

[0089] In the process of translation when using a segment table or area table designation, three types of information units are identified - areas, segments and pages. The area is a block of sequential virtual addresses extending to 2 gigabytes and starting at the border of 2 gigabytes. The segment is a block of sequential virtual addresses extending to 1 megabyte and starting at 1 megabyte. The site is a block of sequential virtual addresses extending to 4 kilobytes and starting at the border of 4 kilobytes.

Virtual address format [0090] Virtual address translation may refer to a plurality of translation tables with a certain hierarchy of translation tables to obtain a real address or an absolute address. The actual address can also be subjected to a prefixing operation to form an absolute address. The virtual address contains indexes to entries in translation tables in the hierarchy of translation tables. Accordingly, the virtual address is divided into four main fields. Bits 0-32 are called the area index (RX), bits 33-43 are called the segment index (SX), bits 44 - 51 are called the page index (PX), and bits 52 - 63 are called the byte index (BX). In one embodiment, the virtual address has the format illustrated in Figure 18.

[0091] According to what is defined by its ASCE control element, the virtual address space can be a 2 gigabyte space consisting of one area or it can be up to 16 exabyte space consisting of up to 8-gigabyte areas. The virtual address RX portion of the 2 gigabyte address space must be all filled with zeros; otherwise, the exception is reported. The RX part of the virtual address itself is divided into three fields. Bits 0 - 10 are called the first area index (RFX), bits 11 - 21 are called the second area index (RSX), and bits 22 - 32 are called the third area index (RTX). In one embodiment, the bits 0 - 32 of the virtual address have the format illustrated in the new figure 19.

[0092] A virtual address in which RTX is the most left-most significant part (42-bit address) is capable of addressing 4 terabytes (2048 areas), the virtual address in which the RSX is the left-most significant part (53-bit address) is capable of to address 8 petabytes (4 193 044 areas), while the virtual address, in which RFX is the most left-most significant part (64-bit address), is capable of addressing 16 exabytes (8,594,934.592 areas).

[0093] The virtual address at which RX is zero may be translated to the real address via two translation tables: the segment table and the page table. In the case of the EDAT functionality enabled, the translation can be completed with only one table of the segment. The RFX may be non-zero, in which case the first area table, the second area table and the third area table are required. If the RFX is zero, but the RSX may be non-zero, a second area table and a third area table are required. If RFX and RSX are zero, but RTX may be non-zero, then the third array of the area is required.

[0094] The exception is recognized when the ASCE element for the address space does not mean the top level of the array (starting with the first area table and continuing down to the segment table) needed to translate the address space reference.

Dynamic translation of the virtual address [0095] Reference is now made to Figure 4 illustrating one embodiment in which the effective control element ASCE, designated in Figure 3, is used to determine the first translation table in the hierarchy of translation tables used for virtual address translation.

[0096] In one embodiment, control register 1 (CR1) includes a PASCE control element. Control register 7 (CR7) contains the SASCE check element. Control register 13 (CR13) contains a HASCE control element, as well as an entry of a second address table array (ASTE), which is obtained by an Access-Register-Translation (ART) translation process, contains an address space control element defined by access register. The effective ASCE 400 control element is selected from one of these locations.

[0097] The first portion of the effective control element ASCE 400 includes the origin of the table 402, which includes the start address denoting either the first area table, the second area table, the third area table, or the segment table. The beginning of the array (bits 0

..51) is supplemented with 12 binary zeros to form the 64-bit address of the beginning of the highest translation table in the hierarchy of translation tables to be used for translation of the virtual address. The effective ASCE 400 also includes a control bit (R) 404 of the real space and bits DT 406. If the control bit (R) of the real space is zero, then the DT bits are decoded by the selector 408 to determine what specific start address is the beginning of the table 402 If the DT bits have the value three (binary 11) then the origin of the table 402 means the first array of area 410. If the DT bits have the value two (binary 10), then the beginning of the table 402 is the first array of area 412. If the DT bits they have the value of one (binary 01), then the beginning of the table 402 means the third array of area 414.

[0098] The first area table, the second area table or the third area table is sometimes simply referred to as an area table. Similarly, the designation of the first area table, the designation of the second area table, or the designation of the third area table is sometimes referred to as the area table designation. Area, segment and page tables reflect the actual real memory allocation. A page is a term used to assign virtual memory. Real memory is distributed in fixed blocks. The pages do not have to be adjacent in real memory even though they are assigned to a set of sequential virtual addresses.

[0099] When the ASCE control element, used in translation, is a first area table design, the translation process consists of a multi-level browse, using for example a first area table, a second area table, a third area table, a segment table, and possibly a page table. These arrays reside in real memory or absolute memory. When an ASCE element is a designation of a second area table, a third area table designation or a segment table designation, browsing in table levels above the marked level is skipped and the upper level tables themselves are skipped.

[0100] Reference is now made to Figure 5A illustrating one embodiment of a dynamic translation of a virtual address using a hierarchy of translation tables.

[0101] The effective ASCE 400 element of figure 4 includes DT 406 bits of the type designation.

If the control bit (R) 404 of the real space of the ASCE element is zero, then the DT bits are decoded by the selector 408 to determine which start address is denoted by the beginning of the table 402. If the control bit (R) 404 of the real space is one then, dynamic translation of the address occurs, as shown in node D 564 of Figure 5B.

[0102] If the DT bits have the value of three (binary 11) in the selector 408, then the designated first table in the hierarchy of translation tables is the first array of the area. The beginning of the table 402 is arithmetically added, at 502, the first region index (RFX) 508 of the virtual address to reference the entry 506 of the first area table in the first region table. The beginning of the array (either with 12 zeros appended on the right side or multiplied by 4096) is added to the product of the index multiplied by 8 (or the index with three zeros appended to the right). The entry of the first region table includes the beginning of the second area table 504 to the next lower table in the hierarchy of translation tables used in translation. The next lower table in relation to the first area table is the second area table. If the bit (I) of the invalid entry in the first area array is equal to one, then the entry of the first area table is invalid and can not be used in translation. The condition of the exception is indicated.

[0103] If the DT bits have the value of two (binary 10) in the selector 408, then the designated first table in the hierarchy of translation tables is the second array of the area. The beginning of the table 402 is arithmetically added, at 510, with the second virtual domain address index (RSX) 516 to reference the 514 entry in the second area table. The beginning of the array (either with 12 zeros appended on the right side or multiplied by 4096) is added to the product of the index multiplied by 8 (or the index with three zeros appended to the right). The entry of the second area table includes the beginning of the third table of area 512 to the next lower table in the hierarchy of translation tables used for translation. The next lower table in relation to the second area table is the third array of the area.

[0104] If the DT bits have the value of one (binary 01) in the selector 408, then the designated first table in the hierarchy of translation tables is the third array of the area. The beginning of the table 402 is arithmetically added, at 518, with the third area index (RTX) 524 of the virtual address to reference entry 522 in the third area table. The beginning of the array (either with 12 zeros appended on the right side or multiplied by 4096) is added to the product of the index multiplied by 8 (or the index with three zeros appended to the right). The entry of the third area table contains the beginning of the segment table array 520 to the next lower table in the hierarchy of translation tables used for translation. The next lower table in relation to the third area table is the segment table.

[0105] If the DT bits have a value of zero (binary 00) in the selector 408, then the designated first table in the hierarchy of translation tables is a segment table. The beginning of the table 402 is arithmetically added, at 526, with the segment index (SX) 532 of the virtual address to reference the entry 530 in the table of the segment. The beginning of the array (either with 12 zeros appended on the right side or multiplied by 4096) is added to the product of the index multiplied by 8 (or the index with three zeros appended to the right). The segment table entry contains either the start address to the page table or the absolute segment frame address (SFFA) shown in 528. If the bit (I) of the invalid entry in the segment table is equal to one, then the segment table entry is invalid and the condition of the exception is indicated .

[0106] At 538, a format control (FC) segment table entry (STE) check is tested. If the STE format control bit is one, then the segment table entry 530 includes the segment frame absolute address (SFAA) 552 and the dynamic address translation continues with the node 562 of Figure 5C. Otherwise, the segment table entry obtained from the segment table contains the address of the origin of the page table and the dynamic translation of the address continues with respect to the node 560 in Figure 5B.

[0107] Referring now to Figure 5B, if the STE format control bit in the segment table entry is zero, then the segment table entry derived from the segment table includes the start address to the next lower table in the hierarchy of the translation tables. The next lower table is the page table. The beginning 528 of the page table obtained from entry 530 of the segment table of FIG. 5A is arithmetically added, at 538, with the page index (PX) 534 of the virtual address to reference page 542 of the page table. The beginning of the array (either with 11 zeros appended to the right or multiplied by 2048) is added to the product of the index multiplied by 8 (or the index with the three zeros appended to the right). The page table entry contains the actual page frame address (PFRA) 546. When the most left-sided address bits of the actual page frame are concatenated, at 548, with the byte index (BX) 536 of the virtual address, a 64-bit real address 550 is obtained. This 64-bit real address can be further subjected to a prefix operation to create absolute address. The translated virtual address refers to the desired 4K bytes of data (4096 bytes) in the main memory.

[0108] Preferably, the information used for dynamically translating the virtual address into a memory address is stored in the popup translation buffer tab together with the address of the memory block associated with the virtual address. Another access to the memory can quickly translate the virtual address by comparing the ASCE information and the virtual address information with the bookmark translation buffer tabs. If it turns out that the bookmark is a virtual address bookmark, you can use the memory block address from the popup translation buffer instead of making a slow sequential access to each associated translation table. In one embodiment, a real page frame (PFRA) address with a tab comprising, for example, an ASCE element and an RX part,

[0109] Reference is now made to Figure 5C. If the STE format control bit in segment table entry 530 is one, then the segment table entry includes the segment frame absolute address (SFAA) 552. When the leftmost bits of the absolute segment frame address are concatenated, at 554, with page index 534 and index byte 536 of the virtual address, a 64-bit absolute address 556 is obtained. The translated virtual address refers to the desired large data block in the main memory. A large data block is at least 1 megabyte (1.048,576 bytes).

[0110] In one embodiment, the segment frame absolute (SFAA) address along with the virtual RX and SX address portions are stored in the cache translation buffer 544. The subsequent translation of this virtual address is then obtained from the information stored in the cache translation buffer.

Translation Table Formats [0111] Embodiments of various translation table entries in the hierarchy of translation tables used in the translation process are as follows.

Area table entries [0112] The term "area table entry" means an entry of the first area table, entry of a second area table, or entry of a third area table. Entries retrieved from the first area table, the second area table, and the third area table have the following formats. The level (first, second or third) of the table containing the entry is identified by the table type (TT) bits in the entry.

[0113] In one embodiment, the entry formats of the first area table, the entry of the second area table, and the third area table entry are illustrated in Figure 20. [0114] Beginning of the second area table, the beginning of the third area table, and the beginning of the segment table: The entry of the first region table contains the beginning of the second area table. The entry of the second area table contains the beginning of the third area table. The entry of the third area table contains the beginning of the segment table. The following description refers to each of the three origins of arrays. Bits 0-51 of the entry, with 12 zeros appended to the right, form a 64-bit address, which marks the beginning of the next lower level table.

[0115] Protection bit (P) DAT: When a DAT is used, bit 54 is treated as an ALTERNATIVE with a DAT protection bit in the entry of each subsequent area table, segment table entry and, where applicable, a page table entry used in translation. Therefore, when this bit is one, DAT protection applies to the entire area or areas specified by the region table entry. When the enriched DAT functionality is not installed, or when the functionality is installed, but the enabling bit of the enriched DAT is zero, then bit 54 of the region table entry is ignored.

[0116] Offsetting the second area table, offsetting the third area table, and moving the segment table (TF): The entry of the first region table includes the offset of the second area table. The entry of the second area table contains the shift of the third area table. The entry of the third area table contains the segment table offset. The following description applies to each of these three table shifts. Bits 56 and 57 of the entry define the length of the part of the next lower-level table that is missing at the beginning of the table, i.e. the bits define the location of the first entry actually existing in the next lower-level table. These bits define the length of the missing part in units of 4096 bytes, thus making the length of the missing part expressed in multiples of 512 entries. Length of the missing part, in units of 4096 bytes, it equals TF values. The contents of the offset field, in conjunction with the length field, bits 62 and 63, are used to determine whether a part of the virtual address (RSX, RTX or SX) intended for translation via the next lower level table means an entry that actually exists in the table.

[0117] Bit of the region invalid (I): Bit 58 in the entry of the first area table or the entry of the second area table controls whether a set of regions associated with that entry is available. Bit 58 in the entry of the third area table controls whether a single associated area is available with this entry. When bit 58 has a value of zero, then the address translation is done by using the area table entry. When this bit is one, then this entry can not be used for translation.

[0118] Table type (TT) bits: Bits 60 and 61 of the first area table entry, the second area table entry, and the third area table entry identify the level of the table containing the given entry as follows: Bits 60 and 61 must identify the correct array level, taking into account the type marking the table, that is, using the ASCE element in translation and the number of table levels that have been used so far; otherwise an exception to the translation specification is considered. The following table shows the array type bits:

<td>Bits 60 and 61</td><td>Area table level</td>

<td>11</td><td>First</td>

<td>10</td><td>Second</td>

<td>01</td><td>Third</td>

Bolds of the array type for arrays of area arrays [0119] The length of the second area table, the length of the third area table, and the length of the segment table (TL): The entry of the first area table contains the length of the second area table. The entry of the second area table contains the length of the third area table. The entry of the third area table contains the length of the segment table. The following description applies to each of these three table lengths. Bits 62 and 63 of the entry specify the length of the next lower-level table in units of 4,096 bytes, making the length of the array change in multiples of 512 entries. The length of the next lower level table, in units of 4096 bytes, is one more than the TL value. The contents of the length field, in conjunction with the offset field, bits 56 and 57, are used to determine, whether the part of the virtual address (RSX, RTX or SX) for translation via the next lower-order table means the entry that actually exists in the table. All other bit positions of the region table entry are reserved for possible later extensions and should contain zero; otherwise, the program may not work in the future. When using enriched DAT, the reserved bit positions of the area table entry should contain zero, even if the entry in the array is incorrect. otherwise, the program may not work in the future. When using enriched DAT, the reserved bit positions of the area table entry should contain zero, even if the entry in the array is incorrect. otherwise, the program may not work in the future. When using enriched DAT, the reserved bit positions of the area table entry should contain zero, even if the entry in the array is incorrect.

Segment table entries [0120] When the enriched DAT does not apply or when the enhanced DAT is used and the STE format check bit 53, the segment table entry 53 is zero, the entry taken from the segment table in one embodiment has the format illustrated in Figure 21. [0121] ] When the enriched DAT applies and the STE format control bit is one, then the entry taken from the segment table in one embodiment has the format illustrated in Figure 22.

[0122] The selected fields in the segment table entry are allocated as follows:

Start of page table: When enriched DAT is not applicable or when enriched DAT applies, but the STE format bit 53, segment table entry is zero, bits 0 - 52, with 11 zeros appended to the right, form a 64-bit address which means the start of the page table. It is not possible to predict whether this address is real or absolute.

[0123] Absolute segment frame address (SFAA): When an enriched DAT applies and the STE format control bit is one, bits 0-43 of the entry, with 20 zeros appended to the right, form the 64-bit absolute segment URL.

[0124] ACCF (AV) Expiry Control: When the enriched DAT applies and the STE format control bit is one, bit 47 is the access control bit and the import control bit (ACCF) of the validity check. When the AV control value is zero, bits 48-52 of the segment table entry are ignored. When the AV control value is one, bits 48-52 are used as described below.

[0125] Access control bits (ACCs): When the enriched DAT applies, when the STE format control is one, and the AV control value is one, bits 48-51 of the segment table entry contain access control bits that can be used to any key-controlled access check that applies to this address.

[0126] Download protection bit (F): When the enriched DAT applies, when the STE format control is one, and the AV checksum is 1, bit 52 of the segment table entry contains a download protection bit that can be used for any key-controlled access check that applies to this address.

[0127] STE format control (FC): When enriched DAT applies, bit 53 is the format control bit for the segment table entry, as follows:

- When the FC bit is zero, bits 0-52 of the entry form the beginning of the page table, while bit 55 is reserved.

- When the FC bit is one, then the bits 0 - 43 of the entry form the absolute address of the segment frame, bit 47 is the ACCF validity bit, bits 48 - 51 are access control bits, bit 52 is the download protection bit, and bit 55 is the cancel bit registration changes. When the enriched DAT does not apply, bit 53 is ignored.

[0128] DAT protection bit (P): Bit 54, when it is one, indicates that DAT protection applies to the entire segment.

- In case the enriched DAT does not apply, bit 54 is treated as an ALTERNATIVE with a DAT protection bit in the page table entry used for translation.

- When an enriched DAT applies, then the DAT protection bit in any and all field table entries used in translation is treated as an ALTERNATIVE with a DAT protection bit in the segment table entry; when the STE format control bit is zero, then the DAT protection bit in the STE is also treated as an ALTERNATIVE with a DAT protection bit in the page table entry.

[0129] The change-change-cancellation bit (CO): When the enriched DAT applies, and the STE format control bit is one, then the segment table entry bit 55 is the change-recording cancellation bit for that segment. When the enriched DAT does not apply or when the enriched DAT applies, but the STE format control bit is zero, then the segment table entry bit 55 is ignored.

[0130] Bit of the segment invalid (I): Bit 58 controls whether the segment associated with the segment table entry is available.

- When this bit is zero, the address translation is performed using the segment table entry.

- When this bit is one, the segment table entry can not be used for translation.

[0131] Bit of the common segment (C): Bit 59 controls the use of a copy of the segment table entry from the popup translation buffer. When the enriched DAT does not apply or when the enriched DAT applies, but the format control bit is zero, then bit 59 also controls the use of the page table copy from the popup translation buffer by the segment table entry.

- Zero identifies the private segment; in this case, the segment table entry and each table of the page it represents can only be used in conjunction with the source of the segment table, which is the segment table in which the segment table entry is located.

- one identifies the common segment; in this case, the segment table entry and each page table it represents can be further used to translate addresses immune to the sequence index, even though a different segment table is specified.

[0132] However, copies of the segment table entry and each page table from the common translation buffer for the common segment are not applicable if the private space control bit, bit 55, is one in the ASCE element used in translation or if that ASCE element is a designation real space. The common segment bit must be zero if the segment table entry is retrieved from memory during translation when the private space control bit is one in the used ASCE. Otherwise, the exception of the translation specification is considered.

[0133] Table-type (TT) bits: Bits 60 and 61 of the segment table entry have a value of 00 binary in order to identify the level of the table containing the entry. The meanings of all possible bit values ​​60 and 61 in a page table entry or segment table entry are as follows:

<td>Bits 60 and 61</td><td>The level of the board</td>

<td>11</td><td>The first area</td>

<td>10</td><td>Second area</td>

<td>01</td><td>Third area</td>

<td>00</td><td>segment</td>

Table Bits 60, 61 [0134] Bits 60 and 61 must identify the correct level of the table, taking into account the type of table designation, i.e. the ASCE element used for translation and the number of table levels that have been used so far; otherwise, the exception of the translation specification is recognized. All other bit positions of the segment table entry are reserved for possible future extensions and should contain zero; otherwise, the program may not work in the future. When enriched DAT applies, the reserved bit positions of the segment table entry should contain zero, even if the array entry is not valid.

Page table entries [0135] In one embodiment, the entry retrieved from the page table has a format, as illustrated in Figure 23.

[0136] The selected entry fields of the page table are allocated as follows:

Real-time page address (PFRA): Bits 0 - 51 are the left-most bits of the real memory address. When these bits are concatenated with the 12-bit virtual address byte field on the right, a 64-bit real address is obtained.

[0137] Bit of the page (I) invalid: Bit 53 controls whether the page associated with the page table entry is available. When this bit is zero, the address translation is done by using the page table entry. When the value of this bit is one, then the page table entry can not be used for translation.

[0138] DAT protection bit (P): Bit 54 controls whether write access can be performed on this page. This protection mechanism is an addition to key-controlled protection mechanisms and low address protection. This bit does not affect download access. If this bit is zero, entries on the page are allowed, with the following additional restrictions:

- A zero protection DAT bit in the segment table entry used for translation.

- When the enriched DAT applies, then the DAT protection bit is zero in all entries of the area table used for translation.

- Other protection mechanisms [0139] If this bit is one, the entries are not allowed. If there are no higher precedence exception conditions, an attempt to write when the DAT protection bit is one causes a protection exception to be recognized. The DAT protection bit in the segment table entry is treated as ALTERNATIVE with bit 54 when determining whether DAT protection applies to the page. When enriched DAT applies, then the DAT protection bits in all region table entries used in translation are also treated as ALTERNATIVES with bit 54 in determining whether DAT protection applies.

[0140] Bit of canceling the change registration (CO): When the enriched DAT does not apply, then the page table entry bit 55 must contain zero; otherwise, the exception of the translation specification is recognized as part of the instruction execution using this entry for address translation. When the enriched DAT applies and the STE format control bit is zero, then the page table entry bit 55 is the change canceling bit for this page.

[0141] The location of the entry bit 52 must contain zero; otherwise, the exception of the translation specification is recognized as part of the instruction execution using this address translation entry. Bit positions 56 - 63 are not assigned and are ignored.

Another embodiment of dynamic address translation [0142] This chapter describes the translation process performed implicitly before using a virtual address to access primary memory.

[0143] Virtual address translation is controlled by a DAT mode bit and address space control bits in the program status word and by ASCE elements in control registers 1, 7 and 13 and as determined by access logs. When the ASCE element used in translation is the first area table design, the translation is performed using the first area table, the second area table, the third area table, the segment table, and the page table, all of which reside in real memory or absolute memory. When an ASCE element is a lower-level table designation (a designation of a second area table, a third area table, or a segment table designation), then the translation is done using only the levels of arrays starting from the marked level, and virtual address bits, which, if they did not have a value of zero, would require the use of a higher-level table or levels, must be equal to zero; otherwise, the exception of type ASCE is recognized. When an ASCE element is a real memory designation, then the virtual address is treated as a real address, while table entries in real memory or absolute memory are not used.

[0144] The ASCE element used for the translation of a specific address is called an effective ASCE element. According to what was said when the main virtual address is translated, the contents of control register 1 are used as an effective ASCE element. Similarly, the content of control register 7 is used for the secondary virtual address; for the virtual address specified by the AR access register, the ASCE element defined by the access register is used; and the content of the control register 13 is used for the home virtual address.

[0145] When the real memory control bit in the effective ASCE element is zero, then the type of the sign in the ASCE determines the type of the table designation: the first area table, the second area table, the third area table, or the segment table. The corresponding part of the virtual address (the first area index, the second area index, the third area index or the segment index) is checked for the length field of the table in the designation and is added to the beginning in the designation to select the entry in the marked table. If the selected entry is outside its array, as determined by the array length field in the designation, or if the I bit has the value one in the selected entry, the first translation exception of the area is recognized, the second exception of region translation, the third translation exception of the area or the exception of the segment translation, depending on the level of the table specified by the designation. If the array type bits in the selected entry do not indicate the expected array level, an exception to the translation specification is recognized.

[0146] The table entry selected via the effective ASCE means the next lower level table to be used. If the current table is the first region table, the second area table, or the third area table, then the next part of the virtual address (the second area index, the third area index, or segment index, respectively) is checked for the array shift fields and array length in the current array entry and is added to the beginning of the entry in order to select the entry in the next lower level table. If the selected entry in the next table is outside its table, as determined by the array shift fields and the length of the array in the current table entry, or if the I bit is one in the selected entry, the second exception of the region translation is recognized, the third region translation exception or the segment translation exception, depending on the level of the next table. If the array type bits in the selected entry do not indicate the expected array level, an exception to the translation specification is recognized.

[0147] Processing of a portion of the virtual address via successive levels of arrays is continued until the segment table entry is selected. The segment table entry contains a page protection bit that applies to all pages in the specified segment. [0148] The portion of the virtual address with the page index is added to the beginning of the page table in the segment table entry to select the entry in the page table. If in the page table entry, bit I has the value of one, a page translation exception is recognized. The page table entry contains the leftmost real address bits that represent the virtual address translation and includes a page protection bit that applies only to the page specified by the page table entry.

[0149] The virtual address byte index field is used in unchanged form as the most right-sided real address bit positions.

[0150] In order to eliminate the delay associated with the references to the translation tables in the real memory or absolute memory, the information retrieved from ta5bic is usually also put in a special buffer, a handheld translation buffer, and subsequent translations using the same table entries can be performed using information stored in a popup translation buffer. The handheld translation buffer can also write virtual address translations into real ones associated with the actual memory designation.

[0151] Whenever an actual or absolute memory is accessed during the address translation process for retrieving an entry from an area table, segment table, or page table, key controlled protection does not apply.

Browsing in an array labeled by an ASCE element [0152] The DT control, bits 60-61 of the effective ASCE element, determines both the type of ASCE table designation of the part of the virtual address to be translated using the marked array, as follows:

Bits 60 and 61

Type of designation Part of the virtual address translated by an array

The first array of the area

The second array of the area

The third array of the area

Segment table

The first area index (bits 010)

Second area index (bits 11-21)

Third area index (bits 22-32)

Segment index (bits 33-43)

Translation via the marked array [0153] When bits 60 and 61 are 11 binary, the part of the virtual address with the first index of the area, in conjunction with the beginning of the first area table included in the ASCE, is used to select the entry from the first table of the table. The 64-bit address of the first area table entry in real memory or absolute memory is obtained by attaching 12 zeros to the right of bits 0 - 51 in the first area table designation and adding the first area index with the three rightmost and 50 most left-sided zeros. As part of the process of browsing the first area table, bits 0 and 1 of the virtual address (which are bits 0 and 1 of the first index of the area) are compared with the length of the table, bits 62 and 63 of the first area table design to determine if the addressed entry is within the first area table. If the value in the array length field is less than the value in the corresponding bit positions of the virtual address, the first exception of the region translation is recognized. The comparison with the length of the table can be omitted if the equivalent of the entry of the first area table from the popup translation buffer is used for translation. The entry taken from the first area table indicates the beginning and determines the offset and length of the corresponding second area table. the first exception of the translation of the area is recognized. The comparison with the length of the table can be omitted if the equivalent of the entry of the first area table from the popup translation buffer is used for translation. The entry taken from the first area table indicates the beginning and determines the offset and length of the corresponding second area table. the first exception of the translation of the area is recognized. The comparison with the length of the table can be omitted if the equivalent of the entry of the first area table from the popup translation buffer is used for translation. The entry taken from the first area table indicates the beginning and determines the offset and length of the corresponding second area table.

[0154] When the bits 60 and 61 of the ASCE element have a binary value, the portion of the virtual address with the second index of the area, in conjunction with the beginning of the second area table included in the ASCE, is used to select an entry from the second area table. Bits 11 and 12 of the virtual address (which are the bits 0 and 1 of the second index of the area) are compared with the length of the table in the ASCE. If the value in the array length field is less than the value in the corresponding bit positions of the virtual address, the second translation exception of the area is recognized. The comparison with the length of the table can be omitted if the equivalent of the entry of the second area table from the handheld translation buffer is used for translation. The process of browsing the second area table is also the same as the process of browsing the first area table;

[0155] When bits 60 and 61 of the ASCE element have a value of 01 binary, then the portion of the virtual address with the third index of the area, in conjunction with the beginning of the third area table included in the ASCE, is used to select an entry from the third area table. Bits 22 and 23 of the virtual address (which are the bits 0 and 1 of the third index of the area) are compared with the length of the table in the ASCE. If the value in the array length field is smaller than the value in the corresponding bit positions of the virtual address, the third translation exception of the area is recognized. The process of browsing the third area table is also the same as the process of browsing the first area table, including checking the array type bits in the third area table entry.

[0156] When the bits 60 and 61 of the ASCE element have the value 00 binary, then the portion of the virtual address with the segment index, in connection with the start of the segment table included in the ASCE element, is used to select the entry from the segment table. Bits 33 and 34 of the virtual address (which are bits 0 and 1 of the segment index) are compared with the length of the array in the ASCE. If the value in the array length field is less than the value in the corresponding bit positions of the virtual address, a segment translation exception is recognized. The comparison with the length of the table can be omitted if the equivalent of the segment table entry from the translation translation buffer is used for translation. The process of browsing the segment table is also the same as the process of browsing the first area table, including checking the array type bits in the segment table entry. The treatment is as follows:

- When an enriched DAT does not apply or when enriched DAT applies, but the STE format control bit is zero, then the entry taken from the segment table marks the beginning of the corresponding page table and the process proceeds as described in the section "Viewing the page table" below.

- When the enriched DAT applies and the STE format control bit is one, then the entry taken from the segment table contains the leftmost bits of the absolute segment frame address. If the DAT protection bit is one in each area table entry used in the translation or in the segment table entry and the reference to the memory for which the translation is performed is a record, a protection exception is recognized.

Browsing in a table marked by an area table entry [0157] When the effective ASCE element is an area table designation, the area table entry is selected as described in the previous section. Then the contents of the selected entry and the next part of the index virtual address are used to select the entry in the next lower level table, which can be another table of the area or segment table. When an array entry selected using an ASCE element is an entry of the first area table, the portion of the virtual address with the second area index, in connection with the beginning of the second area table included in the first area table entry, is used to select an entry from the second area table.

[0158] When creating the address of the entry of the second, third area table or segment table it is not possible to predict if the prefix, if any, is applied to the corresponding start of the table contained in the higher-level table entry before adding the array index value or the prefix is ​​applied to the address an array entry that is formed by adding the start of the array and the array index value.

[0159] As part of the process of reviewing the second area table bits 11 and 12 of the virtual address (which are bits 0 and 1 of the second region index) are compared with the table offset, bits 56 and 57 of the first table table entry and the table length, bits 62 and 63 of the entry. the first area table to determine whether the addressed entry is within the second area table. If the value in the array offset field is greater than the value in the corresponding bit positions of the virtual address or if the value in the array length field is less than the value in the corresponding bit positions of the virtual address, the second translation exception is recognized.

[0160] The second area table is the beginning and determines the offset and length of the corresponding third area table.

[0161] When the table entry selected using the ASCE element is a second area table entry or if the second area table entry was selected using the first area table entry content, then the virtual address portion with the third area index associated with the start of the third area table included in the entry the second area table is used to select an entry from the third area table. Bits 22 and 23 of the virtual address (which are the bits 0 and 1 of the third index of the area) are compared with the offset of the table and the length of the table in the entry of the second area table. The third translation exception of the area is recognized if the array offset is larger than bits 22 and 23 or if the length of the array is smaller than bits 22 and 23. The process of browsing the third area table is also the same as the process of browsing the second area table. The entry taken from the third table of the area marks the beginning and determines the offset and length of the corresponding segment table.

[0162] When the table entry selected using the ASCE element is a third area table entry or if the third area table entry is selected using the content of the second area table entry, the portion of the virtual address with the segment index associated with the start of the segment table included in the third table entry area is used to select an entry from the segment table. Bits 33 and 34 of the virtual address (which are bits 0 and 1 of the segment index) are compared with the table offset and the length of the array in the entry of the third area table. The segment translation error is recognized if the array offset is greater than bits 33 and 34 or if the array length is less than bits 33 and 34. The translation specification exception is recognized if (1) private space control, bit 55, in the ASCE element is one and (2) bit of the common segment, bit 59, in the entry taken from the segment table, has the value of one. The process of browsing the segment table is also the same as the process of browsing the second area table. The treatment is as follows:

- When an enriched DAT does not apply or when an enriched DAT applies, but the STE format control checksum is zero, then the entry taken from the segment table marks the beginning of the corresponding page table and processing continues as described below in the chapter "Viewing the table page. "

- When the enriched DAT applies and the STE format control bit is one, then the entry taken from the segment table contains the leftmost bits of the absolute segment frame address. If the DAT protection bit is one or in each area table entry used in the translation or in the segment table entry, and the reference to the memory for which the translation is performed is a record, a protection exception is recognized.

Browsing the page table When the enriched DAT does not apply or when the enriched DAT applies, but the STE format control checksum is zero, the portion of the virtual address with the page index in connection with the origin of the page table contained in the segment table entry is used to make choosing an entry from the page table.

[0164] The 64-bit address of a page table entry in real memory or absolute memory is obtained by attaching 11 zeros to the right from the start of the page table and adding a page index, with the three most right-handed and the 53 left-most zeros attached. Bit position 0 can not be executed.

[0165] The entry retrieved from the page table indicates the availability of the page and contains the most left-sided address bits of the actual page frame. The page invalidity bit, bit 53, is examined to determine if the relevant page is available. If the bit is one, a page translation exception is recognized. If the location of bit 52 contains a value of one, an exception to the translation specification is recognized. When the enriched DAT does not apply or the enriched DAT applies and the STE format control bit is zero, an exception of the translation specification is also recognized if the position of the bit 55 contains a value of one. If the DAT protection bit is one or in the segment table entry used for translation, in the page table entry or when the enriched DAT applies,

Formation of the real address and the absolute address [0166] When the effective ASCE element is a real memory designation, bits 0 63 of the virtual address are used directly as the real memory address. The actual address can be additionally subjected to prefixing to form an absolute address. When the effective ASCE element is not a real memory designation and no exceptions to the translation process occur, the following conditions apply:

- When an enriched DAT does not apply or when an enriched DAT applies, but the STE format control bit is zero, the actual page frame address is obtained from the page table entry. The actual address of the page frame and the part of the virtual address with the byte index are concatenated, with the real address of the page frame forming the leftmost part. The result is a real address that corresponds to the virtual address. The actual address can be additionally subjected to prefixing to form an absolute address.

- When enriched DAT applies and the STE format control bit is one, then the absolute address of the segment frame and the virtual address part with the page index and byte index are concatenated, from left to right, respectively, to form an absolute address that corresponds to the address virtual.

Recognition of Exceptions during Translation [0167] Array entries marked as invalid or containing invalid addresses or invalid formats may cause exceptions to be recognized during the translation process. Exceptions are recognized when information contained in table entries is used for translation and turns out to be incorrect.

[0168] Furthermore, an exception, for example an exception of an ASCE type, may occur if the virtual address to be translated is outside the range that can be represented by the top-level table labeled by the ASCE element. In one example, an ASCE type exception can occur as a result of the following pseudocode:

If ((DT &lt;3 AND RFX! = 0) OR (DT &lt;2 AND (RFX || RSX)! = 0) OR (DT &lt;1 AND

RTX! = 0)) then asce_type_exception ();

[0169] The DT bits are of the Designation type (bits 60-61 of the ASCE element). RFX is the first index of the area (bits 0 - 10 of the virtual address). RSX is the second area index (bits 11-21 of the virtual address). RX is the entire area index (bits 0 - 32 of the virtual address). An expert in this field will easily understand the logical operations and comparative arguments used in this pseudocode.

Translational Exit Qualifier (TXQ) [0170] With reference to the Translation Exemption Qualifier, it should be understood that the term "when enriched DAT applies" refers to the level (host or guest) at which the translation exception is shown. For example, TXQ is shown with the exception of host translation, whenever enriched DAT applies at the host level, regardless of whether it applies at guest level.

[0171] In the course of interrupting a program associated with the DAT mechanism, the translation exception identifier (TEID) is stored. When the enriched DAT functionality is installed and enabled, then the translation exception qualifier (TXQ) is stored in three bits of the TEID identifier. TXQ supports the configuration of the host in determining whether the interruption was caused by the host or by the guest. If the exception was caused by the guest, TXQ indicates whether the interruption was caused by the address contained in the leaf guest table entry, and if so, whether that leaf entry was a segment table entry or a page table entry. This allows the host to recognize references to areas that the visitor sees as 4K bytes in comparison to 1 megabyte frames. TXQ is designed so that it can be expanded,

[0172] In a program interruption due to an ASCE type exception, a first area table, a second area table, a third area table, a segment table, or a page table, the virtual address bits 0-51 that cause the exception are stored in bit positions 0-51 of the 168-position location. 175. This address is sometimes referred to as the translation exception address. Bits 52 - 56 locations 168 - 175 are unpredictable.

[0173] When the enriched DAT functionality is installed and enabled in the host configuration and an ASCE host type exception, field translation, segment translation, or page translation is recognized, the bits 57-59 include a translation exception qualifier (TXQ) according to what follows:

· 0 - The exception was caused by the current configuration (i.e., the guest DAT exception is shown during guest execution or DAT host exits during host execution).

· 1 - The exception has been associated with a virtual host address received from a guest address other than those listed below.

· 2 - The exception has been associated with the virtual host address obtained from the real address of the guest page frame.

· 3 - The exception has been associated with the virtual host address obtained from the absolute segment of the guest segment frame.

· 4 - 7 - Reserved.

TXQ 1 - 3 values ​​are designed only on host outputs that occurred during guest execution. DAT two-level.

[0174] As explained above, when performing a paged guest, a two-level DAT is performed: the guest virtual addresses are translated via the guest DAT, and when it can be applied, prefix to the absolute guest addresses, which are then treated as virtual addresses of the host in the main address space of the host and translated via the host DAT, as well as, where possible, prefixing to the absolute addresses of the host. During the DAT guest process, reference is made to the entries of the guest translation tables, located via the absolute addresses of the guests, which must also be translated via the host DAT, and also, when possible, to use the prefix. This process may result in DAT guest exceptions based on the guest and content table specifications, and any reference to the absolute guest address, to the guest table entry, or the guest's final guest translation target, can give host DAT exceptions. The corresponding TXQ must be generated for each of these exceptions for the above specifications. Figures 6 - 9 illustrate in detail the guest DAT process, and figures 9 - 11 illustrate the host DAT process.

Guest DAT Process [0175] Reference is now made to Figure 6, which illustrates a flowchart of one embodiment of dynamic translation of a guest address to a receiving point of a format control field from a guest segment table entry.

[0176] At 602, the virtual address of the guest to be translated is obtained. At 604, the start address, table level, and table length of the highest translation table used in the virtual address translation are obtained. The address of the beginning of the first translation table used in the translation is taken from the start field of the table in the ASCE element; the level of the table and the length of the table depend respectively on bits DT and TL in the ASCE element. An array shift for the highest used translation table is always treated as zero. At 606, the index portion of the virtual address to be used to reference the corresponding table entry in the translation table is first checked for the table offset and the length of the table, which define the minimum and maximum index values ​​represented in this table. If, at 606, the index is outside of this range, then further translation of the virtual address can not be performed. In one embodiment, a node 608 illustrates a guest translation exit corresponding to the level of the just indexed table (e.g., the exception of the first area table, the second area table, the third area table, or the segment table). Because the guest DAT exception is encountered during guest execution, TXQ is set to zero to select an exception at the current configuration level. The translation of this virtual address is then stopped at node 610. If, at 606, the index lies within an important range, then at node 612, the index multiplied by the length of the array entry is added to the beginning of the array in order to generate the absolute address of the table entry. At 614, this guest absolute address is treated as the virtual host address and the host DAT mechanism is used and, if applicable, the prefixing should be used to obtain the corresponding absolute host address. An additional parameter to the host DAT mechanism, for use in generating TXQ, if necessary, indicates that the source of the translation address is a guest address other than the actual address of the page frame or the real address of the segment frame. Figures 9-11, discussed below, show the host DAT process in detail. If, at 616, the host DAT process failed, then at 618, the guest translation process is terminated; the host DAT process will have an exception generated. The TXQ for this host exception is determined as described in Figure 9. If, at 616, the host DAT process has completed successfully, then at 620, the guest translation table entry is fetched using the resulting absolute host address. At 622, the invalid bit (I) is examined in the guest table entry. If it is set, then further translation of the virtual address can not take place using the table entry, because it has been marked as invalid; at 608, a guest translation exit is illustrated, with a TXQ value indicating the current configuration as above, and a further translation of that virtual address using this segment table entry stops at node 610. Otherwise, at 624, if the entry retrieved from the guest translation table is not a segment table entry, then the segment table in the hierarchy of translation tables has not yet been invoked. In this case, at node 626, the origin, offset and length of the next lower table in the hierarchy of guest translation tables is obtained from the table entry. The control returns to step 606, in which the next index field within the virtual guest address is examined for a new offset and length and, if it falls within the range, the index is used to reference the corresponding table entry in the next lower table used in translation. the beginning, offset and length of the next lower table in the hierarchy of guest translation tables, is obtained from the table entry. The control returns to step 606, in which the next index field within the virtual guest address is examined for a new offset and length and, if it falls within the range, the index is used to reference the corresponding table entry in the next lower table used in translation. the beginning, offset and length of the next lower table in the hierarchy of guest translation tables, is obtained from the table entry. The control returns to step 606, in which the next index field within the virtual guest address is examined for a new offset and length and, if it falls within the range, the index is used to reference the corresponding table entry in the next lower table used in translation.

[0177] For example, if the origin address of the first table of the guest translation table used in the translation is the first region table, the part of the guest virtual address with the RFX index is used to reference the first table entry of the first area table. If the table origin address is in the second area table, then the part of the virtual address with the RSX index is used to reference the entry of the second area table within the second area table. If the table origin address is in the third area array, then the part of the virtual address with the RTX index is used to reference the entry of the third area table within the third area table. If the beginning address of the array is to the segment table, it then uses the part of the virtual address with the SX index to reference the segment table entry inside the segment table. The following tables are invoked until the segment table entry is retrieved.

[0178] After retrieving the guest segment table entry, the segment table segment (STE) format control checksum is examined, at node 628, to determine if format control is enabled for this particular virtual address. If the STE format control is set to zero, then the dynamic address translation occurs relative to node 630. If the STE format control is one, then the dynamic address translation takes place with respect to node 632.

Dynamic translation of the guest address (STE format control bit is zero) [0179] Reference is now made to Figure 7, which illustrates the continuation of the operation network from node 630 of Figure 6, when the guest STE control bit is zero.

[0180] At node 710, the beginning address of the guest page table is obtained based on the entry of the guest segment table. In node 712, the part of the guest virtual address with the PX index multiplies by the length of the table entry and adds to the beginning of the guest page table to generate the absolute guest address of the guest page table entry. At 714, this guest absolute address is treated as the virtual host address and the host DAT mechanism is used, and if applicable, prefixing to obtain the corresponding absolute host address. An additional parameter to the host DAT mechanism, for use in generating TXQ, if necessary, indicates that the source of the translation address is a guest address other than the actual address of the page frame or the absolute address of the segment frame. If, at 716, the host DAT process failed, then at 718, the guest translation process is terminated; the host DAT process will have an exception generated. If, at 716, the host DAT process has completed successfully, then the node of the guest page is fetched at 712 using the resulting absolute host address. From the guest page table entry, an invalid bit (I) is obtained. If, at 722, the invalid bit (I) and the value one, then the virtual address translation can not be continued using this page table entry, because the entry has been marked as invalid; at 724, a guest page translation exception is shown, with a TXQ value indicating that the exception is due to translation at the current configuration level.If at 722, the invalid bit (I) is zero, then at 728, the real party frame address (PFRA) of the guest is connected to the virtual guest address part containing the byte index (BX) to generate the real guest address corresponding to the guest's virtual guest address. At 730, this guest real address is also subjected to guest prefixing to create an absolute guest address. At 732, this absolute guest address is treated as the virtual host address and the host DAT process is used and, if applicable, the prefixing to obtain the corresponding absolute host address. An additional parameter to the host DAT process, to be used for generating TXQ, if necessary, indicates that the source of the translation address is the real address of the guest page frame. If, at 734, the host DAT process failed, then at 718, the guest translation process is terminated; the host DAT process will have an exception raised. If, at 734, the host DAT process has completed successfully, then at 736, the resulting host absolute address is used to access the data block addressed by the translated virtual guest address.

Dynamic translation of the guest address (STE format control bit is one) [0181] Reference is now made to Figure 8, which illustrates the continuation of the activity network from node 632 of Figure 6, when the STE format control bit is one.

[0182] At node 810, the absolute guest frame address (SFAA) is obtained based on the part of the guest segment table entry. At 812, the absolute address of the guest segment frame (SFAA) is combined with the PX and BX portions of the guest virtual address to generate the absolute guest address of the desired data block in the main memory or in memory. At 814, this guest absolute address is treated as the virtual host address and the host DAT process is used and, if applicable, prefixed to obtain the corresponding absolute host address. An additional parameter to the host DAT process, for use in generating TXQ, if necessary, indicates that the source of the translation address is the absolute address of the guest segment frame. If, at 816, the host DAT process failed, it is then at node 818 that the guest translation process is terminated; the host DAT process will have an exception generated. If, at the node, the host DAT process has completed successfully, then at node 720, the resulting host absolute address is used to access the desired data block addressed by the translated virtual guest address.

Host DAT Process [0183] Reference is now made to Figure 9, which illustrates a flowchart of one host dynamic host address translation instance that can be invoked from a guest enrichment DAT process to obtain a format control field from a host segment table entry.

[0184] At 902, a host virtual address is obtained for translation. At 904, the start address, table level, and table length of the highest host translation table used in the virtual host address translation are obtained. The start address of the first host translation table used in translation is retrieved from the start field of the array in the ASCE element; the level of the table and the length of the table depend respectively on bits DT and TL in the ASCE element. An array shift for the highest used translation table is always treated as zero. At 906, the index portion of the virtual host address to be used to reference the corresponding table entry in the translation table is first checked for the table offset and table length, which designate the minimum and maximum values ​​represented in the table. If at index 906 the index is outside of this range, then further tran of the virtual address can not be kept; a host translation exception must be provided, corresponding to the level of the indexed translation table (for example, the exception of the first area table, the second area table, the third area table, or the segment table). In one embodiment, at 908, a test is performed to determine whether the guest program is currently being executed. If not, that is, if the host program is executed, then, at node 910, the host translation error is shown with the TXQ qualifier set, e.g. to zero, in order to mark the exception at the current configuration level. However, if a guest program is being executed, then, at node 912, the host translation error is shown with the qualifier TXQ set to the value of the address source that has changed from the visitor translation operation. In any case, the translation process is stopped at node 914.

[0185] If, at 906, the index is within a valid range, then, at node 916, the index multiplied by the length of the array entry is added to the beginning of the host table to generate the host host host absolute address. At node 918, the host translation table entry is retrieved using this absolute host address. At 920, the invalid bit (I) is examined in the host table entry. If it is set, then further translation of the virtual address can not be carried out using the table entry because it has been marked as invalid; control is passed to node 908 to show the host translation exception with the corresponding TXQ value as above and further translation of this virtual address using this segment table entry is stopped. Otherwise, at node 902, if the entry retrieved from the translation table is not a segment table entry, then the segment table in the hierarchy of translation tables has not yet been invoked. In this case, at node 924, the origin, offset and length of the next lower table in the hierarchy of translation tables are obtained from the table entry. The check returns to block 906, in which the next index field within the virtual host address is checked for a new offset and length and, if within the range, this index is used to reference the corresponding host table entry in the next lower level table used in translation . In this case, at node 924, the origin, offset and length of the next lower table in the hierarchy of translation tables are obtained from the table entry. The check returns to block 906, in which the next index field within the virtual host address is checked for a new offset and length and, if within the range, this index is used to reference the corresponding host table entry in the next lower level table used in translation . In this case, at node 924, the origin, offset and length of the next lower table in the hierarchy of translation tables are obtained from the table entry. The check returns to block 906, in which the next index field within the virtual host address is checked for a new offset and length and, if within the range, this index is used to reference the corresponding host table entry in the next lower level table used in translation .

[0186] For example, if the origin address of the first host translation table array to be used in translation is the first area table, then the part of the virtual host address with the RFX index is used to reference the first table table entry with the first area table. If the table origin address refers to the second area table then the part of the virtual address with the RSX index is used to reference the entry of the second area table within the second area table. If the table origin address is in the third area array, then the part of the virtual address with the RTX index is used to reference the entry of the third area table within the third area table. If the beginning address of the array is to the segment table, it then uses the part of the virtual address with the SX index to reference the segment table entry inside the segment table. The following tables are invoked until the segment table entry is retrieved.

[0187] After retrieving the host segment table entry, at node 926, the segment table segment (STE) format control bit is examined to determine if format control is enabled for this particular virtual address. If the STE format control is set to zero, the dynamic address translation takes place relative to node 928. If the STE format control is one, then the dynamic address translation takes place relative to node 930.

Dynamic host address translation (STE format control bit is zero) [0188] Reference is now made to Figure 10, which illustrates a continuation of the operation network from node 928 of Figure 9, when the host STE format control bit is zero.

[0189] At 1002, a start address is obtained to the host page table based on the entry of the host segment table. At 1004, the portion of the virtual host address with the page index (PX) multiplies by the length of the array entry and adds to the beginning of the page array to generate the absolute host address of the host page table entry. At 1006, the host page table entry is retrieved using this absolute host address. The invalid bit (I) is obtained from the host page table entry. If, at 1008, the validity bit (I) is one, then the virtual address translation can not be continued using this page table entry because this entry is marked as invalid; control is passed to node 940 of figure 9 to represent the host translation exception with the corresponding TXQ value, as above, and further translation of this virtual address using this page table entry is stopped. If, at 1008, the invalid bit (I) is zero, then at node 1010, the real host page frame (PFRA) address from the page table entry is combined with the virtual host address part with the byte index (BX) to generate the actual host address corresponding to the host's virtual host address.

At 1012, this real host address is further subjected to a host prefix operation to create the absolute host address. At 1014, this absolute host address is returned as a result of the host address translation to be used, e.g., in the guest DAT process that called it, or, if there is not one, to access the target data during host execution.

Dynamic host address translation (STE format control bit is one) [0190] Reference is now made to Figure 11, which illustrates the continuation of the activity network from node 930 of Figure 9, when the host STE format control bit is one.

[0191] At node 1102, the absolute host frame address (SFAA) is obtained from the part of the host segment table entry. At 1104, the absolute address of the host frame segment (SFAA) is combined with the virtual host address part with the PX and BX indexes to generate the absolute address of the desired data block host in the main memory or in memory. At 1106, this absolute host address is returned as the result of the host address translation, for use, for example, in the guest DAT process that called it, or, if there is not one, to access the target data during host execution.

[0192] The field of the translation exception qualifier (TXQ) therefore has the ability to indicate that the interrupt was caused by the address contained in the leaf guest table entry, and if so, whether this leaf entry was a segment table entry or a page table entry; that is, the exception was related to the virtual address of the host received from the real address of the guest page frame or to the virtual host address received from the absolute segment of the guest segment frame. The TXQ field is thus able to indicate the correct size of the host frame from which to store the guest frame. It is further capable of indicating that a larger frame size is needed, e.g. 2 gigabytes or more.

Commercial Implementation [0193] Although the IBM® z / Architecture architecture is mentioned herein, one or more aspects of the present invention may equally well be applicable to other machine architectures and / or computing environments using paged entities or similar constructs.

[0194] Commercial implementations of EDAT, TXQ functionality and other formats, instructions and attributes disclosed herein may be implemented either on the hardware platform by programmers, such as, for example, operating system programmers writing for example in assembly language. Such programming instructions may be stored on a storage medium intended to be executed natively in a computing environment such as, for example, IBM^® System with Server or possibly on machines performing different architectures. Instructions can be emulated in existing and future servers as well as on other machines or host computers. They can be performed on machines on which in general execution takes place in emulation mode.

[0195] In emulation mode, the specific emulated instruction is decoded and a procedure is performed to implement an individual instruction, e.g. in a subroutine or controller, or some other technique is used to provide a driver for specific hardware, such as in the knowledge of those skilled in the art of this description. Various software and hardware emulation techniques are described in numerous US patents, including, for example, 5551013, 5574873, 5790825, 6009261, 6308255 and 6463582. Many other descriptions further illustrate various ways to emulate a set of instructions constructed for a target architecture.

Other Variations and Architectures [0196] Various embodiments described herein are examples only. There may be many variations to these embodiments.

[0197] One or more of the functionalities of the present invention may be implemented on a software platform, firmware, hardware or any combination thereof. Embodiments of the invention are beneficial for many types of environments, including other environments that have multiple zones and non-partitioned environments. In addition, central processor complexes may be missing, but there are still multiple processors connected together. Various embodiments of the present invention can be used in single-processor environments.

[0198] If the environment is logically partitioned, more or fewer logical partitions may be included in the environment. In addition, numerous central computational complexes connected to one another can be present. In addition, other variants are possible.

[0199] Although the term &amp; quot; page &amp; quot; is used to determine a fixed or assumed size memory area, the page size may vary. Similarly, the block size can change. There may be different sizes of blocks and / or pages. A page can be an equivalent of a block. Other structures may optionally be used or otherwise implemented through software and / or hardware. In addition, many variations can be present in the examples described herein, including, without limitation, words of different sizes or addresses; different number of bits; bits in another order; more, less or other bits; more, less or other fields; fields in another order; different sizes of fields; and the like. Again, the above is given as an example only. Many varieties are possible.

[0200] A possible variation from the translation process described herein is treating the addresses of DAT table entries as real and not absolute addresses. Another possible variation is to perform a transformation between the guest's absolute address and the virtual address of the host, such as adding the beginning of the main guest memory or testing for the guest main memory limit, so as to limit the guest's absolute memory to the desired part of the host's address space.

Another variation would be to allow the user to refer to the absolute addresses of the guest in numerous host address spaces, selected for example by the content of access registers.

[0201] The computing unit includes paged entities, such as guests, hosts, other processors, emulators, virtual machines, and / or other similar structures. Bu20 for includes a memory area as well as other types of data structures, including but not limited to matrices or paged entities. The table may also include other data structures. The instruction may reference other registers. In addition, the page, segment and / or area may have different sizes, other than those described herein.

[0202] One or more aspects of the present invention may be included in a manufactured product (e.g. one or more computer programs) having, for example, a computer or machine readable medium. The carrier has implemented, for example, a computer program code or logic (e.g., instructions, code, instructions and others) to provide and facilitate the possibilities of the present invention. The produced product may be part of a computer system or it may be sold separately. Furthermore, at least one program storage device may be present, read by a machine executing at least one program of machine-executable instructions to perform the possibilities of the present invention.