Matrix expansion lattice

TECHNICAL FIELD [0001] The present invention relates generally to telecommunications switching systems, and in particular to large, efficient and economical crossover switching architecture.

BACKGROUND OF THE INVENTION [0002] Digital crossover systems are an integral part of the modern modern telecommunications transport network. They are increasingly used by all service providers, including exchange operators, long distance carriers and by-pass carriers. Significant advances in technology have allowed the evolution of cross-linked digital systems from the preparation of narrowband and test applications to cross-linking larger network signals in broadband frequency fields.

[0003] A broadband system is typically used to terminate high speed SONET optical network signals and electrical signals to terminate the path and prepare lower speed broadband signals. The broadband system also supports performance monitoring and test access functions. Normal wideband crossover systems use either a single-stage or three-stage Clos matrix architecture. In a three-stage matrix architecture, the crossover includes switches grouped into the initial stage, middle stage and end stage. The three-stage matrix architecture is best suited for applications with maximum capacity for cross-linking large amounts of signals. Single-stage matrix architecture organizes single-stage arrays into rows and columns, resulting in more switches than three-stage architecture. The article "Adaptive Routing in HighRadix Clos Network", John Kim et al, November 2006, XP031044199 discloses adaptive routing techniques in Closa networks to reduce latency and reduce variance in packet latency.

SUMMARY [0004] Although the three-stage Clos architecture is the basis for high-capacity cross-over tables, the inventors have noticed the need for matrices with even greater capacity. Embodiments configured in accordance with the invention facilitate the provision of such capacity.

A switchboard is proposed containing: (a) numerous three-stage switchboards; and (b) an extended switching board, in which the second stage of each of the three-stage switching boards includes an extended section containing switches that facilitate interconnection of each three-stage board with the expanded switching board; (c) where each of the numerous three-stage switching boards includes a first stage table having N inputs and K outputs and a third-stage table having K inputs and N outputs, where each second-stage table of each three-stage switch board adopts M local inputs from the first-stage table and provides M local outputs to the third stage switching board, each second stage switching board also provides P outputs to the extended table and takes P inputs from the extended table, where K, N, M and P are integers; and also (d) where the switching board contains numerous nodes and where, in each node, there are K second-degree tables, M first-degree tables and M third-degree tables, and where the number of extended switching boards in the extended table is equal to KX P.

A selection of optional claim properties is set out in the dependent claims.

DESCRIPTION OF THE FIGURES [0005] Figure 1 is a schematic diagram of a switching board according to an illustrative embodiment.

[0006] Figure 2 is a schematic diagram of a switching identifier table according to an illustrative embodiment.

[0007] Figure 3 is a block diagram of a computer processor and associated memory according to an illustrative embodiment.

[0008] Figure 4 is a flowchart of a switch selection process using the illustrative embodiment.

[0009] Figures 5 and 6 contain circuit diagrams in the form of a block array of switches 32 according to an illustrative embodiment.

[0010] Figures 7 and 8 are circuit diagrams of control elements for controlling switches, such as those disclosed in Figures 5 and 6.

[0011] Figure 9 is an enlarged view of one of the table switches shown in figures 5 and 6.

[0012] Figures 10 and 11 show waveform diagrams useful in illustrating the method of controlling the array switches of figures 1 and 2 with a reduced number of control elements.

DETAILED DESCRIPTION [0013] Figure 1 illustrates a switching board network 11 according to an illustrative embodiment. The system 11 of figure 1 is a relatively large system comprising a plurality of nodes 1 ... Q and an expanded table 21 also identified as node 0. In figure 1, each of the nodes, e.g. node 1, is drawn twice, once on the left side of the expanded table 21 and once to the right of the extended table 21. This designation is used so that interconnections, for example 15, 17, to the extended table on the left and right of the boards "B" in each of the nodes do not overlap the other parts of the drawing and are therefore more clearly visible.

[0014] All nodes 1 ... Q have a common three-stage structure formed of switching boards A, B and C, interconnected, as shown. The extended table contains the "D" switching column. Tables A, B, C and D are defined as follows:

Type A board has N inputs and K outputs.

The type B board has M + P inputs and M + P outputs.

Type C board has K inputs and N outputs.

The D-type array has Q inputs and Q outputs.

[0015] Furthermore, with respect to the topology of Figure 1, it can be seen that node 1 to Q only has tables of type A, B and C, while node 0 has only tables of type D. With respect to the number of tables, there are M tables of type A in each node from 1 to Q, there are K tables of type B in nodes from 1 to Q, there are M tables of type C in each node from 1 to Q, and there are R tables of type D in node 0, where R = KXP. Various tables can be identified as follows:

A (m) means the table of type A in node q where m = 1 .. M; and q = 1 .. Q.

B (k) means table type K in node q where k = 1 .. K; and q = 1 .. Q.

C (m) means the table of type C in node q where m = 1 .. M; and q = 1 .. Q.

D (r) is a table of type D at node 0 where r = P (k-1) + p; k = 1 .. K; p = 1 .. P.

[0016] Interconnection of the respective tables A, B, C and D are defined as follows:

1. The output k of table A (m) in node q connects with the input m of table B (k) in the same node q, where m = 1 .. M and k = 1 .. K.

2. Output m of table B (k) in node q connects with input k of table C (m) in the same node q, where m = 1 .. M and k = 1 .. K.

3. The output M + p of table B (k) in node q connects to the input q of table D (r = P (k1) + p) in node 0, where p = 1 .. P; k = 1 .. K; and q = 1 .. Q.

4. Output q of table D (r = P (kl) + p) in node 0 connects to input M + p of table B (k) in node le q, where q = 1 .. Q; k = 1 .. K; and p = 1 .. P.

In connection with the above, it can be noticed that the M + 1 ... M + p outputs on each left table of the B node and the M + 1 ... M + p inputs on each right table of the N node B facilitate the implementation of the type D tables of the extended table.

In the commutation table of figure 1, the switch is a device that can be activated to connect one input to one output of the same table. Each switch is represented by an S symbol (node, array type, array number, input, output). For example, S (I, A, 2,1,3) means a switch that connects input 1 with output 3 of type A table 2 at node 1; S (0, D, 3,2,5) means the switch that connects input 2 with output 5 of table number 3 of type D at node 0.

[0018] Using the switch notation convention just discussed, the switches of the tables A, B, C and D are identified as follows:

1. The switch that connects input x with output k of array A of type A in node q is identified by S (q, A, m, x; k), where q = 1 .. Q; m = 1 .. M; x = 1 .. N; k = I .. K.

2. The switch that connects the input m with the output n of the table type B in the node q is identified by S (q, B, k, m, n), where q = 1 .. Q; k = 1 .. K; m = 1 .. M; n = 1 .. M.

3. The switch that connects the input k with the output y of the array type C in node q is identified by S (q, C, m, k, y), where q = 1 .. Q; m = 1 .. M; k = 1 .. K; y = 1 .. N.

4. The switch that connects the input p with the output t of the array D of the type D at node 0 is identified by S (0, D, r, p, t), where r = 1 .. P (k-1) + p; p = 1 P; t = 1 .. P.

Furthermore, in the illustrative embodiment of Figure 1, type A board input is also seen as network input. The output of array type C is also known as network output. The path (continuity) between one network input and one network output (one type A array input and one type C array output) can be established by connecting five switches in series (S1, S2, S3, S4 and S5), where S1 is the switch that connects the input and output of the first array of type A; S2 is the switch that connects the input and output of a second type B array; S3 is the switch that connects the input and output of a third type D array; S4 is the switch that connects the input and output of the fourth array type B; and S5 is the switch that connects the input and output of the fifth (last) type C board.

[0019] As can be seen, there is more than one possible path (more than one set of switches (S1, S2, S3, S4, S5)) between any two network I / O points. In an illustrative embodiment, the following procedure is used to determine all possible paths (S1, S2, S3, S4, S5) between two I / O points.

[0020] First, the following constants are defined:

Q = number of I / O nodes in the network

N = number of entries on each type A board

N = also the number of outputs on each type C array

K = number of outputs on each type A board

K = also the number of entries on each type C board

M = number of local inputs (from table type A) on each table type B

M = also the number of local outputs (to table type C) on each table type B

P = the number of external inputs (from the D table) on each B table

P = the number of external outputs (this is a type D array) on each type B array

Next, for the port (X = 1 .. (N x Mx Q)) and for (k = 1 .. K), the following values ​​are defined for the variables q, m, and n:

q = int (X / (N x M x Q)) + 1 m = int (X / (N x Mx q)) + 1 n = X- int (X / (qxmx M) x N

In this case, the set of all switches S1, S2, S3, S4, S5 available for interconnection of the selected "X" port with the selected "Y" port on the same node, is selected as follows for (t = 1 .. M) and for port (Y = 1 .. N):

<td>^{S1 = S}(Q, A, m, n, k)</td><td>(Equation 1)</td>

<td>^{S2 = S}(Q, B, k, m, t)</td><td>(Equation 2)</td>

<td>^{S3 = S}(0, D, 0,0,0)</td><td>(Equation 3)</td>

<td>^{S4 = S.}(Q, B, k, m, t)</td><td>(Equation 4)</td>

<td>^{S5 = S}(Q, C, T, K, Y)</td><td>(Equation 5)</td>

and the set of switches S1, S2, S3, S4, S5 for connecting the "X" port on one node with the "Y" port on another node is determined as follows for (t = 1 .. .. P), for (h = 1 .. K) and for the port (y = 1..N):

<td>^{S1 = S}(Q, A, m, n, k)</td><td>(Equation 6)</td>

<td>^{S2 = S}(Q, B, k, m, t)</td><td>(Equation 7)</td>

<td>^{S3 = S}(0, D, Q (k-1) + t q))</td><td>(Equation 8)</td>

<td>^{S4 = S.}(W, B, k, t, h)</td><td>(Equation 9)</td>

<td>^{S5 = S}(W, C, h, k, Y)</td><td>(Equation 10)</td>

[0021] It will be appreciated by those skilled in the art that a key task in a system such as illustrated in figure 1 is to select the appropriate switches in nodes I ... Q and the expanded table 21 to complete the desired patch connection. For example, if it is desired to connect port "1" (port "X") of table type A on node 1 with port "1" (port "Y") of table type C on node 1, then the appropriate switches on node must be selected and closed 1 (not the switches in the extended table 21) to create the desired signal path. Accordingly, as said above, a "path" may contain a group or set of switches that in series connect the desired pair of ports ("X" and "Y") through the hardware system.

[0022] One approach to making the switch selection and the interconnection task just discussed will be to use the software to determine the appropriate group of switches in real time during the operation of the switching board in figure 1. This approach produces a huge excess of software and complexity. According to a preferred embodiment, this approach is avoided by using software to first create an array of switch identifiers based on a specific known switching system architecture, which greatly simplifies the selection of appropriate switches to create the desired path in real time of the system used. Therefore, such an array of switch identifiers is preferably determined and stored in the system as part of the system manufacturing process prior to the system being used by the end user. Then a relatively simple forward indexing operation can be used to designate those switches that can be closed to achieve the desired connection.

More specifically, in the illustrative embodiment of Figures 2 and 3, and as shown in Figure 4, after creating (step 101) of the switching system architecture, the software 61 running on the computer processor 57 generates an array of 55 identifiers switching (step 103) and stores table 55 in memory 59. As shown in figure 2, table 55 is divided into sub-tables, e.g. 71, 73. Each sub-table contains all sets of switches S1, S2, S3, S4, S5, which are able to connect the selected "X" port with the selected "Y" port. For example, all sets of switches SA (1,1) ... SN (1,1) for connecting the port "X" 1 with the port "Y" 1 are stored in table 71, while all sets SA (1,2) ... SN (1,2) for connecting the "X" port 1 and the "Y" port 2 are stored in sub-table 73 and so on. Each sub-table is defined by software programming steps 61, which may, for example, calculate for the specific pair of ports considered (X, Y) the above equations 1-5 or equations 6-10. Such software may be written, for example, in C ++ or any other appropriate language.

[0024] After generating the table of figure 2, for example before sending and installing the switching board, such as shown in figure 1, for example, switch selection software 63, which actually selects a specific set of switches (such as, for example, a set of switches SA1,1) in to create a connection between a pair of ports (such as 1.1 ports, for example), it only needs to use an index (e.g., "1.1") during real-time operation to access a set of 71 all possible switches to establish a specific port-to-port connection (step 105, figure 4). Then, in step 107 of Figure 4, for example, the switch selection software may perform a specific switch selection procedure using various criteria, such as known to those skilled in the art, to select a specific pair of switches from among those available.

[0025] The implementation of a cross-switched commutation architecture such as that shown in figure 1 can be enriched in some embodiments by implementing the approach of activating the switching device, which allows the elimination of a number of discrete control elements by the counter controlling the coils of parasitic EM devices with pulse-modulated electromotive force (EMF) to counteract the coupled switching of adjacent devices. According to an illustrative embodiment, the EMF duty cycle and polarization applied to parasitic paths is determined by the switching EMF tolerance and the proximity of the coupled EM device to the target device within the matrix array. The result is that EM devices in parasitic paths are not switched for any possible initial state, and the total number of controls required for large tables of EM devices, such as relays and solenoids, is significantly reduced. The implementation of the above approach is illustrated with reference to Figures 5-11.

[0026] Figures 5 and 6 show a table 32 of switching devices S1, S2, S3, ... S32. The individual switching devices shown are MEMS cantilever switches, but in other embodiments they can be switches or relays of a different type.

[0027] Each of the switches S1 ... S32 includes an activation coil (for example 21 in figure 9) having a positive terminal ("Y") and a negative terminal ("X"). According to the illustrative embodiment, eight positive terminal control elements and four negative terminal control elements are sufficient to switch ("close") each of the selected switching devices S1 ... S32. Eight positive controls produce the appropriate control signals AYS_ 01, AYS_02, AYS_03 ... AYS_08; while four negative control elements produce four corresponding control signals AXS_01, AXS_02, AXS_03, AXS_04.

[0028] Figures 7 and 8 show a control circuit for generating control signals AXS_01 and AYS_01, respectively. These controls can be conventional MOSFET controls. The control element of figure 3 is triggered by the gate signals AXS_HD_01 and AXS_LD_01, while the one of figure 4 is triggered by the gate signals AYS_HD_01 and AYS_LD_01.

[0029] The specific switching device S27 of the MEMS type is shown in enlargement in Figure 9. It can be seen that the coil 21 of this device S27 is controlled by the control signals AYS_01 and AXS_ 01. Lead 7 and 4 are the "input signal" and the leads 8 and 3 respectively are the outputs of the "return signal". The instantaneous magnetic field created by the energy pulse of the coil 21 begins to attract and close the respective signal paths through the respective bracket S23, S24. The brackets 23, 24 after the activation pulse of the coil 21 are held in place by a permanent magnet.

[0030] Figure 10 illustrates the pulse waveforms used when setting the switch S27, i.e. closing the brackets 23, 24, is desired. As can be seen, AXS_01 rises to a DC voltage positive for a period of time t1, which can be, for example, 200 microseconds. At the same time, AYS_01 drops to a DC voltage with a negative value in the same interval t1. The other "X" control signals AXS_02, AXS_03 and AXS_04 are pulsed according to a periodic sequence that varies between positive and negative voltage levels. Other control signals "Y" AYS_02 ... AYS-08 are controlled by impulse train, which can be the same, but with opposite polarization to control string AXS_02-04.

[0031] In this way, only the switch S27 receives the energy necessary to activate or "close" it, while the pulse-modulated energy prevents the erroneous release of the other switching devices in the array. As can be seen, the other three switches S25, S29, S31 in the 32-switch table of figures 5 and 6 are controlled by the output AYS_01 of the control circuit shown in figure 8. However, each of these other switches receives the appropriate modulated control signal "X" AXS_02, AXS_03, AXS_04, which prevents the tripping of these three switches S25, S29, S31.

[0032] To reset or reset the switch S27, the energy waveforms shown in figure 11 are used. In this case, AXS_01 contains a negative pulse of duration t2 and AYS_01 contains a positive pulse of duration t2. Mileage for

AXS_02 - 04 and AYS_02 -08 are the same as those of figure 10; thus, the switch 27 is reset without the other switches in the table being triggered incorrectly. [0033] With respect to switch S27, an impulse interval and voltage level supplied by AXS_01 and AYS_01 may usually be needed to close the switch. Such levels and durations will usually vary depending on the type of switch used, for example the MEMS switch or electromagnetic relay or solenoid. In addition, voltage levels and duty cycles of pulse-modulated waveforms, for example AXS_02, AXS_03, AXS_04 of Figure 10, will vary depending on the application, but are selected in each application to be sufficient to prevent erroneous triggering of other devices in the array. Routes analogous to those shown in Figures 10 and 11 are used to set and reset any specific switch among the other switches in the 32 switch table. With reference to the table of Figures 6 and 6, it can be seen that this type of table will conventionally require 4x8 + 4 (Ν · Μ + Ν) = 36 control elements, while in the illustrative embodiment 12 control elements are used.

[0034] The methods according to illustrative embodiments are effective in addressing arrays of EM devices that are symmetrical (N = M), asymmetrical (N&gt; M or N &lt;M) or also asymmetrical and non-orthogonal (array built of many asymmetrical under arrays with various segments N or M).

[0035] Those skilled in the art will recognize that various adaptations and modifications of the preferred embodiment just described can be configured. Therefore, it is understood that within the scope of the appended claims the invention may be implemented differently than it has been specifically described in this document.