Method and apparatus for error detection in a data block

TECHNICAL FIELD [0001] The invention relates generally to data transfer, and more specifically, to performing error detection in one field of a data block using an error detection mechanism in another field of the same data block.

BACKGROUND ART [0002] When transmitting data blocks between transmitting and receiving devices in a communication system via a wireless interface, a certain type of error detection and error correction mechanism is typically used to assist in decoding each data block on the receiving device to allow further processing of the data block. Here a data block is generally defined as a block of continuous bits containing information and / or signaling, and decoding is defined as the initial processing of a received data block to identify the received bits (e.g. as 1 or 0) and may include detecting and / or correcting errors in received bits. Signaling is taken into account when establishing and controlling network connections.

[0003] Generally, a data block has a predefined logical structure having many different types of fields for organizing bits in a data block, and one or more of these fields may include bits that allow error detection and / or error correction for that field. However, depending on the protocol used, some fields may contain error correction bits, but not error detection bits or limited error detection bits, due to the limitation of the number of bits resulting, for example, from the bandwidth restrictions associated with the physical channels through which the data block is transmitted. . There is such a limitation that the inability to detect errors in certain fields can cause quite significant problems regarding further processing of the data block if there are actually errors that go unnoticed.

[0004] An example of an air interface protocol that has a data block structure that includes fields having error correction but no error detection is the air interface protocol defined according to TS (Technical Specification) 102 361-1 ETSI - European Telecommunications Standards Institute (European Telecommunications Standards Institute). The data block structure identified in this technical specification is a packet that is defined as the smallest, predetermined block of continuous bits containing information or signaling. The TDMA package of Time Division Multiple Access (DMR) is described in more detail here. Digital Mobile Radio. Package (ang. burst) DMR TDMA contains, for example, the Data Type field Data Type), which identifies the type of data transmitted in the Information field, which is also included in the packet. There are a number of data types listed in the technical specification, including LC voice header Voice LC Header), Terminator with LC, CSBK, Data header Data Header), etc. As this field is subject to error correction (in this case corrective coding (FEC)) which is well known in the art, but not detecting errors, it is not possible for the receiver to know if the error correction in the Data Type field was successful. Therefore, under certain error conditions, incorrect processing may be possible for some types of packets.

[0005] For illustrative purposes, two examples of problems that may arise due to the inability to detect an incorrectly identified data type are further presented. In one example, CSBK could be mistakenly interpreted as a data header (which is the first packet 1

EP 2 052 482 B1 multi-packet data message) due to uncorrectable channel errors. As the data header contains a "Blocks to Follow" field, specifying how many additional packets belong to this transmission, and CSBK does not, the receiver treats the next packets as part of the data transmission. Accordingly, other transmissions, such as new voice transmissions, CSBK and new data transmissions are lost during this period of time.

[0006] As another example, the LC Terminator could be mistakenly interpreted as a LC LC (Voice LC Header). As many Terminator packets with LC are typically transmitted during a call hold time, potential side effects include causing the receiver to start processing a new voice transmission when none exist.

[0007] It is therefore desirable to have a method and apparatus for providing reliable error detection for a field without bits or with a limited number of bits reserved for error detection.

DESCRIPTION OF THE DRAWINGS [0008] Accompanying drawings, where similar reference numerals refer to identical or functionally similar elements through separate views and which, together with the detailed description below, are incorporated into the specification and form part thereof, serve to further present various embodiments and to explain various principles and advantages, all according to the invention.

Fig. 1 shows an example system implementing embodiments of the invention.

Fig. 2 shows an exemplary block of data according to embodiments of the invention.

Fig. 3 shows a method for detecting errors according to an embodiment of the invention.

Fig. 4 shows a method for detecting errors according to an embodiment of the invention.

Fig. 5 shows an example of error detection in the data block shown in Fig. 2 using the methods shown in Figs. 3 and 4.

Fig. 6 shows an example of error detection in the data block shown in Fig. 2 using the methods shown in Figs. 3 and 4.

Fig. 7 shows an exemplary error detection in the data block shown in Fig. 2 using the methods shown in Figs. 3 and 4.

Fig. 8 shows an example of error detection in the data block shown in Fig. 2 using the methods shown in Figs. 3 and 4.

Fig. 9 shows an example of error detection in the data block shown in Fig. 2 using the methods shown in Figs. 3 and 4.

Fig. 10 shows an example TDMA DMR packet according to embodiments of the invention.

Fig. 11 illustrates a method for detecting an error in the TDMA DMR packet shown in Fig. 10 according to an embodiment of the invention.

Fig. 12 illustrates a method for detecting an error in the TDMA DMR packet shown in Fig. 10 according to an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION [0009] Before describing in detail embodiments that are in accordance with the invention, it should be followed that the embodiments reside essentially in combinations of method steps and device components associated with the method and apparatus for detecting errors in a data block. 2

EP 2 052 482 B1

Accordingly, the device components and method steps are shown where appropriate with conventional symbols in the drawings, showing only those special details that are relevant to understanding the embodiments of the invention so as not to obscure the disclosure with details, which will be readily apparent to those skilled in the art. using this description. Therefore, it is important to realize that for simplicity and clarity of communication, ordinary and well-known elements that are useful or necessary in a commercially executable embodiment, such as Forward Error Correction (FEC) and interleaving, may not be shown to allow a less obscured view of these various embodiments.

[0010] It is important to realize that the embodiments of the invention described herein can be combined with one or more generic or specialized processors (or "processing devices") such as microprocessors, digital signal processors, custom processors and gate systems programmable by the user (FPGA) and unique, saved program instructions (including both application software, and hardware), which control one or more processors to implement, in combination with some non-processor systems, some, most or all of the functions of the method and apparatus for detecting errors in a data block described herein. Nonprocessor systems may include, but are not limited to, a radio receiver, radio transmitter, and user input devices. As such, these functions can be interpreted as steps of a method for performing the error detection of a data block described herein. Alternatively, some or all of the functions may be implemented by a state machine that has no program instructions written, or in one or more Application Specific Integrated Circuits (ASICs) in which each function or certain combinations of some functions are implemented as adapted logic. Of course, combinations of these approaches can be used. Both the state machine and ASIC are also considered herein as "processing device" for the purposes of the preceding discussion and the language of the claims.

[0011] Generally speaking, according to various embodiments, reliable error detection for a field in a data block is performed in the absence of limited detection bits or a limited number thereof. These embodiments can be applied to any data block structure, including the TDMA DMR package as defined in ETSI TS 102 361-1. For example, when generating a packet having (among other fields) an Information field with data bits and error detection bits (also referred to herein as error detection "parity"), and also having a Data Type field identifying the type of data bits in the Information field, error injection mask is selected based on the identified data type. The mask is applied to data bits and error detection parity to (usually) modify data bits, error detection parity, or both. The resulting packet is then sent to the receiving device. The receiving device receives the packet; identifies the data type; selects the error injection mask that corresponds to the identified data type and applies the error injection mask to the received data bits and the error detection parity in the Information field. After application, the resulting data bits and error detection bits can be used to confirm (under certain conditions) that the data type has been correctly identified.

[0012] This offers the advantage of reliable error detection for the Data Type field to protect against the problems identified above in communication between transmitting and receiving devices. Those skilled in the art will recognize that the above recognized advantages and other advantages described herein are only examples and are not understood as a complete representation of all the advantages of various examples 3

EP 2 052 482 B1 of the invention.

[0013] Referring now to the drawings, and in particular to Fig. 1, an exemplary wireless communication system implementing the embodiments of the present invention is indicated, generally indicated as 100. However, those skilled in the art will recognize and realize that the peculiarities of this illustrative example are not peculiarities of the invention itself, and that the information provided herein applies to various alternative settings. E.g, because the information described does not depend on the type of air interface protocol used or the channel access scheme (e.g., TDMA (Multiple access in time domain), CDMA (Multi-access in the field of code), FDMA (Multi-access in the frequency domain), and similar), this information can be applied to any type of air interface protocol and channel access scheme, although the examples provided herein describe the air interface protocol (for digital mobile radio using the TDMA channel access scheme) as defined in ETSI TS 102 361-1. In addition, the information contained herein can be used within any system and with any protocol that uses an error detection mechanism for reliable transmission and reception of data blocks, including systems using wireless links. In this state of affairs, other alternative implementations of the use of different types of wired or wireless protocols and channel access schemes are considered, and are within the scope of the various information described.

[0014] The wireless communication system 100 includes a communication device 102 and the communication device 104 may be, for example, a portable or mobile radio, a personal digital assistant, a mobile telephone, and the like. For the purposes of the following discussions, communication devices will be referred to as "radios", but in this field of technology they are also referred to as mobile stations, mobile devices, handsets, etc. In addition, in this embodiment, radios 102 and 104 communicate over the radio access network 106. However, those skilled in the art will recognize that any type of network is within the scope of information herein. Network 106 may include infrastructure such as, but not limited to, base stations (BS) (with a single BS 108 shown for clarity), base station controllers (not shown), network elements (such as mobile switching center, home location register, location register) guests, etc.) and the like to allow communication between radios having access to this network.

[0015] For example, radio 102 and radio 104 may communicate with each other by establishing a wireless link 102 or radio connection 110 with BS 108 via radio 102 through an available radio frequency (RF) channel and establishing wireless link 112 with BS 108 through radio 104 available radio frequency (RF) channel. As is well understood in the art, BS 108 generally includes a repeater device that can receive a signal from radio 102 via link 110 and retransmit that signal to radio 104 via link 112 or can receive a signal from radio 104 via link 112 and retransmit this signal to radio 102 via connection 110. For ease of display, only two radios and one BS are shown. However, those skilled in the art will realize that in a typical system it is served by a radio network having many more BS stations, a much larger number of radio devices than shown in Fig. 1. Furthermore, although in this embodiment the communication between radios 102 and 104 is illustrated as being enabled via BS 108, radios 102 and 104 can communicate using a direct mode of operation without BS. The information contained herein applies equally to direct operation between two radios.

[0016] Because the network 106 is a wireless network, which means that it supports a wireless or air interface protocol for signal transmission, both radios 102 and 104 and BS 108 contain transceivers that include a transmitter apparatus and a receiver respectively for transmitting and receiving RF signals. Radios 102 and 104 and BS 108 further include one or more of the processing devices mentioned above (e.g. DSP, microprocessor, etc.) and typically some type of conventional memory element to perform (among other functionalities) the air interface protocol and channel access scheme, supported by network 106.

[0017] Using these protocols, radios 102 and 104 may generate RF signals comprising one or more data blocks containing a plurality of fields for organizing continuous bits of information and / or signaling for transmission to another radio. As mentioned above, some of these fields may not include error detection or may include limited error detection to verify that bits in this field have been received and decoded correctly. According to the embodiments described herein, error detection for a field with or without limited error detection bits can be implemented using a field that includes error detection bits.

[0018] Turning now to Fig. 2, an exemplary data block according to the embodiments shown herein is generally indicated as 200. Data block 200 can be generated on radio 102 or 104 and has an overall logical structure including field 1 (210) and field 2 (220) for organizing information and / or signaling bits broadcast from radio 102 or 104 to another radio connected to network 106 . In the embodiments illustrated with reference to Figures 3-8, field 220 has no error detection. Thus, field 210 (which includes error detection) is used to perform reliable error detection for field 220, as provided herein. The information contained herein is not limited by the special information and / or signaling contained in fields 210 and 220 or the specific logical structure of data block 200, as long as at least one field includes error detection.

[0019] Furthermore, in Fig. 2 is an exploded view of a field 210 having a plurality of bits contained therein which include data bits 212 and error detection bits 214, with error detection calculated based on data bits. It should be noted that the arrows from data bits to error detection bits are not part of field 210, but are only used to illustrate that error detection bits are calculated from data bits. Error detection can be implemented using mechanisms such as cyclic redundancy check (CRC), checksum and simple parity check, to name a few. These error detection techniques are well known in the art and will not be further elucidated for brevity.

[0020] For simplicity of imaging, in the various embodiments described herein only a limited number of fields are shown. However, those skilled in the art will recognize that data block 200 may contain any number of fields and any structure of these fields as determined by the various protocols supported by the network and implemented in communications devices. For example, data block 200 may further include an additional field 3 (230), shown by dashed lines. The field 230 may also have no error detection bits or may have limited error detection bits, wherein the error detection mechanism in field 210 may further be used in another embodiment for detecting field 230 error (and field 220) as shown by reference to FIG. 9. In addition, although this has not been shown for simplicity, fields 210 and 220 (and 230) typically also contain some type of correction mechanism.

EP 2 052 482 B1 errors, such as, for example, FEC (correction coding). These error correction techniques are well known in the art and will not be further described herein for brevity.

[0021] Figures 3 and 4 show methods for detecting errors in a data block according to embodiments of the invention. FIG. 3 is a method performed in a transmitting device, and Fig. 4 is a method performed in the receiving device. The methods described by referring to figures 3 and 4 may be performed in communication devices, BS and base station controller, for example using a processing device which may include one or more of the processing devices described above, such as DSP.

[0022] Turning now to Fig. 3, method 300 performed on the transmitting device (e.g. radio 102) includes the step 302 of generating a data block containing the first field (e.g. 210), having the first set of bits that includes the error detection portion (e.g. 214), indicating the value of error detection based on another part (e.g. 212) the first set of bits and used to detect errors in decoding another portion (212) of the first set of bits, and the data block further comprises a second field (e.g. 220), having a second set of bits (not shown in Fig. 3). The error detection value is identified or indicated by bits ("e") in the error detection portion 214 of field 210, and this value is calculated based on the type of error detection technique used in the transmitting device.

[0023] In step 304, an error injection mask is selected based on the second set of bits in field 220. The error injection mask can be implemented in any number of forms, but generally contains a predetermined number of bits representing a specific mask value. The mask value, in turn, corresponds to the value represented by the bits contained in field 220. Typically, for a given number of N different values ​​that can be represented as bit values ​​in a second field, there are at least N different mask values ​​that correspond to the bit values ​​in the second field. Exemplary mask values ​​are given below for the embodiment explained with reference to figures 10 to 12.

[0024] In step 306, the first set of bits is "modified" with an error injection mask to generate a "modified" first set of bits, which is used to detect errors in decoding the second set of bits. The expression 'modifying the first set of bits with the error injection mask' is used synonymously with the expression 'applying the error injection mask to the first set of bits' and both generally refer to processing by which at least part of the first set of bits in field 210 is combined with the error injection mask ( value) using some type of arithmetic operation. In one embodiment, this arithmetic operation is a bit addition modulo 2, wherein if the sum of two bits is "2" then the value of this sum is represented as zero, i.e. 1 + 1 = 0. However, those skilled in the art should understand that another type of arithmetic may be used, such as, for example, Galois field arithmetic.

[0025] Furthermore, the expression "modified first bit set" does not necessarily mean that one or more bit values ​​in the first bit set are changed after the application of the error injection mask, even though this usually happens. This is because an error injection mask having a value of zero can be selected, which would cause the first bit set not to change. Accordingly, "modified first bit set" means that an error injection mask has been applied to the first bit set, regardless of whether this has changed the bit value.

[0026] In step 308, a data block with an error injection mask applied to the first set of bits 6

EP 2 052 482 B1 in field 210 is transmitted to a receiving device (e.g. radio 104). Fig. 4 illustrates method 400 performed on radio 104, receiving (in step 402) data block 200 having an error injection mask applied to the first set of bits contained in field 210, and data block 200 further has field 220 with a second set of bits.

[0027] Then, in step 404, the receiving device decodes the second set of bits to generate the decoding results for the field 220. In general and as stated above, the decoding means identify the bits and typically at least includes performing some type of error correction on the received bits. Any type of decoding process may be used in conjunction with the information contained herein, including but not limited to those mentioned above. At step 406, an error injection mask is selected that corresponds to the decoding results from field 220. In step 408, the first set of bits in field 210 is modified using the selected error injection mask to generate the modified first set of bits. Based on this modified first set of bits, it can be determined (in step 410) (among other things) whether the decoding results are correct using, for example, further processing techniques discussed below.

For example, in one implementation, error detection calculation may only be performed on some bits (e.g. 212) in the modified first bit set, and the calculated error detection value compared to the error detection value that was in field 210 of the received data block before the error detection calculation. This implementation is illustrated with reference to the embodiments shown in figures 5 to 9. For simplicity of display, only field 210 of data block 200 is shown, as it is the field to which the mask is applied and on which error detection calculations are performed. In another implementation, the error detection calculation may be performed on the entire modified first bit set including error detection bits, and the calculated error detection value compared to a predetermined value (e.g. zero value).

[0029] In all figures 5 to 9, field 210 in data block 200 is processed according to the information contained herein. However, field 210 is shown as having a different reference number as a result of applying an error injection mask to it. Turning now to fig. 5, an embodiment is shown in which, in the transmitting device, the selected error injection mask 520 (which is selected based on bit values ​​in field 220) is combined (using bit modulo 2 addition) with data bits 212 and error detection bits 214 in field 210 to modify only the 214 error detection bits, resulting in a modified field 530. Data block 200 comprising field 530 and field 220 is transmitted and received at the receiving device.

[0030] In the receiving device, the selected error injection mask 550 (which is selected based on the decoded bit values ​​in field 220) is combined (using bit modulo 2 addition) with data bits 532 and error detection bits 534 in field 530 to modify only the 534 error detection bits, resulting in a modified 560 field. The error detection calculation (in this example the checksum calculation) is applied to data bits 562, and the calculated checksum 570 is compared with the error detection bits 564. If these two values ​​are equal, then it can be said that the field 220 has been correctly decoded and normal processing can be continued at the receiving device, which depends on the type of data block received. If these two values ​​are not equal, then it can be concluded that an error has occurred (e.g. in decoding bits in field 220, in decoding data bits 532, or both) and the receiving device performs error handling, 7

EP 2 052 482 B1 including, but not limited to, rejecting the received data block and sending a NACK (negative acknowledgment message) to the transmitting device, or simply rejecting the received data block. In this example, the results indicate that field 220 has been correctly decoded.

[0031] Turning now to Fig. 6, an embodiment is shown in which, in the transmitting device, the selected error injection mask 620 (which is selected based on bit values ​​in field 220) is combined (using modulo 2 bit addition) with the bits data 212 and error detection bits 214 in field 210 to modify only data bits 212, resulting in modified field 630. Data block 200 comprising field 630 and field 220 is transmitted and received at the receiving device.

[0032] In the receiving device, the selected error injection mask 650 (which is selected based on the decoded bit values ​​in field 220) is combined (using bit modulo 2 addition) with data bits 632 and error detection bits 634 in field 630 to modify only data bits 632, resulting in a modified field 660. The error detection calculation (in this example the checksum calculation) is applied to data bits 662, and the calculated checksum 670 is compared with the error detection bits 664. If these two values ​​are equal, then it can be said that the field 220 has been correctly decoded and normal processing can be continued at the receiving device, which depends on the type of data block received. If these two values ​​are not equal, then it can be concluded that an error has occurred (e.g. when decoding bits in field 220, in decoding data bits 632, or both), and the receiving device should perform error handling. In this example, the results indicate that field 220 has been correctly decoded.

[0033] Turning now to Fig. 7, an embodiment is shown in which, in the transmitting device, the selected error injection mask 720 (which is selected based on bit values ​​in field 220) is combined (using modulo 2 bit addition) with the bits data 212 and error detection bits 214 in field 210 to modify only data bits 212, resulting in a modified field 730. Data block 200 comprising field 730 and field 220 is transmitted and received at the receiving device.

[0034] In the receiving device, the selected error injection mask 750 (which is selected based on the decoded bit values ​​in field 220) is combined (using bit modulo 2 addition) with data bits 732 and error detection bits 734 in field 730 to modify both data bits 732 and error detection bits 734, resulting in a modified 760 field. The error detection calculation (in this example the checksum calculation) is applied to data bits 762, and the calculated checksum 770 is compared with the error detection bits 764. If these two values ​​are equal, then it can be said that the field 220 has been correctly decoded and normal processing can be continued at the receiving device, which depends on the type of data block received. If these two values ​​are not equal, then it can be concluded that an error has occurred (e.g. when decoding bits in field 220, in decoding data bits 732, or both), and the receiving device should perform error handling. In this example, the results indicate that field 220 has been correctly decoded.

[0035] Turning now to Fig. 8, an embodiment is shown in which, in the transmitting device, the selected error injection mask 820 (which is selected based on bit values ​​in field 220) is combined (using modulo 2 bit addition) with the bits data 212 and error detection bits 214 in field 210 to modify only data bits 212, resulting in a modified field 830. Data block 200 comprising field 830 and field 220 is transmitted and received at the receiving device.

[0036] In the receiving device, the selected error injection mask 850 (which is selected based on the decoded bit values ​​in field 220) is combined (using modulo 2 bit addition) with data bits 832 and error detection bits 834 in field 830 to modify both 832 data bits and 834 error detection bits, resulting in a modified 860 field. The error detection calculation (in this example the checksum calculation) is applied to data bits 862, and the calculated checksum 870 is compared with the error detection bits 864. If these two values ​​are equal, then it can be said that the field 220 has been correctly decoded and normal processing can be continued at the receiving device, which depends on the type of data block received. If these two values ​​are not equal, then it can be concluded that an error has occurred (e.g. when decoding bits in field 220, in decoding data bits 832, or both), and the receiving device should perform error handling. In this example, the results indicate that field 220 has not been correctly decoded.

[0037] Turning now to Fig. 9 it is shown an embodiment in which multiple masks are applied to data bits 212 and field 220 error detection bits 21 to detect errors in decoding multiple field bits in data block 200, none of which have error detection bits or have limited error detection bits. In the specific drawing shown in fig. 2, two masks are used (one corresponding to field 220 and the other corresponding to field 230). However, based on the information provided here, any number of masks can be used. However, care should be taken when choosing predetermined mask values ​​so that errors in more than one field potentially do not cancel each other, leading to unreliable results.

[0038] In the transmitting device, the selected error injection masks 920 (which are selected based on bit values ​​in field 220) are combined (using bit modulo 2 addition) with data bits 212 and error detection bits 214 in field 210 to modify both bits data 212 as well as error detection bits 214, resulting in a modified field 930. Data block 200 comprising field 930 and fields 220 and 230 is transmitted and received at the receiving device.

[0039] In the receiving device, the selected error injection masks 940 (which are selected based on decoded bit values ​​in field 220) and 950 (which are selected based on decoded bit values ​​in field 230) are combined (using modulo 2 bit addition) data bits 932 and error detection bits 934 in field 930 to modify both data bits 932 and error detection bits 934, resulting in a modified field 960. The error detection calculation (in this example the checksum calculation) is applied to data bits 962, and the calculated checksum 970 is compared with the error detection bits 964. If these two values ​​are equal, then it can be said that the field 220 has been correctly decoded and normal processing can be continued at the receiving device, which depends on the type of data block received. If these two values ​​are not equal, then it can be concluded that an error has occurred (e.g. when decoding bits in fields 220 or 230, in decoding data bits 832, or in combination of these three fields), and the receiving device should perform error handling. In this example, the results indicate that fields 220 and 230 have been correctly decoded.

[0040] Fig. 10 illustrates an example DMR Data and Control Data packet as defined in ETSI TS 102 361-1. The data and control packet contains an Info 1010 field that holds 196 bits of information. In this example, the information consists of Link Control (LC) 1016, Error Detection (CRC) 1018, Turbocode 9

EP 2 052 482 B1 block product (BPTC) and FEC parity (not shown) added by BPTC encoder 1014 (196, 96). The data and control packet also contains a 20-bit Slot Type 1020 field that defines the meaning of the information bits. The Slot Type field contains the Color Code (CC) 1022 field, Data Type 1024 field and FEC 1026 parity field, according to ETSI TS 102 361-1. In this example, the Data Type 1024 field may be set to LC Voice Header. The center of the packet includes either a synchronization pattern or embedded signaling information field 1030 according to ETSI TS 102 361-1. Also shown is interleaver 1012 according to ETSI TS 102 361-1.

[0041] Turning now to Fig. 11, a method 1100 is provided for detecting errors in a TDMA DMR packet, such as packet 1000 according to an embodiment of the invention. In this embodiment, the transmitting device generates a TDMA DMR packet 1000 according to the information herein, which enables detection of data type 1024 bit errors in the Slot Type 1020 field, using the error detection mechanism in the Information 1010 field. It should be noted that with respect to this exemplary packet 1000, only the data and / or the parity of error detection in Information field 1010 are "modified" according to the information contained herein, and the bit generation for the remaining fields is shown in Fig. 10 is as disclosed in ETSI TS 102 361-1, the generation of which will not be further described herein for brevity.

[0042] In step 1102 of method 1100, the data type bits 1024 and data bits (in this case LC bits) 1016 are generated and appropriately received, to the Slot type field 1020 and to the Information field 1010 of packet 1000. At step 1104, the error detection parity is calculated (e.g. CRC) 1018 for LC 1016 data bits and attached to LC 1016 data bits within packet Information 1010 field at step 1106. At step 1108, the transmitting device selects an error injection mask for specific bits of data type 1024, adopted at step 1102. In step 1110, the selected error injection mask is applied (e.g., using modulo 2 bit addition) to LC 1016 data bits and CRC 1018 parity to generate the modified LC 1016 data bits and / or CRC 1018 parity. At step 1112, the transmitting device transmits to the receiving device a packet 1000 that includes (of course, inter alia, fields with their corresponding bits), slot type 1020 field, containing data type 1024 bits and information field 1010, containing modified LC 1016 data bits and / or parity CRC 1018.

[0043] It will now temporarily return to steps 1108 and 1110 for selecting and using the error injection mask. Each data type, already marked in ETSI TS 102 361-1, is assigned a predefined error injection mask. Additional error injection masks can also be predefined and reserved for future data types. Tables 1 and 2 below show examples of error injection masks that can be assigned to current and future data types. These sample data masks are selected based on the data type specified in the table and applied to the Information 1010 field to modify only the CRC 1018 parity. In this case, since the data type is LC voice header, mask 96969616 corresponding to LC voice header is selected and applied to the Information 1010 field to modify the parity of CRC 1018. However, as explained above, in other embodiments, error injection masks may be predetermined that would only modify LC 1016 data bits or both LC 1016 data bits and CRC 1018 parity.

Table 1

<td>Data Type</td><td>8 bit mask</td><td>9-bit mask</td><td>16-bit mask</td>

EP 2 052 482 B1

<td colspan="3"></td><td>(base 16)</td><td>(base 8)</td><td>(base 16)</td><td></td>

<td></td><td>PI header</td><td>0</td><td>69</td><td>551</td><td>6969</td><td></td>

<td></td><td>LC voice header</td><td>1</td><td>96</td><td>226</td><td>9696</td><td></td>

<td></td><td>Terminator with LC</td><td>2</td><td>99</td><td>631</td><td>9999</td><td></td>

<td></td><td>CSBK</td><td>3</td><td>a5</td><td>645</td><td>a5a5</td><td></td>

<td></td><td>MBC header</td><td>4</td><td>aa</td><td>252</td><td>aaaa</td><td></td>

<td></td><td>Continuation of MBC</td><td>5</td><td>c3</td><td>703</td><td>c3c3</td><td></td>

<td></td><td>Data header</td><td>6</td><td>cc</td><td>314</td><td>cccc</td><td></td>

<td></td><td>Speed ​​1/2 continuation data</td><td>7</td><td>f0</td><td>360</td><td>Fofo</td><td></td>

<td></td><td>Speed% of data continuation</td><td>8</td><td>ff</td><td>777</td><td>ffff</td><td></td>

<td></td><td>idle</td><td>9</td><td>00</td><td>000</td><td>0000</td><td></td>

<td></td><td>Reserved for future use</td><td>and</td><td>0f</td><td>417</td><td>0f0f</td><td></td>

<td></td><td>Reserved for future use</td><td>b</td><td>33</td><td>463</td><td>3333</td><td></td>

<td></td><td>Reserved for future use</td><td>c</td><td>3c</td><td>074</td><td>3c3c</td><td></td>

<td></td><td>Reserved for future use</td><td>d</td><td>55</td><td>525</td><td>5555</td><td></td>

<td></td><td>Reserved for future use</td><td>e</td><td>5a</td><td>132</td><td>5a5a</td><td></td>

<td></td><td>Reserved for future use</td><td>f</td><td>66</td><td>146</td><td>6666</td><td></td>

Table 2

<td>Data Type</td><td colspan="2">24-bit mask (base 16)</td><td>32-bit mask (base 16)</td>

<td>PI header</td><td>0</td><td>696969</td><td>69696969</td>

<td>LC voice header</td><td>1</td><td>969696</td><td>96969696</td>

<td>Terminator with LC</td><td>2</td><td>999999</td><td>99999999</td>

<td>CSBK</td><td>3</td><td>a5a5a5</td><td>a5a5a5a5</td>

<td>MBC header</td><td>4</td><td>aaaaaa</td><td>aaaaaaaa</td>

<td>Continuation of MBC</td><td>5</td><td>c3c3c3</td><td>c3c3c3c3</td>

<td>Data header</td><td>6</td><td>cccccc</td><td>cccccccc</td>

<td>Speed ​​1/2 data continuation</td><td>7</td><td>fOfOfO</td><td>fOfOfOfO</td>

<td>Speed% of data continuation</td><td>8</td><td>ffffff</td><td>ffffffff</td>

<td>idle</td><td>9</td><td>000000</td><td>00000000</td>

<td>Reserved for future use</td><td>and</td><td>0f0f0f</td><td>0f0f0f0f</td>

EP 2 052 482 B1

<td>Reserved use</td><td>down</td><td>the future</td><td>b</td><td>333333</td><td>33333333</td>

<td>Reserved use</td><td>down</td><td>the future</td><td>c</td><td>3c3c3c</td><td>3c3c3c3c</td>

<td>Reserved use</td><td>down</td><td>the future</td><td>d</td><td>555555</td><td>55555555</td>

<td>Reserved use</td><td>down</td><td>the future</td><td>e</td><td>5a5a5a</td><td>5a5a5a5a</td>

<td>Reserved use</td><td>down</td><td>the future</td><td>f</td><td>666666</td><td>66666666</td>

[0044] In another embodiment, error detection for at least one other field in the packet can be performed, using Error field 1010's error detection mechanism. For example, another field that does not have error detection and which may be the second field for which error detection can be performed using error detection of Information field 1010 is field 922 Color Code (CC). In this embodiment, a second set of predetermined masks may be used, e.g. shown in Tables 3 and 4 below, to enable detection of errors in the CC field according to the above information. Accordingly, both masks would use CRC parity to modify the transmitting device, and two selected masks would be used on the receiving device to modify CRC parity again. Error detection can then be performed similarly to the one described below with reference to fig. 12.

Table 3

<td colspan="2">Field secondary</td><td>8-bit mask (base 16)</td><td>9-bit mask (base 8)</td><td>16-bit mask (base 16)</td>

<td>Value 0</td><td>0</td><td>6a</td><td>626</td><td>6996</td>

<td>Value of 1</td><td>1</td><td>95</td><td>151</td><td>9669</td>

<td>Value 2</td><td>2</td><td>9a</td><td>546</td><td>9966</td>

<td>Value 3</td><td>3</td><td>What</td><td>474</td><td>a55a</td>

<td>Value 4</td><td>4</td><td>cf</td><td>063</td><td>aa55</td>

<td>Value 5</td><td>5</td><td>a6</td><td>532</td><td>c33c</td>

<td>Value 6</td><td>6</td><td>a9</td><td>125</td><td>cc33</td>

<td>Value 7</td><td>7</td><td>f3</td><td>017</td><td>Foofa</td>

<td>Value 8</td><td>8</td><td>fc</td><td>400</td><td>ffOO</td>

<td>Value 9</td><td>9</td><td>03</td><td>377</td><td>OOff</td>

<td>Value of 10</td><td>and</td><td>oc</td><td>760</td><td>OFFO</td>

<td>Value 11</td><td>b</td><td>thirty</td><td>714</td><td>33cc</td>

<td>Value 12</td><td>c</td><td>3f</td><td>303</td><td>3cc3</td>

<td>Value 13</td><td>d</td><td>56</td><td>652</td><td>55aa</td>

<td>Value 14</td><td>e</td><td>59</td><td>245</td><td>5aa5</td>

EP 2 052 482 B1

<td>Value 15</td><td>f</td><td>65</td><td>231</td><td>6699</td>

Table 4

<td colspan="2">Secondary field</td><td>24-bit mask (base 16)</td><td>32-bit mask (base 16)</td>

<td>Value 0</td><td>0</td><td>699669</td><td>69966996</td>

<td>Value of 1</td><td>1</td><td>966996</td><td>96699669</td>

<td>Value 2</td><td>2</td><td>996699</td><td>99669966</td>

<td>Value 3</td><td>3</td><td>a55aa5</td><td>a55aa55a</td>

<td>Value 4</td><td>4</td><td>aa55aa</td><td>aa55aa55</td>

<td>Value 5</td><td>5</td><td>c33cc3</td><td>c33cc33c</td>

<td>Value 6</td><td>6</td><td>cc33cc</td><td>cc33cc33</td>

<td>Value 7</td><td>7</td><td>fOOffO</td><td>fOOffOOf</td>

<td>Value 8</td><td>8</td><td>ffOOff</td><td>ffOOffOO</td>

<td>Value 9</td><td>9</td><td>OOffOO</td><td>0 OffO Off</td>

<td>Value of 10</td><td>and</td><td>OffO Of</td><td>OffO OffO</td>

<td>Value 11</td><td>b</td><td>33cc33</td><td>33cc33cc</td>

<td>Value 12</td><td>c</td><td>3cc33c</td><td>3cc333c3</td>

<td>Value 13</td><td>d</td><td>55aa55</td><td>55aa55aa</td>

<td>Value 14</td><td>e</td><td>5aa55a</td><td>5aa55aa5</td>

<td>Value 15</td><td>f</td><td>669966</td><td>66996699</td>

[0045] Turning now to Fig. 12, the receiving device, at step 1202, receives from the transmitting device a packet 1000, which includes (of course, among others, fields with their corresponding bits), slot type field 1020 containing data type 1024 bits and information field 1010 containing modified LC 1016 data bits and / or parity CRC 1018. At 1204, the receiving device decodes data type 1024 bits in the Slot Type 1020 field to identify the data type for data bits 1016 in the Information field 1010 of the received packet 1000. The receiving device uses (196, 96) the BPTC decoder to decode the bits that have been encoded by (196, 96) the BPTC encoder in the transmitting device. The receiving device then selects the error injection mask corresponding to the decoded bits of the data type 1024. If the receiver decodes the data type correctly, it selects the error injection mask corresponding to the LC Voice Header data type (in this case 96969616).

[0046] The receiving device applies the selected error injection mask (using modulo 2 bit arithmetic) to data bits 1016 and CRC parity 1018 at step 1208 to (in this case) modify the CRC parity 1018. The receiving device performs the error detection calculation, in step 1210 (in this case, the CRC calculation) on the modified Information field. From the CRC calculation, in step 1212, the receiving device determines whether to continue normal processing in step 1216, when the CRC calculation indicates no decoding errors in decoding bit data type 1024 and in decoding LC bit 1016. If the CRC calculation indicates a decoding error (which may occur in data or data type bits), the receiving device performs error handling in step 1214, for example as discussed above.

[0047] Thus, when the receiving device correctly decodes data type bits and data bits, CRC also

EP 2 052 482 B1 will likewise indicate, with a specific indication depending on how the CRC calculation was performed. In one embodiment, for example as discussed generally above, the calculation of CRC can only be performed on the LC 1016 data bits themselves, and the comparison made between the calculated CRC and CRC 1018 bits before modifying the Information field using an error injection mask. Where these two values ​​are equal, it means that the receiving device has correctly decoded the data type 1024 bits and correctly decoded the LC 1016 bits. The difference in these values ​​similarly indicates that the CRC 1018 bits and / or LC 1018 bits have been incorrectly decoded. In another embodiment, also discussed above, the CRC calculation may be performed on both the LC 1016 data bits and the current CRC 1018 bits, and the comparison made between the calculated CRC and the predetermined bit value, such as zero. Where the calculated CRC is zero, it means that the receiving device correctly decoded the data type 1024 bits and correctly decoded the LC 1016 bits. A non-zero CRC indicates that the CRC 1018 bits and / or LC 1018 bits have been incorrectly decoded.

[0048] The preceding specification describes specific embodiments of the invention. However, those skilled in the art will recognize that various modifications and changes can be made without departing from the scope of the invention as defined in the claims below. Accordingly, specifications and figures should be considered as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the invention. Benefits, advantages, problem solutions, and any elements that may cause any benefit, advantage or solution to occur or become clearer are not to be interpreted as critical, required or essential features, or elements of any or all claims. The invention is defined only by the appended claims, including any corrections made during the course of this application, and all the equivalents of these claims in their issued form.

[0049] Furthermore, in this document, relative concepts, such as first and second, top and bottom, and the like, can only be used to distinguish one object or activity from another object or activity, without requiring or implying any such actual dependencies or order between such objects or activities. The terms "contains", "containing", "has", "having", "includes", "including", "housing", "housing" or any other variations thereof are intended to include non-exclusive incorporation so that the process, method , an article or apparatus that includes, has, includes, includes a list of items does not include only these items, but may include other items not explicitly mentioned or inherent in such a process, method, article or device. The element processed by "contains ... certain "," has ... certain "," includes ... certain "," accommodates ... certain ”does not exclude, without further limitation, the existence of additional, identical elements in a process, method, article or apparatus that contains, has, includes, houses this element. The concept of indefinite article No. (Ang. "A", "an") are defined as one or more, unless explicitly stated otherwise. The terms "substantially", "essentially", "approximately", "about" or any other versions thereof are defined as being close to one another as understood by one of ordinary skill in the art, and in a non-limiting embodiment the term is defined as falling within within 10%, in another embodiment within 5%, in another embodiment within 1%, and in another embodiment within 0.5%. The term "coupled" as used herein is defined as connected, though not necessarily directly and not necessarily mechanically. A device or structure that is "configured" in some way is configured in at least that way, but can also be 14

Configured in ways that are not mentioned.