Scalable bus structure

[0001] The present invention relates generally to digital systems and in particular to the scalable bus structure.

Background [0002] Computers have revolutionized the electronics industry by enabling advanced processing tasks to be carried out quickly. These advanced tasks can be performed by systems containing a large number of complex components that communicate with each other quickly and efficiently using the bus. A bus is a channel or path between elements in a computer, computer subsystem, computer system or other electronic system.

[0003] Many buses present in a computer are traditionally implemented in the form of shared buses. The shared bus provides means for any number of elements to communicate on a common path or channel. In recent years, shared bus technology has been supplemented with point-to-point switching connections. Connections with point-to-point switching ensure a direct connection between two elements on the bus during their mutual communication. Multiple direct links can be used to allow simultaneous communication of several elements.

[0004] A common configuration for a computer includes a microprocessor with system memory. A high bandwidth system bus can be used to support communication between these two components. In addition, a peripheral bus may also be present, which is used for data transmission to peripheral devices. In some cases, a configuration bus may also be present, which is used to program various resources. bridges

53 / 59P26888EN00 can be used to efficiently transfer data between higher and lower bandwidth buses, as well as to provide the necessary protocol translation. Each of these buses has been implemented using different protocols and there may be large differences in performance requirements between them.

[0005] The use of many bus structures in a computer has proved to be a useful solution for many years. However, when surface area and power have become major design issues for integrated circuits, there is an increasing need to reduce the complexity of the bus structure.

SUMMARY OF THE INVENTION [0006] According to the present invention, there is provided a method of communication between a sending element and a receiving element over a bus according to claim 1 and a processing system according to claim 12.

[0007] The method may further include storing write data transmitted on the first channel in the receiving element based on the information about the write address and write control signals, retrieving read data from the receiving element based on the read address information and read control signals, and transmitting from the element. receiving downloaded read data on the second channel.

[0008] The sending means may be configured to signal the receiving element in such a way that the receiving element can make a distinction between read and write address information, read and write control signals, and write data transmitted on the first channel.

[0009] The processing system may include a bus having a first channel and a second channel. System

The processing means may include sending means for transmitting read and write address information, read and write control signals and write data on the first channel. The processing system may further include receiving means for storing write data transmitted in the first channel based on the write address information and the write control signals, download the read data based on the address read information and the read control signals and transmit the downloaded read data in the second channel to the sending element . The sending means may further include means for signaling the receiving means in such a way that the receiving means can distinguish between read and write address information, read and write control signals, and write data transmitted on the first channel.

[0010] It will be appreciated that it will be readily apparent to those skilled in the art that embodiments of the present invention other than those set forth in the following detailed description may be made, and the various embodiments of the invention have been illustrated and illustrative. As will be explained, the invention may be implemented in other and different embodiments, and several of its details may be modified in various other respects, all without departing from the spirit and scope of the present invention. Accordingly, the drawings and detailed description should be considered illustrative rather than restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS [0011] Aspects of the present invention have been illustrated by way of example, and not limitation, in the accompanying drawings, in which:

[0012] Fig. 1 is a conceptual block diagram illustrating an example of a point-to-point after connection

53 / 59P26888EN00 through a two-channel bus between two components in the processing system.

[0013] Fig. 2 is a time course showing the read and write operation between two elements in a processing system having a point-to-point connection via a two-channel bus.

[0014] Fig. 3 is a conceptual block diagram illustrating an example of a point-to-point connection via a high-performance two-channel bus between two components in a processing system.

[0015] Fig. 4 is a conceptual block diagram illustrating the high performance bus of Fig. 3, multiplexed with time division.

[0016] Fig. 5 is a conceptual block diagram illustrating an example of a point-to-point connection via a two-channel low bandwidth bus between two components in a processing system.

[0017] Fig. 6 is a conceptual block diagram illustrating the low bandwidth bus of Fig. 5, multiplexed with time division, and [0018] Fig. 7 is a conceptual block diagram illustrating an example of a point-to-point connection between a high element performance and the element with smaller bandwidth, via a bridge.

DETAILED DESCRIPTION [0019] The following detailed description, in conjunction with the accompanying drawings, is provided as a description of various embodiments of the present invention, but not the only embodiments in which the present invention may be implemented. The detailed description includes specific details to facilitate an in-depth understanding of the present invention. However, those skilled in the art will recognize that the present invention can be implemented without these specific details. IN

In some cases, well-known structures and elements are shown in block diagram form in order to preserve the clarity of the idea of ​​the present invention. Acronyms and other descriptive nomenclature can only be used for convenience and clarity, and is not intended to limit the scope of the invention.

[0020] In the processing system, different elements may communicate via the bus. This bus can be scalable in terms of width and clock frequency to meet the bandwidth requirements for various components. The bus can also use a common architecture and signaling protocol for all scalable configurations. This can be achieved by reducing the bus signaling protocol only to those signals that are necessary for transmitting or receiving information.

[0021] The bus may be configured for transmission ", which is the standard for transmitting information from a sending element to a receiving element using the same signaling protocol in a time division multiplexing model. The "receiving channel" may also use the same signaling protocol to transmit information from the receiving component to the sending component.

[0022] Fig. 1 is a conceptual block diagram illustrating this fundamental idea. Element-type connection via bus is shown. The processing system 100 may be a set of elements that interact to perform one or more processing functions. Typically, the processing system will be a computer or a "carrier channel for."

In a point-to-point processing system between two, it will reside in processing, downloading the computer will be able to store information. The processing system may be an autonomous system. Alternatively,

The processing system may be embedded in any device such as, for example, a cellular telephone.

[0023] In one embodiment of the processing system 100, the bus 106 is a dedicated bus between the sending element 102 and the receiving element. In another embodiment of the processing system 100, the sending element 102 communicates with the receiving element 104 via a point-to-point connection on the bus 106 via a bus interconnection (not shown). In addition, as will be readily apparent to those skilled in the art, the novel aspects of this description are not limited to a dedicated bus or point-to-point switching connection, but can be used in any type of bus technology, including, for example, a shared bus.

[0024] The sending element 102 may be any type of bus-supporting element, including, for example, a microprocessor, digital signal processor (DSP), direct memory access controller, bridge, programmable logic element, discrete gate or transistor logic element or any other element processing information.

[0025] The receiving element 104 may be any memory element, including, for example, registers, memory, a bridge, or any other element capable of retrieving and storing information. The memory capacity at each address location of the receiving component may vary depending on the particular application and general construction restrictions. For the purposes of explanation, the receiving component will be described for a memory capacity of 1 byte per one address location.

[0026] The sending element 102 may perform a read from or write to the receiving element 104. In the event that the sending element 102 writes to the receiving element 104, the sending element may transmit the address location,

The respective control signals, as well as the data field to the receiving element 104 on the transmission channel 108. "Data field" means data associated with a particular read or write operation, and in this case associated with a write operation.

[0027] The control signals may include transfer qualifiers. The term "transfer qualifier" refers to a parameter that describes the attribute of a read operation, write operation, or other bus-related operation. In this case, the transfer qualifiers may contain a "data field size signal" to indicate the number of bytes of data contained in the data field. If the data field is a plurality of bytes, then the receiving component 104 may store the data field in a block of consecutive address locations beginning with the address location transmitted on transmission channel 108. For example, if the sending device 102 transmits the 100HEX address location followed by a 4-byte data field, then the receiving element 104 may write this data field in a block of consecutive address locations starting from the 100HEX address and ending at the 103HEX address.

[0028] The control signals may also include byte write permission. "Write byte permissions" can be used to indicate which byte lines on transmission channel 108 will be used to transmit a data field for write operations. For example, a 2-byte data field transmitted on a 32-bit transmission channel 108 may use 2 to 4 byte lines. Write byte permissions can be used to indicate to the receiving element 104 which of the 2-byte lines in transmission channel 108 will be used to transmit the data field.

[0029] In the event that the sending component 102 performs a reading from the receiving component 104, then the address location and appropriate transfer qualifiers may be the only information that must be sent in

53 / 59P26888EN00 transmission channel 108. Transfer qualifiers may include a data field size signal to indicate the number of bytes of data contained in the data field. The receiving component 104 may acknowledge this transmission and send the data field on the receiving channel 110. If the data field is a plurality of bytes, then the receiving element 104 can read this data field from the block of consecutive address locations, starting from the address location transmitted on transmission channel 108. For example, if the sending device 102 transmits a 200HEX address location and requests a 4-byte data field, then the receiving element 104 may retrieve the data field from the block of sequential address locations, starting from the 200HEX address and ending at the 203HEX address.

[0030] In an embodiment of the processing system of the hitherto described sending element 102 has total control over the transmission channel 108 and may transmit one or more address locations along with associated control signals before, during or after the active write operation. Also, transmission channel 108 and receiving channel 110 are completely independent, and thus the transmission of address locations, control signals and write data by the sending element may coincide with the transmission of read data by the receiving element 104. The term "write data" refers to data transmitted by sending element 102, and the term "read data" refers to data read from the receiving element 104 and transmitted on the receiving channel 110.

[0031] An implicit addressing scheme may be used to control the sequence of data read and write operations on the transmission channel 108 and the receiving channel 110. For example, if the sending element 102 initiates a plurality of write operations by transmitting a series of address locations with the corresponding control signals on transmission channel 108, then the sending element 102 will

53 / 59P26888EN00 transmitted the data field for each write operation in the same order in which the address locations are transmitted. Similarly, if the sending element 102 initiates multiple read operations by transmitting a series of address locations with the appropriate control signals, then the receiving element 104 will download the data field for each read operation in the same order in which it receives the address locations.

[0032] The term "transfer tags" can be used as an alternative to this implicit addressing scheme. The sending element 102 may assign a transfer tag for each read and write operation. The transfer marker may be included in the transfer qualifiers transmitted on transmission channel 108. For the write operation, the sending element 102 may send the transfer tag with the data field, and the receiving element 104 may use the transfer tag recovered from the transfer qualifiers to identify the data field. In the case of a read operation, the receiving component 104 may send the downloaded transfer tag along with the data field, and the sending item may use the transfer tag to identify the data field.

[0033] The various concepts described so far can be implemented using any number of protocols. The following detailed description will show an example of a bus protocol. This bus protocol is presented to illustrate the innovative aspects of the processing system, understanding that such innovative aspects can be applied with any suitable protocol. The basic signaling protocol for the transmission channel is shown below in Table 1. Those skilled in the art will easily be able to change and / or add signals to this protocol in a real implementation of the bus structure described herein.

53 / 59P26888PL00

Table 1

<td>Signal</td><td>Definition</td><td>controlled by</td>

<td>Clock</td><td>Reference clock signal</td><td>System</td>

<td>Current</td><td>Current information is transmitted on the transmission channel</td><td>Sending item</td>

<td>Type (2: 0)</td><td>Indicates the type of broadcast information</td><td>Element the sender</td>

<td>Request for Transfer</td><td>Indicates that the receiving element is ready to receive data recording</td><td>Element receiver</td>

<td>Channel broadcasting</td><td>Channel controlled by element sender to transmit information</td><td>Element the sender</td>

[0034] The same signaling protocol can be used for a reception channel as shown below in Table 2.

Table 2

<td>Signal</td><td>Definition</td><td>controlled by</td>

<td>Clock</td><td>Reference clock signal</td><td>System</td>

<td>Current</td><td>Transmitted on the receiving channel is current information</td><td>Element receiver</td>

<td>Type (2: 0)</td><td>Indicates the type of broadcast information</td><td>Element receiver</td>

<td>Request for Transfer</td><td>Indicates that the sending item is ready to receive read data</td><td>Sending item</td>

<td>Channel receiving</td><td>Channel controlled by element receiving to transmit information</td><td>Element receiver</td>

[0035] The definition of the Type field used in this signaling protocol is provided in Table 3.

53 / 59P26888PL00

Table 3

<td>Value type</td><td>Definition</td>

<td> 000</td><td>Reserved</td>

<td> 001</td><td>Current address save location</td>

<td> 010</td><td>Current control signals record</td>

<td> 011</td><td>Current recording data</td>

<td> 100</td><td>Reserved</td>

<td> 101</td><td>Current address read location</td>

<td> 110</td><td>Current control signals reading</td>

<td> 111</td><td>Current read data</td>

[0036] The definitions of the fields: Current and Transfer Request in this signaling protocol are presented in Table 4.

Table 4

<td>Current; Request for Transfer</td><td>Definition</td>

<td> 0 ; 0</td><td>The current information is not transmitted and the element at the other end is not ready to receive the transmission</td>

<td> 0 ; 1</td><td>Current information is not transmitted, but the element at the other end is ready to receive the transmission</td>

<td> 1 ; 0</td><td>Current information is being transmitted, but the element at the other end is not ready to receive the transmission</td>

<td> 1 ; 1</td><td>Current information is transmitted and the element at the other end is ready to receive the transmission</td>

[0037] Fig. 2 is a time course illustrating the read and write operation on the 32-bit transmission channel

Transmitted by the receiver.

and a 32-bit receive channel. A System Clock 202 may be used to synchronize communication between the sending and receiving elements. The System Clock 202 is depicted with eleven clock cycles, with each cycle numbered consecutively for ease of explanation.

[0038] The write operation may be initiated by the sending element during the second clock cycle 203. This can be achieved by setting the Current 204 signal and the Type 206 field to signal the location address transmission for write operations. The address location may also be on the Transmission Channel 208 to the element. In response to this transmission, the receiving element stores the address location in its address queue.

[0039] After the location address transmission has been performed, the control signal may be transmitted for the write operation in the third clock cycle 205. The sending component may alert the receiving component that the control signal has been transmitted by maintaining the Current 204 signal assurance and by changing the Type 206 field accordingly. The control signal transmission may include transfer qualifiers and byte write permissions for write operations. In this case, the transfer qualifiers may include a data field size signal indicating a 8 byte data field. Write byte permissions may indicate that an 8-byte data field will be transmitted on all byte lines of Transmission Channel 208. The receiving component may determine based on this information that the data field will be transmitted in two clock cycles.

[0040] The first 4 bytes of the data field for the write operation may be transmitted on Transmission Channel 208 during the fourth clock cycle 207. The sending element may alert the receiving element about data field transmission by maintenance

Provide a Current 204 signal and perform a Type 206 field change to signal transmission of the data field. In the absence of transfer markers, the receiving component recognizes the write data as the first 4 bytes of the data field based on the implicit addressing scheme discussed earlier. In response to this transmission, the first 4 bytes of the data field can be written to the receiving element.

[0041] In the next clock cycle 209, the Current signal 204 and Type 206 field remain unchanged, since the second 4 bytes of the data field are transmitted on Transmission Channel 208. However, the receiving component did not provide the Transfer Request 210 signal, indicating that it will not could accept the transmission. The sending member can detect that the Transfer Request 210 signal is not provided at the end of the fifth clock cycle 209 and repeat transmission of the second 4 bytes of data field in the next clock cycle 211. The sending element may continue to transmit the second 4 bytes of the data field in each clock cycle until the sending element detects the provision of a Transfer Request 210 signal from the receiving element. In this case, only one repeat transmission is required. The second 4 bytes of the data field can be written to the receiving element in the sixth clock cycle. At the end of the sixth clock cycle 211, the sending element detects the provision of the Transfer Request 210 signal and states that the transmission has been received.

[0042] The read operation may be initiated by the sending element during the seventh clock cycle 213. This can be accomplished by providing a Current 204 signal and setting a Type 206 field to signal location address transmission for read operations. The address location may then be transmitted on the Transmission Channel 208 to the receiving component. In response to this transmission, the receiving component stores the address location in its address queue.

[0043] After the location address transmission, the control signal may be transmitted for the read operation in the eighth clock cycle 215. The sending component may alert the receiving component about the transmission of the control signal by maintaining the Current 204 signal provision and changing the Type 206 field accordingly. The control signal transmission may include transfer qualifiers for the read operation. In this case, the transfer qualifiers may include a data field size signal indicating a 4 byte data field. The receiving component can conclude from this information that the data field can be transmitted in one clock cycle.

[0044] Due to the latency of reading the receiving element, several delay clock cycles may occur before the read data is transient. When a 4-byte data field is already available, the receiving element can provide a Current 212 signal and provides a Type 214 field by signaling the transmission of the data field on Receiving Channel 216. Due to the fact that the Request 218 Transfer signal is provided by the sending element, the transmission of the data field can be completed in one clock cycle. The receiving component detects the provision of the Transfer 218 Request signal at the end of the tenth cycle 219 of the clock and thereby determines that the data field transmission was successful.

[0045] Fig. 3 is a conceptual block diagram illustrating a point-to-point connection between two elements via a high performance bus. Transmission channel 108 and high performance bus receiving channel 110 may be implemented in the form of multiple sub-channels, each sub-channel having a width of 32 bits. In actual implementations, the number of subchannels and the width of each subchannel may vary depending on the performance requirements of the application. In this example, the transmission channel contains 4 32-bit subchannels 108a-108d, while

The receiving channel includes 2 32-bit subchannels 110a - 110b.

The implementation of this bus can be suitable for, for example, a computer or any other high performance bus. The term "subchannel" refers to a group of cables or wires that can be controlled independently of other cables or wires in a channel. This means that each subchannel can have independent signaling capability.

[0046]

This high performance bus can be used by the sending element 102 to simultaneously transmit several combinations of information. For example, the sending element may transmit a 32-bit address location, 32 bits of control signals containing transfer qualifiers and write byte permissions, as well as 8 bytes of write data in a single clock cycle. For the receiving channel 110, 8 bytes of read data may be transmitted from the receiving element 104 to the sending element 102 in one clock cycle.

[0047] Because the various embodiments of the processing system described so far do not contain any other type of information transmitted on the receiving channel 110 other than the read data, there is no need for subchannels. A single 64-bit receive channel can be implemented to reduce signaling requirements (i.e. without subchannels). However, in some embodiments of the processing system, the Type field in the signaling protocol may be extended to allow transmission of other information. For example, a "write response" may be transmitted on the receiving channel 110 to signal to the sending member that data has been recorded on the receiving element 104. The write response may be transmitted on the receiving channel 110 using one of the reserved Type fields. In this case it may be useful to have two independently controlled 32-bit ones

It is thus possible to simultaneously transmit 4 bytes of read data, 2 bytes of read data and a 32-bit write response or two 32-bit write responses. On the other hand, a single 64-bit receive channel 110 may only be able to handle read data or write responses at any given clock cycle.

[0048] In a similar manner, the transmission channel may also be extended to cover the transmission of other types of information that are common to many bus protocols, such as standard commands. For example, a microprocessor connected to the bus may need to transmit information to other components in the system, such as the TAB Sync command or the TAB invalidate command. These commands can be classified in the Type field without the need for additional signaling.

[0049] Fig. 4 is a block diagram illustrating transmission channel 108, time division multiplexed, with 4 subchannels 108a-108d. In this example, the full transmission of an 8-byte data field can be completed in 4 subchannels in one clock cycle. In particular, during the first clock cycle 401, the sending element may transmit a 32-bit address location in the first sub-channel 108a and 32 bits of control signals in the second sub-channel 108b for the first write operation. The sending component may also perform, during the same clock cycle, 4 bytes of the higher order data field in the third subchannel 108c and 4 bytes of the lower order data field in the fourth subchannel 108d. Each of the sub-channels 108a-108d may have the ability to independently signal, and in the case described above, it can provide a Current signal with a corresponding Type field for each sub-channel.

[0050] When a Transfer Request signal is provided for each sub-channel 108a-108d at the end of the first clock cycle 401, two read operations by the sending component during the second clock cycle 403 may be initiated. This can be accomplished by transmitting a 32-bit address location in the first sub-channel 108a and 32 bits of control signals in the second sub-channel 108b for the first read operation, along with corresponding signaling in each sub-channel 108a-108b. The sending element may also transmit the 32-bit address location in the third subchannel 108c and the 32 bits of control signals in the fourth subchannel 108d for the second read operation, again together with the corresponding signaling for the subchannels 108c-108d.

[0051] When a Transfer Request signal is provided for each sub-channel 108a-108d at the end of the second clock cycle, the second write operation and the third read operation may be initiated by the sending element during the third clock cycle 405. This can be accomplished by transmitting a 32-bit address location in the first sub-channel 108a and 32 bits of control signals in the second sub-channel 108b for the second write operation, along with corresponding signaling in each sub-channel 108-108b. The sending element may also transmit the 32-bit address location in the third subchannel 108c and the 32 bits of control signals in the fourth subchannel 108d for the third read operation, again together with the corresponding signaling for the subchannels 108c-108d.

[0052] In this example, at the end of the third clock cycle 405, a Transfer Request signal is provided in the first and second subchannels, 108a and 108b, but not in the third and fourth subchannels, 108c and 108d. The sending component may detect that Transfer Request signals in the third and fourth subchannels, 108c and 108d, are not provided and therefore determine that the address location and control signals for the third read operation should be re-transmitted.

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The address location and control signals for the third read operation have been shown to be transmitted during the fourth clock cycle 407 in the third and fourth subchannels 108c and 108d, respectively, but may be re-transmitted in any subchannels during any subsequent clock cycle.

[0053] In the above example, the receiving element is configured to either accept or reject both the address location and control signals for the third read operation. However, in some embodiments of the processing system, the receiving element may be configured to accept the address location and reject the control signals, or vice versa, for the same read or write operation. Similarly, the receiving element may be configured to accept or reject the higher order or lower order bytes of the data field individually. In this case, there must be a way to associate retransmission, e.g., control signals, for the third read operation with the address location for the same operation that was previously transmitted. This can be achieved in different ways. For example, when an address location for a read or write operation is sent and acknowledged by the receiving element, the address for the next read or write operation is not transmitted until control signals associated with the current request of the read or write operation are received and confirmed by receiving element. [0054] During the fourth clock cycle 407, the sending element may transmit the data field for the second write operation and attempt to initiate the third read operation a second time. This can be accomplished by transmitting 4 bytes of a higher order data field in the first subchannel 108a and 4 bytes of a lower order data field in the second subchannel 108b for the second write operation, along with the appropriate signaling in each

Subchannel 108a-108b. The sending element may also re-transmit the 32-bit address location in the third subchannel 108c and the 32 bits of control signals in the fourth subchannel 108d for the third read operation.

[0055] In this embodiment of the high performance bus, determining the ordering of read / write requests can be inferred from the location. The sending element may transmit the first read / write request in the first

<td>subchannel</td><td>108a,</td><td>second</td><td>request</td><td>read / write</td><td>in second</td>

<td>subchannel</td><td>108b,</td><td>third</td><td>request</td><td>read / write</td><td>in third</td>

<td>subchannel</td><td>108c,</td><td>and</td><td>fourth</td><td colspan="2">read / write request in</td>

<td>fourth</td><td>subchannel</td><td>108d.</td><td colspan="2">The receiving element can</td><td>process</td>

these claims based on this alleged position to maintain sequential consistency. For example, if the address locations for read and write operations initiated during the third clock cycle 405 are the same, then the receiving component may wait until the data transmitted in the first subchannel and the second subchannel, 108a and 108b, during the fourth clock cycle 407 are saved at this address location before delivering this newly stored data at this address location to the receiving channel for transmission to the sending component.

[0056] In the high-performance bus embodiment described so far, write data need not be transmitted immediately after transmission of the write operation request (i.e., address location and control signals). On the transmission channel 108, other requests for higher priority read operations and / or commands may be interleaved along with the transmission of write data. However, if the sending element interleaves requests for read operations and / or commands with write data, then the sending element should be configured with an address rollback mechanism.

[0057] As described previously with reference to Fig. 2, the sending element samples the Transfer Request 210 signal after transmission on Transmission Channel 208. If the sending component fails to detect the provided Transfer Request 210 signal, then it can repeat the transmission during the next clock cycle. This transmission can be repeated at every clock cycle until the sending element detects the assured Transfer Request 210 signal. The problem may arise when the address queue is full during the request for a read operation, and thus will no longer be able to accept any address locations. At the same time, the receiving component must complete the current write operation to free space in the address queue. In this case, the receiving element is said to be jammed.

[0058] The address rollback mechanism is intended to allow the write operation to end when the receiving component is jammed. This can be achieved by limiting the number of repeated transmissions by the sending element in connection with the request of the read operation. If the receiving component does not acknowledge the request for the read operation using the Transfer Request signal within a specified number of clock cycles, then the sending element may terminate the request by sending the remaining write data instead of the address location for the request of the current read operation. If there is no current write operation to complete, then the read operation request transmission need not be interrupted. This transmission can continue until the receiving component confirms the request.

[0059] An address rollback mechanism may not be needed if the sending element does not interleave read operation requests with write data. That is, if the address location for the write operation is followed immediately by control signals and then directly by the write data, the receiving element will never jam. However, maybe this

Cause the performance of the receive channel to deteriorate because the sending component may not be able to maintain a read operation pipeline sufficient to make full use of the receiver channel bandwidth.

[0060] Fig. 5 is a conceptual block diagram illustrating a point-to-point connection between two components via a low bandwidth bus. The low bandwidth bus can be implemented with a single transmission channel 108 and a single receiving channel 110, requiring less signals and giving less power dissipation. In the example shown in Fig. 5, the sending element 102 may transmit information to the receiving element 104 on the 32 bit transmission channel 108, and the receiving element 104 may transmit information back to the sending element 102 on the 32 bit receiving channel 110. Alternatively, the same bus architecture may be implemented for smaller bus width.

[0061] Although this configuration still allows the simultaneous transmission of information on the transmission channel 108 and the receiving channel 110, each read or write operation may now require multiple clock cycles as shown in the block diagram of Fig. 6 In this example, two clock cycles are used to initiate the read operation. More specifically, the 32-bit address location can be transmitted on transmission channel 108 in the first clock cycle 601, followed by 32 bits of control signals in the next clock cycle 603. A 4-byte data field may be read from the receiving component in response to this request and transmitted on the receiving channel 110 in the third clock cycle 605.

[0062] Concurrently with the transmission of the data field on the receiving channel, the sending element may initiate a write operation. In this case, the write operation uses three cycles

Clock. In the third clock cycle 605, the sending element transmits a 32-bit address location on transmission channel 108, followed by 32 bits of control signals in the fourth clock cycle 607, followed by a 4-byte data field in the fifth clock cycle 609.

[0063] In many processing systems, some devices may require interconnection with a large bandwidth, while others may work well enough with interconnection with a much smaller bandwidth. Thanks to the use of scaled bus architecture, the implementation of bridges can be implemented with a common signaling protocol. In fig. 7 is a conceptual block diagram illustrating a point-to-point connection between two elements via a bridge. Bridge 702 can be used to create an interface between the sending element 102 connected to the high performance bus with the receiving element 104 connected to the bus with a smaller bandwidth. The high performance bus can be implemented with a transmission channel 108 having four 32-bit subchannels 108a-108d and a receiving channel 110 having two 32-bit receive channels 110a and 110b. The bus with a smaller bandwidth can be implemented with a single 32-bit transmission channel 108 'and a single 32-bit receiving channel 110'.

[0064] In this example, the write operation can be completed between the sending device 102 and the bridge 702 during a single clock cycle using 4 transmission subchannels 108a - 108d of the high performance bus for the transmission of location addresses, control signals and - a byte data field as described previously in connection with Figs. 3 and 4. Bridge 702 can buffer and transmit information to receiving element 104 on a 32-bit bus channel 108 'with a smaller bus

Bandwidth in 4 clock cycles as previously described in connection with Figs. 5 and 6.

[0065] For read operations, the address location and control signals may be transmitted by sending element 102 to bridge 702 in 2 high performance transmission subchannels in one clock cycle. Bridge 702 may buffer and transmit this information to receiving component 104 on 32-bit transmission channel 108 'in two clock cycles. Then, an 8-byte data field from the receiving element 104 to the bridge 702 on the 32-bit receive channel 110 'can be transmitted, buffered in the bridge 702, and then transmitted via the bridge 702 to the sending element 102 in the two receiving sub-channels 110a and 110b in a single clock cycle.

[0066] Various illustrative logic blocks, modules and circuits described in relation to the exemplary embodiments described herein may be implemented or implemented using a general purpose processor, a signal processor (DSP), a specialized integrated circuit (ASIC), directly programmable gate matrix (FPGA) or other programmable logic element, logic based on discrete gates or transistor logic, hardware components or any combination designed to perform the general purpose processor described herein may discrete the above functions.

be a microprocessor or, but alternatively, the processor may be a traditional processor, controller, microcontroller, state machine. The processor may be implemented as a combination of computing elements, e.g., a combination of DSP and microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or any combination of this type.

[0067] The methods or algorithms described in connection with the embodiments shown herein can be implemented

53 / 59P26888EN00 directly in hardware form, in a program module executed by the processor or in a combination of both. The program module can be located in RAM memory, in flash memory, ROM memory, EPROM memory, EEPROM memory, in registers, on the hard disk, portable disk, on the CDROM or on any form of storage medium known in the art. The storage medium may be connected to the processor such that the processor can read and write information to the storage medium. In an alternative solution, the data carrier may be integrated with the processor. The processor and data carrier may be in the ASIC. The ASIC may be located in the sending element and / or receiving element, or anywhere else. Alternatively, the processor and the data carrier may be located as discrete elements in the sending element and / or receiving element or anywhere else.